sys/dev/sfxge/common/efx_impl.h

   1 /*-
   2  * Copyright (c) 2007-2015 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #ifndef _SYS_EFX_IMPL_H
  34 #define _SYS_EFX_IMPL_H
  35
  36 #include "efx.h"
  37 #include "efx_regs.h"
  38 #include "efx_regs_ef10.h"
  39
  40 /* FIXME: Add definition for driver generated software events */
  41 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  42 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  43 #endif
  44
  45
  46 #if EFSYS_OPT_SIENA
  47 #include "siena_impl.h"
  48 #endif  /* EFSYS_OPT_SIENA */
  49
  50 #if EFSYS_OPT_HUNTINGTON
  51 #include "hunt_impl.h"
  52 #endif  /* EFSYS_OPT_HUNTINGTON */
  53
  54 #if EFSYS_OPT_MEDFORD
  55 #include "medford_impl.h"
  56 #endif  /* EFSYS_OPT_MEDFORD */
  57
  58 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  59 #include "ef10_impl.h"
  60 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  61
  62 #ifdef  __cplusplus
  63 extern "C" {
  64 #endif
  65
  66 #define EFX_MOD_MCDI            0x00000001
  67 #define EFX_MOD_PROBE           0x00000002
  68 #define EFX_MOD_NVRAM           0x00000004
  69 #define EFX_MOD_VPD             0x00000008
  70 #define EFX_MOD_NIC             0x00000010
  71 #define EFX_MOD_INTR            0x00000020
  72 #define EFX_MOD_EV              0x00000040
  73 #define EFX_MOD_RX              0x00000080
  74 #define EFX_MOD_TX              0x00000100
  75 #define EFX_MOD_PORT            0x00000200
  76 #define EFX_MOD_MON             0x00000400
  77 #define EFX_MOD_WOL             0x00000800
  78 #define EFX_MOD_FILTER          0x00001000
  79 #define EFX_MOD_LIC             0x00002000
  80
  81 #define EFX_RESET_PHY           0x00000001
  82 #define EFX_RESET_RXQ_ERR       0x00000002
  83 #define EFX_RESET_TXQ_ERR       0x00000004
  84
  85 typedef enum efx_mac_type_e {
  86         EFX_MAC_INVALID = 0,
  87         EFX_MAC_SIENA,
  88         EFX_MAC_HUNTINGTON,
  89         EFX_MAC_MEDFORD,
  90         EFX_MAC_NTYPES
  91 } efx_mac_type_t;
  92
  93 typedef struct efx_ev_ops_s {
  94         efx_rc_t        (*eevo_init)(efx_nic_t *);
  95         void            (*eevo_fini)(efx_nic_t *);
  96         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  97                                           efsys_mem_t *, size_t, uint32_t,
  98                                           efx_evq_t *);
  99         void            (*eevo_qdestroy)(efx_evq_t *);
 100         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
 101         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
 102         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 103 #if EFSYS_OPT_QSTATS
 104         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 105 #endif
 106 } efx_ev_ops_t;
 107
 108 typedef struct efx_tx_ops_s {
 109         efx_rc_t        (*etxo_init)(efx_nic_t *);
 110         void            (*etxo_fini)(efx_nic_t *);
 111         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 112                                         unsigned int, unsigned int,
 113                                         efsys_mem_t *, size_t,
 114                                         uint32_t, uint16_t,
 115                                         efx_evq_t *, efx_txq_t *,
 116                                         unsigned int *);
 117         void            (*etxo_qdestroy)(efx_txq_t *);
 118         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 119                                       unsigned int, unsigned int,
 120                                       unsigned int *);
 121         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 122         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 123         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 124         void            (*etxo_qenable)(efx_txq_t *);
 125         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 126         void            (*etxo_qpio_disable)(efx_txq_t *);
 127         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
 128                                            size_t);
 129         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 130                                            unsigned int *);
 131         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 132                                       unsigned int, unsigned int,
 133                                       unsigned int *);
 134         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 135                                                 size_t, boolean_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint8_t,
 139                                                 efx_desc_t *);
 140         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 141                                                 uint32_t, uint16_t,
 142                                                 efx_desc_t *, int);
 143         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 144                                                 efx_desc_t *);
 145 #if EFSYS_OPT_QSTATS
 146         void            (*etxo_qstats_update)(efx_txq_t *,
 147                                               efsys_stat_t *);
 148 #endif
 149 } efx_tx_ops_t;
 150
 151 typedef struct efx_rx_ops_s {
 152         efx_rc_t        (*erxo_init)(efx_nic_t *);
 153         void            (*erxo_fini)(efx_nic_t *);
 154 #if EFSYS_OPT_RX_SCATTER
 155         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 156 #endif
 157 #if EFSYS_OPT_RX_SCALE
 158         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 159                                                efx_rx_hash_type_t, boolean_t);
 160         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 161         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 162                                               size_t);
 163         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 164                                             uint8_t *);
 165 #endif /* EFSYS_OPT_RX_SCALE */
 166         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 167                                               uint16_t *);
 168         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 169                                       unsigned int, unsigned int,
 170                                       unsigned int);
 171         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 172         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 173         void            (*erxo_qenable)(efx_rxq_t *);
 174         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 175                                         unsigned int, efx_rxq_type_t,
 176                                         efsys_mem_t *, size_t, uint32_t,
 177                                         efx_evq_t *, efx_rxq_t *);
 178         void            (*erxo_qdestroy)(efx_rxq_t *);
 179 } efx_rx_ops_t;
 180
 181 typedef struct efx_mac_ops_s {
 182         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 183         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 184         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 185         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 186         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 187         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 188         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 189                                                       efx_rxq_t *, boolean_t);
 190         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 191 #if EFSYS_OPT_LOOPBACK
 192         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 193                                             efx_loopback_type_t);
 194 #endif  /* EFSYS_OPT_LOOPBACK */
 195 #if EFSYS_OPT_MAC_STATS
 196         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 197         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 198                                               uint16_t, boolean_t);
 199         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 200                                             efsys_stat_t *, uint32_t *);
 201 #endif  /* EFSYS_OPT_MAC_STATS */
 202 } efx_mac_ops_t;
 203
 204 typedef struct efx_phy_ops_s {
 205         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 206         efx_rc_t        (*epo_reset)(efx_nic_t *);
 207         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 208         efx_rc_t        (*epo_verify)(efx_nic_t *);
 209         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 210 #if EFSYS_OPT_PHY_STATS
 211         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 212                                             uint32_t *);
 213 #endif  /* EFSYS_OPT_PHY_STATS */
 214 #if EFSYS_OPT_BIST
 215         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 216         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 217         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 218                                          efx_bist_result_t *, uint32_t *,
 219                                          unsigned long *, size_t);
 220         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 221 #endif  /* EFSYS_OPT_BIST */
 222 } efx_phy_ops_t;
 223
 224 #if EFSYS_OPT_FILTER
 225 typedef struct efx_filter_ops_s {
 226         efx_rc_t        (*efo_init)(efx_nic_t *);
 227         void            (*efo_fini)(efx_nic_t *);
 228         efx_rc_t        (*efo_restore)(efx_nic_t *);
 229         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 230                                    boolean_t may_replace);
 231         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 232         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 233         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 234                                    boolean_t, boolean_t, boolean_t,
 235                                    uint8_t const *, uint32_t);
 236 } efx_filter_ops_t;
 237
 238 extern  __checkReturn   efx_rc_t
 239 efx_filter_reconfigure(
 240         __in                            efx_nic_t *enp,
 241         __in_ecount(6)                  uint8_t const *mac_addr,
 242         __in                            boolean_t all_unicst,
 243         __in                            boolean_t mulcst,
 244         __in                            boolean_t all_mulcst,
 245         __in                            boolean_t brdcst,
 246         __in_ecount(6*count)            uint8_t const *addrs,
 247         __in                            uint32_t count);
 248
 249 #endif /* EFSYS_OPT_FILTER */
 250
 251
 252 typedef struct efx_port_s {
 253         efx_mac_type_t          ep_mac_type;
 254         uint32_t                ep_phy_type;
 255         uint8_t                 ep_port;
 256         uint32_t                ep_mac_pdu;
 257         uint8_t                 ep_mac_addr[6];
 258         efx_link_mode_t         ep_link_mode;
 259         boolean_t               ep_all_unicst;
 260         boolean_t               ep_mulcst;
 261         boolean_t               ep_all_mulcst;
 262         boolean_t               ep_brdcst;
 263         unsigned int            ep_fcntl;
 264         boolean_t               ep_fcntl_autoneg;
 265         efx_oword_t             ep_multicst_hash[2];
 266         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 267                                                     EFX_MAC_MULTICAST_LIST_MAX];
 268         uint32_t                ep_mulcst_addr_count;
 269 #if EFSYS_OPT_LOOPBACK
 270         efx_loopback_type_t     ep_loopback_type;
 271         efx_link_mode_t         ep_loopback_link_mode;
 272 #endif  /* EFSYS_OPT_LOOPBACK */
 273 #if EFSYS_OPT_PHY_FLAGS
 274         uint32_t                ep_phy_flags;
 275 #endif  /* EFSYS_OPT_PHY_FLAGS */
 276 #if EFSYS_OPT_PHY_LED_CONTROL
 277         efx_phy_led_mode_t      ep_phy_led_mode;
 278 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 279         efx_phy_media_type_t    ep_fixed_port_type;
 280         efx_phy_media_type_t    ep_module_type;
 281         uint32_t                ep_adv_cap_mask;
 282         uint32_t                ep_lp_cap_mask;
 283         uint32_t                ep_default_adv_cap_mask;
 284         uint32_t                ep_phy_cap_mask;
 285         boolean_t               ep_mac_drain;
 286         boolean_t               ep_mac_stats_pending;
 287 #if EFSYS_OPT_BIST
 288         efx_bist_type_t         ep_current_bist;
 289 #endif
 290         const efx_mac_ops_t     *ep_emop;
 291         const efx_phy_ops_t     *ep_epop;
 292 } efx_port_t;
 293
 294 typedef struct efx_mon_ops_s {
 295         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 296 #if EFSYS_OPT_MON_STATS
 297         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 298                                             efx_mon_stat_value_t *);
 299 #endif  /* EFSYS_OPT_MON_STATS */
 300 } efx_mon_ops_t;
 301
 302 typedef struct efx_mon_s {
 303         efx_mon_type_t          em_type;
 304         const efx_mon_ops_t     *em_emop;
 305 } efx_mon_t;
 306
 307 typedef struct efx_intr_ops_s {
 308         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 309         void            (*eio_enable)(efx_nic_t *);
 310         void            (*eio_disable)(efx_nic_t *);
 311         void            (*eio_disable_unlocked)(efx_nic_t *);
 312         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 313         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 314         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 315                                  boolean_t *);
 316         void            (*eio_fatal)(efx_nic_t *);
 317         void            (*eio_fini)(efx_nic_t *);
 318 } efx_intr_ops_t;
 319
 320 typedef struct efx_intr_s {
 321         const efx_intr_ops_t    *ei_eiop;
 322         efsys_mem_t             *ei_esmp;
 323         efx_intr_type_t         ei_type;
 324         unsigned int            ei_level;
 325 } efx_intr_t;
 326
 327 typedef struct efx_nic_ops_s {
 328         efx_rc_t        (*eno_probe)(efx_nic_t *);
 329         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 330         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 331         efx_rc_t        (*eno_reset)(efx_nic_t *);
 332         efx_rc_t        (*eno_init)(efx_nic_t *);
 333         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 334         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 335                                         uint32_t *, size_t *);
 336 #if EFSYS_OPT_DIAG
 337         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 338 #endif  /* EFSYS_OPT_DIAG */
 339         void            (*eno_fini)(efx_nic_t *);
 340         void            (*eno_unprobe)(efx_nic_t *);
 341 } efx_nic_ops_t;
 342
 343 #ifndef EFX_TXQ_LIMIT_TARGET
 344 #define EFX_TXQ_LIMIT_TARGET 259
 345 #endif
 346 #ifndef EFX_RXQ_LIMIT_TARGET
 347 #define EFX_RXQ_LIMIT_TARGET 512
 348 #endif
 349 #ifndef EFX_TXQ_DC_SIZE
 350 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 351 #endif
 352 #ifndef EFX_RXQ_DC_SIZE
 353 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 354 #endif
 355
 356 #if EFSYS_OPT_FILTER
 357
 358 typedef struct siena_filter_spec_s {
 359         uint8_t         sfs_type;
 360         uint32_t        sfs_flags;
 361         uint32_t        sfs_dmaq_id;
 362         uint32_t        sfs_dword[3];
 363 } siena_filter_spec_t;
 364
 365 typedef enum siena_filter_type_e {
 366         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 367         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 368         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 369         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 370         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 371         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 372
 373         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 374         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 375         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 376         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 377         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 378         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 379
 380         EFX_SIENA_FILTER_NTYPES
 381 } siena_filter_type_t;
 382
 383 typedef enum siena_filter_tbl_id_e {
 384         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 385         EFX_SIENA_FILTER_TBL_RX_MAC,
 386         EFX_SIENA_FILTER_TBL_TX_IP,
 387         EFX_SIENA_FILTER_TBL_TX_MAC,
 388         EFX_SIENA_FILTER_NTBLS
 389 } siena_filter_tbl_id_t;
 390
 391 typedef struct siena_filter_tbl_s {
 392         int                     sft_size;       /* number of entries */
 393         int                     sft_used;       /* active count */
 394         uint32_t                *sft_bitmap;    /* active bitmap */
 395         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 396 } siena_filter_tbl_t;
 397
 398 typedef struct siena_filter_s {
 399         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 400         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 401 } siena_filter_t;
 402
 403 typedef struct efx_filter_s {
 404 #if EFSYS_OPT_SIENA
 405         siena_filter_t          *ef_siena_filter;
 406 #endif /* EFSYS_OPT_SIENA */
 407 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 408         ef10_filter_table_t     *ef_ef10_filter_table;
 409 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 410 } efx_filter_t;
 411
 412 extern                  void
 413 siena_filter_tbl_clear(
 414         __in            efx_nic_t *enp,
 415         __in            siena_filter_tbl_id_t tbl);
 416
 417 #endif  /* EFSYS_OPT_FILTER */
 418
 419 #if EFSYS_OPT_MCDI
 420
 421 typedef struct efx_mcdi_ops_s {
 422         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 423         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 424                                         void *, size_t);
 425         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 426         boolean_t       (*emco_poll_response)(efx_nic_t *);
 427         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 428         void            (*emco_fini)(efx_nic_t *);
 429         efx_rc_t        (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
 430 } efx_mcdi_ops_t;
 431
 432 typedef struct efx_mcdi_s {
 433         const efx_mcdi_ops_t            *em_emcop;
 434         const efx_mcdi_transport_t      *em_emtp;
 435         efx_mcdi_iface_t                em_emip;
 436 } efx_mcdi_t;
 437
 438 #endif /* EFSYS_OPT_MCDI */
 439
 440 #if EFSYS_OPT_NVRAM
 441 typedef struct efx_nvram_ops_s {
 442 #if EFSYS_OPT_DIAG
 443         efx_rc_t        (*envo_test)(efx_nic_t *);
 444 #endif  /* EFSYS_OPT_DIAG */
 445         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 446                                             uint32_t *);
 447         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 448         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 449         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 450                                             unsigned int, caddr_t, size_t);
 451         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 452                                             unsigned int, size_t);
 453         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 454                                             unsigned int, caddr_t, size_t);
 455         void            (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
 456         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 457                                             uint32_t *, uint16_t *);
 458         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 459                                             uint16_t *);
 460         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 461                                             caddr_t, size_t);
 462 } efx_nvram_ops_t;
 463 #endif /* EFSYS_OPT_NVRAM */
 464
 465 extern  __checkReturn           efx_rc_t
 466 efx_nvram_tlv_validate(
 467         __in                    efx_nic_t *enp,
 468         __in                    uint32_t partn,
 469         __in_bcount(partn_size) caddr_t partn_data,
 470         __in                    size_t partn_size);
 471
 472
 473 #if EFSYS_OPT_VPD
 474 typedef struct efx_vpd_ops_s {
 475         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 476         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 477         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 478         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 479         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 480         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 481                                         efx_vpd_value_t *);
 482         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 483                                         efx_vpd_value_t *);
 484         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 485                                         efx_vpd_value_t *, unsigned int *);
 486         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 487         void            (*evpdo_fini)(efx_nic_t *);
 488 } efx_vpd_ops_t;
 489 #endif  /* EFSYS_OPT_VPD */
 490
 491 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 492
 493         __checkReturn           efx_rc_t
 494 efx_mcdi_nvram_partitions(
 495         __in                    efx_nic_t *enp,
 496         __out_bcount(size)      caddr_t data,
 497         __in                    size_t size,
 498         __out                   unsigned int *npartnp);
 499
 500         __checkReturn           efx_rc_t
 501 efx_mcdi_nvram_metadata(
 502         __in                    efx_nic_t *enp,
 503         __in                    uint32_t partn,
 504         __out                   uint32_t *subtypep,
 505         __out_ecount(4)         uint16_t version[4],
 506         __out_bcount_opt(size)  char *descp,
 507         __in                    size_t size);
 508
 509         __checkReturn           efx_rc_t
 510 efx_mcdi_nvram_info(
 511         __in                    efx_nic_t *enp,
 512         __in                    uint32_t partn,
 513         __out_opt               size_t *sizep,
 514         __out_opt               uint32_t *addressp,
 515         __out_opt               uint32_t *erase_sizep,
 516         __out_opt               uint32_t *write_sizep);
 517
 518         __checkReturn           efx_rc_t
 519 efx_mcdi_nvram_update_start(
 520         __in                    efx_nic_t *enp,
 521         __in                    uint32_t partn);
 522
 523         __checkReturn           efx_rc_t
 524 efx_mcdi_nvram_read(
 525         __in                    efx_nic_t *enp,
 526         __in                    uint32_t partn,
 527         __in                    uint32_t offset,
 528         __out_bcount(size)      caddr_t data,
 529         __in                    size_t size,
 530         __in                    uint32_t mode);
 531
 532         __checkReturn           efx_rc_t
 533 efx_mcdi_nvram_erase(
 534         __in                    efx_nic_t *enp,
 535         __in                    uint32_t partn,
 536         __in                    uint32_t offset,
 537         __in                    size_t size);
 538
 539         __checkReturn           efx_rc_t
 540 efx_mcdi_nvram_write(
 541         __in                    efx_nic_t *enp,
 542         __in                    uint32_t partn,
 543         __in                    uint32_t offset,
 544         __out_bcount(size)      caddr_t data,
 545         __in                    size_t size);
 546
 547         __checkReturn           efx_rc_t
 548 efx_mcdi_nvram_update_finish(
 549         __in                    efx_nic_t *enp,
 550         __in                    uint32_t partn,
 551         __in                    boolean_t reboot);
 552
 553 #if EFSYS_OPT_DIAG
 554
 555         __checkReturn           efx_rc_t
 556 efx_mcdi_nvram_test(
 557         __in                    efx_nic_t *enp,
 558         __in                    uint32_t partn);
 559
 560 #endif  /* EFSYS_OPT_DIAG */
 561
 562 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 563
 564 #if EFSYS_OPT_LICENSING
 565
 566 typedef struct efx_lic_ops_s {
 567         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 568         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 569         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 570         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 571                                       size_t *, uint8_t *);
 572 } efx_lic_ops_t;
 573
 574 #endif
 575
 576 typedef struct efx_drv_cfg_s {
 577         uint32_t                edc_min_vi_count;
 578         uint32_t                edc_max_vi_count;
 579
 580         uint32_t                edc_max_piobuf_count;
 581         uint32_t                edc_pio_alloc_size;
 582 } efx_drv_cfg_t;
 583
 584 struct efx_nic_s {
 585         uint32_t                en_magic;
 586         efx_family_t            en_family;
 587         uint32_t                en_features;
 588         efsys_identifier_t      *en_esip;
 589         efsys_lock_t            *en_eslp;
 590         efsys_bar_t             *en_esbp;
 591         unsigned int            en_mod_flags;
 592         unsigned int            en_reset_flags;
 593         efx_nic_cfg_t           en_nic_cfg;
 594         efx_drv_cfg_t           en_drv_cfg;
 595         efx_port_t              en_port;
 596         efx_mon_t               en_mon;
 597         efx_intr_t              en_intr;
 598         uint32_t                en_ev_qcount;
 599         uint32_t                en_rx_qcount;
 600         uint32_t                en_tx_qcount;
 601         const efx_nic_ops_t     *en_enop;
 602         const efx_ev_ops_t      *en_eevop;
 603         const efx_tx_ops_t      *en_etxop;
 604         const efx_rx_ops_t      *en_erxop;
 605 #if EFSYS_OPT_FILTER
 606         efx_filter_t            en_filter;
 607         const efx_filter_ops_t  *en_efop;
 608 #endif  /* EFSYS_OPT_FILTER */
 609 #if EFSYS_OPT_MCDI
 610         efx_mcdi_t              en_mcdi;
 611 #endif  /* EFSYS_OPT_MCDI */
 612 #if EFSYS_OPT_NVRAM
 613         efx_nvram_type_t        en_nvram_locked;
 614         const efx_nvram_ops_t   *en_envop;
 615 #endif  /* EFSYS_OPT_NVRAM */
 616 #if EFSYS_OPT_VPD
 617         const efx_vpd_ops_t     *en_evpdop;
 618 #endif  /* EFSYS_OPT_VPD */
 619 #if EFSYS_OPT_RX_SCALE
 620         efx_rx_hash_support_t   en_hash_support;
 621         efx_rx_scale_support_t  en_rss_support;
 622         uint32_t                en_rss_context;
 623 #endif  /* EFSYS_OPT_RX_SCALE */
 624         uint32_t                en_vport_id;
 625 #if EFSYS_OPT_LICENSING
 626         const efx_lic_ops_t     *en_elop;
 627 #endif
 628         union {
 629 #if EFSYS_OPT_SIENA
 630                 struct {
 631 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 632                         unsigned int            enu_partn_mask;
 633 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 634 #if EFSYS_OPT_VPD
 635                         caddr_t                 enu_svpd;
 636                         size_t                  enu_svpd_length;
 637 #endif  /* EFSYS_OPT_VPD */
 638                         int                     enu_unused;
 639                 } siena;
 640 #endif  /* EFSYS_OPT_SIENA */
 641                 int     enu_unused;
 642         } en_u;
 643 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 644         union en_arch {
 645                 struct {
 646                         int                     ena_vi_base;
 647                         int                     ena_vi_count;
 648                         int                     ena_vi_shift;
 649 #if EFSYS_OPT_VPD
 650                         caddr_t                 ena_svpd;
 651                         size_t                  ena_svpd_length;
 652 #endif  /* EFSYS_OPT_VPD */
 653                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 654                         uint32_t                ena_piobuf_count;
 655                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 656                         uint32_t                ena_pio_write_vi_base;
 657                         /* Memory BAR mapping regions */
 658                         uint32_t                ena_uc_mem_map_offset;
 659                         size_t                  ena_uc_mem_map_size;
 660                         uint32_t                ena_wc_mem_map_offset;
 661                         size_t                  ena_wc_mem_map_size;
 662                 } ef10;
 663         } en_arch;
 664 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 665 };
 666
 667
 668 #define EFX_NIC_MAGIC   0x02121996
 669
 670 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 671     const efx_ev_callbacks_t *, void *);
 672
 673 typedef struct efx_evq_rxq_state_s {
 674         unsigned int                    eers_rx_read_ptr;
 675         unsigned int                    eers_rx_mask;
 676 } efx_evq_rxq_state_t;
 677
 678 struct efx_evq_s {
 679         uint32_t                        ee_magic;
 680         efx_nic_t                       *ee_enp;
 681         unsigned int                    ee_index;
 682         unsigned int                    ee_mask;
 683         efsys_mem_t                     *ee_esmp;
 684 #if EFSYS_OPT_QSTATS
 685         uint32_t                        ee_stat[EV_NQSTATS];
 686 #endif  /* EFSYS_OPT_QSTATS */
 687
 688         efx_ev_handler_t                ee_rx;
 689         efx_ev_handler_t                ee_tx;
 690         efx_ev_handler_t                ee_driver;
 691         efx_ev_handler_t                ee_global;
 692         efx_ev_handler_t                ee_drv_gen;
 693 #if EFSYS_OPT_MCDI
 694         efx_ev_handler_t                ee_mcdi;
 695 #endif  /* EFSYS_OPT_MCDI */
 696
 697         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 698 };
 699
 700 #define EFX_EVQ_MAGIC   0x08081997
 701
 702 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 703
 704 struct efx_rxq_s {
 705         uint32_t                        er_magic;
 706         efx_nic_t                       *er_enp;
 707         efx_evq_t                       *er_eep;
 708         unsigned int                    er_index;
 709         unsigned int                    er_label;
 710         unsigned int                    er_mask;
 711         efsys_mem_t                     *er_esmp;
 712 };
 713
 714 #define EFX_RXQ_MAGIC   0x15022005
 715
 716 struct efx_txq_s {
 717         uint32_t                        et_magic;
 718         efx_nic_t                       *et_enp;
 719         unsigned int                    et_index;
 720         unsigned int                    et_mask;
 721         efsys_mem_t                     *et_esmp;
 722 #if EFSYS_OPT_HUNTINGTON
 723         uint32_t                        et_pio_bufnum;
 724         uint32_t                        et_pio_blknum;
 725         uint32_t                        et_pio_write_offset;
 726         uint32_t                        et_pio_offset;
 727         size_t                          et_pio_size;
 728 #endif
 729 #if EFSYS_OPT_QSTATS
 730         uint32_t                        et_stat[TX_NQSTATS];
 731 #endif  /* EFSYS_OPT_QSTATS */
 732 };
 733
 734 #define EFX_TXQ_MAGIC   0x05092005
 735
 736 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 737         do {                                                            \
 738                 (_dst)[0] = (_src)[0];                                  \
 739                 (_dst)[1] = (_src)[1];                                  \
 740                 (_dst)[2] = (_src)[2];                                  \
 741                 (_dst)[3] = (_src)[3];                                  \
 742                 (_dst)[4] = (_src)[4];                                  \
 743                 (_dst)[5] = (_src)[5];                                  \
 744         _NOTE(CONSTANTCONDITION)                                        \
 745         } while (B_FALSE)
 746
 747 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 748         do {                                                            \
 749                 uint16_t *_d = (uint16_t *)(_dst);                      \
 750                 _d[0] = 0xffff;                                         \
 751                 _d[1] = 0xffff;                                         \
 752                 _d[2] = 0xffff;                                         \
 753         _NOTE(CONSTANTCONDITION)                                        \
 754         } while (B_FALSE)
 755
 756 #if EFSYS_OPT_CHECK_REG
 757 #define EFX_CHECK_REG(_enp, _reg)                                       \
 758         do {                                                            \
 759                 const char *name = #_reg;                               \
 760                 char min = name[4];                                     \
 761                 char max = name[5];                                     \
 762                 char rev;                                               \
 763                                                                         \
 764                 switch ((_enp)->en_family) {                            \
 765                 case EFX_FAMILY_SIENA:                                  \
 766                         rev = 'C';                                      \
 767                         break;                                          \
 768                                                                         \
 769                 case EFX_FAMILY_HUNTINGTON:                             \
 770                         rev = 'D';                                      \
 771                         break;                                          \
 772                                                                         \
 773                 case EFX_FAMILY_MEDFORD:                                \
 774                         rev = 'E';                                      \
 775                         break;                                          \
 776                                                                         \
 777                 default:                                                \
 778                         rev = '?';                                      \
 779                         break;                                          \
 780                 }                                                       \
 781                                                                         \
 782                 EFSYS_ASSERT3S(rev, >=, min);                           \
 783                 EFSYS_ASSERT3S(rev, <=, max);                           \
 784                                                                         \
 785         _NOTE(CONSTANTCONDITION)                                        \
 786         } while (B_FALSE)
 787 #else
 788 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 789         _NOTE(CONSTANTCONDITION)                                        \
 790         } while(B_FALSE)
 791 #endif
 792
 793 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 794         do {                                                            \
 795                 EFX_CHECK_REG((_enp), (_reg));                          \
 796                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 797                     (_edp), (_lock));                                   \
 798                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 799                     uint32_t, _reg ## _OFST,                            \
 800                     uint32_t, (_edp)->ed_u32[0]);                       \
 801         _NOTE(CONSTANTCONDITION)                                        \
 802         } while (B_FALSE)
 803
 804 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 805         do {                                                            \
 806                 EFX_CHECK_REG((_enp), (_reg));                          \
 807                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 808                     uint32_t, _reg ## _OFST,                            \
 809                     uint32_t, (_edp)->ed_u32[0]);                       \
 810                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 811                     (_edp), (_lock));                                   \
 812         _NOTE(CONSTANTCONDITION)                                        \
 813         } while (B_FALSE)
 814
 815 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 816         do {                                                            \
 817                 EFX_CHECK_REG((_enp), (_reg));                          \
 818                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 819                     (_eqp));                                            \
 820                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 821                     uint32_t, _reg ## _OFST,                            \
 822                     uint32_t, (_eqp)->eq_u32[1],                        \
 823                     uint32_t, (_eqp)->eq_u32[0]);                       \
 824         _NOTE(CONSTANTCONDITION)                                        \
 825         } while (B_FALSE)
 826
 827 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 828         do {                                                            \
 829                 EFX_CHECK_REG((_enp), (_reg));                          \
 830                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 831                     uint32_t, _reg ## _OFST,                            \
 832                     uint32_t, (_eqp)->eq_u32[1],                        \
 833                     uint32_t, (_eqp)->eq_u32[0]);                       \
 834                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 835                     (_eqp));                                            \
 836         _NOTE(CONSTANTCONDITION)                                        \
 837         } while (B_FALSE)
 838
 839 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 840         do {                                                            \
 841                 EFX_CHECK_REG((_enp), (_reg));                          \
 842                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 843                     (_eop), B_TRUE);                                    \
 844                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 845                     uint32_t, _reg ## _OFST,                            \
 846                     uint32_t, (_eop)->eo_u32[3],                        \
 847                     uint32_t, (_eop)->eo_u32[2],                        \
 848                     uint32_t, (_eop)->eo_u32[1],                        \
 849                     uint32_t, (_eop)->eo_u32[0]);                       \
 850         _NOTE(CONSTANTCONDITION)                                        \
 851         } while (B_FALSE)
 852
 853 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 854         do {                                                            \
 855                 EFX_CHECK_REG((_enp), (_reg));                          \
 856                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 857                     uint32_t, _reg ## _OFST,                            \
 858                     uint32_t, (_eop)->eo_u32[3],                        \
 859                     uint32_t, (_eop)->eo_u32[2],                        \
 860                     uint32_t, (_eop)->eo_u32[1],                        \
 861                     uint32_t, (_eop)->eo_u32[0]);                       \
 862                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 863                     (_eop), B_TRUE);                                    \
 864         _NOTE(CONSTANTCONDITION)                                        \
 865         } while (B_FALSE)
 866
 867 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 868         do {                                                            \
 869                 EFX_CHECK_REG((_enp), (_reg));                          \
 870                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 871                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 872                     (_edp), (_lock));                                   \
 873                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 874                     uint32_t, (_index),                                 \
 875                     uint32_t, _reg ## _OFST,                            \
 876                     uint32_t, (_edp)->ed_u32[0]);                       \
 877         _NOTE(CONSTANTCONDITION)                                        \
 878         } while (B_FALSE)
 879
 880 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 881         do {                                                            \
 882                 EFX_CHECK_REG((_enp), (_reg));                          \
 883                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 884                     uint32_t, (_index),                                 \
 885                     uint32_t, _reg ## _OFST,                            \
 886                     uint32_t, (_edp)->ed_u32[0]);                       \
 887                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 888                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 889                     (_edp), (_lock));                                   \
 890         _NOTE(CONSTANTCONDITION)                                        \
 891         } while (B_FALSE)
 892
 893 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 894         do {                                                            \
 895                 EFX_CHECK_REG((_enp), (_reg));                          \
 896                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 897                     uint32_t, (_index),                                 \
 898                     uint32_t, _reg ## _OFST,                            \
 899                     uint32_t, (_edp)->ed_u32[0]);                       \
 900                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 901                     (_reg ## _OFST +                                    \
 902                     (2 * sizeof (efx_dword_t)) +                        \
 903                     ((_index) * _reg ## _STEP)),                        \
 904                     (_edp), (_lock));                                   \
 905         _NOTE(CONSTANTCONDITION)                                        \
 906         } while (B_FALSE)
 907
 908 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 909         do {                                                            \
 910                 EFX_CHECK_REG((_enp), (_reg));                          \
 911                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 912                     uint32_t, (_index),                                 \
 913                     uint32_t, _reg ## _OFST,                            \
 914                     uint32_t, (_edp)->ed_u32[0]);                       \
 915                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 916                     (_reg ## _OFST +                                    \
 917                     (3 * sizeof (efx_dword_t)) +                        \
 918                     ((_index) * _reg ## _STEP)),                        \
 919                     (_edp), (_lock));                                   \
 920         _NOTE(CONSTANTCONDITION)                                        \
 921         } while (B_FALSE)
 922
 923 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 924         do {                                                            \
 925                 EFX_CHECK_REG((_enp), (_reg));                          \
 926                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 927                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 928                     (_eqp));                                            \
 929                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 930                     uint32_t, (_index),                                 \
 931                     uint32_t, _reg ## _OFST,                            \
 932                     uint32_t, (_eqp)->eq_u32[1],                        \
 933                     uint32_t, (_eqp)->eq_u32[0]);                       \
 934         _NOTE(CONSTANTCONDITION)                                        \
 935         } while (B_FALSE)
 936
 937 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 938         do {                                                            \
 939                 EFX_CHECK_REG((_enp), (_reg));                          \
 940                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 941                     uint32_t, (_index),                                 \
 942                     uint32_t, _reg ## _OFST,                            \
 943                     uint32_t, (_eqp)->eq_u32[1],                        \
 944                     uint32_t, (_eqp)->eq_u32[0]);                       \
 945                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 946                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 947                     (_eqp));                                            \
 948         _NOTE(CONSTANTCONDITION)                                        \
 949         } while (B_FALSE)
 950
 951 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 952         do {                                                            \
 953                 EFX_CHECK_REG((_enp), (_reg));                          \
 954                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 955                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 956                     (_eop), (_lock));                                   \
 957                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 958                     uint32_t, (_index),                                 \
 959                     uint32_t, _reg ## _OFST,                            \
 960                     uint32_t, (_eop)->eo_u32[3],                        \
 961                     uint32_t, (_eop)->eo_u32[2],                        \
 962                     uint32_t, (_eop)->eo_u32[1],                        \
 963                     uint32_t, (_eop)->eo_u32[0]);                       \
 964         _NOTE(CONSTANTCONDITION)                                        \
 965         } while (B_FALSE)
 966
 967 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 968         do {                                                            \
 969                 EFX_CHECK_REG((_enp), (_reg));                          \
 970                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 971                     uint32_t, (_index),                                 \
 972                     uint32_t, _reg ## _OFST,                            \
 973                     uint32_t, (_eop)->eo_u32[3],                        \
 974                     uint32_t, (_eop)->eo_u32[2],                        \
 975                     uint32_t, (_eop)->eo_u32[1],                        \
 976                     uint32_t, (_eop)->eo_u32[0]);                       \
 977                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 978                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 979                     (_eop), (_lock));                                   \
 980         _NOTE(CONSTANTCONDITION)                                        \
 981         } while (B_FALSE)
 982
 983 /*
 984  * Allow drivers to perform optimised 128-bit doorbell writes.
 985  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 986  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
 987  * the need for locking in the host, and are the only ones known to be safe to
 988  * use 128-bites write with.
 989  */
 990 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
 991         do {                                                            \
 992                 EFX_CHECK_REG((_enp), (_reg));                          \
 993                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
 994                     const char *,                                       \
 995                     #_reg,                                              \
 996                     uint32_t, (_index),                                 \
 997                     uint32_t, _reg ## _OFST,                            \
 998                     uint32_t, (_eop)->eo_u32[3],                        \
 999                     uint32_t, (_eop)->eo_u32[2],                        \
1000                     uint32_t, (_eop)->eo_u32[1],                        \
1001                     uint32_t, (_eop)->eo_u32[0]);                       \
1002                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1003                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1004                     (_eop));                                            \
1005         _NOTE(CONSTANTCONDITION)                                        \
1006         } while (B_FALSE)
1007
1008 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1009         do {                                                            \
1010                 unsigned int _new = (_wptr);                            \
1011                 unsigned int _old = (_owptr);                           \
1012                                                                         \
1013                 if ((_new) >= (_old))                                   \
1014                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1015                             (_old) * sizeof (efx_desc_t),               \
1016                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1017                 else                                                    \
1018                         /*                                              \
1019                          * It is cheaper to sync entire map than sync   \
1020                          * two parts especially when offset/size are    \
1021                          * ignored and entire map is synced in any case.\
1022                          */                                             \
1023                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1024                             0,                                          \
1025                             (_entries) * sizeof (efx_desc_t));          \
1026         _NOTE(CONSTANTCONDITION)                                        \
1027         } while (B_FALSE)
1028
1029 extern  __checkReturn   efx_rc_t
1030 efx_nic_biu_test(
1031         __in            efx_nic_t *enp);
1032
1033 extern  __checkReturn   efx_rc_t
1034 efx_mac_select(
1035         __in            efx_nic_t *enp);
1036
1037 extern  void
1038 efx_mac_multicast_hash_compute(
1039         __in_ecount(6*count)            uint8_t const *addrs,
1040         __in                            int count,
1041         __out                           efx_oword_t *hash_low,
1042         __out                           efx_oword_t *hash_high);
1043
1044 extern  __checkReturn   efx_rc_t
1045 efx_phy_probe(
1046         __in            efx_nic_t *enp);
1047
1048 extern                  void
1049 efx_phy_unprobe(
1050         __in            efx_nic_t *enp);
1051
1052 #if EFSYS_OPT_VPD
1053
1054 /* VPD utility functions */
1055
1056 extern  __checkReturn           efx_rc_t
1057 efx_vpd_hunk_length(
1058         __in_bcount(size)       caddr_t data,
1059         __in                    size_t size,
1060         __out                   size_t *lengthp);
1061
1062 extern  __checkReturn           efx_rc_t
1063 efx_vpd_hunk_verify(
1064         __in_bcount(size)       caddr_t data,
1065         __in                    size_t size,
1066         __out_opt               boolean_t *cksummedp);
1067
1068 extern  __checkReturn           efx_rc_t
1069 efx_vpd_hunk_reinit(
1070         __in_bcount(size)       caddr_t data,
1071         __in                    size_t size,
1072         __in                    boolean_t wantpid);
1073
1074 extern  __checkReturn           efx_rc_t
1075 efx_vpd_hunk_get(
1076         __in_bcount(size)       caddr_t data,
1077         __in                    size_t size,
1078         __in                    efx_vpd_tag_t tag,
1079         __in                    efx_vpd_keyword_t keyword,
1080         __out                   unsigned int *payloadp,
1081         __out                   uint8_t *paylenp);
1082
1083 extern  __checkReturn                   efx_rc_t
1084 efx_vpd_hunk_next(
1085         __in_bcount(size)               caddr_t data,
1086         __in                            size_t size,
1087         __out                           efx_vpd_tag_t *tagp,
1088         __out                           efx_vpd_keyword_t *keyword,
1089         __out_opt                       unsigned int *payloadp,
1090         __out_opt                       uint8_t *paylenp,
1091         __inout                         unsigned int *contp);
1092
1093 extern  __checkReturn           efx_rc_t
1094 efx_vpd_hunk_set(
1095         __in_bcount(size)       caddr_t data,
1096         __in                    size_t size,
1097         __in                    efx_vpd_value_t *evvp);
1098
1099 #endif  /* EFSYS_OPT_VPD */
1100
1101 #if EFSYS_OPT_DIAG
1102
1103 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1104
1105 typedef struct efx_register_set_s {
1106         unsigned int            address;
1107         unsigned int            step;
1108         unsigned int            rows;
1109         efx_oword_t             mask;
1110 } efx_register_set_t;
1111
1112 extern  __checkReturn   efx_rc_t
1113 efx_nic_test_registers(
1114         __in            efx_nic_t *enp,
1115         __in            efx_register_set_t *rsp,
1116         __in            size_t count);
1117
1118 extern  __checkReturn   efx_rc_t
1119 efx_nic_test_tables(
1120         __in            efx_nic_t *enp,
1121         __in            efx_register_set_t *rsp,
1122         __in            efx_pattern_type_t pattern,
1123         __in            size_t count);
1124
1125 #endif  /* EFSYS_OPT_DIAG */
1126
1127 #if EFSYS_OPT_MCDI
1128
1129 extern  __checkReturn           efx_rc_t
1130 efx_mcdi_set_workaround(
1131         __in                    efx_nic_t *enp,
1132         __in                    uint32_t type,
1133         __in                    boolean_t enabled,
1134         __out_opt               uint32_t *flagsp);
1135
1136 extern  __checkReturn           efx_rc_t
1137 efx_mcdi_get_workarounds(
1138         __in                    efx_nic_t *enp,
1139         __out_opt               uint32_t *implementedp,
1140         __out_opt               uint32_t *enabledp);
1141
1142 #endif /* EFSYS_OPT_MCDI */
1143
1144 #ifdef  __cplusplus
1145 }
1146 #endif
1147
1148 #endif  /* _SYS_EFX_IMPL_H */