2 * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef _SYS_EFX_IMPL_H
29 #define _SYS_EFX_IMPL_H
36 #include "falcon_impl.h"
37 #endif /* EFSYS_OPT_FALCON */
40 #include "siena_impl.h"
41 #endif /* EFSYS_OPT_SIENA */
47 #define EFX_MOD_MCDI 0x00000001
48 #define EFX_MOD_PROBE 0x00000002
49 #define EFX_MOD_NVRAM 0x00000004
50 #define EFX_MOD_VPD 0x00000008
51 #define EFX_MOD_NIC 0x00000010
52 #define EFX_MOD_INTR 0x00000020
53 #define EFX_MOD_EV 0x00000040
54 #define EFX_MOD_RX 0x00000080
55 #define EFX_MOD_TX 0x00000100
56 #define EFX_MOD_PORT 0x00000200
57 #define EFX_MOD_MON 0x00000400
58 #define EFX_MOD_WOL 0x00000800
59 #define EFX_MOD_FILTER 0x00001000
61 #define EFX_RESET_MAC 0x00000001
62 #define EFX_RESET_PHY 0x00000002
64 typedef enum efx_mac_type_e {
72 typedef struct efx_mac_ops_s {
73 int (*emo_reset)(efx_nic_t *); /* optional */
74 int (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
75 int (*emo_up)(efx_nic_t *, boolean_t *);
76 int (*emo_reconfigure)(efx_nic_t *);
77 #if EFSYS_OPT_LOOPBACK
78 int (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
80 #endif /* EFSYS_OPT_LOOPBACK */
81 #if EFSYS_OPT_MAC_STATS
82 int (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
83 int (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
85 int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
86 efsys_stat_t *, uint32_t *);
87 #endif /* EFSYS_OPT_MAC_STATS */
90 typedef struct efx_phy_ops_s {
91 int (*epo_power)(efx_nic_t *, boolean_t); /* optional */
92 int (*epo_reset)(efx_nic_t *);
93 int (*epo_reconfigure)(efx_nic_t *);
94 int (*epo_verify)(efx_nic_t *);
95 int (*epo_uplink_check)(efx_nic_t *,
96 boolean_t *); /* optional */
97 int (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
98 unsigned int *, uint32_t *);
99 int (*epo_oui_get)(efx_nic_t *, uint32_t *);
100 #if EFSYS_OPT_PHY_STATS
101 int (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
103 #endif /* EFSYS_OPT_PHY_STATS */
104 #if EFSYS_OPT_PHY_PROPS
106 const char __cs *(*epo_prop_name)(efx_nic_t *, unsigned int);
107 #endif /* EFSYS_OPT_PHY_PROPS */
108 int (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
110 int (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
111 #endif /* EFSYS_OPT_PHY_PROPS */
112 #if EFSYS_OPT_PHY_BIST
113 int (*epo_bist_start)(efx_nic_t *, efx_phy_bist_type_t);
114 int (*epo_bist_poll)(efx_nic_t *, efx_phy_bist_type_t,
115 efx_phy_bist_result_t *, uint32_t *,
116 unsigned long *, size_t);
117 void (*epo_bist_stop)(efx_nic_t *, efx_phy_bist_type_t);
118 #endif /* EFSYS_OPT_PHY_BIST */
121 typedef struct efx_port_s {
122 efx_mac_type_t ep_mac_type;
123 uint32_t ep_phy_type;
126 uint8_t ep_mac_addr[6];
127 efx_link_mode_t ep_link_mode;
130 unsigned int ep_fcntl;
131 boolean_t ep_fcntl_autoneg;
132 efx_oword_t ep_multicst_hash[2];
133 #if EFSYS_OPT_LOOPBACK
134 efx_loopback_type_t ep_loopback_type;
135 efx_link_mode_t ep_loopback_link_mode;
136 #endif /* EFSYS_OPT_LOOPBACK */
137 #if EFSYS_OPT_PHY_FLAGS
138 uint32_t ep_phy_flags;
139 #endif /* EFSYS_OPT_PHY_FLAGS */
140 #if EFSYS_OPT_PHY_LED_CONTROL
141 efx_phy_led_mode_t ep_phy_led_mode;
142 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
143 efx_phy_media_type_t ep_fixed_port_type;
144 efx_phy_media_type_t ep_module_type;
145 uint32_t ep_adv_cap_mask;
146 uint32_t ep_lp_cap_mask;
147 uint32_t ep_default_adv_cap_mask;
148 uint32_t ep_phy_cap_mask;
149 #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
152 unsigned int bug10934_count;
155 unsigned int bug17190_count;
159 boolean_t ep_mac_poll_needed; /* falcon only */
160 boolean_t ep_mac_up; /* falcon only */
161 uint32_t ep_fwver; /* falcon only */
162 boolean_t ep_mac_drain;
163 boolean_t ep_mac_stats_pending;
164 #if EFSYS_OPT_PHY_BIST
165 efx_phy_bist_type_t ep_current_bist;
167 efx_mac_ops_t *ep_emop;
168 efx_phy_ops_t *ep_epop;
171 typedef struct efx_mon_ops_s {
172 int (*emo_reset)(efx_nic_t *);
173 int (*emo_reconfigure)(efx_nic_t *);
174 #if EFSYS_OPT_MON_STATS
175 int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
176 efx_mon_stat_value_t *);
177 #endif /* EFSYS_OPT_MON_STATS */
180 typedef struct efx_mon_s {
181 efx_mon_type_t em_type;
182 efx_mon_ops_t *em_emop;
185 typedef struct efx_intr_s {
186 efx_intr_type_t ei_type;
187 efsys_mem_t *ei_esmp;
188 unsigned int ei_level;
191 typedef struct efx_nic_ops_s {
192 int (*eno_probe)(efx_nic_t *);
193 int (*eno_reset)(efx_nic_t *);
194 int (*eno_init)(efx_nic_t *);
196 int (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
197 int (*eno_register_test)(efx_nic_t *);
198 #endif /* EFSYS_OPT_DIAG */
199 void (*eno_fini)(efx_nic_t *);
200 void (*eno_unprobe)(efx_nic_t *);
203 #ifndef EFX_TXQ_LIMIT_TARGET
204 # define EFX_TXQ_LIMIT_TARGET 259
206 #ifndef EFX_RXQ_LIMIT_TARGET
207 # define EFX_RXQ_LIMIT_TARGET 512
209 #ifndef EFX_TXQ_DC_SIZE
210 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
212 #ifndef EFX_RXQ_DC_SIZE
213 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
218 typedef enum efx_filter_type_e {
219 EFX_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
220 EFX_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
221 EFX_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
222 EFX_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
225 EFX_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
226 EFX_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
228 EFX_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
229 EFX_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
230 EFX_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
231 EFX_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
233 EFX_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
234 EFX_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
235 #endif /* EFSYS_OPT_SIENA */
240 typedef enum efx_filter_tbl_id_e {
241 EFX_FILTER_TBL_RX_IP = 0,
242 EFX_FILTER_TBL_RX_MAC,
243 EFX_FILTER_TBL_TX_IP,
244 EFX_FILTER_TBL_TX_MAC,
246 } efx_filter_tbl_id_t;
248 typedef struct efx_filter_tbl_s {
249 int eft_size; /* number of entries */
250 int eft_used; /* active count */
251 uint32_t *eft_bitmap; /* active bitmap */
252 efx_filter_spec_t *eft_spec; /* array of saved specs */
255 typedef struct efx_filter_s {
256 efx_filter_tbl_t ef_tbl[EFX_FILTER_NTBLS];
257 unsigned int ef_depth[EFX_FILTER_NTYPES];
261 extern __checkReturn int
262 efx_filter_insert_filter(
264 __in efx_filter_spec_t *spec,
265 __in boolean_t replace);
267 extern __checkReturn int
268 efx_filter_remove_filter(
270 __in efx_filter_spec_t *spec);
273 efx_filter_remove_index(
274 __inout efx_nic_t *enp,
275 __in efx_filter_type_t type,
276 __in int filter_idx);
279 efx_filter_redirect_index(
280 __inout efx_nic_t *enp,
281 __in efx_filter_type_t type,
282 __in int filter_index,
285 extern __checkReturn int
286 efx_filter_clear_tbl(
288 __in efx_filter_tbl_id_t tbl);
290 #endif /* EFSYS_OPT_FILTER */
293 typedef struct efx_nvram_ops_s {
295 int (*envo_test)(efx_nic_t *);
296 #endif /* EFSYS_OPT_DIAG */
297 int (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
298 int (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
299 uint32_t *, uint16_t *);
300 int (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
301 int (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
302 unsigned int, caddr_t, size_t);
303 int (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
304 int (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
305 unsigned int, caddr_t, size_t);
306 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
307 int (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, uint16_t *);
310 #endif /* EFSYS_OPT_NVRAM */
313 typedef struct efx_vpd_ops_s {
314 int (*evpdo_init)(efx_nic_t *);
315 int (*evpdo_size)(efx_nic_t *, size_t *);
316 int (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
317 int (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
318 int (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
319 int (*evpdo_get)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *);
320 int (*evpdo_set)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *);
321 int (*evpdo_next)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *,
323 int (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
324 void (*evpdo_fini)(efx_nic_t *);
326 #endif /* EFSYS_OPT_VPD */
330 efx_family_t en_family;
331 uint32_t en_features;
332 efsys_identifier_t *en_esip;
333 efsys_lock_t *en_eslp;
334 efsys_bar_t *en_esbp;
335 unsigned int en_mod_flags;
336 unsigned int en_reset_flags;
337 efx_nic_cfg_t en_nic_cfg;
341 uint32_t en_ev_qcount;
342 uint32_t en_rx_qcount;
343 uint32_t en_tx_qcount;
344 efx_nic_ops_t *en_enop;
346 efx_filter_t en_filter;
347 #endif /* EFSYS_OPT_FILTER */
349 efx_nvram_type_t en_nvram_locked;
350 efx_nvram_ops_t *en_envop;
351 #endif /* EFSYS_OPT_NVRAM */
353 efx_vpd_ops_t *en_evpdop;
354 #endif /* EFSYS_OPT_VPD */
358 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
359 falcon_i2c_t enu_fip;
360 boolean_t enu_i2c_locked;
361 #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
362 const uint8_t *enu_forced_cfg;
363 #endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
364 uint8_t enu_mon_devid;
365 #if EFSYS_OPT_PCIE_TUNE
366 unsigned int enu_nlanes;
367 #endif /* EFSYS_OPT_PCIE_TUNE */
368 uint16_t enu_board_rev;
369 boolean_t enu_internal_sram;
370 uint8_t enu_sram_num_bank;
371 uint8_t enu_sram_bank_size;
373 #endif /* EFSYS_OPT_FALCON */
377 efx_mcdi_iface_t enu_mip;
378 #endif /* EFSYS_OPT_MCDI */
379 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
380 unsigned int enu_partn_mask;
381 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
384 size_t enu_svpd_length;
385 #endif /* EFSYS_OPT_VPD */
387 #endif /* EFSYS_OPT_SIENA */
392 #define EFX_NIC_MAGIC 0x02121996
394 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
395 const efx_ev_callbacks_t *, void *);
400 unsigned int ee_index;
401 unsigned int ee_mask;
402 efsys_mem_t *ee_esmp;
404 uint32_t ee_stat[EV_NQSTATS];
405 #endif /* EFSYS_OPT_QSTATS */
406 efx_ev_handler_t ee_handler[1 << FSF_AZ_EV_CODE_WIDTH];
409 #define EFX_EVQ_MAGIC 0x08081997
411 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
412 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
417 unsigned int er_index;
418 unsigned int er_mask;
419 efsys_mem_t *er_esmp;
422 #define EFX_RXQ_MAGIC 0x15022005
427 unsigned int et_index;
428 unsigned int et_mask;
429 efsys_mem_t *et_esmp;
431 uint32_t et_stat[TX_NQSTATS];
432 #endif /* EFSYS_OPT_QSTATS */
435 #define EFX_TXQ_MAGIC 0x05092005
437 #define EFX_MAC_ADDR_COPY(_dst, _src) \
439 (_dst)[0] = (_src)[0]; \
440 (_dst)[1] = (_src)[1]; \
441 (_dst)[2] = (_src)[2]; \
442 (_dst)[3] = (_src)[3]; \
443 (_dst)[4] = (_src)[4]; \
444 (_dst)[5] = (_src)[5]; \
445 _NOTE(CONSTANTCONDITION) \
448 #if EFSYS_OPT_CHECK_REG
449 #define EFX_CHECK_REG(_enp, _reg) \
451 const char __cs *name = #_reg; \
452 char min = name[4]; \
453 char max = name[5]; \
456 switch ((_enp)->en_family) { \
457 case EFX_FAMILY_FALCON: \
461 case EFX_FAMILY_SIENA: \
470 EFSYS_ASSERT3S(rev, >=, min); \
471 EFSYS_ASSERT3S(rev, <=, max); \
473 _NOTE(CONSTANTCONDITION) \
476 #define EFX_CHECK_REG(_enp, _reg) do { \
477 _NOTE(CONSTANTCONDITION) \
481 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
483 EFX_CHECK_REG((_enp), (_reg)); \
484 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
486 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
487 uint32_t, _reg ## _OFST, \
488 uint32_t, (_edp)->ed_u32[0]); \
489 _NOTE(CONSTANTCONDITION) \
492 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
494 EFX_CHECK_REG((_enp), (_reg)); \
495 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
496 uint32_t, _reg ## _OFST, \
497 uint32_t, (_edp)->ed_u32[0]); \
498 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
500 _NOTE(CONSTANTCONDITION) \
503 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
505 EFX_CHECK_REG((_enp), (_reg)); \
506 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
508 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
509 uint32_t, _reg ## _OFST, \
510 uint32_t, (_eqp)->eq_u32[1], \
511 uint32_t, (_eqp)->eq_u32[0]); \
512 _NOTE(CONSTANTCONDITION) \
515 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
517 EFX_CHECK_REG((_enp), (_reg)); \
518 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
519 uint32_t, _reg ## _OFST, \
520 uint32_t, (_eqp)->eq_u32[1], \
521 uint32_t, (_eqp)->eq_u32[0]); \
522 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
524 _NOTE(CONSTANTCONDITION) \
527 #define EFX_BAR_READO(_enp, _reg, _eop) \
529 EFX_CHECK_REG((_enp), (_reg)); \
530 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
532 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
533 uint32_t, _reg ## _OFST, \
534 uint32_t, (_eop)->eo_u32[3], \
535 uint32_t, (_eop)->eo_u32[2], \
536 uint32_t, (_eop)->eo_u32[1], \
537 uint32_t, (_eop)->eo_u32[0]); \
538 _NOTE(CONSTANTCONDITION) \
541 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
543 EFX_CHECK_REG((_enp), (_reg)); \
544 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
545 uint32_t, _reg ## _OFST, \
546 uint32_t, (_eop)->eo_u32[3], \
547 uint32_t, (_eop)->eo_u32[2], \
548 uint32_t, (_eop)->eo_u32[1], \
549 uint32_t, (_eop)->eo_u32[0]); \
550 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
552 _NOTE(CONSTANTCONDITION) \
555 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
557 EFX_CHECK_REG((_enp), (_reg)); \
558 EFSYS_BAR_READD((_enp)->en_esbp, \
559 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
561 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
562 uint32_t, (_index), \
563 uint32_t, _reg ## _OFST, \
564 uint32_t, (_edp)->ed_u32[0]); \
565 _NOTE(CONSTANTCONDITION) \
568 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
570 EFX_CHECK_REG((_enp), (_reg)); \
571 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
572 uint32_t, (_index), \
573 uint32_t, _reg ## _OFST, \
574 uint32_t, (_edp)->ed_u32[0]); \
575 EFSYS_BAR_WRITED((_enp)->en_esbp, \
576 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
578 _NOTE(CONSTANTCONDITION) \
581 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
583 EFX_CHECK_REG((_enp), (_reg)); \
584 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
585 uint32_t, (_index), \
586 uint32_t, _reg ## _OFST, \
587 uint32_t, (_edp)->ed_u32[0]); \
588 EFSYS_BAR_WRITED((_enp)->en_esbp, \
590 (3 * sizeof (efx_dword_t)) + \
591 ((_index) * _reg ## _STEP)), \
593 _NOTE(CONSTANTCONDITION) \
596 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
598 EFX_CHECK_REG((_enp), (_reg)); \
599 EFSYS_BAR_READQ((_enp)->en_esbp, \
600 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
602 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
603 uint32_t, (_index), \
604 uint32_t, _reg ## _OFST, \
605 uint32_t, (_eqp)->eq_u32[1], \
606 uint32_t, (_eqp)->eq_u32[0]); \
607 _NOTE(CONSTANTCONDITION) \
610 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
612 EFX_CHECK_REG((_enp), (_reg)); \
613 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
614 uint32_t, (_index), \
615 uint32_t, _reg ## _OFST, \
616 uint32_t, (_eqp)->eq_u32[1], \
617 uint32_t, (_eqp)->eq_u32[0]); \
618 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
619 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
621 _NOTE(CONSTANTCONDITION) \
624 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop) \
626 EFX_CHECK_REG((_enp), (_reg)); \
627 EFSYS_BAR_READO((_enp)->en_esbp, \
628 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
630 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
631 uint32_t, (_index), \
632 uint32_t, _reg ## _OFST, \
633 uint32_t, (_eop)->eo_u32[3], \
634 uint32_t, (_eop)->eo_u32[2], \
635 uint32_t, (_eop)->eo_u32[1], \
636 uint32_t, (_eop)->eo_u32[0]); \
637 _NOTE(CONSTANTCONDITION) \
640 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop) \
642 EFX_CHECK_REG((_enp), (_reg)); \
643 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
644 uint32_t, (_index), \
645 uint32_t, _reg ## _OFST, \
646 uint32_t, (_eop)->eo_u32[3], \
647 uint32_t, (_eop)->eo_u32[2], \
648 uint32_t, (_eop)->eo_u32[1], \
649 uint32_t, (_eop)->eo_u32[0]); \
650 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
651 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
653 _NOTE(CONSTANTCONDITION) \
656 extern __checkReturn int
658 __in efx_nic_t *enp);
660 extern __checkReturn int
662 __in efx_nic_t *enp);
666 __in efx_nic_t *enp);
670 /* VPD utility functions */
672 extern __checkReturn int
674 __in_bcount(size) caddr_t data,
676 __out size_t *lengthp);
678 extern __checkReturn int
680 __in_bcount(size) caddr_t data,
682 __out_opt boolean_t *cksummedp);
684 extern __checkReturn int
688 __in boolean_t wantpid);
690 extern __checkReturn int
692 __in_bcount(size) caddr_t data,
694 __in efx_vpd_tag_t tag,
695 __in efx_vpd_keyword_t keyword,
696 __out unsigned int *payloadp,
697 __out uint8_t *paylenp);
699 extern __checkReturn int
701 __in_bcount(size) caddr_t data,
703 __out efx_vpd_tag_t *tagp,
704 __out efx_vpd_keyword_t *keyword,
705 __out_bcount_opt(*paylenp) unsigned int *payloadp,
706 __out_opt uint8_t *paylenp,
707 __inout unsigned int *contp);
709 extern __checkReturn int
711 __in_bcount(size) caddr_t data,
713 __in efx_vpd_value_t *evvp);
715 #endif /* EFSYS_OPT_VPD */
719 extern efx_sram_pattern_fn_t __cs __efx_sram_pattern_fns[];
721 typedef struct efx_register_set_s {
722 unsigned int address;
726 } efx_register_set_t;
728 extern __checkReturn int
729 efx_nic_test_registers(
731 __in efx_register_set_t *rsp,
734 extern __checkReturn int
737 __in efx_register_set_t *rsp,
738 __in efx_pattern_type_t pattern,
741 #endif /* EFSYS_OPT_DIAG */
747 #endif /* _SYS_EFX_IMPL_H */