2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * The views and conclusions contained in the software and documentation are
29 * those of the authors and should not be interpreted as representing official
30 * policies, either expressed or implied, of the FreeBSD Project.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
39 __checkReturn efx_rc_t
43 __out efx_family_t *efp,
44 __out unsigned int *membarp)
46 if (venid == EFX_PCI_VENID_SFC) {
49 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
51 * Hardware default for PF0 of uninitialised Siena.
52 * manftest must be able to cope with this device id.
54 case EFX_PCI_DEVID_BETHPAGE:
55 case EFX_PCI_DEVID_SIENA:
56 *efp = EFX_FAMILY_SIENA;
57 *membarp = EFX_MEM_BAR_SIENA;
59 #endif /* EFSYS_OPT_SIENA */
61 #if EFSYS_OPT_HUNTINGTON
62 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
64 * Hardware default for PF0 of uninitialised Huntington.
65 * manftest must be able to cope with this device id.
67 case EFX_PCI_DEVID_FARMINGDALE:
68 case EFX_PCI_DEVID_GREENPORT:
69 *efp = EFX_FAMILY_HUNTINGTON;
70 *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
73 case EFX_PCI_DEVID_FARMINGDALE_VF:
74 case EFX_PCI_DEVID_GREENPORT_VF:
75 *efp = EFX_FAMILY_HUNTINGTON;
76 *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
78 #endif /* EFSYS_OPT_HUNTINGTON */
81 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
83 * Hardware default for PF0 of uninitialised Medford.
84 * manftest must be able to cope with this device id.
86 case EFX_PCI_DEVID_MEDFORD:
87 *efp = EFX_FAMILY_MEDFORD;
88 *membarp = EFX_MEM_BAR_MEDFORD_PF;
91 case EFX_PCI_DEVID_MEDFORD_VF:
92 *efp = EFX_FAMILY_MEDFORD;
93 *membarp = EFX_MEM_BAR_MEDFORD_VF;
95 #endif /* EFSYS_OPT_MEDFORD */
97 #if EFSYS_OPT_MEDFORD2
98 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
100 * Hardware default for PF0 of uninitialised Medford2.
101 * manftest must be able to cope with this device id.
103 case EFX_PCI_DEVID_MEDFORD2:
104 case EFX_PCI_DEVID_MEDFORD2_VF:
105 *efp = EFX_FAMILY_MEDFORD2;
106 *membarp = EFX_MEM_BAR_MEDFORD2;
108 #endif /* EFSYS_OPT_MEDFORD2 */
110 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
116 *efp = EFX_FAMILY_INVALID;
122 static const efx_nic_ops_t __efx_nic_siena_ops = {
123 siena_nic_probe, /* eno_probe */
124 NULL, /* eno_board_cfg */
125 NULL, /* eno_set_drv_limits */
126 siena_nic_reset, /* eno_reset */
127 siena_nic_init, /* eno_init */
128 NULL, /* eno_get_vi_pool */
129 NULL, /* eno_get_bar_region */
130 NULL, /* eno_hw_unavailable */
131 NULL, /* eno_set_hw_unavailable */
133 siena_nic_register_test, /* eno_register_test */
134 #endif /* EFSYS_OPT_DIAG */
135 siena_nic_fini, /* eno_fini */
136 siena_nic_unprobe, /* eno_unprobe */
139 #endif /* EFSYS_OPT_SIENA */
141 #if EFSYS_OPT_HUNTINGTON
143 static const efx_nic_ops_t __efx_nic_hunt_ops = {
144 ef10_nic_probe, /* eno_probe */
145 hunt_board_cfg, /* eno_board_cfg */
146 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
147 ef10_nic_reset, /* eno_reset */
148 ef10_nic_init, /* eno_init */
149 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
150 ef10_nic_get_bar_region, /* eno_get_bar_region */
151 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
152 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
154 ef10_nic_register_test, /* eno_register_test */
155 #endif /* EFSYS_OPT_DIAG */
156 ef10_nic_fini, /* eno_fini */
157 ef10_nic_unprobe, /* eno_unprobe */
160 #endif /* EFSYS_OPT_HUNTINGTON */
162 #if EFSYS_OPT_MEDFORD
164 static const efx_nic_ops_t __efx_nic_medford_ops = {
165 ef10_nic_probe, /* eno_probe */
166 medford_board_cfg, /* eno_board_cfg */
167 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
168 ef10_nic_reset, /* eno_reset */
169 ef10_nic_init, /* eno_init */
170 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
171 ef10_nic_get_bar_region, /* eno_get_bar_region */
172 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
173 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
175 ef10_nic_register_test, /* eno_register_test */
176 #endif /* EFSYS_OPT_DIAG */
177 ef10_nic_fini, /* eno_fini */
178 ef10_nic_unprobe, /* eno_unprobe */
181 #endif /* EFSYS_OPT_MEDFORD */
183 #if EFSYS_OPT_MEDFORD2
185 static const efx_nic_ops_t __efx_nic_medford2_ops = {
186 ef10_nic_probe, /* eno_probe */
187 medford2_board_cfg, /* eno_board_cfg */
188 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
189 ef10_nic_reset, /* eno_reset */
190 ef10_nic_init, /* eno_init */
191 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
192 ef10_nic_get_bar_region, /* eno_get_bar_region */
193 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
194 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
196 ef10_nic_register_test, /* eno_register_test */
197 #endif /* EFSYS_OPT_DIAG */
198 ef10_nic_fini, /* eno_fini */
199 ef10_nic_unprobe, /* eno_unprobe */
202 #endif /* EFSYS_OPT_MEDFORD2 */
204 __checkReturn efx_rc_t
206 __in efx_family_t family,
207 __in efsys_identifier_t *esip,
208 __in efsys_bar_t *esbp,
209 __in efsys_lock_t *eslp,
210 __deref_out efx_nic_t **enpp)
215 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
216 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
218 /* Allocate a NIC object */
219 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
226 enp->en_magic = EFX_NIC_MAGIC;
230 case EFX_FAMILY_SIENA:
231 enp->en_enop = &__efx_nic_siena_ops;
234 EFX_FEATURE_LFSR_HASH_INSERT |
235 EFX_FEATURE_LINK_EVENTS |
236 EFX_FEATURE_PERIODIC_MAC_STATS |
238 EFX_FEATURE_LOOKAHEAD_SPLIT |
239 EFX_FEATURE_MAC_HEADER_FILTERS |
240 EFX_FEATURE_TX_SRC_FILTERS;
242 #endif /* EFSYS_OPT_SIENA */
244 #if EFSYS_OPT_HUNTINGTON
245 case EFX_FAMILY_HUNTINGTON:
246 enp->en_enop = &__efx_nic_hunt_ops;
249 EFX_FEATURE_LINK_EVENTS |
250 EFX_FEATURE_PERIODIC_MAC_STATS |
252 EFX_FEATURE_MAC_HEADER_FILTERS |
253 EFX_FEATURE_MCDI_DMA |
254 EFX_FEATURE_PIO_BUFFERS |
255 EFX_FEATURE_FW_ASSISTED_TSO |
256 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
257 EFX_FEATURE_PACKED_STREAM |
258 EFX_FEATURE_TXQ_CKSUM_OP_DESC;
260 #endif /* EFSYS_OPT_HUNTINGTON */
262 #if EFSYS_OPT_MEDFORD
263 case EFX_FAMILY_MEDFORD:
264 enp->en_enop = &__efx_nic_medford_ops;
266 * FW_ASSISTED_TSO omitted as Medford only supports firmware
267 * assisted TSO version 2, not the v1 scheme used on Huntington.
271 EFX_FEATURE_LINK_EVENTS |
272 EFX_FEATURE_PERIODIC_MAC_STATS |
274 EFX_FEATURE_MAC_HEADER_FILTERS |
275 EFX_FEATURE_MCDI_DMA |
276 EFX_FEATURE_PIO_BUFFERS |
277 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
278 EFX_FEATURE_PACKED_STREAM |
279 EFX_FEATURE_TXQ_CKSUM_OP_DESC;
281 #endif /* EFSYS_OPT_MEDFORD */
283 #if EFSYS_OPT_MEDFORD2
284 case EFX_FAMILY_MEDFORD2:
285 enp->en_enop = &__efx_nic_medford2_ops;
288 EFX_FEATURE_LINK_EVENTS |
289 EFX_FEATURE_PERIODIC_MAC_STATS |
291 EFX_FEATURE_MAC_HEADER_FILTERS |
292 EFX_FEATURE_MCDI_DMA |
293 EFX_FEATURE_PIO_BUFFERS |
294 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
295 EFX_FEATURE_PACKED_STREAM |
296 EFX_FEATURE_TXQ_CKSUM_OP_DESC;
298 #endif /* EFSYS_OPT_MEDFORD2 */
305 enp->en_family = family;
319 /* Free the NIC object */
320 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
323 EFSYS_PROBE1(fail1, efx_rc_t, rc);
328 __checkReturn efx_rc_t
331 __in efx_fw_variant_t efv)
333 const efx_nic_ops_t *enop;
336 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
338 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
339 #endif /* EFSYS_OPT_MCDI */
340 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
342 /* Ensure FW variant codes match with MC_CMD_FW codes */
343 EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
344 MC_CMD_FW_FULL_FEATURED);
345 EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
346 MC_CMD_FW_LOW_LATENCY);
347 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
348 MC_CMD_FW_PACKED_STREAM);
349 EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
350 MC_CMD_FW_HIGH_TX_RATE);
351 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
352 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
353 EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
354 MC_CMD_FW_RULES_ENGINE);
355 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
357 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
358 (int)MC_CMD_FW_DONT_CARE);
363 if ((rc = enop->eno_probe(enp)) != 0)
366 if ((rc = efx_phy_probe(enp)) != 0)
369 enp->en_mod_flags |= EFX_MOD_PROBE;
376 enop->eno_unprobe(enp);
379 EFSYS_PROBE1(fail1, efx_rc_t, rc);
384 __checkReturn efx_rc_t
385 efx_nic_set_drv_limits(
386 __inout efx_nic_t *enp,
387 __in efx_drv_limits_t *edlp)
389 const efx_nic_ops_t *enop = enp->en_enop;
392 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
393 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
395 if (enop->eno_set_drv_limits != NULL) {
396 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
403 EFSYS_PROBE1(fail1, efx_rc_t, rc);
408 __checkReturn efx_rc_t
409 efx_nic_get_bar_region(
411 __in efx_nic_region_t region,
412 __out uint32_t *offsetp,
415 const efx_nic_ops_t *enop = enp->en_enop;
418 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
419 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
420 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
422 if (enop->eno_get_bar_region == NULL) {
426 if ((rc = (enop->eno_get_bar_region)(enp,
427 region, offsetp, sizep)) != 0) {
437 EFSYS_PROBE1(fail1, efx_rc_t, rc);
442 __checkReturn efx_rc_t
445 __out uint32_t *evq_countp,
446 __out uint32_t *rxq_countp,
447 __out uint32_t *txq_countp)
449 const efx_nic_ops_t *enop = enp->en_enop;
450 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
453 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
454 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
455 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
457 if (enop->eno_get_vi_pool != NULL) {
458 uint32_t vi_count = 0;
460 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
463 *evq_countp = vi_count;
464 *rxq_countp = vi_count;
465 *txq_countp = vi_count;
467 /* Use NIC limits as default value */
468 *evq_countp = encp->enc_evq_limit;
469 *rxq_countp = encp->enc_rxq_limit;
470 *txq_countp = encp->enc_txq_limit;
476 EFSYS_PROBE1(fail1, efx_rc_t, rc);
481 __checkReturn efx_rc_t
485 const efx_nic_ops_t *enop = enp->en_enop;
488 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
489 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
491 if (enp->en_mod_flags & EFX_MOD_NIC) {
496 if ((rc = enop->eno_init(enp)) != 0)
499 enp->en_mod_flags |= EFX_MOD_NIC;
506 EFSYS_PROBE1(fail1, efx_rc_t, rc);
515 const efx_nic_ops_t *enop = enp->en_enop;
517 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
518 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
519 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
520 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
521 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
522 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
523 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
527 enp->en_mod_flags &= ~EFX_MOD_NIC;
534 const efx_nic_ops_t *enop = enp->en_enop;
536 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
538 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
539 #endif /* EFSYS_OPT_MCDI */
540 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
541 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
542 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
543 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
544 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
545 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
547 efx_phy_unprobe(enp);
549 enop->eno_unprobe(enp);
551 enp->en_mod_flags &= ~EFX_MOD_PROBE;
558 efsys_identifier_t *esip = enp->en_esip;
560 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
561 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
563 enp->en_family = EFX_FAMILY_INVALID;
572 /* Free the NIC object */
573 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
576 __checkReturn efx_rc_t
580 const efx_nic_ops_t *enop = enp->en_enop;
581 unsigned int mod_flags;
584 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
585 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
587 * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
588 * (which we do not reset here) must have been shut down or never
591 * A rule of thumb here is: If the controller or MC reboots, is *any*
592 * state lost. If it's lost and needs reapplying, then the module
593 * *must* not be initialised during the reset.
595 mod_flags = enp->en_mod_flags;
596 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
597 EFX_MOD_VPD | EFX_MOD_MON);
599 mod_flags &= ~EFX_MOD_TUNNEL;
600 #endif /* EFSYS_OPT_TUNNEL */
601 EFSYS_ASSERT3U(mod_flags, ==, 0);
602 if (mod_flags != 0) {
607 if ((rc = enop->eno_reset(enp)) != 0)
615 EFSYS_PROBE1(fail1, efx_rc_t, rc);
620 const efx_nic_cfg_t *
624 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
625 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
627 return (&(enp->en_nic_cfg));
630 __checkReturn efx_rc_t
631 efx_nic_get_fw_version(
633 __out efx_nic_fw_info_t *enfip)
635 uint16_t mc_fw_version[4];
643 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
644 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
646 /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
647 EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
648 MC_CMD_GET_CAPABILITIES_OUT_RXDP);
649 EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
650 MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
651 EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
652 MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
653 EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
654 MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
655 EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
656 MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
658 rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
662 rc = efx_mcdi_get_capabilities(enp, NULL,
663 &enfip->enfi_rx_dpcpu_fw_id,
664 &enfip->enfi_tx_dpcpu_fw_id,
667 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
668 } else if (rc == ENOTSUP) {
669 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
670 enfip->enfi_rx_dpcpu_fw_id = 0;
671 enfip->enfi_tx_dpcpu_fw_id = 0;
676 memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
677 sizeof (mc_fw_version));
686 EFSYS_PROBE1(fail1, efx_rc_t, rc);
691 __checkReturn boolean_t
692 efx_nic_hw_unavailable(
695 const efx_nic_ops_t *enop = enp->en_enop;
697 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
698 /* NOTE: can be used by MCDI before NIC probe */
700 if (enop->eno_hw_unavailable != NULL) {
701 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
712 efx_nic_set_hw_unavailable(
715 const efx_nic_ops_t *enop = enp->en_enop;
717 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
719 if (enop->eno_set_hw_unavailable != NULL)
720 enop->eno_set_hw_unavailable(enp);
725 __checkReturn efx_rc_t
726 efx_nic_register_test(
729 const efx_nic_ops_t *enop = enp->en_enop;
732 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
733 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
734 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
736 if ((rc = enop->eno_register_test(enp)) != 0)
742 EFSYS_PROBE1(fail1, efx_rc_t, rc);
747 #endif /* EFSYS_OPT_DIAG */
749 #if EFSYS_OPT_LOOPBACK
753 __in efx_loopback_kind_t loopback_kind,
754 __out efx_qword_t *maskp)
758 EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
759 EFSYS_ASSERT(maskp != NULL);
761 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
762 #define LOOPBACK_CHECK(_mcdi, _efx) \
763 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
765 LOOPBACK_CHECK(NONE, OFF);
766 LOOPBACK_CHECK(DATA, DATA);
767 LOOPBACK_CHECK(GMAC, GMAC);
768 LOOPBACK_CHECK(XGMII, XGMII);
769 LOOPBACK_CHECK(XGXS, XGXS);
770 LOOPBACK_CHECK(XAUI, XAUI);
771 LOOPBACK_CHECK(GMII, GMII);
772 LOOPBACK_CHECK(SGMII, SGMII);
773 LOOPBACK_CHECK(XGBR, XGBR);
774 LOOPBACK_CHECK(XFI, XFI);
775 LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
776 LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
777 LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
778 LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
779 LOOPBACK_CHECK(GPHY, GPHY);
780 LOOPBACK_CHECK(PHYXS, PHY_XS);
781 LOOPBACK_CHECK(PCS, PCS);
782 LOOPBACK_CHECK(PMAPMD, PMA_PMD);
783 LOOPBACK_CHECK(XPORT, XPORT);
784 LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
785 LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
786 LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
787 LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
788 LOOPBACK_CHECK(GMII_WS, GMII_WS);
789 LOOPBACK_CHECK(XFI_WS, XFI_WS);
790 LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
791 LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
792 LOOPBACK_CHECK(PMA_INT, PMA_INT);
793 LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
794 LOOPBACK_CHECK(SD_FAR, SD_FAR);
795 LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
796 LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
797 LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
798 LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
799 LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
800 LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
801 LOOPBACK_CHECK(DATA_WS, DATA_WS);
802 LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
803 #undef LOOPBACK_CHECK
805 /* Build bitmask of possible loopback types */
806 EFX_ZERO_QWORD(mask);
808 if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
809 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
810 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
813 if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
814 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
816 * The "MAC" grouping has historically been used by drivers to
817 * mean loopbacks supported by on-chip hardware. Keep that
818 * meaning here, and include on-chip PHY layer loopbacks.
820 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
821 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
822 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
823 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
824 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
825 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
826 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
827 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
828 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
829 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
830 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
831 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
832 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
833 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
834 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
835 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
838 if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
839 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
841 * The "PHY" grouping has historically been used by drivers to
842 * mean loopbacks supported by off-chip hardware. Keep that
845 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
846 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
847 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
848 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
854 __checkReturn efx_rc_t
855 efx_mcdi_get_loopback_modes(
858 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
860 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
861 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
866 req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
867 req.emr_in_buf = payload;
868 req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
869 req.emr_out_buf = payload;
870 req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
872 efx_mcdi_execute(enp, &req);
874 if (req.emr_rc != 0) {
879 if (req.emr_out_length_used <
880 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
881 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
887 * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
888 * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
890 efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
893 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
895 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
896 EFX_AND_QWORD(modes, mask);
897 encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
899 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
900 EFX_AND_QWORD(modes, mask);
901 encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
903 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
904 EFX_AND_QWORD(modes, mask);
905 encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
907 if (req.emr_out_length_used >=
908 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
909 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
910 /* Response includes 40G loopback modes */
911 modes = *MCDI_OUT2(req, efx_qword_t,
912 GET_LOOPBACK_MODES_OUT_40G);
913 EFX_AND_QWORD(modes, mask);
914 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
917 if (req.emr_out_length_used >=
918 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
919 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
920 /* Response includes 25G loopback modes */
921 modes = *MCDI_OUT2(req, efx_qword_t,
922 GET_LOOPBACK_MODES_OUT_V2_25G);
923 EFX_AND_QWORD(modes, mask);
924 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
927 if (req.emr_out_length_used >=
928 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
929 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
930 /* Response includes 50G loopback modes */
931 modes = *MCDI_OUT2(req, efx_qword_t,
932 GET_LOOPBACK_MODES_OUT_V2_50G);
933 EFX_AND_QWORD(modes, mask);
934 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
937 if (req.emr_out_length_used >=
938 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
939 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
940 /* Response includes 100G loopback modes */
941 modes = *MCDI_OUT2(req, efx_qword_t,
942 GET_LOOPBACK_MODES_OUT_V2_100G);
943 EFX_AND_QWORD(modes, mask);
944 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
947 EFX_ZERO_QWORD(modes);
948 EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
949 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
950 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
951 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
952 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
953 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
954 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
955 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
956 encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
963 EFSYS_PROBE1(fail1, efx_rc_t, rc);
968 #endif /* EFSYS_OPT_LOOPBACK */
970 __checkReturn efx_rc_t
971 efx_nic_calculate_pcie_link_bandwidth(
972 __in uint32_t pcie_link_width,
973 __in uint32_t pcie_link_gen,
974 __out uint32_t *bandwidth_mbpsp)
976 uint32_t lane_bandwidth;
977 uint32_t total_bandwidth;
980 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
981 !ISP2(pcie_link_width)) {
986 switch (pcie_link_gen) {
987 case EFX_PCIE_LINK_SPEED_GEN1:
988 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
989 lane_bandwidth = 2000;
991 case EFX_PCIE_LINK_SPEED_GEN2:
992 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
993 lane_bandwidth = 4000;
995 case EFX_PCIE_LINK_SPEED_GEN3:
996 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
997 lane_bandwidth = 7877;
1004 total_bandwidth = lane_bandwidth * pcie_link_width;
1005 *bandwidth_mbpsp = total_bandwidth;
1012 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1017 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1019 __checkReturn efx_rc_t
1020 efx_nic_get_fw_subvariant(
1021 __in efx_nic_t *enp,
1022 __out efx_nic_fw_subvariant_t *subvariantp)
1027 rc = efx_mcdi_get_nic_global(enp,
1028 MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
1032 /* Mapping is not required since values match MCDI */
1033 EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
1034 MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
1035 EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
1036 MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
1039 case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
1040 case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1041 *subvariantp = value;
1054 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1059 __checkReturn efx_rc_t
1060 efx_nic_set_fw_subvariant(
1061 __in efx_nic_t *enp,
1062 __in efx_nic_fw_subvariant_t subvariant)
1066 switch (subvariant) {
1067 case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1068 case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1069 /* Mapping is not required since values match MCDI */
1076 rc = efx_mcdi_set_nic_global(enp,
1077 MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1087 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1092 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1094 __checkReturn efx_rc_t
1095 efx_nic_check_pcie_link_speed(
1096 __in efx_nic_t *enp,
1097 __in uint32_t pcie_link_width,
1098 __in uint32_t pcie_link_gen,
1099 __out efx_pcie_link_performance_t *resultp)
1101 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1103 efx_pcie_link_performance_t result;
1106 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1107 (pcie_link_width == 0) || (pcie_link_width == 32) ||
1108 (pcie_link_gen == 0)) {
1110 * No usable info on what is required and/or in use. In virtual
1111 * machines, sometimes the PCIe link width is reported as 0 or
1112 * 32, or the speed as 0.
1114 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1118 /* Calculate the available bandwidth in megabits per second */
1119 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1120 pcie_link_gen, &bandwidth);
1124 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1125 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1126 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1127 /* The link provides enough bandwidth but not optimal latency */
1128 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1130 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1139 EFSYS_PROBE1(fail1, efx_rc_t, rc);