sys/dev/sfxge/common/efx_nic.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *    this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright notice,
  13  *    this list of conditions and the following disclaimer in the documentation
  14  *    and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  18  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  19  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  23  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  25  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * The views and conclusions contained in the software and documentation are
  29  * those of the authors and should not be interpreted as representing official
  30  * policies, either expressed or implied, of the FreeBSD Project.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include "efx.h"
  37 #include "efx_impl.h"
  38
  39
  40         __checkReturn   efx_rc_t
  41 efx_family(
  42         __in            uint16_t venid,
  43         __in            uint16_t devid,
  44         __out           efx_family_t *efp,
  45         __out           unsigned int *membarp)
  46 {
  47         if (venid == EFX_PCI_VENID_SFC) {
  48                 switch (devid) {
  49 #if EFSYS_OPT_SIENA
  50                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  51                         /*
  52                          * Hardware default for PF0 of uninitialised Siena.
  53                          * manftest must be able to cope with this device id.
  54                          */
  55                 case EFX_PCI_DEVID_BETHPAGE:
  56                 case EFX_PCI_DEVID_SIENA:
  57                         *efp = EFX_FAMILY_SIENA;
  58                         *membarp = EFX_MEM_BAR_SIENA;
  59                         return (0);
  60 #endif /* EFSYS_OPT_SIENA */
  61
  62 #if EFSYS_OPT_HUNTINGTON
  63                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  64                         /*
  65                          * Hardware default for PF0 of uninitialised Huntington.
  66                          * manftest must be able to cope with this device id.
  67                          */
  68                 case EFX_PCI_DEVID_FARMINGDALE:
  69                 case EFX_PCI_DEVID_GREENPORT:
  70                         *efp = EFX_FAMILY_HUNTINGTON;
  71                         *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
  72                         return (0);
  73
  74                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  75                 case EFX_PCI_DEVID_GREENPORT_VF:
  76                         *efp = EFX_FAMILY_HUNTINGTON;
  77                         *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
  78                         return (0);
  79 #endif /* EFSYS_OPT_HUNTINGTON */
  80
  81 #if EFSYS_OPT_MEDFORD
  82                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  83                         /*
  84                          * Hardware default for PF0 of uninitialised Medford.
  85                          * manftest must be able to cope with this device id.
  86                          */
  87                 case EFX_PCI_DEVID_MEDFORD:
  88                         *efp = EFX_FAMILY_MEDFORD;
  89                         *membarp = EFX_MEM_BAR_MEDFORD_PF;
  90                         return (0);
  91
  92                 case EFX_PCI_DEVID_MEDFORD_VF:
  93                         *efp = EFX_FAMILY_MEDFORD;
  94                         *membarp = EFX_MEM_BAR_MEDFORD_VF;
  95                         return (0);
  96 #endif /* EFSYS_OPT_MEDFORD */
  97
  98 #if EFSYS_OPT_MEDFORD2
  99                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
 100                         /*
 101                          * Hardware default for PF0 of uninitialised Medford2.
 102                          * manftest must be able to cope with this device id.
 103                          */
 104                 case EFX_PCI_DEVID_MEDFORD2:
 105                 case EFX_PCI_DEVID_MEDFORD2_VF:
 106                         *efp = EFX_FAMILY_MEDFORD2;
 107                         *membarp = EFX_MEM_BAR_MEDFORD2;
 108                         return (0);
 109 #endif /* EFSYS_OPT_MEDFORD2 */
 110
 111                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
 112                 default:
 113                         break;
 114                 }
 115         }
 116
 117         *efp = EFX_FAMILY_INVALID;
 118         return (ENOTSUP);
 119 }
 120
 121
 122 #if EFSYS_OPT_SIENA
 123
 124 static const efx_nic_ops_t      __efx_nic_siena_ops = {
 125         siena_nic_probe,                /* eno_probe */
 126         NULL,                           /* eno_board_cfg */
 127         NULL,                           /* eno_set_drv_limits */
 128         siena_nic_reset,                /* eno_reset */
 129         siena_nic_init,                 /* eno_init */
 130         NULL,                           /* eno_get_vi_pool */
 131         NULL,                           /* eno_get_bar_region */
 132 #if EFSYS_OPT_DIAG
 133         siena_nic_register_test,        /* eno_register_test */
 134 #endif  /* EFSYS_OPT_DIAG */
 135         siena_nic_fini,                 /* eno_fini */
 136         siena_nic_unprobe,              /* eno_unprobe */
 137 };
 138
 139 #endif  /* EFSYS_OPT_SIENA */
 140
 141 #if EFSYS_OPT_HUNTINGTON
 142
 143 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 144         ef10_nic_probe,                 /* eno_probe */
 145         hunt_board_cfg,                 /* eno_board_cfg */
 146         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 147         ef10_nic_reset,                 /* eno_reset */
 148         ef10_nic_init,                  /* eno_init */
 149         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 150         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 151 #if EFSYS_OPT_DIAG
 152         ef10_nic_register_test,         /* eno_register_test */
 153 #endif  /* EFSYS_OPT_DIAG */
 154         ef10_nic_fini,                  /* eno_fini */
 155         ef10_nic_unprobe,               /* eno_unprobe */
 156 };
 157
 158 #endif  /* EFSYS_OPT_HUNTINGTON */
 159
 160 #if EFSYS_OPT_MEDFORD
 161
 162 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 163         ef10_nic_probe,                 /* eno_probe */
 164         medford_board_cfg,              /* eno_board_cfg */
 165         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 166         ef10_nic_reset,                 /* eno_reset */
 167         ef10_nic_init,                  /* eno_init */
 168         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 169         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 170 #if EFSYS_OPT_DIAG
 171         ef10_nic_register_test,         /* eno_register_test */
 172 #endif  /* EFSYS_OPT_DIAG */
 173         ef10_nic_fini,                  /* eno_fini */
 174         ef10_nic_unprobe,               /* eno_unprobe */
 175 };
 176
 177 #endif  /* EFSYS_OPT_MEDFORD */
 178
 179 #if EFSYS_OPT_MEDFORD2
 180
 181 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 182         ef10_nic_probe,                 /* eno_probe */
 183         medford2_board_cfg,             /* eno_board_cfg */
 184         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 185         ef10_nic_reset,                 /* eno_reset */
 186         ef10_nic_init,                  /* eno_init */
 187         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 188         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 189 #if EFSYS_OPT_DIAG
 190         ef10_nic_register_test,         /* eno_register_test */
 191 #endif  /* EFSYS_OPT_DIAG */
 192         ef10_nic_fini,                  /* eno_fini */
 193         ef10_nic_unprobe,               /* eno_unprobe */
 194 };
 195
 196 #endif  /* EFSYS_OPT_MEDFORD2 */
 197
 198
 199         __checkReturn   efx_rc_t
 200 efx_nic_create(
 201         __in            efx_family_t family,
 202         __in            efsys_identifier_t *esip,
 203         __in            efsys_bar_t *esbp,
 204         __in            efsys_lock_t *eslp,
 205         __deref_out     efx_nic_t **enpp)
 206 {
 207         efx_nic_t *enp;
 208         efx_rc_t rc;
 209
 210         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 211         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 212
 213         /* Allocate a NIC object */
 214         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 215
 216         if (enp == NULL) {
 217                 rc = ENOMEM;
 218                 goto fail1;
 219         }
 220
 221         enp->en_magic = EFX_NIC_MAGIC;
 222
 223         switch (family) {
 224 #if EFSYS_OPT_SIENA
 225         case EFX_FAMILY_SIENA:
 226                 enp->en_enop = &__efx_nic_siena_ops;
 227                 enp->en_features =
 228                     EFX_FEATURE_IPV6 |
 229                     EFX_FEATURE_LFSR_HASH_INSERT |
 230                     EFX_FEATURE_LINK_EVENTS |
 231                     EFX_FEATURE_PERIODIC_MAC_STATS |
 232                     EFX_FEATURE_MCDI |
 233                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 234                     EFX_FEATURE_MAC_HEADER_FILTERS |
 235                     EFX_FEATURE_TX_SRC_FILTERS;
 236                 break;
 237 #endif  /* EFSYS_OPT_SIENA */
 238
 239 #if EFSYS_OPT_HUNTINGTON
 240         case EFX_FAMILY_HUNTINGTON:
 241                 enp->en_enop = &__efx_nic_hunt_ops;
 242                 enp->en_features =
 243                     EFX_FEATURE_IPV6 |
 244                     EFX_FEATURE_LINK_EVENTS |
 245                     EFX_FEATURE_PERIODIC_MAC_STATS |
 246                     EFX_FEATURE_MCDI |
 247                     EFX_FEATURE_MAC_HEADER_FILTERS |
 248                     EFX_FEATURE_MCDI_DMA |
 249                     EFX_FEATURE_PIO_BUFFERS |
 250                     EFX_FEATURE_FW_ASSISTED_TSO |
 251                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 252                     EFX_FEATURE_PACKED_STREAM;
 253                 break;
 254 #endif  /* EFSYS_OPT_HUNTINGTON */
 255
 256 #if EFSYS_OPT_MEDFORD
 257         case EFX_FAMILY_MEDFORD:
 258                 enp->en_enop = &__efx_nic_medford_ops;
 259                 /*
 260                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 261                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 262                  */
 263                 enp->en_features =
 264                     EFX_FEATURE_IPV6 |
 265                     EFX_FEATURE_LINK_EVENTS |
 266                     EFX_FEATURE_PERIODIC_MAC_STATS |
 267                     EFX_FEATURE_MCDI |
 268                     EFX_FEATURE_MAC_HEADER_FILTERS |
 269                     EFX_FEATURE_MCDI_DMA |
 270                     EFX_FEATURE_PIO_BUFFERS |
 271                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 272                     EFX_FEATURE_PACKED_STREAM;
 273                 break;
 274 #endif  /* EFSYS_OPT_MEDFORD */
 275
 276 #if EFSYS_OPT_MEDFORD2
 277         case EFX_FAMILY_MEDFORD2:
 278                 enp->en_enop = &__efx_nic_medford2_ops;
 279                 enp->en_features =
 280                     EFX_FEATURE_IPV6 |
 281                     EFX_FEATURE_LINK_EVENTS |
 282                     EFX_FEATURE_PERIODIC_MAC_STATS |
 283                     EFX_FEATURE_MCDI |
 284                     EFX_FEATURE_MAC_HEADER_FILTERS |
 285                     EFX_FEATURE_MCDI_DMA |
 286                     EFX_FEATURE_PIO_BUFFERS |
 287                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 288                     EFX_FEATURE_PACKED_STREAM;
 289                 break;
 290 #endif  /* EFSYS_OPT_MEDFORD2 */
 291
 292         default:
 293                 rc = ENOTSUP;
 294                 goto fail2;
 295         }
 296
 297         enp->en_family = family;
 298         enp->en_esip = esip;
 299         enp->en_esbp = esbp;
 300         enp->en_eslp = eslp;
 301
 302         *enpp = enp;
 303
 304         return (0);
 305
 306 fail2:
 307         EFSYS_PROBE(fail2);
 308
 309         enp->en_magic = 0;
 310
 311         /* Free the NIC object */
 312         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 313
 314 fail1:
 315         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 316
 317         return (rc);
 318 }
 319
 320         __checkReturn   efx_rc_t
 321 efx_nic_probe(
 322         __in            efx_nic_t *enp)
 323 {
 324         const efx_nic_ops_t *enop;
 325         efx_rc_t rc;
 326
 327         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 328 #if EFSYS_OPT_MCDI
 329         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 330 #endif  /* EFSYS_OPT_MCDI */
 331         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 332
 333         enop = enp->en_enop;
 334         if ((rc = enop->eno_probe(enp)) != 0)
 335                 goto fail1;
 336
 337         if ((rc = efx_phy_probe(enp)) != 0)
 338                 goto fail2;
 339
 340         enp->en_mod_flags |= EFX_MOD_PROBE;
 341
 342         return (0);
 343
 344 fail2:
 345         EFSYS_PROBE(fail2);
 346
 347         enop->eno_unprobe(enp);
 348
 349 fail1:
 350         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 351
 352         return (rc);
 353 }
 354
 355         __checkReturn   efx_rc_t
 356 efx_nic_set_drv_limits(
 357         __inout         efx_nic_t *enp,
 358         __in            efx_drv_limits_t *edlp)
 359 {
 360         const efx_nic_ops_t *enop = enp->en_enop;
 361         efx_rc_t rc;
 362
 363         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 364         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 365
 366         if (enop->eno_set_drv_limits != NULL) {
 367                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 368                         goto fail1;
 369         }
 370
 371         return (0);
 372
 373 fail1:
 374         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 375
 376         return (rc);
 377 }
 378
 379         __checkReturn   efx_rc_t
 380 efx_nic_get_bar_region(
 381         __in            efx_nic_t *enp,
 382         __in            efx_nic_region_t region,
 383         __out           uint32_t *offsetp,
 384         __out           size_t *sizep)
 385 {
 386         const efx_nic_ops_t *enop = enp->en_enop;
 387         efx_rc_t rc;
 388
 389         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 390         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 391         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 392
 393         if (enop->eno_get_bar_region == NULL) {
 394                 rc = ENOTSUP;
 395                 goto fail1;
 396         }
 397         if ((rc = (enop->eno_get_bar_region)(enp,
 398                     region, offsetp, sizep)) != 0) {
 399                 goto fail2;
 400         }
 401
 402         return (0);
 403
 404 fail2:
 405         EFSYS_PROBE(fail2);
 406
 407 fail1:
 408         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 409
 410         return (rc);
 411 }
 412
 413
 414         __checkReturn   efx_rc_t
 415 efx_nic_get_vi_pool(
 416         __in            efx_nic_t *enp,
 417         __out           uint32_t *evq_countp,
 418         __out           uint32_t *rxq_countp,
 419         __out           uint32_t *txq_countp)
 420 {
 421         const efx_nic_ops_t *enop = enp->en_enop;
 422         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 423         efx_rc_t rc;
 424
 425         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 426         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 427         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 428
 429         if (enop->eno_get_vi_pool != NULL) {
 430                 uint32_t vi_count = 0;
 431
 432                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 433                         goto fail1;
 434
 435                 *evq_countp = vi_count;
 436                 *rxq_countp = vi_count;
 437                 *txq_countp = vi_count;
 438         } else {
 439                 /* Use NIC limits as default value */
 440                 *evq_countp = encp->enc_evq_limit;
 441                 *rxq_countp = encp->enc_rxq_limit;
 442                 *txq_countp = encp->enc_txq_limit;
 443         }
 444
 445         return (0);
 446
 447 fail1:
 448         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 449
 450         return (rc);
 451 }
 452
 453
 454         __checkReturn   efx_rc_t
 455 efx_nic_init(
 456         __in            efx_nic_t *enp)
 457 {
 458         const efx_nic_ops_t *enop = enp->en_enop;
 459         efx_rc_t rc;
 460
 461         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 462         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 463
 464         if (enp->en_mod_flags & EFX_MOD_NIC) {
 465                 rc = EINVAL;
 466                 goto fail1;
 467         }
 468
 469         if ((rc = enop->eno_init(enp)) != 0)
 470                 goto fail2;
 471
 472         enp->en_mod_flags |= EFX_MOD_NIC;
 473
 474         return (0);
 475
 476 fail2:
 477         EFSYS_PROBE(fail2);
 478 fail1:
 479         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 480
 481         return (rc);
 482 }
 483
 484                         void
 485 efx_nic_fini(
 486         __in            efx_nic_t *enp)
 487 {
 488         const efx_nic_ops_t *enop = enp->en_enop;
 489
 490         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 491         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 492         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 493         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 494         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 495         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 496         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 497
 498         enop->eno_fini(enp);
 499
 500         enp->en_mod_flags &= ~EFX_MOD_NIC;
 501 }
 502
 503                         void
 504 efx_nic_unprobe(
 505         __in            efx_nic_t *enp)
 506 {
 507         const efx_nic_ops_t *enop = enp->en_enop;
 508
 509         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 510 #if EFSYS_OPT_MCDI
 511         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 512 #endif  /* EFSYS_OPT_MCDI */
 513         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 514         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 515         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 516         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 517         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 518         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 519
 520         efx_phy_unprobe(enp);
 521
 522         enop->eno_unprobe(enp);
 523
 524         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 525 }
 526
 527                         void
 528 efx_nic_destroy(
 529         __in    efx_nic_t *enp)
 530 {
 531         efsys_identifier_t *esip = enp->en_esip;
 532
 533         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 534         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 535
 536         enp->en_family = EFX_FAMILY_INVALID;
 537         enp->en_esip = NULL;
 538         enp->en_esbp = NULL;
 539         enp->en_eslp = NULL;
 540
 541         enp->en_enop = NULL;
 542
 543         enp->en_magic = 0;
 544
 545         /* Free the NIC object */
 546         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 547 }
 548
 549         __checkReturn   efx_rc_t
 550 efx_nic_reset(
 551         __in            efx_nic_t *enp)
 552 {
 553         const efx_nic_ops_t *enop = enp->en_enop;
 554         unsigned int mod_flags;
 555         efx_rc_t rc;
 556
 557         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 558         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 559         /*
 560          * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
 561          * (which we do not reset here) must have been shut down or never
 562          * initialized.
 563          *
 564          * A rule of thumb here is: If the controller or MC reboots, is *any*
 565          * state lost. If it's lost and needs reapplying, then the module
 566          * *must* not be initialised during the reset.
 567          */
 568         mod_flags = enp->en_mod_flags;
 569         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 570             EFX_MOD_VPD | EFX_MOD_MON);
 571 #if EFSYS_OPT_TUNNEL
 572         mod_flags &= ~EFX_MOD_TUNNEL;
 573 #endif /* EFSYS_OPT_TUNNEL */
 574         EFSYS_ASSERT3U(mod_flags, ==, 0);
 575         if (mod_flags != 0) {
 576                 rc = EINVAL;
 577                 goto fail1;
 578         }
 579
 580         if ((rc = enop->eno_reset(enp)) != 0)
 581                 goto fail2;
 582
 583         return (0);
 584
 585 fail2:
 586         EFSYS_PROBE(fail2);
 587 fail1:
 588         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 589
 590         return (rc);
 591 }
 592
 593                         const efx_nic_cfg_t *
 594 efx_nic_cfg_get(
 595         __in            efx_nic_t *enp)
 596 {
 597         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 598
 599         return (&(enp->en_nic_cfg));
 600 }
 601
 602         __checkReturn           efx_rc_t
 603 efx_nic_get_fw_version(
 604         __in                    efx_nic_t *enp,
 605         __out                   efx_nic_fw_info_t *enfip)
 606 {
 607         uint16_t mc_fw_version[4];
 608         efx_rc_t rc;
 609
 610         if (enfip == NULL) {
 611                 rc = EINVAL;
 612                 goto fail1;
 613         }
 614
 615         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 616         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 617
 618         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 619         if (rc != 0)
 620                 goto fail2;
 621
 622         rc = efx_mcdi_get_capabilities(enp, NULL,
 623             &enfip->enfi_rx_dpcpu_fw_id,
 624             &enfip->enfi_tx_dpcpu_fw_id,
 625             NULL, NULL);
 626         if (rc == 0) {
 627                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 628         } else if (rc == ENOTSUP) {
 629                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 630                 enfip->enfi_rx_dpcpu_fw_id = 0;
 631                 enfip->enfi_tx_dpcpu_fw_id = 0;
 632         } else {
 633                 goto fail3;
 634         }
 635
 636         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 637             sizeof (mc_fw_version));
 638
 639         return (0);
 640
 641 fail3:
 642         EFSYS_PROBE(fail3);
 643 fail2:
 644         EFSYS_PROBE(fail2);
 645 fail1:
 646         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 647
 648         return (rc);
 649 }
 650
 651 #if EFSYS_OPT_DIAG
 652
 653         __checkReturn   efx_rc_t
 654 efx_nic_register_test(
 655         __in            efx_nic_t *enp)
 656 {
 657         const efx_nic_ops_t *enop = enp->en_enop;
 658         efx_rc_t rc;
 659
 660         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 661         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 662         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 663
 664         if ((rc = enop->eno_register_test(enp)) != 0)
 665                 goto fail1;
 666
 667         return (0);
 668
 669 fail1:
 670         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 671
 672         return (rc);
 673 }
 674
 675 #endif  /* EFSYS_OPT_DIAG */
 676
 677 #if EFSYS_OPT_LOOPBACK
 678
 679 extern                  void
 680 efx_loopback_mask(
 681         __in    efx_loopback_kind_t loopback_kind,
 682         __out   efx_qword_t *maskp)
 683 {
 684         efx_qword_t mask;
 685
 686         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 687         EFSYS_ASSERT(maskp != NULL);
 688
 689         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */
 690         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
 691         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
 692         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
 693         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
 694         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
 695         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
 696         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
 697         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
 698         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
 699         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI);
 700         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR);
 701         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR);
 702         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR);
 703         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR);
 704         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY);
 705         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS);
 706         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS);
 707         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD);
 708         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XPORT == EFX_LOOPBACK_XPORT);
 709         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII_WS == EFX_LOOPBACK_XGMII_WS);
 710         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS == EFX_LOOPBACK_XAUI_WS);
 711         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_FAR ==
 712             EFX_LOOPBACK_XAUI_WS_FAR);
 713         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_NEAR ==
 714             EFX_LOOPBACK_XAUI_WS_NEAR);
 715         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_WS == EFX_LOOPBACK_GMII_WS);
 716         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS == EFX_LOOPBACK_XFI_WS);
 717         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS_FAR ==
 718             EFX_LOOPBACK_XFI_WS_FAR);
 719         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS_WS == EFX_LOOPBACK_PHYXS_WS);
 720         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT == EFX_LOOPBACK_PMA_INT);
 721         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_NEAR == EFX_LOOPBACK_SD_NEAR);
 722         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FAR == EFX_LOOPBACK_SD_FAR);
 723         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT_WS ==
 724             EFX_LOOPBACK_PMA_INT_WS);
 725         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP2_WS ==
 726             EFX_LOOPBACK_SD_FEP2_WS);
 727         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP1_5_WS ==
 728             EFX_LOOPBACK_SD_FEP1_5_WS);
 729         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP_WS == EFX_LOOPBACK_SD_FEP_WS);
 730         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FES_WS == EFX_LOOPBACK_SD_FES_WS);
 731
 732         /* Build bitmask of possible loopback types */
 733         EFX_ZERO_QWORD(mask);
 734
 735         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 736             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 737                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 738         }
 739
 740         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 741             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 742                 /*
 743                  * The "MAC" grouping has historically been used by drivers to
 744                  * mean loopbacks supported by on-chip hardware. Keep that
 745                  * meaning here, and include on-chip PHY layer loopbacks.
 746                  */
 747                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 748                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 749                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 750                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 751                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 752                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 753                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 754                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 755                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 756                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 757                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 758                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 759                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 760                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 761                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 762                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 763         }
 764
 765         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 766             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 767                 /*
 768                  * The "PHY" grouping has historically been used by drivers to
 769                  * mean loopbacks supported by off-chip hardware. Keep that
 770                  * meaning here.
 771                  */
 772                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 773                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 774                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 775                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 776         }
 777
 778         *maskp = mask;
 779 }
 780
 781         __checkReturn   efx_rc_t
 782 efx_mcdi_get_loopback_modes(
 783         __in            efx_nic_t *enp)
 784 {
 785         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 786         efx_mcdi_req_t req;
 787         uint8_t payload[MAX(MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 788                             MC_CMD_GET_LOOPBACK_MODES_OUT_LEN)];
 789         efx_qword_t mask;
 790         efx_qword_t modes;
 791         efx_rc_t rc;
 792
 793         (void) memset(payload, 0, sizeof (payload));
 794         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 795         req.emr_in_buf = payload;
 796         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 797         req.emr_out_buf = payload;
 798         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_LEN;
 799
 800         efx_mcdi_execute(enp, &req);
 801
 802         if (req.emr_rc != 0) {
 803                 rc = req.emr_rc;
 804                 goto fail1;
 805         }
 806
 807         if (req.emr_out_length_used <
 808             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 809             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 810                 rc = EMSGSIZE;
 811                 goto fail2;
 812         }
 813
 814         /*
 815          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 816          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 817          */
 818         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 819
 820         EFX_AND_QWORD(mask,
 821             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 822
 823         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 824         EFX_AND_QWORD(modes, mask);
 825         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 826
 827         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 828         EFX_AND_QWORD(modes, mask);
 829         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 830
 831         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 832         EFX_AND_QWORD(modes, mask);
 833         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 834
 835         if (req.emr_out_length_used >=
 836             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 837             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 838                 /* Response includes 40G loopback modes */
 839                 modes =
 840                     *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_40G);
 841                 EFX_AND_QWORD(modes, mask);
 842                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 843         }
 844
 845         EFX_ZERO_QWORD(modes);
 846         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
 847         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
 848         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
 849         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
 850         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
 851         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
 852
 853         return (0);
 854
 855 fail2:
 856         EFSYS_PROBE(fail2);
 857 fail1:
 858         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 859
 860         return (rc);
 861 }
 862
 863 #endif /* EFSYS_OPT_LOOPBACK */
 864
 865         __checkReturn   efx_rc_t
 866 efx_nic_calculate_pcie_link_bandwidth(
 867         __in            uint32_t pcie_link_width,
 868         __in            uint32_t pcie_link_gen,
 869         __out           uint32_t *bandwidth_mbpsp)
 870 {
 871         uint32_t lane_bandwidth;
 872         uint32_t total_bandwidth;
 873         efx_rc_t rc;
 874
 875         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
 876             !ISP2(pcie_link_width)) {
 877                 rc = EINVAL;
 878                 goto fail1;
 879         }
 880
 881         switch (pcie_link_gen) {
 882         case EFX_PCIE_LINK_SPEED_GEN1:
 883                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
 884                 lane_bandwidth = 2000;
 885                 break;
 886         case EFX_PCIE_LINK_SPEED_GEN2:
 887                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
 888                 lane_bandwidth = 4000;
 889                 break;
 890         case EFX_PCIE_LINK_SPEED_GEN3:
 891                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
 892                 lane_bandwidth = 7877;
 893                 break;
 894         default:
 895                 rc = EINVAL;
 896                 goto fail2;
 897         }
 898
 899         total_bandwidth = lane_bandwidth * pcie_link_width;
 900         *bandwidth_mbpsp = total_bandwidth;
 901
 902         return (0);
 903
 904 fail2:
 905         EFSYS_PROBE(fail2);
 906 fail1:
 907         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 908
 909         return (rc);
 910 }
 911
 912
 913         __checkReturn   efx_rc_t
 914 efx_nic_check_pcie_link_speed(
 915         __in            efx_nic_t *enp,
 916         __in            uint32_t pcie_link_width,
 917         __in            uint32_t pcie_link_gen,
 918         __out           efx_pcie_link_performance_t *resultp)
 919 {
 920         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 921         uint32_t bandwidth;
 922         efx_pcie_link_performance_t result;
 923         efx_rc_t rc;
 924
 925         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
 926             (pcie_link_width == 0) || (pcie_link_width == 32) ||
 927             (pcie_link_gen == 0)) {
 928                 /*
 929                  * No usable info on what is required and/or in use. In virtual
 930                  * machines, sometimes the PCIe link width is reported as 0 or
 931                  * 32, or the speed as 0.
 932                  */
 933                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
 934                 goto out;
 935         }
 936
 937         /* Calculate the available bandwidth in megabits per second */
 938         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
 939                                             pcie_link_gen, &bandwidth);
 940         if (rc != 0)
 941                 goto fail1;
 942
 943         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
 944                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
 945         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
 946                 /* The link provides enough bandwidth but not optimal latency */
 947                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
 948         } else {
 949                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
 950         }
 951
 952 out:
 953         *resultp = result;
 954
 955         return (0);
 956
 957 fail1:
 958         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 959
 960         return (rc);
 961 }