2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
39 static const efx_phy_ops_t __efx_phy_siena_ops = {
40 siena_phy_power, /* epo_power */
42 siena_phy_reconfigure, /* epo_reconfigure */
43 siena_phy_verify, /* epo_verify */
44 siena_phy_oui_get, /* epo_oui_get */
45 #if EFSYS_OPT_PHY_STATS
46 siena_phy_stats_update, /* epo_stats_update */
47 #endif /* EFSYS_OPT_PHY_STATS */
49 NULL, /* epo_bist_enable_offline */
50 siena_phy_bist_start, /* epo_bist_start */
51 siena_phy_bist_poll, /* epo_bist_poll */
52 siena_phy_bist_stop, /* epo_bist_stop */
53 #endif /* EFSYS_OPT_BIST */
55 #endif /* EFSYS_OPT_SIENA */
57 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
58 static const efx_phy_ops_t __efx_phy_ef10_ops = {
59 ef10_phy_power, /* epo_power */
61 ef10_phy_reconfigure, /* epo_reconfigure */
62 ef10_phy_verify, /* epo_verify */
63 ef10_phy_oui_get, /* epo_oui_get */
64 #if EFSYS_OPT_PHY_STATS
65 ef10_phy_stats_update, /* epo_stats_update */
66 #endif /* EFSYS_OPT_PHY_STATS */
68 ef10_bist_enable_offline, /* epo_bist_enable_offline */
69 ef10_bist_start, /* epo_bist_start */
70 ef10_bist_poll, /* epo_bist_poll */
71 ef10_bist_stop, /* epo_bist_stop */
72 #endif /* EFSYS_OPT_BIST */
74 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
76 __checkReturn efx_rc_t
80 efx_port_t *epp = &(enp->en_port);
81 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
82 const efx_phy_ops_t *epop;
85 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
87 epp->ep_port = encp->enc_port;
88 epp->ep_phy_type = encp->enc_phy_type;
90 /* Hook in operations structure */
91 switch (enp->en_family) {
93 case EFX_FAMILY_SIENA:
94 epop = &__efx_phy_siena_ops;
96 #endif /* EFSYS_OPT_SIENA */
97 #if EFSYS_OPT_HUNTINGTON
98 case EFX_FAMILY_HUNTINGTON:
99 epop = &__efx_phy_ef10_ops;
101 #endif /* EFSYS_OPT_HUNTINGTON */
102 #if EFSYS_OPT_MEDFORD
103 case EFX_FAMILY_MEDFORD:
104 epop = &__efx_phy_ef10_ops;
106 #endif /* EFSYS_OPT_MEDFORD */
117 EFSYS_PROBE1(fail1, efx_rc_t, rc);
120 epp->ep_phy_type = 0;
125 __checkReturn efx_rc_t
129 efx_port_t *epp = &(enp->en_port);
130 const efx_phy_ops_t *epop = epp->ep_epop;
132 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
133 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
135 return (epop->epo_verify(enp));
138 #if EFSYS_OPT_PHY_LED_CONTROL
140 __checkReturn efx_rc_t
143 __in efx_phy_led_mode_t mode)
145 efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
146 efx_port_t *epp = &(enp->en_port);
147 const efx_phy_ops_t *epop = epp->ep_epop;
151 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
152 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
154 if (epp->ep_phy_led_mode == mode)
157 mask = (1 << EFX_PHY_LED_DEFAULT);
158 mask |= encp->enc_led_mask;
160 if (!((1 << mode) & mask)) {
165 EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
166 epp->ep_phy_led_mode = mode;
168 if ((rc = epop->epo_reconfigure(enp)) != 0)
177 EFSYS_PROBE1(fail1, efx_rc_t, rc);
181 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
187 __out uint32_t *maskp)
189 efx_port_t *epp = &(enp->en_port);
191 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
192 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
195 case EFX_PHY_CAP_CURRENT:
196 *maskp = epp->ep_adv_cap_mask;
198 case EFX_PHY_CAP_DEFAULT:
199 *maskp = epp->ep_default_adv_cap_mask;
201 case EFX_PHY_CAP_PERM:
202 *maskp = epp->ep_phy_cap_mask;
205 EFSYS_ASSERT(B_FALSE);
210 __checkReturn efx_rc_t
215 efx_port_t *epp = &(enp->en_port);
216 const efx_phy_ops_t *epop = epp->ep_epop;
220 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
221 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
223 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
228 if (epp->ep_adv_cap_mask == mask)
231 old_mask = epp->ep_adv_cap_mask;
232 epp->ep_adv_cap_mask = mask;
234 if ((rc = epop->epo_reconfigure(enp)) != 0)
243 epp->ep_adv_cap_mask = old_mask;
244 /* Reconfigure for robustness */
245 if (epop->epo_reconfigure(enp) != 0) {
247 * We may have an inconsistent view of our advertised speed
254 EFSYS_PROBE1(fail1, efx_rc_t, rc);
262 __out uint32_t *maskp)
264 efx_port_t *epp = &(enp->en_port);
266 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
267 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
269 *maskp = epp->ep_lp_cap_mask;
272 __checkReturn efx_rc_t
275 __out uint32_t *ouip)
277 efx_port_t *epp = &(enp->en_port);
278 const efx_phy_ops_t *epop = epp->ep_epop;
280 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
281 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
283 return (epop->epo_oui_get(enp, ouip));
287 efx_phy_media_type_get(
289 __out efx_phy_media_type_t *typep)
291 efx_port_t *epp = &(enp->en_port);
293 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
294 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
296 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
297 *typep = epp->ep_module_type;
299 *typep = epp->ep_fixed_port_type;
302 __checkReturn efx_rc_t
303 efx_phy_module_get_info(
305 __in uint8_t dev_addr,
308 __out_bcount(len) uint8_t *data)
312 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
313 EFSYS_ASSERT(data != NULL);
315 if ((uint32_t)offset + len > 0xff) {
320 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
321 offset, len, data)) != 0)
329 EFSYS_PROBE1(fail1, efx_rc_t, rc);
334 #if EFSYS_OPT_PHY_STATS
338 /* START MKCONFIG GENERATED PhyStatNamesBlock af9ffa24da3bc100 */
339 static const char * const __efx_phy_stat_name[] = {
388 /* END MKCONFIG GENERATED PhyStatNamesBlock */
393 __in efx_phy_stat_t type)
395 _NOTE(ARGUNUSED(enp))
396 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
397 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
399 return (__efx_phy_stat_name[type]);
402 #endif /* EFSYS_OPT_NAMES */
404 __checkReturn efx_rc_t
405 efx_phy_stats_update(
407 __in efsys_mem_t *esmp,
408 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
410 efx_port_t *epp = &(enp->en_port);
411 const efx_phy_ops_t *epop = epp->ep_epop;
413 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
414 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
416 return (epop->epo_stats_update(enp, esmp, stat));
419 #endif /* EFSYS_OPT_PHY_STATS */
424 __checkReturn efx_rc_t
425 efx_bist_enable_offline(
428 efx_port_t *epp = &(enp->en_port);
429 const efx_phy_ops_t *epop = epp->ep_epop;
432 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
434 if (epop->epo_bist_enable_offline == NULL) {
439 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
447 EFSYS_PROBE1(fail1, efx_rc_t, rc);
453 __checkReturn efx_rc_t
456 __in efx_bist_type_t type)
458 efx_port_t *epp = &(enp->en_port);
459 const efx_phy_ops_t *epop = epp->ep_epop;
462 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
464 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
465 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
466 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
468 if (epop->epo_bist_start == NULL) {
473 if ((rc = epop->epo_bist_start(enp, type)) != 0)
476 epp->ep_current_bist = type;
483 EFSYS_PROBE1(fail1, efx_rc_t, rc);
488 __checkReturn efx_rc_t
491 __in efx_bist_type_t type,
492 __out efx_bist_result_t *resultp,
493 __out_opt uint32_t *value_maskp,
494 __out_ecount_opt(count) unsigned long *valuesp,
497 efx_port_t *epp = &(enp->en_port);
498 const efx_phy_ops_t *epop = epp->ep_epop;
501 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
503 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
504 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
505 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
507 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
508 if (epop->epo_bist_poll == NULL) {
513 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
514 valuesp, count)) != 0)
522 EFSYS_PROBE1(fail1, efx_rc_t, rc);
530 __in efx_bist_type_t type)
532 efx_port_t *epp = &(enp->en_port);
533 const efx_phy_ops_t *epop = epp->ep_epop;
535 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
537 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
538 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
539 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
541 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
543 if (epop->epo_bist_stop != NULL)
544 epop->epo_bist_stop(enp, type);
546 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
549 #endif /* EFSYS_OPT_BIST */
554 efx_port_t *epp = &(enp->en_port);
556 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
560 epp->ep_adv_cap_mask = 0;
563 epp->ep_phy_type = 0;