2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
37 #include "falcon_nvram.h"
40 #if EFSYS_OPT_MAC_FALCON_XMAC
41 #include "falcon_xmac.h"
44 #if EFSYS_OPT_MAC_FALCON_GMAC
45 #include "falcon_gmac.h"
48 #if EFSYS_OPT_PHY_NULL
52 #if EFSYS_OPT_PHY_QT2022C2
56 #if EFSYS_OPT_PHY_SFX7101
60 #if EFSYS_OPT_PHY_TXC43128
64 #if EFSYS_OPT_PHY_SFT9001
68 #if EFSYS_OPT_PHY_QT2025C
72 #if EFSYS_OPT_PHY_NULL
73 static efx_phy_ops_t __efx_phy_null_ops = {
75 nullphy_reset, /* epo_reset */
76 nullphy_reconfigure, /* epo_reconfigure */
77 nullphy_verify, /* epo_verify */
78 NULL, /* epo_uplink_check */
79 nullphy_downlink_check, /* epo_downlink_check */
80 nullphy_oui_get, /* epo_oui_get */
81 #if EFSYS_OPT_PHY_STATS
82 nullphy_stats_update, /* epo_stats_update */
83 #endif /* EFSYS_OPT_PHY_STATS */
84 #if EFSYS_OPT_PHY_PROPS
86 nullphy_prop_name, /* epo_prop_name */
88 nullphy_prop_get, /* epo_prop_get */
89 nullphy_prop_set, /* epo_prop_set */
90 #endif /* EFSYS_OPT_PHY_PROPS */
92 NULL, /* epo_bist_enable_offline */
93 NULL, /* epo_bist_start */
94 NULL, /* epo_bist_poll */
95 NULL, /* epo_bist_stop */
96 #endif /* EFSYS_OPT_BIST */
98 #endif /* EFSYS_OPT_PHY_NULL */
100 #if EFSYS_OPT_PHY_QT2022C2
101 static efx_phy_ops_t __efx_phy_qt2022c2_ops = {
102 NULL, /* epo_power */
103 qt2022c2_reset, /* epo_reset */
104 qt2022c2_reconfigure, /* epo_reconfigure */
105 qt2022c2_verify, /* epo_verify */
106 qt2022c2_uplink_check, /* epo_uplink_check */
107 qt2022c2_downlink_check, /* epo_downlink_check */
108 qt2022c2_oui_get, /* epo_oui_get */
109 #if EFSYS_OPT_PHY_STATS
110 qt2022c2_stats_update, /* epo_stats_update */
111 #endif /* EFSYS_OPT_PHY_STATS */
112 #if EFSYS_OPT_PHY_PROPS
114 qt2022c2_prop_name, /* epo_prop_name */
116 qt2022c2_prop_get, /* epo_prop_get */
117 qt2022c2_prop_set, /* epo_prop_set */
118 #endif /* EFSYS_OPT_PHY_PROPS */
120 NULL, /* epo_bist_enable_offline */
121 NULL, /* epo_bist_start */
122 NULL, /* epo_bist_poll */
123 NULL, /* epo_bist_stop */
124 #endif /* EFSYS_OPT_BIST */
126 #endif /* EFSYS_OPT_PHY_QT2022C2 */
128 #if EFSYS_OPT_PHY_SFX7101
129 static efx_phy_ops_t __efx_phy_sfx7101_ops = {
130 sfx7101_power, /* epo_power */
131 sfx7101_reset, /* epo_reset */
132 sfx7101_reconfigure, /* epo_reconfigure */
133 sfx7101_verify, /* epo_verify */
134 sfx7101_uplink_check, /* epo_uplink_check */
135 sfx7101_downlink_check, /* epo_downlink_check */
136 sfx7101_oui_get, /* epo_oui_get */
137 #if EFSYS_OPT_PHY_STATS
138 sfx7101_stats_update, /* epo_stats_update */
139 #endif /* EFSYS_OPT_PHY_STATS */
140 #if EFSYS_OPT_PHY_PROPS
142 sfx7101_prop_name, /* epo_prop_name */
144 sfx7101_prop_get, /* epo_prop_get */
145 sfx7101_prop_set, /* epo_prop_set */
146 #endif /* EFSYS_OPT_PHY_PROPS */
148 NULL, /* epo_bist_enable_offline */
149 NULL, /* epo_bist_start */
150 NULL, /* epo_bist_poll */
151 NULL, /* epo_bist_stop */
152 #endif /* EFSYS_OPT_BIST */
154 #endif /* EFSYS_OPT_PHY_SFX7101 */
156 #if EFSYS_OPT_PHY_TXC43128
157 static efx_phy_ops_t __efx_phy_txc43128_ops = {
158 NULL, /* epo_power */
159 txc43128_reset, /* epo_reset */
160 txc43128_reconfigure, /* epo_reconfigure */
161 txc43128_verify, /* epo_verify */
162 txc43128_uplink_check, /* epo_uplink_check */
163 txc43128_downlink_check, /* epo_downlink_check */
164 txc43128_oui_get, /* epo_oui_get */
165 #if EFSYS_OPT_PHY_STATS
166 txc43128_stats_update, /* epo_stats_update */
167 #endif /* EFSYS_OPT_PHY_STATS */
168 #if EFSYS_OPT_PHY_PROPS
170 txc43128_prop_name, /* epo_prop_name */
172 txc43128_prop_get, /* epo_prop_get */
173 txc43128_prop_set, /* epo_prop_set */
174 #endif /* EFSYS_OPT_PHY_PROPS */
176 NULL, /* epo_bist_enable_offline */
177 NULL, /* epo_bist_start */
178 NULL, /* epo_bist_poll */
179 NULL, /* epo_bist_stop */
180 #endif /* EFSYS_OPT_BIST */
182 #endif /* EFSYS_OPT_PHY_TXC43128 */
184 #if EFSYS_OPT_PHY_SFT9001
185 static efx_phy_ops_t __efx_phy_sft9001_ops = {
186 NULL, /* epo_power */
187 sft9001_reset, /* epo_reset */
188 sft9001_reconfigure, /* epo_reconfigure */
189 sft9001_verify, /* epo_verify */
190 sft9001_uplink_check, /* epo_uplink_check */
191 sft9001_downlink_check, /* epo_downlink_check */
192 sft9001_oui_get, /* epo_oui_get */
193 #if EFSYS_OPT_PHY_STATS
194 sft9001_stats_update, /* epo_stats_update */
195 #endif /* EFSYS_OPT_PHY_STATS */
196 #if EFSYS_OPT_PHY_PROPS
198 sft9001_prop_name, /* epo_prop_name */
200 sft9001_prop_get, /* epo_prop_get */
201 sft9001_prop_set, /* epo_prop_set */
202 #endif /* EFSYS_OPT_PHY_PROPS */
204 NULL, /* epo_bist_enable_offline */
205 sft9001_bist_start, /* epo_bist_start */
206 sft9001_bist_poll, /* epo_bist_poll */
207 sft9001_bist_stop, /* epo_bist_stop */
208 #endif /* EFSYS_OPT_BIST */
210 #endif /* EFSYS_OPT_PHY_SFT9001 */
212 #if EFSYS_OPT_PHY_QT2025C
213 static efx_phy_ops_t __efx_phy_qt2025c_ops = {
214 NULL, /* epo_power */
215 qt2025c_reset, /* epo_reset */
216 qt2025c_reconfigure, /* epo_reconfigure */
217 qt2025c_verify, /* epo_verify */
218 qt2025c_uplink_check, /* epo_uplink_check */
219 qt2025c_downlink_check, /* epo_downlink_check */
220 qt2025c_oui_get, /* epo_oui_get */
221 #if EFSYS_OPT_PHY_STATS
222 qt2025c_stats_update, /* epo_stats_update */
223 #endif /* EFSYS_OPT_PHY_STATS */
224 #if EFSYS_OPT_PHY_PROPS
226 qt2025c_prop_name, /* epo_prop_name */
228 qt2025c_prop_get, /* epo_prop_get */
229 qt2025c_prop_set, /* epo_prop_set */
230 #endif /* EFSYS_OPT_PHY_PROPS */
232 NULL, /* epo_bist_enable_offline */
233 NULL, /* epo_bist_start */
234 NULL, /* epo_bist_poll */
235 NULL, /* epo_bist_stop */
236 #endif /* EFSYS_OPT_BIST */
238 #endif /* EFSYS_OPT_PHY_QT2025C */
241 static efx_phy_ops_t __efx_phy_siena_ops = {
242 siena_phy_power, /* epo_power */
243 NULL, /* epo_reset */
244 siena_phy_reconfigure, /* epo_reconfigure */
245 siena_phy_verify, /* epo_verify */
246 NULL, /* epo_uplink_check */
247 NULL, /* epo_downlink_check */
248 siena_phy_oui_get, /* epo_oui_get */
249 #if EFSYS_OPT_PHY_STATS
250 siena_phy_stats_update, /* epo_stats_update */
251 #endif /* EFSYS_OPT_PHY_STATS */
252 #if EFSYS_OPT_PHY_PROPS
254 siena_phy_prop_name, /* epo_prop_name */
256 siena_phy_prop_get, /* epo_prop_get */
257 siena_phy_prop_set, /* epo_prop_set */
258 #endif /* EFSYS_OPT_PHY_PROPS */
260 NULL, /* epo_bist_enable_offline */
261 siena_phy_bist_start, /* epo_bist_start */
262 siena_phy_bist_poll, /* epo_bist_poll */
263 siena_phy_bist_stop, /* epo_bist_stop */
264 #endif /* EFSYS_OPT_BIST */
266 #endif /* EFSYS_OPT_SIENA */
268 #if EFSYS_OPT_HUNTINGTON
269 static efx_phy_ops_t __efx_phy_hunt_ops = {
270 hunt_phy_power, /* epo_power */
271 NULL, /* epo_reset */
272 hunt_phy_reconfigure, /* epo_reconfigure */
273 hunt_phy_verify, /* epo_verify */
274 NULL, /* epo_uplink_check */
275 NULL, /* epo_downlink_check */
276 hunt_phy_oui_get, /* epo_oui_get */
277 #if EFSYS_OPT_PHY_STATS
278 hunt_phy_stats_update, /* epo_stats_update */
279 #endif /* EFSYS_OPT_PHY_STATS */
280 #if EFSYS_OPT_PHY_PROPS
282 hunt_phy_prop_name, /* epo_prop_name */
284 hunt_phy_prop_get, /* epo_prop_get */
285 hunt_phy_prop_set, /* epo_prop_set */
286 #endif /* EFSYS_OPT_PHY_PROPS */
288 hunt_bist_enable_offline, /* epo_bist_enable_offline */
289 hunt_bist_start, /* epo_bist_start */
290 hunt_bist_poll, /* epo_bist_poll */
291 hunt_bist_stop, /* epo_bist_stop */
292 #endif /* EFSYS_OPT_BIST */
294 #endif /* EFSYS_OPT_HUNTINGTON */
296 __checkReturn efx_rc_t
300 efx_port_t *epp = &(enp->en_port);
301 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
305 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
307 epp->ep_port = encp->enc_port;
308 epp->ep_phy_type = encp->enc_phy_type;
310 /* Hook in operations structure */
311 switch (enp->en_family) {
313 case EFX_FAMILY_FALCON:
314 switch (epp->ep_phy_type) {
315 #if EFSYS_OPT_PHY_NULL
316 case PHY_TYPE_NONE_DECODE:
317 epop = (efx_phy_ops_t *)&__efx_phy_null_ops;
320 #if EFSYS_OPT_PHY_QT2022C2
321 case PHY_TYPE_QT2022C2_DECODE:
322 epop = (efx_phy_ops_t *)&__efx_phy_qt2022c2_ops;
325 #if EFSYS_OPT_PHY_SFX7101
326 case PHY_TYPE_SFX7101_DECODE:
327 epop = (efx_phy_ops_t *)&__efx_phy_sfx7101_ops;
330 #if EFSYS_OPT_PHY_TXC43128
331 case PHY_TYPE_TXC43128_DECODE:
332 epop = (efx_phy_ops_t *)&__efx_phy_txc43128_ops;
335 #if EFSYS_OPT_PHY_SFT9001
336 case PHY_TYPE_SFT9001A_DECODE:
337 case PHY_TYPE_SFT9001B_DECODE:
338 epop = (efx_phy_ops_t *)&__efx_phy_sft9001_ops;
341 #if EFSYS_OPT_PHY_QT2025C
342 case EFX_PHY_QT2025C:
343 epop = (efx_phy_ops_t *)&__efx_phy_qt2025c_ops;
351 #endif /* EFSYS_OPT_FALCON */
353 case EFX_FAMILY_SIENA:
354 epop = (efx_phy_ops_t *)&__efx_phy_siena_ops;
356 #endif /* EFSYS_OPT_SIENA */
357 #if EFSYS_OPT_HUNTINGTON
358 case EFX_FAMILY_HUNTINGTON:
359 epop = (efx_phy_ops_t *)&__efx_phy_hunt_ops;
361 #endif /* EFSYS_OPT_HUNTINGTON */
372 EFSYS_PROBE1(fail1, efx_rc_t, rc);
375 epp->ep_phy_type = 0;
380 __checkReturn efx_rc_t
384 efx_port_t *epp = &(enp->en_port);
385 efx_phy_ops_t *epop = epp->ep_epop;
387 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
388 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
390 return (epop->epo_verify(enp));
393 #if EFSYS_OPT_PHY_LED_CONTROL
395 __checkReturn efx_rc_t
398 __in efx_phy_led_mode_t mode)
400 efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
401 efx_port_t *epp = &(enp->en_port);
402 efx_phy_ops_t *epop = epp->ep_epop;
406 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
407 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
409 if (epp->ep_phy_led_mode == mode)
412 mask = (1 << EFX_PHY_LED_DEFAULT);
413 mask |= encp->enc_led_mask;
415 if (!((1 << mode) & mask)) {
420 EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
421 epp->ep_phy_led_mode = mode;
423 if ((rc = epop->epo_reconfigure(enp)) != 0)
432 EFSYS_PROBE1(fail1, efx_rc_t, rc);
436 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
442 __out uint32_t *maskp)
444 efx_port_t *epp = &(enp->en_port);
446 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
447 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
450 case EFX_PHY_CAP_CURRENT:
451 *maskp = epp->ep_adv_cap_mask;
453 case EFX_PHY_CAP_DEFAULT:
454 *maskp = epp->ep_default_adv_cap_mask;
456 case EFX_PHY_CAP_PERM:
457 *maskp = epp->ep_phy_cap_mask;
460 EFSYS_ASSERT(B_FALSE);
465 __checkReturn efx_rc_t
470 efx_port_t *epp = &(enp->en_port);
471 efx_phy_ops_t *epop = epp->ep_epop;
475 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
476 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
478 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
483 if (epp->ep_adv_cap_mask == mask)
486 old_mask = epp->ep_adv_cap_mask;
487 epp->ep_adv_cap_mask = mask;
489 if ((rc = epop->epo_reconfigure(enp)) != 0)
498 epp->ep_adv_cap_mask = old_mask;
499 /* Reconfigure for robustness */
500 if (epop->epo_reconfigure(enp) != 0) {
502 * We may have an inconsistent view of our advertised speed
509 EFSYS_PROBE1(fail1, efx_rc_t, rc);
517 __out uint32_t *maskp)
519 efx_port_t *epp = &(enp->en_port);
521 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
522 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
524 *maskp = epp->ep_lp_cap_mask;
527 __checkReturn efx_rc_t
530 __out uint32_t *ouip)
532 efx_port_t *epp = &(enp->en_port);
533 efx_phy_ops_t *epop = epp->ep_epop;
535 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
536 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
538 return (epop->epo_oui_get(enp, ouip));
542 efx_phy_media_type_get(
544 __out efx_phy_media_type_t *typep)
546 efx_port_t *epp = &(enp->en_port);
548 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
549 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
551 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
552 *typep = epp->ep_module_type;
554 *typep = epp->ep_fixed_port_type;
557 #if EFSYS_OPT_PHY_STATS
561 /* START MKCONFIG GENERATED PhyStatNamesBlock d5f79b4bc2c050fe */
562 static const char *__efx_phy_stat_name[] = {
611 /* END MKCONFIG GENERATED PhyStatNamesBlock */
616 __in efx_phy_stat_t type)
618 _NOTE(ARGUNUSED(enp))
619 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
620 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
622 return (__efx_phy_stat_name[type]);
625 #endif /* EFSYS_OPT_NAMES */
627 __checkReturn efx_rc_t
628 efx_phy_stats_update(
630 __in efsys_mem_t *esmp,
631 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
633 efx_port_t *epp = &(enp->en_port);
634 efx_phy_ops_t *epop = epp->ep_epop;
636 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
637 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
639 return (epop->epo_stats_update(enp, esmp, stat));
642 #endif /* EFSYS_OPT_PHY_STATS */
644 #if EFSYS_OPT_PHY_PROPS
650 __in unsigned int id)
652 efx_port_t *epp = &(enp->en_port);
653 efx_phy_ops_t *epop = epp->ep_epop;
655 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
656 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
658 return (epop->epo_prop_name(enp, id));
660 #endif /* EFSYS_OPT_NAMES */
662 __checkReturn efx_rc_t
665 __in unsigned int id,
667 __out uint32_t *valp)
669 efx_port_t *epp = &(enp->en_port);
670 efx_phy_ops_t *epop = epp->ep_epop;
672 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
673 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
675 return (epop->epo_prop_get(enp, id, flags, valp));
678 __checkReturn efx_rc_t
681 __in unsigned int id,
684 efx_port_t *epp = &(enp->en_port);
685 efx_phy_ops_t *epop = epp->ep_epop;
687 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
688 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
690 return (epop->epo_prop_set(enp, id, val));
692 #endif /* EFSYS_OPT_PHY_STATS */
696 __checkReturn efx_rc_t
697 efx_bist_enable_offline(
700 efx_port_t *epp = &(enp->en_port);
701 efx_phy_ops_t *epop = epp->ep_epop;
704 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
706 if (epop->epo_bist_enable_offline == NULL) {
711 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
719 EFSYS_PROBE1(fail1, efx_rc_t, rc);
725 __checkReturn efx_rc_t
728 __in efx_bist_type_t type)
730 efx_port_t *epp = &(enp->en_port);
731 efx_phy_ops_t *epop = epp->ep_epop;
734 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
736 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
737 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
738 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
740 if (epop->epo_bist_start == NULL) {
745 if ((rc = epop->epo_bist_start(enp, type)) != 0)
748 epp->ep_current_bist = type;
755 EFSYS_PROBE1(fail1, efx_rc_t, rc);
760 __checkReturn efx_rc_t
763 __in efx_bist_type_t type,
764 __out efx_bist_result_t *resultp,
765 __out_opt uint32_t *value_maskp,
766 __out_ecount_opt(count) unsigned long *valuesp,
769 efx_port_t *epp = &(enp->en_port);
770 efx_phy_ops_t *epop = epp->ep_epop;
773 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
775 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
776 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
777 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
779 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
780 if (epop->epo_bist_poll == NULL) {
785 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
786 valuesp, count)) != 0)
794 EFSYS_PROBE1(fail1, efx_rc_t, rc);
802 __in efx_bist_type_t type)
804 efx_port_t *epp = &(enp->en_port);
805 efx_phy_ops_t *epop = epp->ep_epop;
807 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
809 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
810 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
811 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
813 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
815 if (epop->epo_bist_stop != NULL)
816 epop->epo_bist_stop(enp, type);
818 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
821 #endif /* EFSYS_OPT_BIST */
826 efx_port_t *epp = &(enp->en_port);
828 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
832 epp->ep_adv_cap_mask = 0;
835 epp->ep_phy_type = 0;