2 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved.
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5 * modification, are permitted provided that the following conditions
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28 #ifndef _SIENA_MC_DRIVER_PCOL_H
29 #define _SIENA_MC_DRIVER_PCOL_H
32 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
33 /* Power-on reset state */
34 #define MC_FW_STATE_POR (1)
35 /* If this is set in MC_RESET_STATE_REG then it should be
36 * possible to jump into IMEM without loading code from flash. */
37 #define MC_FW_WARM_BOOT_OK (2)
38 /* The MC main image has started to boot. */
39 #define MC_FW_STATE_BOOTING (4)
40 /* The Scheduler has started. */
41 #define MC_FW_STATE_SCHED (8)
42 /* If this is set in MC_RESET_STATE_REG then it should be
43 * possible to jump into IMEM without loading code from flash.
44 * Unlike a warm boot, assume DMEM has been reloaded, so that
45 * the MC persistent data must be reinitialised. */
46 #define MC_FW_TEPID_BOOT_OK (16)
47 /* We have entered the main firmware via recovery mode. This
48 * means that MC persistent data must be reinitialised, but that
49 * we shouldn't touch PCIe config. */
50 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)
51 /* BIST state has been initialized */
52 #define MC_FW_BIST_INIT_OK (128)
54 /* Siena MC shared memmory offsets */
55 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
56 #define MC_SMEM_P0_DOORBELL_OFST 0x000
57 #define MC_SMEM_P1_DOORBELL_OFST 0x004
58 /* The rest of these are firmware-defined */
59 #define MC_SMEM_P0_PDU_OFST 0x008
60 #define MC_SMEM_P1_PDU_OFST 0x108
61 #define MC_SMEM_PDU_LEN 0x100
62 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
63 #define MC_SMEM_P0_STATUS_OFST 0x7f8
64 #define MC_SMEM_P1_STATUS_OFST 0x7fc
66 /* Values to be written to the per-port status dword in shared
67 * memory on reboot and assert */
68 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
69 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
71 /* Check whether an mcfw version (in host order) belongs to a bootloader */
72 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
74 /* The current version of the MCDI protocol.
76 * Note that the ROM burnt into the card only talks V0, so at the very
77 * least every driver must support version 0 and MCDI_PCOL_VERSION
80 #define MCDI_PCOL_VERSION 2
82 #define MCDI_PCOL_VERSION 1
85 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
89 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
90 * structure, filled in by the client.
92 * 0 7 8 16 20 22 23 24 31
93 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
97 * \------------------------------ Resync (always set)
99 * The client writes it's request into MC shared memory, and rings the
100 * doorbell. Each request is completed by either by the MC writting
101 * back into shared memory, or by writting out an event.
103 * All MCDI commands support completion by shared memory response. Each
104 * request may also contain additional data (accounted for by HEADER.LEN),
105 * and some response's may also contain additional data (again, accounted
106 * for by HEADER.LEN).
108 * Some MCDI commands support completion by event, in which any associated
109 * response data is included in the event.
111 * The protocol requires one response to be delivered for every request, a
112 * request should not be sent unless the response for the previous request
113 * has been received (either by polling shared memory, or by receiving
117 /** Request/Response structure */
118 #define MCDI_HEADER_OFST 0
119 #define MCDI_HEADER_CODE_LBN 0
120 #define MCDI_HEADER_CODE_WIDTH 7
121 #define MCDI_HEADER_RESYNC_LBN 7
122 #define MCDI_HEADER_RESYNC_WIDTH 1
123 #define MCDI_HEADER_DATALEN_LBN 8
124 #define MCDI_HEADER_DATALEN_WIDTH 8
125 #define MCDI_HEADER_SEQ_LBN 16
126 #define MCDI_HEADER_SEQ_WIDTH 4
127 #define MCDI_HEADER_RSVD_LBN 20
128 #define MCDI_HEADER_RSVD_WIDTH 1
129 #define MCDI_HEADER_NOT_EPOCH_LBN 21
130 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1
131 #define MCDI_HEADER_ERROR_LBN 22
132 #define MCDI_HEADER_ERROR_WIDTH 1
133 #define MCDI_HEADER_RESPONSE_LBN 23
134 #define MCDI_HEADER_RESPONSE_WIDTH 1
135 #define MCDI_HEADER_XFLAGS_LBN 24
136 #define MCDI_HEADER_XFLAGS_WIDTH 8
137 /* Request response using event */
138 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
140 /* Maximum number of payload bytes */
141 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
142 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400
145 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
147 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1
151 /* The MC can generate events for two reasons:
152 * - To complete a shared memory request if XFLAGS_EVREQ was set
153 * - As a notification (link state, i2c event), controlled
154 * via MC_CMD_LOG_CTRL
156 * Both events share a common structure:
158 * 0 32 33 36 44 52 60
159 * | Data | Cont | Level | Src | Code | Rsvd |
161 * \ There is another event pending in this notification
163 * If Code==CMDDONE, then the fields are further interpreted as:
165 * - LEVEL==INFO Command succeeded
166 * - LEVEL==ERR Command failed
169 * | Seq | Datalen | Errno | Rsvd |
171 * These fields are taken directly out of the standard MCDI header, i.e.,
172 * LEVEL==ERR, Datalen == 0 => Reboot
174 * Events can be squirted out of the UART (using LOG_CTRL) without a
175 * MCDI header. An event can be distinguished from a MCDI response by
176 * examining the first byte which is 0xc0. This corresponds to the
177 * non-existent MCDI command MC_CMD_DEBUG_LOG.
180 * | command | Resync | = 0xc0
182 * Since the event is written in big-endian byte order, this works
183 * providing bits 56-63 of the event are 0xc0.
186 * | Rsvd | Code | = 0xc0
188 * Which means for convenience the event code is 0xc for all MC
191 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
194 /* Operation not permitted. */
195 #define MC_CMD_ERR_EPERM 1
196 /* Non-existent command target */
197 #define MC_CMD_ERR_ENOENT 2
198 /* assert() has killed the MC */
199 #define MC_CMD_ERR_EINTR 4
201 #define MC_CMD_ERR_EIO 5
203 #define MC_CMD_ERR_EEXIST 6
205 #define MC_CMD_ERR_EAGAIN 11
207 #define MC_CMD_ERR_ENOMEM 12
208 /* Caller does not hold required locks */
209 #define MC_CMD_ERR_EACCES 13
210 /* Resource is currently unavailable (e.g. lock contention) */
211 #define MC_CMD_ERR_EBUSY 16
213 #define MC_CMD_ERR_ENODEV 19
214 /* Invalid argument to target */
215 #define MC_CMD_ERR_EINVAL 22
217 #define MC_CMD_ERR_EPIPE 32
219 #define MC_CMD_ERR_EROFS 30
221 #define MC_CMD_ERR_ERANGE 34
222 /* Non-recursive resource is already acquired */
223 #define MC_CMD_ERR_EDEADLK 35
224 /* Operation not implemented */
225 #define MC_CMD_ERR_ENOSYS 38
226 /* Operation timed out */
227 #define MC_CMD_ERR_ETIME 62
228 /* Link has been severed */
229 #define MC_CMD_ERR_ENOLINK 67
231 #define MC_CMD_ERR_EPROTO 71
232 /* Operation not supported */
233 #define MC_CMD_ERR_ENOTSUP 95
234 /* Address not available */
235 #define MC_CMD_ERR_EADDRNOTAVAIL 99
237 #define MC_CMD_ERR_ENOTCONN 107
238 /* Operation already in progress */
239 #define MC_CMD_ERR_EALREADY 114
241 /* Resource allocation failed. */
242 #define MC_CMD_ERR_ALLOC_FAIL 0x1000
243 /* V-adaptor not found. */
244 #define MC_CMD_ERR_NO_VADAPTOR 0x1001
245 /* EVB port not found. */
246 #define MC_CMD_ERR_NO_EVB_PORT 0x1002
247 /* V-switch not found. */
248 #define MC_CMD_ERR_NO_VSWITCH 0x1003
249 /* Too many VLAN tags. */
250 #define MC_CMD_ERR_VLAN_LIMIT 0x1004
251 /* Bad PCI function number. */
252 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
253 /* Invalid VLAN mode. */
254 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
255 /* Invalid v-switch type. */
256 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
257 /* Invalid v-port type. */
258 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
259 /* MAC address exists. */
260 #define MC_CMD_ERR_MAC_EXIST 0x1009
261 /* Slave core not present */
262 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
263 /* The datapath is disabled. */
264 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
265 /* The requesting client is not a function */
266 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c
267 /* The requested operation might require the
268 command to be passed between MCs, and the
269 transport doesn't support that. Should
270 only ever been seen over the UART. */
271 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
272 /* VLAN tag(s) exists */
273 #define MC_CMD_ERR_VLAN_EXIST 0x100e
274 /* No MAC address assigned to an EVB port */
275 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f
276 /* Notifies the driver that the request has been relayed
277 * to an admin function for authorization. The driver should
278 * wait for a PROXY_RESPONSE event and then resend its request.
279 * This error code is followed by a 32-bit handle that
280 * helps matching it with the respective PROXY_RESPONSE event. */
281 #define MC_CMD_ERR_PROXY_PENDING 0x1010
282 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
283 /* The request cannot be passed for authorization because
284 * another request from the same function is currently being
285 * authorized. The drvier should try again later. */
286 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
287 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function
288 * that has enabled proxying or BLOCK_INDEX points to a function that
289 * doesn't await an authorization. */
290 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
291 /* This code is currently only used internally in FW. Its meaning is that
292 * an operation failed due to lack of SR-IOV privilege.
293 * Normally it is translated to EPERM by send_cmd_err(),
294 * but it may also be used to trigger some special mechanism
295 * for handling such case, e.g. to relay the failed request
296 * to a designated admin function for authorization. */
297 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013
298 /* Workaround 26807 could not be turned on/off because some functions
299 * have already installed filters. See the comment at
300 * MC_CMD_WORKAROUND_BUG26807. */
301 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014
302 /* The clock whose frequency you've attempted to set set
303 * doesn't exist on this NIC */
304 #define MC_CMD_ERR_NO_CLOCK 0x1015
306 #define MC_CMD_ERR_CODE_OFST 0
308 /* We define 8 "escape" commands to allow
309 for command number space extension */
311 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
312 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
313 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
314 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
315 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
316 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
317 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
318 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
320 /* Vectors in the boot ROM */
321 /* Point to the copycode entry point. */
322 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
323 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
324 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
325 /* Points to the recovery mode entry point. */
326 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
327 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
328 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
330 /* The command set exported by the boot ROM (MCDI v0) */
331 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \
332 (1 << MC_CMD_READ32) | \
333 (1 << MC_CMD_WRITE32) | \
334 (1 << MC_CMD_COPYCODE) | \
335 (1 << MC_CMD_GET_VERSION), \
338 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
339 (MC_CMD_SENSOR_ENTRY_OFST + (_x))
341 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \
342 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
343 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \
344 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
346 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \
347 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
348 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \
349 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
351 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \
352 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
353 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \
354 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
356 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
357 * stack ID (which must be in the range 1-255) along with an EVB port ID.
359 #define EVB_STACK_ID(n) (((n) & 0xff) << 16)
364 /* Version 2 adds an optional argument to error returns: the errno value
365 * may be followed by the (0-based) number of the first argument that
366 * could not be processed.
368 #define MC_CMD_ERR_ARG_OFST 4
371 #define MC_CMD_ERR_ENOSPC 28
375 /* MCDI_EVENT structuredef */
376 #define MCDI_EVENT_LEN 8
377 #define MCDI_EVENT_CONT_LBN 32
378 #define MCDI_EVENT_CONT_WIDTH 1
379 #define MCDI_EVENT_LEVEL_LBN 33
380 #define MCDI_EVENT_LEVEL_WIDTH 3
382 #define MCDI_EVENT_LEVEL_INFO 0x0
384 #define MCDI_EVENT_LEVEL_WARN 0x1
386 #define MCDI_EVENT_LEVEL_ERR 0x2
388 #define MCDI_EVENT_LEVEL_FATAL 0x3
389 #define MCDI_EVENT_DATA_OFST 0
390 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0
391 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
392 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8
393 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
394 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16
395 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
396 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
397 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
398 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
399 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
401 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
403 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
405 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
407 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
408 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
409 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
410 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
411 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
412 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
413 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
414 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8
415 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
416 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16
417 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
418 #define MCDI_EVENT_FWALERT_DATA_LBN 8
419 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24
420 #define MCDI_EVENT_FWALERT_REASON_LBN 0
421 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8
422 /* enum: SRAM Access. */
423 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
424 #define MCDI_EVENT_FLR_VF_LBN 0
425 #define MCDI_EVENT_FLR_VF_WIDTH 8
426 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0
427 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
428 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12
429 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
430 /* enum: Descriptor loader reported failure */
431 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
432 /* enum: Descriptor ring empty and no EOP seen for packet */
433 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2
434 /* enum: Overlength packet */
435 #define MCDI_EVENT_TX_ERR_2BIG 0x3
436 /* enum: Malformed option descriptor */
437 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5
438 /* enum: Option descriptor part way through a packet */
439 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8
440 /* enum: DMA or PIO data access error */
441 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
442 #define MCDI_EVENT_TX_ERR_INFO_LBN 16
443 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16
444 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
445 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
446 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
447 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
448 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
449 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
450 /* enum: PLL lost lock */
451 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
452 /* enum: Filter overflow (PDMA) */
453 #define MCDI_EVENT_PTP_ERR_FILTER 0x2
454 /* enum: FIFO overflow (FPGA) */
455 #define MCDI_EVENT_PTP_ERR_FIFO 0x3
456 /* enum: Merge queue overflow */
457 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4
458 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
459 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
460 /* enum: AOE failed to load - no valid image? */
461 #define MCDI_EVENT_AOE_NO_LOAD 0x1
462 /* enum: AOE FC reported an exception */
463 #define MCDI_EVENT_AOE_FC_ASSERT 0x2
464 /* enum: AOE FC watchdogged */
465 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
466 /* enum: AOE FC failed to start */
467 #define MCDI_EVENT_AOE_FC_NO_START 0x4
468 /* enum: Generic AOE fault - likely to have been reported via other means too
469 * but intended for use by aoex driver.
471 #define MCDI_EVENT_AOE_FAULT 0x5
472 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
473 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
474 /* enum: AOE loaded successfully */
475 #define MCDI_EVENT_AOE_LOAD 0x7
476 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
477 #define MCDI_EVENT_AOE_DMA 0x8
478 /* enum: AOE byteblaster connected/disconnected (Connection status in
481 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9
482 /* enum: DDR ECC status update */
483 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
484 /* enum: PTP status update */
485 #define MCDI_EVENT_AOE_PTP_STATUS 0xb
486 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8
487 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
488 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0
489 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
490 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12
491 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
492 #define MCDI_EVENT_RX_ERR_INFO_LBN 16
493 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16
494 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
495 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
496 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
497 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
498 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
499 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
500 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0
501 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8
502 /* enum: MUM failed to load - no valid image? */
503 #define MCDI_EVENT_MUM_NO_LOAD 0x1
504 /* enum: MUM f/w reported an exception */
505 #define MCDI_EVENT_MUM_ASSERT 0x2
506 /* enum: MUM not kicking watchdog */
507 #define MCDI_EVENT_MUM_WATCHDOG 0x3
508 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8
509 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8
510 #define MCDI_EVENT_DATA_LBN 0
511 #define MCDI_EVENT_DATA_WIDTH 32
512 #define MCDI_EVENT_SRC_LBN 36
513 #define MCDI_EVENT_SRC_WIDTH 8
514 #define MCDI_EVENT_EV_CODE_LBN 60
515 #define MCDI_EVENT_EV_CODE_WIDTH 4
516 #define MCDI_EVENT_CODE_LBN 44
517 #define MCDI_EVENT_CODE_WIDTH 8
518 /* enum: Event generated by host software */
519 #define MCDI_EVENT_SW_EVENT 0x0
520 /* enum: Bad assert. */
521 #define MCDI_EVENT_CODE_BADSSERT 0x1
522 /* enum: PM Notice. */
523 #define MCDI_EVENT_CODE_PMNOTICE 0x2
524 /* enum: Command done. */
525 #define MCDI_EVENT_CODE_CMDDONE 0x3
526 /* enum: Link change. */
527 #define MCDI_EVENT_CODE_LINKCHANGE 0x4
528 /* enum: Sensor Event. */
529 #define MCDI_EVENT_CODE_SENSOREVT 0x5
530 /* enum: Schedule error. */
531 #define MCDI_EVENT_CODE_SCHEDERR 0x6
533 #define MCDI_EVENT_CODE_REBOOT 0x7
534 /* enum: Mac stats DMA. */
535 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
536 /* enum: Firmware alert. */
537 #define MCDI_EVENT_CODE_FWALERT 0x9
538 /* enum: Function level reset. */
539 #define MCDI_EVENT_CODE_FLR 0xa
540 /* enum: Transmit error */
541 #define MCDI_EVENT_CODE_TX_ERR 0xb
542 /* enum: Tx flush has completed */
543 #define MCDI_EVENT_CODE_TX_FLUSH 0xc
544 /* enum: PTP packet received timestamp */
545 #define MCDI_EVENT_CODE_PTP_RX 0xd
546 /* enum: PTP NIC failure */
547 #define MCDI_EVENT_CODE_PTP_FAULT 0xe
548 /* enum: PTP PPS event */
549 #define MCDI_EVENT_CODE_PTP_PPS 0xf
550 /* enum: Rx flush has completed */
551 #define MCDI_EVENT_CODE_RX_FLUSH 0x10
552 /* enum: Receive error */
553 #define MCDI_EVENT_CODE_RX_ERR 0x11
554 /* enum: AOE fault */
555 #define MCDI_EVENT_CODE_AOE 0x12
556 /* enum: Network port calibration failed (VCAL). */
557 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13
558 /* enum: HW PPS event */
559 #define MCDI_EVENT_CODE_HW_PPS 0x14
560 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
561 * a different format)
563 #define MCDI_EVENT_CODE_MC_REBOOT 0x15
564 /* enum: the MC has detected a parity error */
565 #define MCDI_EVENT_CODE_PAR_ERR 0x16
566 /* enum: the MC has detected a correctable error */
567 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
568 /* enum: the MC has detected an uncorrectable error */
569 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
570 /* enum: The MC has entered offline BIST mode */
571 #define MCDI_EVENT_CODE_MC_BIST 0x19
572 /* enum: PTP tick event providing current NIC time */
573 #define MCDI_EVENT_CODE_PTP_TIME 0x1a
574 /* enum: MUM fault */
575 #define MCDI_EVENT_CODE_MUM 0x1b
576 /* enum: notify the designated PF of a new authorization request */
577 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
578 /* enum: notify a function that awaits an authorization that its request has
579 * been processed and it may now resend the command
581 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
582 /* enum: Artificial event generated by host and posted via MC for test
585 #define MCDI_EVENT_CODE_TESTGEN 0xfa
586 #define MCDI_EVENT_CMDDONE_DATA_OFST 0
587 #define MCDI_EVENT_CMDDONE_DATA_LBN 0
588 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32
589 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
590 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
591 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
592 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0
593 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0
594 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
595 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
596 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
597 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
598 #define MCDI_EVENT_TX_ERR_DATA_OFST 0
599 #define MCDI_EVENT_TX_ERR_DATA_LBN 0
600 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32
601 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of
604 #define MCDI_EVENT_PTP_SECONDS_OFST 0
605 #define MCDI_EVENT_PTP_SECONDS_LBN 0
606 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32
607 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of
610 #define MCDI_EVENT_PTP_MAJOR_OFST 0
611 #define MCDI_EVENT_PTP_MAJOR_LBN 0
612 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32
613 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field
616 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
617 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
618 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
619 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of
622 #define MCDI_EVENT_PTP_MINOR_OFST 0
623 #define MCDI_EVENT_PTP_MINOR_LBN 0
624 #define MCDI_EVENT_PTP_MINOR_WIDTH 32
625 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
627 #define MCDI_EVENT_PTP_UUID_OFST 0
628 #define MCDI_EVENT_PTP_UUID_LBN 0
629 #define MCDI_EVENT_PTP_UUID_WIDTH 32
630 #define MCDI_EVENT_RX_ERR_DATA_OFST 0
631 #define MCDI_EVENT_RX_ERR_DATA_LBN 0
632 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32
633 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0
634 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0
635 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
636 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
637 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
638 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
639 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
640 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
641 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
642 /* For CODE_PTP_TIME events, the major value of the PTP clock */
643 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
644 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
645 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32
646 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
647 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36
648 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8
649 /* For CODE_PTP_TIME events where report sync status is enabled, indicates
650 * whether the NIC clock has ever been set
652 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36
653 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
654 /* For CODE_PTP_TIME events where report sync status is enabled, indicates
655 * whether the NIC and System clocks are in sync
657 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37
658 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
659 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
660 * the minor value of the PTP clock
662 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38
663 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6
664 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
665 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
666 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32
667 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
668 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
669 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32
670 /* Zero means that the request has been completed or authorized, and the driver
671 * should resend it. A non-zero value means that the authorization has been
672 * denied, and gives the reason. Typically it will be EPERM.
674 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36
675 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8
677 /* FCDI_EVENT structuredef */
678 #define FCDI_EVENT_LEN 8
679 #define FCDI_EVENT_CONT_LBN 32
680 #define FCDI_EVENT_CONT_WIDTH 1
681 #define FCDI_EVENT_LEVEL_LBN 33
682 #define FCDI_EVENT_LEVEL_WIDTH 3
684 #define FCDI_EVENT_LEVEL_INFO 0x0
686 #define FCDI_EVENT_LEVEL_WARN 0x1
688 #define FCDI_EVENT_LEVEL_ERR 0x2
690 #define FCDI_EVENT_LEVEL_FATAL 0x3
691 #define FCDI_EVENT_DATA_OFST 0
692 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0
693 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
694 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */
695 #define FCDI_EVENT_LINK_UP 0x1 /* enum */
696 #define FCDI_EVENT_DATA_LBN 0
697 #define FCDI_EVENT_DATA_WIDTH 32
698 #define FCDI_EVENT_SRC_LBN 36
699 #define FCDI_EVENT_SRC_WIDTH 8
700 #define FCDI_EVENT_EV_CODE_LBN 60
701 #define FCDI_EVENT_EV_CODE_WIDTH 4
702 #define FCDI_EVENT_CODE_LBN 44
703 #define FCDI_EVENT_CODE_WIDTH 8
704 /* enum: The FC was rebooted. */
705 #define FCDI_EVENT_CODE_REBOOT 0x1
706 /* enum: Bad assert. */
707 #define FCDI_EVENT_CODE_ASSERT 0x2
708 /* enum: DDR3 test result. */
709 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
710 /* enum: Link status. */
711 #define FCDI_EVENT_CODE_LINK_STATE 0x4
712 /* enum: A timed read is ready to be serviced. */
713 #define FCDI_EVENT_CODE_TIMED_READ 0x5
714 /* enum: One or more PPS IN events */
715 #define FCDI_EVENT_CODE_PPS_IN 0x6
716 /* enum: Tick event from PTP clock */
717 #define FCDI_EVENT_CODE_PTP_TICK 0x7
718 /* enum: ECC error counters */
719 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
720 /* enum: Current status of PTP */
721 #define FCDI_EVENT_CODE_PTP_STATUS 0x9
722 /* enum: Port id config to map MC-FC port idx */
723 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa
724 /* enum: Boot result or error code */
725 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb
726 #define FCDI_EVENT_REBOOT_SRC_LBN 36
727 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8
728 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
729 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
730 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
731 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
732 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32
733 #define FCDI_EVENT_ASSERT_TYPE_LBN 36
734 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8
735 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36
736 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8
737 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
738 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
739 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32
740 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0
741 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0
742 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32
743 #define FCDI_EVENT_PTP_STATE_OFST 0
744 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
745 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
746 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
747 #define FCDI_EVENT_PTP_STATE_LBN 0
748 #define FCDI_EVENT_PTP_STATE_WIDTH 32
749 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36
750 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8
751 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
752 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
753 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32
754 /* Index of MC port being referred to */
755 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36
756 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8
757 /* FC Port index that matches the MC port index in SRC */
758 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
759 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
760 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32
761 #define FCDI_EVENT_BOOT_RESULT_OFST 0
762 /* Enum values, see field(s): */
763 /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */
764 #define FCDI_EVENT_BOOT_RESULT_LBN 0
765 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32
767 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events
768 * to the MC. Note that this structure | is overlaid over a normal FCDI event
769 * such that bits 32-63 containing | event code, level, source etc remain the
770 * same. In this case the data | field of the header is defined to be the
771 * number of timestamps
773 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16
774 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248
775 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
776 /* Number of timestamps following */
777 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
778 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
779 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32
780 /* Seconds field of a timestamp record */
781 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8
782 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64
783 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32
784 /* Nanoseconds field of a timestamp record */
785 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12
786 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96
787 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32
788 /* Timestamp records comprising the event */
789 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
790 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
791 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
792 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
793 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
794 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
795 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64
796 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64
798 /* MUM_EVENT structuredef */
799 #define MUM_EVENT_LEN 8
800 #define MUM_EVENT_CONT_LBN 32
801 #define MUM_EVENT_CONT_WIDTH 1
802 #define MUM_EVENT_LEVEL_LBN 33
803 #define MUM_EVENT_LEVEL_WIDTH 3
805 #define MUM_EVENT_LEVEL_INFO 0x0
807 #define MUM_EVENT_LEVEL_WARN 0x1
809 #define MUM_EVENT_LEVEL_ERR 0x2
811 #define MUM_EVENT_LEVEL_FATAL 0x3
812 #define MUM_EVENT_DATA_OFST 0
813 #define MUM_EVENT_SENSOR_ID_LBN 0
814 #define MUM_EVENT_SENSOR_ID_WIDTH 8
815 /* Enum values, see field(s): */
816 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
817 #define MUM_EVENT_SENSOR_STATE_LBN 8
818 #define MUM_EVENT_SENSOR_STATE_WIDTH 8
819 #define MUM_EVENT_PORT_PHY_READY_LBN 0
820 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1
821 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1
822 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1
823 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2
824 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1
825 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3
826 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1
827 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
828 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1
829 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5
830 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1
831 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6
832 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1
833 #define MUM_EVENT_DATA_LBN 0
834 #define MUM_EVENT_DATA_WIDTH 32
835 #define MUM_EVENT_SRC_LBN 36
836 #define MUM_EVENT_SRC_WIDTH 8
837 #define MUM_EVENT_EV_CODE_LBN 60
838 #define MUM_EVENT_EV_CODE_WIDTH 4
839 #define MUM_EVENT_CODE_LBN 44
840 #define MUM_EVENT_CODE_WIDTH 8
841 /* enum: The MUM was rebooted. */
842 #define MUM_EVENT_CODE_REBOOT 0x1
843 /* enum: Bad assert. */
844 #define MUM_EVENT_CODE_ASSERT 0x2
845 /* enum: Sensor failure. */
846 #define MUM_EVENT_CODE_SENSOR 0x3
847 /* enum: Link fault has been asserted, or has cleared. */
848 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
849 #define MUM_EVENT_SENSOR_DATA_OFST 0
850 #define MUM_EVENT_SENSOR_DATA_LBN 0
851 #define MUM_EVENT_SENSOR_DATA_WIDTH 32
852 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0
853 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0
854 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32
855 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
856 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
857 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32
858 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0
859 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0
860 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32
861 #define MUM_EVENT_PORT_PHY_TECH_OFST 0
862 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
863 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
864 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
865 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
866 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
867 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
868 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
869 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
870 #define MUM_EVENT_PORT_PHY_TECH_LBN 0
871 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32
872 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36
873 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
874 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
875 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
876 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
877 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
878 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
879 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40
880 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4
883 /***********************************/
885 * Read multiple 32byte words from MC memory.
887 #define MC_CMD_READ32 0x1
888 #undef MC_CMD_0x1_PRIVILEGE_CTG
890 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
892 /* MC_CMD_READ32_IN msgrequest */
893 #define MC_CMD_READ32_IN_LEN 8
894 #define MC_CMD_READ32_IN_ADDR_OFST 0
895 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4
897 /* MC_CMD_READ32_OUT msgresponse */
898 #define MC_CMD_READ32_OUT_LENMIN 4
899 #define MC_CMD_READ32_OUT_LENMAX 252
900 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
901 #define MC_CMD_READ32_OUT_BUFFER_OFST 0
902 #define MC_CMD_READ32_OUT_BUFFER_LEN 4
903 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
904 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
907 /***********************************/
909 * Write multiple 32byte words to MC memory.
911 #define MC_CMD_WRITE32 0x2
912 #undef MC_CMD_0x2_PRIVILEGE_CTG
914 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
916 /* MC_CMD_WRITE32_IN msgrequest */
917 #define MC_CMD_WRITE32_IN_LENMIN 8
918 #define MC_CMD_WRITE32_IN_LENMAX 252
919 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
920 #define MC_CMD_WRITE32_IN_ADDR_OFST 0
921 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4
922 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4
923 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
924 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
926 /* MC_CMD_WRITE32_OUT msgresponse */
927 #define MC_CMD_WRITE32_OUT_LEN 0
930 /***********************************/
932 * Copy MC code between two locations and jump.
934 #define MC_CMD_COPYCODE 0x3
935 #undef MC_CMD_0x3_PRIVILEGE_CTG
937 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
939 /* MC_CMD_COPYCODE_IN msgrequest */
940 #define MC_CMD_COPYCODE_IN_LEN 16
943 * The main image should be entered via a copy of a single word from and to a
944 * magic address, which controls various aspects of the boot. The magic address
945 * is a bitfield, with each bit as documented below.
947 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
948 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */
949 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
950 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and
951 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)
953 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
954 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,
955 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see
958 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
959 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17
960 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1
961 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2
962 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1
963 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3
964 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1
965 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
966 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1
967 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5
968 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1
969 /* Destination address */
970 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
971 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
972 /* Address of where to jump after copy. */
973 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12
974 /* enum: Control should return to the caller rather than jumping */
975 #define MC_CMD_COPYCODE_JUMP_NONE 0x1
977 /* MC_CMD_COPYCODE_OUT msgresponse */
978 #define MC_CMD_COPYCODE_OUT_LEN 0
981 /***********************************/
983 * Select function for function-specific commands.
985 #define MC_CMD_SET_FUNC 0x4
986 #undef MC_CMD_0x4_PRIVILEGE_CTG
988 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
990 /* MC_CMD_SET_FUNC_IN msgrequest */
991 #define MC_CMD_SET_FUNC_IN_LEN 4
993 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
995 /* MC_CMD_SET_FUNC_OUT msgresponse */
996 #define MC_CMD_SET_FUNC_OUT_LEN 0
999 /***********************************/
1000 /* MC_CMD_GET_BOOT_STATUS
1001 * Get the instruction address from which the MC booted.
1003 #define MC_CMD_GET_BOOT_STATUS 0x5
1004 #undef MC_CMD_0x5_PRIVILEGE_CTG
1006 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1008 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
1009 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
1011 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
1012 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
1014 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
1015 /* enum: indicates that the MC wasn't flash booted */
1016 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
1017 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
1018 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
1019 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
1020 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
1021 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
1022 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
1023 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
1026 /***********************************/
1027 /* MC_CMD_GET_ASSERTS
1028 * Get (and optionally clear) the current assertion status. Only
1029 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other
1030 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
1032 #define MC_CMD_GET_ASSERTS 0x6
1033 #undef MC_CMD_0x6_PRIVILEGE_CTG
1035 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1037 /* MC_CMD_GET_ASSERTS_IN msgrequest */
1038 #define MC_CMD_GET_ASSERTS_IN_LEN 4
1039 /* Set to clear assertion */
1040 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
1042 /* MC_CMD_GET_ASSERTS_OUT msgresponse */
1043 #define MC_CMD_GET_ASSERTS_OUT_LEN 140
1044 /* Assertion status flag. */
1045 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
1046 /* enum: No assertions have failed. */
1047 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
1048 /* enum: A system-level assertion has failed. */
1049 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
1050 /* enum: A thread-level assertion has failed. */
1051 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
1052 /* enum: The system was reset by the watchdog. */
1053 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
1054 /* enum: An illegal address trap stopped the system (huntington and later) */
1055 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
1056 /* Failing PC value */
1057 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
1059 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
1060 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
1061 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
1062 /* enum: A magic value hinting that the value in this register at the time of
1063 * the failure has likely been lost.
1065 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
1066 /* Failing thread address */
1067 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
1068 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
1071 /***********************************/
1073 * Configure the output stream for log events such as link state changes,
1074 * sensor notifications and MCDI completions
1076 #define MC_CMD_LOG_CTRL 0x7
1077 #undef MC_CMD_0x7_PRIVILEGE_CTG
1079 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1081 /* MC_CMD_LOG_CTRL_IN msgrequest */
1082 #define MC_CMD_LOG_CTRL_IN_LEN 8
1083 /* Log destination */
1084 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
1086 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
1087 /* enum: Event queue. */
1088 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
1089 /* Legacy argument. Must be zero. */
1090 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
1092 /* MC_CMD_LOG_CTRL_OUT msgresponse */
1093 #define MC_CMD_LOG_CTRL_OUT_LEN 0
1096 /***********************************/
1097 /* MC_CMD_GET_VERSION
1098 * Get version information about the MC firmware.
1100 #define MC_CMD_GET_VERSION 0x8
1101 #undef MC_CMD_0x8_PRIVILEGE_CTG
1103 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1105 /* MC_CMD_GET_VERSION_IN msgrequest */
1106 #define MC_CMD_GET_VERSION_IN_LEN 0
1108 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */
1109 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4
1110 /* placeholder, set to 0 */
1111 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
1113 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */
1114 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4
1115 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
1116 /* enum: Reserved version number to indicate "any" version. */
1117 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
1118 /* enum: Bootrom version value for Siena. */
1119 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
1120 /* enum: Bootrom version value for Huntington. */
1121 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
1123 /* MC_CMD_GET_VERSION_OUT msgresponse */
1124 #define MC_CMD_GET_VERSION_OUT_LEN 32
1125 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1126 /* Enum values, see field(s): */
1127 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1128 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
1129 /* 128bit mask of functions supported by the current firmware */
1130 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
1131 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
1132 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
1133 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
1134 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
1135 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
1137 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
1138 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48
1139 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1140 /* Enum values, see field(s): */
1141 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1142 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
1143 /* 128bit mask of functions supported by the current firmware */
1144 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8
1145 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16
1146 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
1147 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
1148 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
1149 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
1151 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
1152 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
1155 /***********************************/
1157 * Perform an FC operation
1159 #define MC_CMD_FC 0x9
1161 /* MC_CMD_FC_IN msgrequest */
1162 #define MC_CMD_FC_IN_LEN 4
1163 #define MC_CMD_FC_IN_OP_HDR_OFST 0
1164 #define MC_CMD_FC_IN_OP_LBN 0
1165 #define MC_CMD_FC_IN_OP_WIDTH 8
1166 /* enum: NULL MCDI command to FC. */
1167 #define MC_CMD_FC_OP_NULL 0x1
1168 /* enum: Unused opcode */
1169 #define MC_CMD_FC_OP_UNUSED 0x2
1170 /* enum: MAC driver commands */
1171 #define MC_CMD_FC_OP_MAC 0x3
1172 /* enum: Read FC memory */
1173 #define MC_CMD_FC_OP_READ32 0x4
1174 /* enum: Write to FC memory */
1175 #define MC_CMD_FC_OP_WRITE32 0x5
1176 /* enum: Read FC memory */
1177 #define MC_CMD_FC_OP_TRC_READ 0x6
1178 /* enum: Write to FC memory */
1179 #define MC_CMD_FC_OP_TRC_WRITE 0x7
1180 /* enum: FC firmware Version */
1181 #define MC_CMD_FC_OP_GET_VERSION 0x8
1182 /* enum: Read FC memory */
1183 #define MC_CMD_FC_OP_TRC_RX_READ 0x9
1184 /* enum: Write to FC memory */
1185 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa
1186 /* enum: SFP parameters */
1187 #define MC_CMD_FC_OP_SFP 0xb
1188 /* enum: DDR3 test */
1189 #define MC_CMD_FC_OP_DDR_TEST 0xc
1190 /* enum: Get Crash context from FC */
1191 #define MC_CMD_FC_OP_GET_ASSERT 0xd
1192 /* enum: Get FPGA Build registers */
1193 #define MC_CMD_FC_OP_FPGA_BUILD 0xe
1194 /* enum: Read map support commands */
1195 #define MC_CMD_FC_OP_READ_MAP 0xf
1196 /* enum: FC Capabilities */
1197 #define MC_CMD_FC_OP_CAPABILITIES 0x10
1198 /* enum: FC Global flags */
1199 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11
1200 /* enum: FC IO using relative addressing modes */
1201 #define MC_CMD_FC_OP_IO_REL 0x12
1202 /* enum: FPGA link information */
1203 #define MC_CMD_FC_OP_UHLINK 0x13
1204 /* enum: Configure loopbacks and link on FPGA ports */
1205 #define MC_CMD_FC_OP_SET_LINK 0x14
1206 /* enum: Licensing operations relating to AOE */
1207 #define MC_CMD_FC_OP_LICENSE 0x15
1208 /* enum: Startup information to the FC */
1209 #define MC_CMD_FC_OP_STARTUP 0x16
1210 /* enum: Configure a DMA read */
1211 #define MC_CMD_FC_OP_DMA 0x17
1212 /* enum: Configure a timed read */
1213 #define MC_CMD_FC_OP_TIMED_READ 0x18
1214 /* enum: Control UART logging */
1215 #define MC_CMD_FC_OP_LOG 0x19
1216 /* enum: Get the value of a given clock_id */
1217 #define MC_CMD_FC_OP_CLOCK 0x1a
1218 /* enum: DDR3/QDR3 parameters */
1219 #define MC_CMD_FC_OP_DDR 0x1b
1220 /* enum: PTP and timestamp control */
1221 #define MC_CMD_FC_OP_TIMESTAMP 0x1c
1222 /* enum: Commands for SPI Flash interface */
1223 #define MC_CMD_FC_OP_SPI 0x1d
1224 /* enum: Commands for diagnostic components */
1225 #define MC_CMD_FC_OP_DIAG 0x1e
1226 /* enum: External AOE port. */
1227 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0
1228 /* enum: Internal AOE port. */
1229 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40
1231 /* MC_CMD_FC_IN_NULL msgrequest */
1232 #define MC_CMD_FC_IN_NULL_LEN 4
1233 #define MC_CMD_FC_IN_CMD_OFST 0
1235 /* MC_CMD_FC_IN_PHY msgrequest */
1236 #define MC_CMD_FC_IN_PHY_LEN 5
1237 /* MC_CMD_FC_IN_CMD_OFST 0 */
1238 /* FC PHY driver operation code */
1239 #define MC_CMD_FC_IN_PHY_OP_OFST 4
1240 #define MC_CMD_FC_IN_PHY_OP_LEN 1
1241 /* enum: PHY init handler */
1242 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1
1243 /* enum: PHY reconfigure handler */
1244 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2
1245 /* enum: PHY reboot handler */
1246 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3
1247 /* enum: PHY get_supported_cap handler */
1248 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4
1249 /* enum: PHY get_config handler */
1250 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5
1251 /* enum: PHY get_media_info handler */
1252 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6
1253 /* enum: PHY set_led handler */
1254 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7
1255 /* enum: PHY lasi_interrupt handler */
1256 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8
1257 /* enum: PHY check_link handler */
1258 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9
1259 /* enum: PHY fill_stats handler */
1260 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa
1261 /* enum: PHY bpx_link_state_changed handler */
1262 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb
1263 /* enum: PHY get_state handler */
1264 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc
1265 /* enum: PHY start_bist handler */
1266 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd
1267 /* enum: PHY poll_bist handler */
1268 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe
1269 /* enum: PHY nvram_test handler */
1270 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf
1271 /* enum: PHY relinquish handler */
1272 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10
1273 /* enum: PHY read connection from FC - may be not required */
1274 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11
1275 /* enum: PHY read flags from FC - may be not required */
1276 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12
1278 /* MC_CMD_FC_IN_PHY_INIT msgrequest */
1279 #define MC_CMD_FC_IN_PHY_INIT_LEN 4
1280 #define MC_CMD_FC_IN_PHY_CMD_OFST 0
1282 /* MC_CMD_FC_IN_MAC msgrequest */
1283 #define MC_CMD_FC_IN_MAC_LEN 8
1284 /* MC_CMD_FC_IN_CMD_OFST 0 */
1285 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4
1286 #define MC_CMD_FC_IN_MAC_OP_LBN 0
1287 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8
1288 /* enum: MAC reconfigure handler */
1289 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1
1290 /* enum: MAC Set command - same as MC_CMD_SET_MAC */
1291 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2
1292 /* enum: MAC statistics */
1293 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3
1294 /* enum: MAC RX statistics */
1295 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6
1296 /* enum: MAC TX statistics */
1297 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7
1298 /* enum: MAC Read status */
1299 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8
1300 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8
1301 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8
1302 /* enum: External FPGA port. */
1303 #define MC_CMD_FC_PORT_EXT 0x0
1304 /* enum: Internal Siena-facing FPGA ports. */
1305 #define MC_CMD_FC_PORT_INT 0x1
1306 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16
1307 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8
1308 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24
1309 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8
1310 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are
1311 * irrelevant. Port number is derived from pci_fn; passed in FC header.
1313 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0
1314 /* enum: Override default port number. Port number determined by fields
1315 * PORT_TYPE and PORT_IDX.
1317 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1
1319 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */
1320 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8
1321 /* MC_CMD_FC_IN_CMD_OFST 0 */
1322 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
1324 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */
1325 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32
1326 /* MC_CMD_FC_IN_CMD_OFST 0 */
1327 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
1329 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8
1331 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12
1332 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16
1333 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8
1334 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16
1335 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20
1336 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24
1337 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0
1338 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1
1339 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1
1340 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1
1341 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28
1343 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */
1344 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8
1345 /* MC_CMD_FC_IN_CMD_OFST 0 */
1346 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
1348 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */
1349 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8
1350 /* MC_CMD_FC_IN_CMD_OFST 0 */
1351 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
1353 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */
1354 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8
1355 /* MC_CMD_FC_IN_CMD_OFST 0 */
1356 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
1358 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */
1359 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20
1360 /* MC_CMD_FC_IN_CMD_OFST 0 */
1361 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
1362 /* MC Statistics index */
1363 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8
1364 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12
1365 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0
1366 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1
1367 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1
1368 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1
1369 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2
1370 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1
1371 /* Number of statistics to read */
1372 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16
1373 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */
1374 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */
1376 /* MC_CMD_FC_IN_READ32 msgrequest */
1377 #define MC_CMD_FC_IN_READ32_LEN 16
1378 /* MC_CMD_FC_IN_CMD_OFST 0 */
1379 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4
1380 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8
1381 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12
1383 /* MC_CMD_FC_IN_WRITE32 msgrequest */
1384 #define MC_CMD_FC_IN_WRITE32_LENMIN 16
1385 #define MC_CMD_FC_IN_WRITE32_LENMAX 252
1386 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num))
1387 /* MC_CMD_FC_IN_CMD_OFST 0 */
1388 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4
1389 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8
1390 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12
1391 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4
1392 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1
1393 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60
1395 /* MC_CMD_FC_IN_TRC_READ msgrequest */
1396 #define MC_CMD_FC_IN_TRC_READ_LEN 12
1397 /* MC_CMD_FC_IN_CMD_OFST 0 */
1398 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4
1399 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8
1401 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */
1402 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28
1403 /* MC_CMD_FC_IN_CMD_OFST 0 */
1404 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4
1405 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8
1406 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12
1407 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4
1408 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4
1410 /* MC_CMD_FC_IN_GET_VERSION msgrequest */
1411 #define MC_CMD_FC_IN_GET_VERSION_LEN 4
1412 /* MC_CMD_FC_IN_CMD_OFST 0 */
1414 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */
1415 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12
1416 /* MC_CMD_FC_IN_CMD_OFST 0 */
1417 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4
1418 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8
1420 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */
1421 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20
1422 /* MC_CMD_FC_IN_CMD_OFST 0 */
1423 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4
1424 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8
1425 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12
1426 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4
1427 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2
1429 /* MC_CMD_FC_IN_SFP msgrequest */
1430 #define MC_CMD_FC_IN_SFP_LEN 28
1431 /* MC_CMD_FC_IN_CMD_OFST 0 */
1432 /* Link speed is 100, 1000, 10000, 40000 */
1433 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4
1434 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */
1435 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8
1436 /* Not relevant for cards with QSFP modules. For older cards, true if module is
1437 * a dual speed SFP+ module.
1439 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12
1440 /* True if an SFP Module is present (other fields valid when true) */
1441 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16
1442 /* The type of the SFP+ Module. For later cards with QSFP modules, this field
1443 * is unused and the type is communicated by other means.
1445 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20
1446 /* Capabilities corresponding to 1 bits. */
1447 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24
1449 /* MC_CMD_FC_IN_DDR_TEST msgrequest */
1450 #define MC_CMD_FC_IN_DDR_TEST_LEN 8
1451 /* MC_CMD_FC_IN_CMD_OFST 0 */
1452 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4
1453 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0
1454 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8
1455 /* enum: DRAM Test Start */
1456 #define MC_CMD_FC_OP_DDR_TEST_START 0x1
1457 /* enum: DRAM Test Poll */
1458 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2
1460 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */
1461 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12
1462 /* MC_CMD_FC_IN_CMD_OFST 0 */
1463 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */
1464 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8
1465 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0
1466 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1
1467 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1
1468 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1
1469 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2
1470 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1
1471 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3
1472 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1
1474 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */
1475 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12
1476 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0
1477 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */
1478 /* Clear previous test result and prepare for restarting DDR test */
1479 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8
1481 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */
1482 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4
1483 /* MC_CMD_FC_IN_CMD_OFST 0 */
1485 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */
1486 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8
1487 /* MC_CMD_FC_IN_CMD_OFST 0 */
1488 /* FPGA build info operation code */
1489 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4
1490 /* enum: Get the build registers */
1491 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1
1492 /* enum: Get the services registers */
1493 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2
1494 /* enum: Get the BSP version */
1495 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3
1496 /* enum: Get build register for V2 (SFA974X) */
1497 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4
1498 /* enum: GEt the services register for V2 (SFA974X) */
1499 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5
1501 /* MC_CMD_FC_IN_READ_MAP msgrequest */
1502 #define MC_CMD_FC_IN_READ_MAP_LEN 8
1503 /* MC_CMD_FC_IN_CMD_OFST 0 */
1504 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4
1505 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0
1506 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8
1507 /* enum: Get the number of map regions */
1508 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1
1509 /* enum: Get the specified map */
1510 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2
1512 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */
1513 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8
1514 /* MC_CMD_FC_IN_CMD_OFST 0 */
1515 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */
1517 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */
1518 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12
1519 /* MC_CMD_FC_IN_CMD_OFST 0 */
1520 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */
1521 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8
1523 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */
1524 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4
1525 /* MC_CMD_FC_IN_CMD_OFST 0 */
1527 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */
1528 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8
1529 /* MC_CMD_FC_IN_CMD_OFST 0 */
1530 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4
1531 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0
1532 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1
1533 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1
1534 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1
1535 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2
1536 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1
1537 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3
1538 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1
1539 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4
1540 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1
1541 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5
1542 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1
1544 /* MC_CMD_FC_IN_IO_REL msgrequest */
1545 #define MC_CMD_FC_IN_IO_REL_LEN 8
1546 /* MC_CMD_FC_IN_CMD_OFST 0 */
1547 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4
1548 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0
1549 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8
1550 /* enum: Get the base address that the FC applies to relative commands */
1551 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1
1552 /* enum: Read data */
1553 #define MC_CMD_FC_IN_IO_REL_READ32 0x2
1554 /* enum: Write data */
1555 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3
1556 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8
1557 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8
1558 /* enum: Application address space */
1559 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1
1560 /* enum: Flash address space */
1561 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2
1563 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */
1564 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8
1565 /* MC_CMD_FC_IN_CMD_OFST 0 */
1566 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
1568 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */
1569 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20
1570 /* MC_CMD_FC_IN_CMD_OFST 0 */
1571 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
1572 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8
1573 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12
1574 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16
1576 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */
1577 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20
1578 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252
1579 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num))
1580 /* MC_CMD_FC_IN_CMD_OFST 0 */
1581 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
1582 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8
1583 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12
1584 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16
1585 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4
1586 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1
1587 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59
1589 /* MC_CMD_FC_IN_UHLINK msgrequest */
1590 #define MC_CMD_FC_IN_UHLINK_LEN 8
1591 /* MC_CMD_FC_IN_CMD_OFST 0 */
1592 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4
1593 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0
1594 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8
1595 /* enum: Get PHY configuration info */
1596 #define MC_CMD_FC_OP_UHLINK_PHY 0x1
1597 /* enum: Get MAC configuration info */
1598 #define MC_CMD_FC_OP_UHLINK_MAC 0x2
1599 /* enum: Get Rx eye table */
1600 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3
1601 /* enum: Get Rx eye plot */
1602 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4
1603 /* enum: Get Rx eye plot */
1604 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5
1605 /* enum: Retune Rx settings */
1606 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6
1607 /* enum: Set loopback mode on fpga port */
1608 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7
1609 /* enum: Get loopback mode config state on fpga port */
1610 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8
1611 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8
1612 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8
1613 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16
1614 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8
1615 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24
1616 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8
1617 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are
1618 * irrelevant. Port number is derived from pci_fn; passed in FC header.
1620 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0
1621 /* enum: Override default port number. Port number determined by fields
1622 * PORT_TYPE and PORT_IDX.
1624 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1
1626 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */
1627 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8
1628 /* MC_CMD_FC_IN_CMD_OFST 0 */
1629 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
1631 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */
1632 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8
1633 /* MC_CMD_FC_IN_CMD_OFST 0 */
1634 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
1636 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */
1637 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12
1638 /* MC_CMD_FC_IN_CMD_OFST 0 */
1639 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
1640 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8
1641 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */
1643 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */
1644 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8
1645 /* MC_CMD_FC_IN_CMD_OFST 0 */
1646 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
1648 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */
1649 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20
1650 /* MC_CMD_FC_IN_CMD_OFST 0 */
1651 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
1652 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8
1653 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12
1654 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16
1655 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */
1657 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */
1658 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8
1659 /* MC_CMD_FC_IN_CMD_OFST 0 */
1660 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
1662 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */
1663 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16
1664 /* MC_CMD_FC_IN_CMD_OFST 0 */
1665 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
1666 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8
1667 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */
1668 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */
1669 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */
1670 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12
1671 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */
1672 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */
1674 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */
1675 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12
1676 /* MC_CMD_FC_IN_CMD_OFST 0 */
1677 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
1678 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8
1680 /* MC_CMD_FC_IN_SET_LINK msgrequest */
1681 #define MC_CMD_FC_IN_SET_LINK_LEN 16
1682 /* MC_CMD_FC_IN_CMD_OFST 0 */
1683 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
1684 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4
1685 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8
1686 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12
1687 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0
1688 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1
1689 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1
1690 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1
1691 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2
1692 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1
1694 /* MC_CMD_FC_IN_LICENSE msgrequest */
1695 #define MC_CMD_FC_IN_LICENSE_LEN 8
1696 /* MC_CMD_FC_IN_CMD_OFST 0 */
1697 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4
1698 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */
1699 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */
1701 /* MC_CMD_FC_IN_STARTUP msgrequest */
1702 #define MC_CMD_FC_IN_STARTUP_LEN 40
1703 /* MC_CMD_FC_IN_CMD_OFST 0 */
1704 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4
1705 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8
1706 /* Length of identifier */
1707 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12
1708 /* Identifier for AOE FPGA */
1709 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16
1710 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1
1711 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24
1713 /* MC_CMD_FC_IN_DMA msgrequest */
1714 #define MC_CMD_FC_IN_DMA_LEN 8
1715 /* MC_CMD_FC_IN_CMD_OFST 0 */
1716 #define MC_CMD_FC_IN_DMA_OP_OFST 4
1717 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */
1718 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */
1720 /* MC_CMD_FC_IN_DMA_STOP msgrequest */
1721 #define MC_CMD_FC_IN_DMA_STOP_LEN 12
1722 /* MC_CMD_FC_IN_CMD_OFST 0 */
1723 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */
1724 /* FC supplied handle */
1725 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8
1727 /* MC_CMD_FC_IN_DMA_READ msgrequest */
1728 #define MC_CMD_FC_IN_DMA_READ_LEN 16
1729 /* MC_CMD_FC_IN_CMD_OFST 0 */
1730 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */
1731 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8
1732 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12
1734 /* MC_CMD_FC_IN_TIMED_READ msgrequest */
1735 #define MC_CMD_FC_IN_TIMED_READ_LEN 8
1736 /* MC_CMD_FC_IN_CMD_OFST 0 */
1737 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4
1738 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */
1739 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */
1740 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */
1742 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */
1743 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52
1744 /* MC_CMD_FC_IN_CMD_OFST 0 */
1745 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
1746 /* Host supplied handle (unique) */
1747 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8
1748 /* Address into which to transfer data in host */
1749 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12
1750 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8
1751 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12
1752 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16
1753 /* AOE address from which to transfer data */
1754 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20
1755 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8
1756 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20
1757 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24
1758 /* Length of AOE transfer (total) */
1759 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28
1760 /* Length of host transfer (total) */
1761 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32
1762 /* Offset back from aoe_address to apply operation to */
1763 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36
1764 /* Data to apply at offset */
1765 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40
1766 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44
1767 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0
1768 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1
1769 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1
1770 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1
1771 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2
1772 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1
1773 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3
1774 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2
1775 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */
1776 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */
1777 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */
1778 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */
1779 /* Period at which reads are performed (100ms units) */
1780 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48
1782 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */
1783 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12
1784 /* MC_CMD_FC_IN_CMD_OFST 0 */
1785 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
1786 /* FC supplied handle */
1787 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8
1789 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */
1790 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12
1791 /* MC_CMD_FC_IN_CMD_OFST 0 */
1792 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
1793 /* FC supplied handle */
1794 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8
1796 /* MC_CMD_FC_IN_LOG msgrequest */
1797 #define MC_CMD_FC_IN_LOG_LEN 8
1798 /* MC_CMD_FC_IN_CMD_OFST 0 */
1799 #define MC_CMD_FC_IN_LOG_OP_OFST 4
1800 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */
1801 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */
1803 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */
1804 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20
1805 /* MC_CMD_FC_IN_CMD_OFST 0 */
1806 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */
1807 /* Partition offset into flash */
1808 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8
1809 /* Partition length */
1810 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12
1811 /* Partition erase size */
1812 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16
1814 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */
1815 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12
1816 /* MC_CMD_FC_IN_CMD_OFST 0 */
1817 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */
1818 /* Enable/disable printing to JTAG UART */
1819 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8
1821 /* MC_CMD_FC_IN_CLOCK msgrequest */
1822 #define MC_CMD_FC_IN_CLOCK_LEN 12
1823 /* MC_CMD_FC_IN_CMD_OFST 0 */
1824 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4
1825 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */
1826 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */
1827 /* Perform a clock operation */
1828 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8
1829 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */
1830 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */
1832 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */
1833 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12
1834 /* MC_CMD_FC_IN_CMD_OFST 0 */
1835 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */
1836 /* Retrieve the clock value of the specified clock */
1837 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */
1839 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */
1840 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24
1841 /* MC_CMD_FC_IN_CMD_OFST 0 */
1842 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */
1843 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */
1844 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12
1845 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8
1846 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12
1847 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16
1848 /* Set the clock value of the specified clock */
1849 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20
1851 /* MC_CMD_FC_IN_DDR msgrequest */
1852 #define MC_CMD_FC_IN_DDR_LEN 12
1853 /* MC_CMD_FC_IN_CMD_OFST 0 */
1854 #define MC_CMD_FC_IN_DDR_OP_OFST 4
1855 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */
1856 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */
1857 #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */
1858 #define MC_CMD_FC_IN_DDR_BANK_OFST 8
1859 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */
1860 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */
1861 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */
1862 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */
1863 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */
1865 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */
1866 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148
1867 /* MC_CMD_FC_IN_CMD_OFST 0 */
1868 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */
1870 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */
1872 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12
1873 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */
1874 /* 128-byte page of serial presence detect data read from module's EEPROM */
1875 #define MC_CMD_FC_IN_DDR_SPD_OFST 16
1876 #define MC_CMD_FC_IN_DDR_SPD_LEN 1
1877 #define MC_CMD_FC_IN_DDR_SPD_NUM 128
1878 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */
1879 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144
1881 /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */
1882 #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16
1883 /* MC_CMD_FC_IN_CMD_OFST 0 */
1884 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */
1886 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */
1888 #define MC_CMD_FC_IN_DDR_SIZE_OFST 12
1890 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */
1891 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12
1892 /* MC_CMD_FC_IN_CMD_OFST 0 */
1893 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */
1895 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */
1897 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */
1898 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8
1899 /* MC_CMD_FC_IN_CMD_OFST 0 */
1900 /* FC timestamp operation code */
1901 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4
1902 /* enum: Read transmit timestamp(s) */
1903 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0
1904 /* enum: Read snapshot timestamps */
1905 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1
1906 /* enum: Clear all transmit timestamps */
1907 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2
1909 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */
1910 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28
1911 /* MC_CMD_FC_IN_CMD_OFST 0 */
1912 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4
1913 /* Control filtering of the returned timestamp and sequence number specified
1916 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8
1917 /* enum: Return most recent timestamp. No filtering */
1918 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0
1919 /* enum: Match timestamp against the PTP clock ID, port number and sequence
1922 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1
1923 /* Clock identity of PTP packet for which timestamp required */
1924 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12
1925 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8
1926 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12
1927 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16
1928 /* Port number of PTP packet for which timestamp required */
1929 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20
1930 /* Sequence number of PTP packet for which timestamp required */
1931 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24
1933 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */
1934 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8
1935 /* MC_CMD_FC_IN_CMD_OFST 0 */
1936 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4
1938 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */
1939 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8
1940 /* MC_CMD_FC_IN_CMD_OFST 0 */
1941 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4
1943 /* MC_CMD_FC_IN_SPI msgrequest */
1944 #define MC_CMD_FC_IN_SPI_LEN 8
1945 /* MC_CMD_FC_IN_CMD_OFST 0 */
1946 /* Basic commands for SPI Flash. */
1947 #define MC_CMD_FC_IN_SPI_OP_OFST 4
1948 /* enum: SPI Flash read */
1949 #define MC_CMD_FC_IN_SPI_READ 0x0
1950 /* enum: SPI Flash write */
1951 #define MC_CMD_FC_IN_SPI_WRITE 0x1
1952 /* enum: SPI Flash erase */
1953 #define MC_CMD_FC_IN_SPI_ERASE 0x2
1955 /* MC_CMD_FC_IN_SPI_READ msgrequest */
1956 #define MC_CMD_FC_IN_SPI_READ_LEN 16
1957 /* MC_CMD_FC_IN_CMD_OFST 0 */
1958 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4
1959 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8
1960 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12
1962 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */
1963 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16
1964 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252
1965 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num))
1966 /* MC_CMD_FC_IN_CMD_OFST 0 */
1967 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4
1968 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8
1969 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12
1970 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4
1971 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1
1972 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60
1974 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */
1975 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16
1976 /* MC_CMD_FC_IN_CMD_OFST 0 */
1977 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4
1978 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8
1979 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12
1981 /* MC_CMD_FC_IN_DIAG msgrequest */
1982 #define MC_CMD_FC_IN_DIAG_LEN 8
1983 /* MC_CMD_FC_IN_CMD_OFST 0 */
1984 /* Operation code indicating component type */
1985 #define MC_CMD_FC_IN_DIAG_OP_OFST 4
1986 /* enum: Power noise generator. */
1987 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0
1988 /* enum: DDR soak test component. */
1989 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1
1990 /* enum: Diagnostics datapath control component. */
1991 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2
1993 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */
1994 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12
1995 /* MC_CMD_FC_IN_CMD_OFST 0 */
1996 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4
1997 /* Sub-opcode describing the operation to be carried out */
1998 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8
1999 /* enum: Read the configuration (the 32-bit values in each of the clock enable
2000 * count and toggle count registers)
2002 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0
2003 /* enum: Write a new configuration to the clock enable count and toggle count
2006 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1
2008 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */
2009 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12
2010 /* MC_CMD_FC_IN_CMD_OFST 0 */
2011 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4
2012 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8
2014 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */
2015 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20
2016 /* MC_CMD_FC_IN_CMD_OFST 0 */
2017 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4
2018 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8
2019 /* The 32-bit value to be written to the toggle count register */
2020 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12
2021 /* The 32-bit value to be written to the clock enable count register */
2022 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16
2024 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */
2025 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12
2026 /* MC_CMD_FC_IN_CMD_OFST 0 */
2027 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4
2028 /* Sub-opcode describing the operation to be carried out */
2029 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8
2030 /* enum: Starts DDR soak test on selected banks */
2031 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0
2032 /* enum: Read status of DDR soak test */
2033 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1
2034 /* enum: Stop test */
2035 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2
2036 /* enum: Set or clear bit that triggers fake errors. These cause subsequent
2037 * tests to fail until the bit is cleared.
2039 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3
2041 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */
2042 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24
2043 /* MC_CMD_FC_IN_CMD_OFST 0 */
2044 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4
2045 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8
2046 /* Mask of DDR banks to be tested */
2047 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12
2048 /* Pattern to use in the soak test */
2049 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16
2050 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */
2051 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */
2052 /* Either multiple automatic tests until a STOP command is issued, or one
2055 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20
2056 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */
2057 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */
2059 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */
2060 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16
2061 /* MC_CMD_FC_IN_CMD_OFST 0 */
2062 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4
2063 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8
2064 /* DDR bank to read status from */
2065 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12
2066 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */
2067 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */
2068 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */
2069 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */
2070 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */
2072 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */
2073 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16
2074 /* MC_CMD_FC_IN_CMD_OFST 0 */
2075 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4
2076 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8
2077 /* Mask of DDR banks to be tested */
2078 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12
2080 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */
2081 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20
2082 /* MC_CMD_FC_IN_CMD_OFST 0 */
2083 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4
2084 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8
2085 /* Mask of DDR banks to set/clear error flag on */
2086 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12
2087 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16
2088 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */
2089 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */
2091 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */
2092 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12
2093 /* MC_CMD_FC_IN_CMD_OFST 0 */
2094 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4
2095 /* Sub-opcode describing the operation to be carried out */
2096 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8
2097 /* enum: Set a known datapath configuration */
2098 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0
2099 /* enum: Apply raw config to datapath control registers */
2100 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1
2102 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */
2103 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16
2104 /* MC_CMD_FC_IN_CMD_OFST 0 */
2105 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4
2106 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8
2107 /* Datapath configuration identifier */
2108 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12
2109 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */
2110 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */
2112 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */
2113 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24
2114 /* MC_CMD_FC_IN_CMD_OFST 0 */
2115 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4
2116 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8
2117 /* Value to write into control register 1 */
2118 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12
2119 /* Value to write into control register 2 */
2120 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16
2121 /* Value to write into control register 3 */
2122 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20
2124 /* MC_CMD_FC_OUT msgresponse */
2125 #define MC_CMD_FC_OUT_LEN 0
2127 /* MC_CMD_FC_OUT_NULL msgresponse */
2128 #define MC_CMD_FC_OUT_NULL_LEN 0
2130 /* MC_CMD_FC_OUT_READ32 msgresponse */
2131 #define MC_CMD_FC_OUT_READ32_LENMIN 4
2132 #define MC_CMD_FC_OUT_READ32_LENMAX 252
2133 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num))
2134 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0
2135 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4
2136 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1
2137 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63
2139 /* MC_CMD_FC_OUT_WRITE32 msgresponse */
2140 #define MC_CMD_FC_OUT_WRITE32_LEN 0
2142 /* MC_CMD_FC_OUT_TRC_READ msgresponse */
2143 #define MC_CMD_FC_OUT_TRC_READ_LEN 16
2144 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0
2145 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4
2146 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4
2148 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */
2149 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0
2151 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */
2152 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12
2153 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0
2154 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4
2155 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8
2156 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4
2157 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8
2159 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */
2160 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8
2161 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0
2162 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4
2163 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2
2165 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */
2166 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0
2168 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */
2169 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0
2171 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */
2172 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0
2174 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */
2175 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4
2176 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0
2178 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */
2179 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3)
2180 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0
2181 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8
2182 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0
2183 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4
2184 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS
2185 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */
2186 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */
2187 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */
2188 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */
2189 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */
2190 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */
2191 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */
2192 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */
2193 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */
2194 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */
2195 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */
2196 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */
2197 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */
2198 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */
2199 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */
2200 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */
2201 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */
2202 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */
2203 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */
2204 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */
2205 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */
2206 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */
2207 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */
2208 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */
2209 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */
2210 /* enum: (Last entry) */
2211 #define MC_CMD_FC_MAC_RX_NSTATS 0x19
2213 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */
2214 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3)
2215 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0
2216 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8
2217 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0
2218 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4
2219 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS
2220 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */
2221 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */
2222 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */
2223 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */
2224 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */
2225 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */
2226 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */
2227 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */
2228 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */
2229 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */
2230 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */
2231 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */
2232 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */
2233 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */
2234 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */
2235 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */
2236 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */
2237 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */
2238 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */
2239 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */
2240 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */
2241 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */
2242 /* enum: (Last entry) */
2243 #define MC_CMD_FC_MAC_TX_NSTATS 0x16
2245 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */
2246 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3)
2247 /* MAC Statistics */
2248 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0
2249 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8
2250 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0
2251 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4
2252 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK
2254 /* MC_CMD_FC_OUT_MAC msgresponse */
2255 #define MC_CMD_FC_OUT_MAC_LEN 0
2257 /* MC_CMD_FC_OUT_SFP msgresponse */
2258 #define MC_CMD_FC_OUT_SFP_LEN 0
2260 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */
2261 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0
2263 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */
2264 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8
2265 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0
2266 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0
2267 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8
2268 /* enum: Test not yet initiated */
2269 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0
2270 /* enum: Test is in progress */
2271 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1
2272 /* enum: Timed completed */
2273 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2
2274 /* enum: Test did not complete in specified time */
2275 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3
2276 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11
2277 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1
2278 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10
2279 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1
2280 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9
2281 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1
2282 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8
2283 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1
2284 /* Test result from FPGA */
2285 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4
2286 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31
2287 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1
2288 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30
2289 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1
2290 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29
2291 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1
2292 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28
2293 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1
2294 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15
2295 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5
2296 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10
2297 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5
2298 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5
2299 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5
2300 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0
2301 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5
2302 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */
2303 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */
2304 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */
2305 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */
2306 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */
2308 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */
2309 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0
2311 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */
2312 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144
2313 /* Assertion status flag. */
2314 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0
2315 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8
2316 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8
2317 /* enum: No crash data available */
2318 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0
2319 /* enum: New crash data available */
2320 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1
2321 /* enum: Crash data has been sent */
2322 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2
2323 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0
2324 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8
2325 /* enum: No crash has been recorded. */
2326 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0
2327 /* enum: Crash due to exception. */
2328 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1
2329 /* enum: Crash due to assertion. */
2330 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2
2331 /* Failing PC value */
2332 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4
2334 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8
2335 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4
2336 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31
2337 /* Exception Type */
2338 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132
2339 /* Instruction at which exception occurred */
2340 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136
2341 /* BAD Address that triggered address-based exception */
2342 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140
2344 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */
2345 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32
2346 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0
2347 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31
2348 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1
2349 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30
2350 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1
2351 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16
2352 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14
2353 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12
2354 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4
2355 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4
2356 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8
2357 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0
2358 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4
2359 /* Build timestamp (seconds since epoch) */
2360 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4
2361 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8
2362 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0
2363 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8
2364 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */
2365 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */
2366 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8
2367 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10
2368 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18
2369 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1
2370 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19
2371 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1
2372 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20
2373 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1
2374 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21
2375 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1
2376 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22
2377 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1
2378 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23
2379 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1
2380 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24
2381 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1
2382 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25
2383 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1
2384 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26
2385 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1
2386 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27
2387 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1
2388 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28
2389 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1
2390 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29
2391 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2
2392 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31
2393 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1
2394 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12
2395 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0
2396 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16
2397 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16
2398 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1
2399 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */
2400 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */
2401 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17
2402 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15
2403 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16
2404 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0
2405 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16
2406 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16
2407 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16
2408 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20
2409 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0
2410 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16
2411 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16
2412 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16
2413 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16
2414 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8
2415 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16
2416 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20
2417 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24
2418 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28
2419 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0
2420 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16
2422 /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */
2423 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32
2424 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0
2425 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31
2426 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1
2427 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30
2428 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1
2429 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16
2430 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14
2431 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12
2432 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4
2433 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4
2434 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8
2435 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0
2436 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4
2437 /* Build timestamp (seconds since epoch) */
2438 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4
2439 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8
2440 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31
2441 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1
2442 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29
2443 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1
2444 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28
2445 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1
2446 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27
2447 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1
2448 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26
2449 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1
2450 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25
2451 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1
2452 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24
2453 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1
2454 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23
2455 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1
2456 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22
2457 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1
2458 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21
2459 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1
2460 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20
2461 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1
2462 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19
2463 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1
2464 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18
2465 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1
2466 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */
2467 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */
2468 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17
2469 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1
2470 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */
2471 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */
2472 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16
2473 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1
2474 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */
2475 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */
2476 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15
2477 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1
2478 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14
2479 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1
2480 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13
2481 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1
2482 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12
2483 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1
2484 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11
2485 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1
2486 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10
2487 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1
2488 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9
2489 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1
2490 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8
2491 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1
2492 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7
2493 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1
2494 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6
2495 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1
2496 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5
2497 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1
2498 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4
2499 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1
2500 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0
2501 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4
2502 #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */
2503 #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */
2504 #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */
2505 #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */
2506 #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */
2507 #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */
2508 #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */
2509 #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */
2510 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12
2511 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0
2512 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16
2513 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16
2514 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1
2515 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */
2516 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */
2517 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16
2518 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0
2519 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16
2520 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16
2521 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16
2522 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20
2523 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0
2524 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16
2525 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16
2526 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16
2527 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24
2528 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28
2529 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0
2530 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16
2532 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */
2533 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32
2534 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0
2535 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31
2536 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1
2537 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30
2538 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1
2539 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16
2540 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14
2541 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12
2542 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4
2543 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4
2544 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8
2545 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0
2546 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4
2547 /* Build timestamp (seconds since epoch) */
2548 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4
2549 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8
2550 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8
2551 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1
2552 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27
2553 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1
2554 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28
2555 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1
2556 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29
2557 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1
2558 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30
2559 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1
2560 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31
2561 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1
2562 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12
2563 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0
2564 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16
2565 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16
2566 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1
2567 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16
2568 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0
2569 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16
2570 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16
2571 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16
2572 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20
2573 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0
2574 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16
2575 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16
2576 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16
2577 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24
2578 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28
2579 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0
2580 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16
2582 /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */
2583 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32
2584 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0
2585 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31
2586 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1
2587 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30
2588 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1
2589 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16
2590 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14
2591 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12
2592 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4
2593 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4
2594 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8
2595 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0
2596 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4
2597 /* Build timestamp (seconds since epoch) */
2598 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4
2599 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8
2600 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0
2601 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1
2602 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8
2603 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1
2604 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12
2605 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0
2606 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16
2607 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16
2608 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1
2609 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */
2610 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */
2611 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24
2612 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28
2613 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0
2614 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16
2616 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */
2617 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4
2618 /* Qsys system ID */
2619 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0
2620 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12
2621 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4
2622 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4
2623 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8
2624 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0
2625 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4
2627 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */
2628 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4
2629 /* Number of maps */
2630 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0
2632 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */
2633 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164
2634 /* Index of the map */
2635 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0
2636 /* Options for the map */
2637 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4
2638 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */
2639 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */
2640 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */
2641 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */
2642 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */
2643 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */
2644 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */
2645 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */
2646 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */
2647 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */
2648 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */
2649 /* Address of start of map */
2650 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8
2651 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8
2652 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8
2653 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12
2654 /* Length of address map */
2655 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16
2656 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8
2657 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16
2658 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20
2659 /* Component information field */
2660 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24
2661 /* License expiry data for map */
2662 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28
2663 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8
2664 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28
2665 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32
2666 /* Name of the component */
2667 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36
2668 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1
2669 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128
2671 /* MC_CMD_FC_OUT_READ_MAP msgresponse */
2672 #define MC_CMD_FC_OUT_READ_MAP_LEN 0
2674 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */
2675 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8
2676 /* Number of internal ports */
2677 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0
2678 /* Number of external ports */
2679 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4
2681 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */
2682 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4
2683 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0
2685 /* MC_CMD_FC_OUT_IO_REL msgresponse */
2686 #define MC_CMD_FC_OUT_IO_REL_LEN 0
2688 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */
2689 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8
2690 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0
2691 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4
2693 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */
2694 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4
2695 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252
2696 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num))
2697 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0
2698 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4
2699 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1
2700 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63
2702 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */
2703 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0
2705 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */
2706 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48
2707 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0
2708 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0
2709 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16
2710 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16
2711 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16
2712 /* Transceiver Transmit settings */
2713 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4
2714 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0
2715 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16
2716 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16
2717 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16
2718 /* Transceiver Receive settings */
2719 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8
2720 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0
2721 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16
2722 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16
2723 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16
2724 /* Rx eye opening */
2725 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12
2726 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0
2727 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16
2728 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16
2729 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16
2730 /* PCS status word */
2731 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16
2732 /* Link status word */
2733 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20
2734 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0
2735 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1
2736 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1
2737 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1
2738 /* Current SFp parameters applied */
2739 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24
2740 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20
2741 /* Link speed is 100, 1000, 10000 */
2742 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24
2743 /* Length of copper cable - zero when not relevant */
2744 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28
2745 /* True if a dual speed SFP+ module */
2746 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32
2747 /* True if an SFP Module is present (other fields valid when true) */
2748 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36
2749 /* The type of the SFP+ Module */
2750 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40
2751 /* PHY config flags */
2752 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44
2753 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0
2754 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1
2755 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1
2756 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1
2757 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2
2758 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1
2760 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */
2761 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20
2762 /* MAC configuration applied */
2763 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0
2765 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4
2766 /* IF Mode status */
2767 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8
2768 /* MAC address configured */
2769 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12
2770 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8
2771 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12
2772 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16
2774 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */
2775 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)
2776 /* Rx Eye measurements */
2777 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0
2778 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4
2779 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK
2781 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */
2782 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0
2784 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */
2785 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3)
2786 /* Has the eye plot dump completed and data returned is valid? */
2787 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0
2788 /* Rx Eye binary plot */
2789 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4
2790 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8
2791 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4
2792 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8
2793 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK
2795 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */
2796 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0
2798 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */
2799 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0
2801 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */
2802 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4
2803 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0
2805 /* MC_CMD_FC_OUT_UHLINK msgresponse */
2806 #define MC_CMD_FC_OUT_UHLINK_LEN 0
2808 /* MC_CMD_FC_OUT_SET_LINK msgresponse */
2809 #define MC_CMD_FC_OUT_SET_LINK_LEN 0
2811 /* MC_CMD_FC_OUT_LICENSE msgresponse */
2812 #define MC_CMD_FC_OUT_LICENSE_LEN 12
2813 /* Count of valid keys */
2814 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0
2815 /* Count of invalid keys */
2816 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4
2817 /* Count of blacklisted keys */
2818 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8
2820 /* MC_CMD_FC_OUT_STARTUP msgresponse */
2821 #define MC_CMD_FC_OUT_STARTUP_LEN 4
2822 /* Capabilities of the FPGA/FC */
2823 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0
2824 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0
2825 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1
2827 /* MC_CMD_FC_OUT_DMA_READ msgresponse */
2828 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1
2829 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252
2830 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num))
2832 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0
2833 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1
2834 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1
2835 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252
2837 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */
2838 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4
2840 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0
2842 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */
2843 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52
2844 /* Host supplied handle (unique) */
2845 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0
2846 /* Address into which to transfer data in host */
2847 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4
2848 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8
2849 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4
2850 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8
2851 /* AOE address from which to transfer data */
2852 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12
2853 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8
2854 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12
2855 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16
2856 /* Length of AOE transfer (total) */
2857 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20
2858 /* Length of host transfer (total) */
2859 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24
2860 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */
2861 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28
2862 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32
2863 /* When active, start read time */
2864 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36
2865 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8
2866 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36
2867 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40
2868 /* When active, end read time */
2869 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44
2870 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8
2871 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44
2872 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48
2874 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */
2875 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0
2877 /* MC_CMD_FC_OUT_LOG msgresponse */
2878 #define MC_CMD_FC_OUT_LOG_LEN 0
2880 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */
2881 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24
2882 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0
2883 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4
2884 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8
2885 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4
2886 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8
2887 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12
2888 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16
2889 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20
2891 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */
2892 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0
2894 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */
2895 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0
2897 /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */
2898 #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0
2900 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */
2901 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4
2902 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0
2903 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0
2904 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1
2905 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1
2906 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1
2908 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */
2909 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8
2910 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0
2911 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4
2913 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */
2914 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8
2915 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248
2916 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num))
2917 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0
2918 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4
2919 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0
2920 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8
2921 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0
2922 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4
2923 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0
2924 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31
2926 /* MC_CMD_FC_OUT_SPI_READ msgresponse */
2927 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4
2928 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252
2929 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num))
2930 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0
2931 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4
2932 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1
2933 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63
2935 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */
2936 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0
2938 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */
2939 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0
2941 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */
2942 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8
2943 /* The 32-bit value read from the toggle count register */
2944 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0
2945 /* The 32-bit value read from the clock enable count register */
2946 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4
2948 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */
2949 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0
2951 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */
2952 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0
2954 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */
2955 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8
2956 /* DDR soak test status word; bits [4:0] are relevant. */
2957 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0
2958 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0
2959 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1
2960 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1
2961 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1
2962 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2
2963 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1
2964 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3
2965 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1
2966 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4
2967 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1
2968 /* DDR soak test error count */
2969 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4
2971 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */
2972 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0
2974 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */
2975 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0
2977 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */
2978 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0
2980 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */
2981 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0
2984 /***********************************/
2986 * AOE operations on MC
2988 #define MC_CMD_AOE 0xa
2990 /* MC_CMD_AOE_IN msgrequest */
2991 #define MC_CMD_AOE_IN_LEN 4
2992 #define MC_CMD_AOE_IN_OP_HDR_OFST 0
2993 #define MC_CMD_AOE_IN_OP_LBN 0
2994 #define MC_CMD_AOE_IN_OP_WIDTH 8
2995 /* enum: FPGA and CPLD information */
2996 #define MC_CMD_AOE_OP_INFO 0x1
2997 /* enum: Currents and voltages read from MCP3424s; DEBUG */
2998 #define MC_CMD_AOE_OP_CURRENTS 0x2
2999 /* enum: Temperatures at locations around the PCB; DEBUG */
3000 #define MC_CMD_AOE_OP_TEMPERATURES 0x3
3001 /* enum: Set CPLD to idle */
3002 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4
3003 /* enum: Read from CPLD register */
3004 #define MC_CMD_AOE_OP_CPLD_READ 0x5
3005 /* enum: Write to CPLD register */
3006 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6
3007 /* enum: Execute CPLD instruction */
3008 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7
3009 /* enum: Reprogram the CPLD on the AOE device */
3010 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8
3011 /* enum: AOE power control */
3012 #define MC_CMD_AOE_OP_POWER 0x9
3013 /* enum: AOE image loading */
3014 #define MC_CMD_AOE_OP_LOAD 0xa
3015 /* enum: Fan monitoring */
3016 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb
3017 /* enum: Fan failures since last reset */
3018 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc
3019 /* enum: Get generic AOE MAC statistics */
3020 #define MC_CMD_AOE_OP_MAC_STATS 0xd
3021 /* enum: Retrieve PHY specific information */
3022 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe
3023 /* enum: Write a number of JTAG primitive commands, return will give data */
3024 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf
3025 /* enum: Control access to the FPGA via the Siena JTAG Chain */
3026 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10
3027 /* enum: Set the MTU offset between Siena and AOE MACs */
3028 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11
3029 /* enum: How link state is handled */
3030 #define MC_CMD_AOE_OP_LINK_STATE 0x12
3031 /* enum: How Siena MAC statistics are reported (deprecated - use
3032 * MC_CMD_AOE_OP_ASIC_STATS)
3034 #define MC_CMD_AOE_OP_SIENA_STATS 0x13
3035 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated
3036 * command MC_CMD_AOE_OP_SIENA_STATS
3038 #define MC_CMD_AOE_OP_ASIC_STATS 0x13
3039 /* enum: DDR memory information */
3040 #define MC_CMD_AOE_OP_DDR 0x14
3041 /* enum: FC control */
3042 #define MC_CMD_AOE_OP_FC 0x15
3043 /* enum: DDR ECC status reads */
3044 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16
3045 /* enum: Commands for MC-SPI Master emulation */
3046 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17
3047 /* enum: Commands for FC boot control */
3048 #define MC_CMD_AOE_OP_FC_BOOT 0x18
3050 /* MC_CMD_AOE_OUT msgresponse */
3051 #define MC_CMD_AOE_OUT_LEN 0
3053 /* MC_CMD_AOE_IN_INFO msgrequest */
3054 #define MC_CMD_AOE_IN_INFO_LEN 4
3055 #define MC_CMD_AOE_IN_CMD_OFST 0
3057 /* MC_CMD_AOE_IN_CURRENTS msgrequest */
3058 #define MC_CMD_AOE_IN_CURRENTS_LEN 4
3059 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3061 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */
3062 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4
3063 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3065 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */
3066 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4
3067 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3069 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */
3070 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12
3071 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3072 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4
3073 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8
3075 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */
3076 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16
3077 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3078 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4
3079 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8
3080 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12
3082 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */
3083 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8
3084 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3085 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4
3087 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */
3088 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8
3089 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3090 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4
3091 /* enum: Reprogram CPLD, poll for completion */
3092 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1
3093 /* enum: Reprogram CPLD, send event on completion */
3094 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3
3095 /* enum: Get status of reprogramming operation */
3096 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4
3098 /* MC_CMD_AOE_IN_POWER msgrequest */
3099 #define MC_CMD_AOE_IN_POWER_LEN 8
3100 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3101 /* Turn on or off AOE power */
3102 #define MC_CMD_AOE_IN_POWER_OP_OFST 4
3103 /* enum: Turn off FPGA power */
3104 #define MC_CMD_AOE_IN_POWER_OFF 0x0
3105 /* enum: Turn on FPGA power */
3106 #define MC_CMD_AOE_IN_POWER_ON 0x1
3107 /* enum: Clear peak power measurement */
3108 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2
3109 /* enum: Show current power in sensors output */
3110 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3
3111 /* enum: Show peak power in sensors output */
3112 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4
3113 /* enum: Show current DDR current */
3114 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5
3115 /* enum: Show peak DDR current */
3116 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6
3117 /* enum: Clear peak DDR current */
3118 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7
3120 /* MC_CMD_AOE_IN_LOAD msgrequest */
3121 #define MC_CMD_AOE_IN_LOAD_LEN 8
3122 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3123 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence
3125 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4
3127 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */
3128 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8
3129 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3130 /* If non zero report measured fan RPM rather than nominal */
3131 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4
3133 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */
3134 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4
3135 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3137 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */
3138 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24
3139 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3141 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4
3142 /* Host memory address for statistics */
3143 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8
3144 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8
3145 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8
3146 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12
3147 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16
3148 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0
3149 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1
3150 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1
3151 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1
3152 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2
3153 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1
3154 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3
3155 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1
3156 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4
3157 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1
3158 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5
3159 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1
3160 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16
3161 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16
3162 /* Length of DMA data (optional) */
3163 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20
3165 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */
3166 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12
3167 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3169 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4
3170 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8
3172 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */
3173 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12
3174 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252
3175 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num))
3176 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3177 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4
3178 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8
3179 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4
3180 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1
3181 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61
3183 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */
3184 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8
3185 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3186 /* Enable or disable access */
3187 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4
3188 /* enum: Enable access */
3189 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1
3190 /* enum: Disable access */
3191 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2
3193 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */
3194 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12
3195 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3196 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */
3197 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4
3198 /* enum: Apply to all external ports */
3199 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000
3200 /* enum: Apply to all internal ports */
3201 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000
3202 /* The MTU offset to be applied to the external ports */
3203 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8
3205 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */
3206 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8
3207 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3208 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4
3209 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0
3210 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8
3211 /* enum: AOE and associated external port */
3212 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0
3213 /* enum: AOE and OR of all external ports */
3214 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1
3215 /* enum: Individual ports */
3216 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2
3217 /* enum: Configure link state mode on given AOE port */
3218 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3
3219 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8
3220 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8
3222 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0
3223 /* enum: logical OR of all SFP ports link status */
3224 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1
3225 /* enum: logical AND of all SFP ports link status */
3226 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2
3227 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16
3228 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16
3230 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */
3231 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8
3232 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3233 /* How MAC statistics are reported */
3234 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4
3235 /* enum: Statistics from Siena (default) */
3236 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0
3237 /* enum: Statistics from AOE external ports */
3238 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1
3240 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */
3241 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8
3242 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3243 /* How MAC statistics are reported */
3244 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4
3245 /* enum: Statistics from the ASIC (default) */
3246 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0
3247 /* enum: Statistics from AOE external ports */
3248 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1
3250 /* MC_CMD_AOE_IN_DDR msgrequest */
3251 #define MC_CMD_AOE_IN_DDR_LEN 12
3252 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3253 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4
3254 /* Enum values, see field(s): */
3255 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */
3256 /* Page index of SPD data */
3257 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8
3259 /* MC_CMD_AOE_IN_FC msgrequest */
3260 #define MC_CMD_AOE_IN_FC_LEN 4
3261 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3263 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */
3264 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8
3265 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3266 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4
3267 /* Enum values, see field(s): */
3268 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */
3270 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */
3271 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8
3272 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3273 /* Basic commands for MC SPI Master emulation. */
3274 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4
3275 /* enum: MC SPI read */
3276 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0
3277 /* enum: MC SPI write */
3278 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1
3280 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */
3281 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12
3282 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3283 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4
3284 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8
3286 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */
3287 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16
3288 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3289 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4
3290 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8
3291 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12
3293 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */
3294 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8
3295 /* MC_CMD_AOE_IN_CMD_OFST 0 */
3296 /* FC boot control flags */
3297 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4
3298 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0
3299 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1
3301 /* MC_CMD_AOE_OUT_INFO msgresponse */
3302 #define MC_CMD_AOE_OUT_INFO_LEN 44
3303 /* JTAG IDCODE of CPLD */
3304 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0
3305 /* Version of CPLD */
3306 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4
3307 /* JTAG IDCODE of FPGA */
3308 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8
3309 /* JTAG USERCODE of FPGA */
3310 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12
3311 /* FPGA type - read from CPLD straps */
3312 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16
3313 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */
3314 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */
3315 /* FPGA state (debug) */
3316 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20
3317 /* FPGA image - partition from which loaded */
3318 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24
3320 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28
3321 /* enum: Set if watchdog working */
3322 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1
3323 /* enum: Set if MC-FC communications working */
3324 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2
3325 /* Random pieces of information */
3326 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32
3327 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */
3328 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1
3329 /* enum: CPLD apparently good */
3330 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2
3331 /* enum: FPGA working normally */
3332 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4
3333 /* enum: FPGA is powered */
3334 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8
3335 /* enum: Board has incompatible SODIMMs fitted */
3336 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10
3337 /* enum: Board has ByteBlaster connected */
3338 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20
3339 /* enum: FPGA Boot flash has an invalid header. */
3340 #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40
3341 /* enum: FPGA Application flash is accessible. */
3342 #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80
3343 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */
3344 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36
3345 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */
3346 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */
3347 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */
3348 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */
3349 #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */
3350 /* Result of FC booting - not valid while a ByteBlaster is connected. */
3351 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40
3352 /* enum: No error */
3353 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0
3354 /* enum: Bad address set in CPLD */
3355 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1
3356 /* enum: Bad header */
3357 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2
3358 /* enum: Bad text section details */
3359 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3
3360 /* enum: Bad checksum */
3361 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4
3363 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5
3364 /* enum: Flash mode is invalid */
3365 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6
3366 /* enum: FC application loaded and execution attempted */
3367 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80
3368 /* enum: FC application Started */
3369 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81
3370 /* enum: No bootrom in FPGA */
3371 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff
3373 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */
3374 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68
3375 /* Set of currents and voltages (mA or mV as appropriate) */
3376 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0
3377 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4
3378 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17
3379 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */
3380 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */
3381 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */
3382 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */
3383 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */
3384 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */
3385 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */
3386 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */
3387 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */
3388 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */
3389 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */
3390 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */
3391 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */
3392 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */
3393 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */
3394 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */
3395 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */
3397 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */
3398 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40
3399 /* Set of temperatures */
3400 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0
3401 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4
3402 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10
3403 /* enum: The first set of enum values are for Modena code. */
3404 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0
3405 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */
3406 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */
3407 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */
3408 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */
3409 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */
3410 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */
3411 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */
3412 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */
3413 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */
3414 /* enum: The second set of enum values are for Sorrento code. */
3415 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0
3416 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */
3417 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */
3418 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */
3419 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */
3420 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */
3421 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */
3422 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */
3423 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */
3425 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */
3426 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4
3427 /* The value read from the CPLD */
3428 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0
3430 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */
3431 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4
3432 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252
3433 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num))
3434 /* Failure counts for each fan */
3435 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0
3436 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4
3437 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1
3438 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63
3440 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */
3441 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4
3442 /* Results of status command (only) */
3443 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0
3445 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */
3446 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0
3448 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */
3449 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0
3451 /* MC_CMD_AOE_OUT_LOAD msgresponse */
3452 #define MC_CMD_AOE_OUT_LOAD_LEN 0
3454 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */
3455 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0
3457 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA
3460 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
3461 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0
3462 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8
3463 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0
3464 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4
3465 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
3467 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */
3468 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5
3469 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252
3470 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num))
3472 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0
3473 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4
3474 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1
3475 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1
3476 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248
3478 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */
3479 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12
3480 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252
3481 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num))
3482 /* Used to align the in and out data blocks so the MC can re-use the cmd */
3483 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0
3485 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4
3486 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8
3487 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4
3488 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1
3489 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61
3491 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */
3492 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0
3494 /* MC_CMD_AOE_OUT_DDR msgresponse */
3495 #define MC_CMD_AOE_OUT_DDR_LENMIN 17
3496 #define MC_CMD_AOE_OUT_DDR_LENMAX 252
3497 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num))
3498 /* Information on the module. */
3499 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0
3500 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0
3501 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1
3502 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1
3503 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1
3504 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2
3505 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1
3506 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3
3507 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1
3508 /* Memory size, in MB. */
3509 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4
3510 /* The memory type, as reported from SPD information */
3511 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8
3512 /* Nominal voltage of the module (as applied) */
3513 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12
3514 /* SPD data read from the module */
3515 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16
3516 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1
3517 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1
3518 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236
3520 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */
3521 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0
3523 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */
3524 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0
3526 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */
3527 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0
3529 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */
3530 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0
3532 /* MC_CMD_AOE_OUT_FC msgresponse */
3533 #define MC_CMD_AOE_OUT_FC_LEN 0
3535 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */
3536 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8
3537 /* Flags describing status info on the module. */
3538 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0
3539 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0
3540 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1
3541 /* DDR ECC status on the module. */
3542 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4
3543 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0
3544 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1
3545 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1
3546 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1
3547 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2
3548 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1
3549 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8
3550 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8
3551 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16
3552 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8
3553 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24
3554 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8
3556 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */
3557 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4
3558 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0
3560 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */
3561 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0
3563 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */
3564 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0
3566 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */
3567 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0
3570 /***********************************/
3572 * Perform PTP operation
3574 #define MC_CMD_PTP 0xb
3575 #undef MC_CMD_0xb_PRIVILEGE_CTG
3577 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3579 /* MC_CMD_PTP_IN msgrequest */
3580 #define MC_CMD_PTP_IN_LEN 1
3581 /* PTP operation code */
3582 #define MC_CMD_PTP_IN_OP_OFST 0
3583 #define MC_CMD_PTP_IN_OP_LEN 1
3584 /* enum: Enable PTP packet timestamping operation. */
3585 #define MC_CMD_PTP_OP_ENABLE 0x1
3586 /* enum: Disable PTP packet timestamping operation. */
3587 #define MC_CMD_PTP_OP_DISABLE 0x2
3588 /* enum: Send a PTP packet. */
3589 #define MC_CMD_PTP_OP_TRANSMIT 0x3
3590 /* enum: Read the current NIC time. */
3591 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
3592 /* enum: Get the current PTP status. */
3593 #define MC_CMD_PTP_OP_STATUS 0x5
3594 /* enum: Adjust the PTP NIC's time. */
3595 #define MC_CMD_PTP_OP_ADJUST 0x6
3596 /* enum: Synchronize host and NIC time. */
3597 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
3598 /* enum: Basic manufacturing tests. */
3599 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
3600 /* enum: Packet based manufacturing tests. */
3601 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
3602 /* enum: Reset some of the PTP related statistics */
3603 #define MC_CMD_PTP_OP_RESET_STATS 0xa
3604 /* enum: Debug operations to MC. */
3605 #define MC_CMD_PTP_OP_DEBUG 0xb
3606 /* enum: Read an FPGA register */
3607 #define MC_CMD_PTP_OP_FPGAREAD 0xc
3608 /* enum: Write an FPGA register */
3609 #define MC_CMD_PTP_OP_FPGAWRITE 0xd
3610 /* enum: Apply an offset to the NIC clock */
3611 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
3612 /* enum: Change Apply an offset to the NIC clock */
3613 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
3614 /* enum: Set the MC packet filter VLAN tags for received PTP packets */
3615 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
3616 /* enum: Set the MC packet filter UUID for received PTP packets */
3617 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
3618 /* enum: Set the MC packet filter Domain for received PTP packets */
3619 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
3620 /* enum: Set the clock source */
3621 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
3622 /* enum: Reset value of Timer Reg. */
3623 #define MC_CMD_PTP_OP_RST_CLK 0x14
3624 /* enum: Enable the forwarding of PPS events to the host */
3625 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15
3626 /* enum: Get the time format used by this NIC for PTP operations */
3627 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
3628 /* enum: Get the clock attributes. NOTE- extended version of
3629 * MC_CMD_PTP_OP_GET_TIME_FORMAT
3631 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
3632 /* enum: Get corrections that should be applied to the various different
3635 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
3636 /* enum: Subscribe to receive periodic time events indicating the current NIC
3639 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
3640 /* enum: Unsubscribe to stop receiving time events */
3641 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
3642 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS
3643 * input on the same NIC.
3645 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
3646 /* enum: Set the PTP sync status. Status is used by firmware to report to event
3649 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
3650 /* enum: Above this for future use. */
3651 #define MC_CMD_PTP_OP_MAX 0x1c
3653 /* MC_CMD_PTP_IN_ENABLE msgrequest */
3654 #define MC_CMD_PTP_IN_ENABLE_LEN 16
3655 #define MC_CMD_PTP_IN_CMD_OFST 0
3656 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
3657 /* Event queue for PTP events */
3658 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
3659 /* PTP timestamping mode */
3660 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
3661 /* enum: PTP, version 1 */
3662 #define MC_CMD_PTP_MODE_V1 0x0
3663 /* enum: PTP, version 1, with VLAN headers - deprecated */
3664 #define MC_CMD_PTP_MODE_V1_VLAN 0x1
3665 /* enum: PTP, version 2 */
3666 #define MC_CMD_PTP_MODE_V2 0x2
3667 /* enum: PTP, version 2, with VLAN headers - deprecated */
3668 #define MC_CMD_PTP_MODE_V2_VLAN 0x3
3669 /* enum: PTP, version 2, with improved UUID filtering */
3670 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
3671 /* enum: FCoE (seconds and microseconds) */
3672 #define MC_CMD_PTP_MODE_FCOE 0x5
3674 /* MC_CMD_PTP_IN_DISABLE msgrequest */
3675 #define MC_CMD_PTP_IN_DISABLE_LEN 8
3676 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3677 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3679 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */
3680 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
3681 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
3682 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
3683 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3684 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3685 /* Transmit packet length */
3686 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
3687 /* Transmit packet data */
3688 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
3689 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
3690 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
3691 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
3693 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
3694 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
3695 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3696 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3698 /* MC_CMD_PTP_IN_STATUS msgrequest */
3699 #define MC_CMD_PTP_IN_STATUS_LEN 8
3700 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3701 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3703 /* MC_CMD_PTP_IN_ADJUST msgrequest */
3704 #define MC_CMD_PTP_IN_ADJUST_LEN 24
3705 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3706 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3707 /* Frequency adjustment 40 bit fixed point ns */
3708 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
3709 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
3710 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
3711 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
3712 /* enum: Number of fractional bits in frequency adjustment */
3713 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28
3714 /* Time adjustment in seconds */
3715 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
3716 /* Time adjustment major value */
3717 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16
3718 /* Time adjustment in nanoseconds */
3719 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
3720 /* Time adjustment minor value */
3721 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20
3723 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
3724 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
3725 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3726 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3727 /* Number of time readings to capture */
3728 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
3729 /* Host address in which to write "synchronization started" indication (64
3732 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
3733 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
3734 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
3735 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
3737 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
3738 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
3739 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3740 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3742 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
3743 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
3744 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3745 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3746 /* Enable or disable packet testing */
3747 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
3749 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */
3750 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8
3751 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3752 /* Reset PTP statistics */
3753 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3755 /* MC_CMD_PTP_IN_DEBUG msgrequest */
3756 #define MC_CMD_PTP_IN_DEBUG_LEN 12
3757 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3758 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3759 /* Debug operations */
3760 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
3762 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */
3763 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16
3764 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3765 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3766 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8
3767 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12
3769 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
3770 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
3771 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
3772 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
3773 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3774 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3775 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8
3776 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12
3777 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
3778 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
3779 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
3781 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
3782 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
3783 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3784 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3785 /* Time adjustment in seconds */
3786 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
3787 /* Time adjustment major value */
3788 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8
3789 /* Time adjustment in nanoseconds */
3790 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
3791 /* Time adjustment minor value */
3792 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12
3794 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
3795 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
3796 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3797 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3798 /* Frequency adjustment 40 bit fixed point ns */
3799 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
3800 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
3801 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
3802 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
3803 /* enum: Number of fractional bits in frequency adjustment */
3804 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
3806 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
3807 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
3808 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3809 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3810 /* Number of VLAN tags, 0 if not VLAN */
3811 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
3812 /* Set of VLAN tags to filter against */
3813 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
3814 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
3815 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3
3817 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */
3818 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
3819 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3820 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3821 /* 1 to enable UUID filtering, 0 to disable */
3822 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
3823 /* UUID to filter against */
3824 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
3825 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
3826 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
3827 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
3829 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
3830 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
3831 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3832 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3833 /* 1 to enable Domain filtering, 0 to disable */
3834 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
3835 /* Domain number to filter against */
3836 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
3838 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */
3839 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12
3840 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3841 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3842 /* Set the clock source. */
3843 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8
3844 /* enum: Internal. */
3845 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
3846 /* enum: External. */
3847 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
3849 /* MC_CMD_PTP_IN_RST_CLK msgrequest */
3850 #define MC_CMD_PTP_IN_RST_CLK_LEN 8
3851 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3852 /* Reset value of Timer Reg. */
3853 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3855 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
3856 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
3857 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3858 /* Enable or disable */
3859 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
3861 #define MC_CMD_PTP_ENABLE_PPS 0x0
3863 #define MC_CMD_PTP_DISABLE_PPS 0x1
3864 /* Queue id to send events back */
3865 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
3867 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */
3868 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8
3869 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3870 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3872 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */
3873 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8
3874 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3875 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3877 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */
3878 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8
3879 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3880 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3882 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */
3883 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12
3884 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3885 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3886 /* Original field containing queue ID. Now extended to include flags. */
3887 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8
3888 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
3889 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16
3890 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31
3891 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1
3893 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */
3894 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16
3895 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3896 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3897 /* Unsubscribe options */
3898 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8
3899 /* enum: Unsubscribe a single queue */
3900 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
3901 /* enum: Unsubscribe all queues */
3902 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
3903 /* Event queue ID */
3904 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
3906 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
3907 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
3908 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3909 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3910 /* 1 to enable PPS test mode, 0 to disable and return result. */
3911 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8
3913 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */
3914 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24
3915 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3916 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3917 /* NIC - Host System Clock Synchronization status */
3918 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8
3919 /* enum: Host System clock and NIC clock are not in sync */
3920 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
3921 /* enum: Host System clock and NIC clock are synchronized */
3922 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
3923 /* If synchronized, number of seconds until clocks should be considered to be
3924 * no longer in sync.
3926 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12
3927 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16
3928 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20
3930 /* MC_CMD_PTP_OUT msgresponse */
3931 #define MC_CMD_PTP_OUT_LEN 0
3933 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
3934 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8
3935 /* Value of seconds timestamp */
3936 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
3937 /* Timestamp major value */
3938 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
3939 /* Value of nanoseconds timestamp */
3940 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
3941 /* Timestamp minor value */
3942 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
3944 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */
3945 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
3947 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */
3948 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
3950 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
3951 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
3952 /* Value of seconds timestamp */
3953 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
3954 /* Timestamp major value */
3955 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
3956 /* Value of nanoseconds timestamp */
3957 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
3958 /* Timestamp minor value */
3959 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
3961 /* MC_CMD_PTP_OUT_STATUS msgresponse */
3962 #define MC_CMD_PTP_OUT_STATUS_LEN 64
3963 /* Frequency of NIC's hardware clock */
3964 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
3965 /* Number of packets transmitted and timestamped */
3966 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
3967 /* Number of packets received and timestamped */
3968 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
3969 /* Number of packets timestamped by the FPGA */
3970 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
3971 /* Number of packets filter matched */
3972 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
3973 /* Number of packets not filter matched */
3974 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
3975 /* Number of PPS overflows (noise on input?) */
3976 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
3977 /* Number of PPS bad periods */
3978 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
3979 /* Minimum period of PPS pulse in nanoseconds */
3980 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
3981 /* Maximum period of PPS pulse in nanoseconds */
3982 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
3983 /* Last period of PPS pulse in nanoseconds */
3984 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
3985 /* Mean period of PPS pulse in nanoseconds */
3986 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
3987 /* Minimum offset of PPS pulse in nanoseconds (signed) */
3988 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
3989 /* Maximum offset of PPS pulse in nanoseconds (signed) */
3990 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
3991 /* Last offset of PPS pulse in nanoseconds (signed) */
3992 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
3993 /* Mean offset of PPS pulse in nanoseconds (signed) */
3994 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
3996 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
3997 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
3998 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
3999 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
4000 /* A set of host and NIC times */
4001 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
4002 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
4003 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
4004 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
4005 /* Host time immediately before NIC's hardware clock read */
4006 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
4007 /* Value of seconds timestamp */
4008 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
4009 /* Timestamp major value */
4010 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
4011 /* Value of nanoseconds timestamp */
4012 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
4013 /* Timestamp minor value */
4014 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8
4015 /* Host time immediately after NIC's hardware clock read */
4016 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
4017 /* Number of nanoseconds waited after reading NIC's hardware clock */
4018 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
4020 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
4021 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
4022 /* Results of testing */
4023 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
4024 /* enum: Successful test */
4025 #define MC_CMD_PTP_MANF_SUCCESS 0x0
4026 /* enum: FPGA load failed */
4027 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
4028 /* enum: FPGA version invalid */
4029 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
4030 /* enum: FPGA registers incorrect */
4031 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
4032 /* enum: Oscillator possibly not working? */
4033 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4
4034 /* enum: Timestamps not increasing */
4035 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
4036 /* enum: Mismatched packet count */
4037 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
4038 /* enum: Mismatched packet count (Siena filter and FPGA) */
4039 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
4040 /* enum: Not enough packets to perform timestamp check */
4041 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
4042 /* enum: Timestamp trigger GPIO not working */
4043 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
4044 /* enum: Insufficient PPS events to perform checks */
4045 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
4046 /* enum: PPS time event period not sufficiently close to 1s. */
4047 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb
4048 /* enum: PPS time event nS reading not sufficiently close to zero. */
4049 #define MC_CMD_PTP_MANF_PPS_NS 0xc
4050 /* enum: PTP peripheral registers incorrect */
4051 #define MC_CMD_PTP_MANF_REGISTERS 0xd
4052 /* enum: Failed to read time from PTP peripheral */
4053 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe
4054 /* Presence of external oscillator */
4055 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
4057 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
4058 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
4059 /* Results of testing */
4060 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
4061 /* Number of packets received by FPGA */
4062 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
4063 /* Number of packets received by Siena filters */
4064 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
4066 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
4067 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
4068 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
4069 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
4070 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
4071 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
4072 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
4073 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
4075 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */
4076 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
4077 /* Time format required/used by for this NIC. Applies to all PTP MCDI
4078 * operations that pass times between the host and firmware. If this operation
4079 * is not supported (older firmware) a format of seconds and nanoseconds should
4082 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
4083 /* enum: Times are in seconds and nanoseconds */
4084 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
4085 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
4086 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
4087 /* enum: Major register has units of seconds, minor 2^-27s per tick */
4088 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
4090 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */
4091 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24
4092 /* Time format required/used by for this NIC. Applies to all PTP MCDI
4093 * operations that pass times between the host and firmware. If this operation
4094 * is not supported (older firmware) a format of seconds and nanoseconds should
4097 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
4098 /* enum: Times are in seconds and nanoseconds */
4099 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
4100 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
4101 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
4102 /* enum: Major register has units of seconds, minor 2^-27s per tick */
4103 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
4104 /* Minimum acceptable value for a corrected synchronization timeset. When
4105 * comparing host and NIC clock times, the MC returns a set of samples that
4106 * contain the host start and end time, the MC time when the host start was
4107 * detected and the time the MC waited between reading the time and detecting
4108 * the host end. The corrected sync window is the difference between the host
4109 * end and start times minus the time that the MC waited for host end.
4111 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
4112 /* Various PTP capabilities */
4113 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8
4114 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
4115 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
4116 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12
4117 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16
4118 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20
4120 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */
4121 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16
4122 /* Uncorrected error on PTP transmit timestamps in NIC clock format */
4123 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
4124 /* Uncorrected error on PTP receive timestamps in NIC clock format */
4125 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
4126 /* Uncorrected error on PPS output in NIC clock format */
4127 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8
4128 /* Uncorrected error on PPS input in NIC clock format */
4129 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12
4131 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */
4132 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24
4133 /* Uncorrected error on PTP transmit timestamps in NIC clock format */
4134 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
4135 /* Uncorrected error on PTP receive timestamps in NIC clock format */
4136 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
4137 /* Uncorrected error on PPS output in NIC clock format */
4138 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8
4139 /* Uncorrected error on PPS input in NIC clock format */
4140 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12
4141 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
4142 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16
4143 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */
4144 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20
4146 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */
4147 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
4148 /* Results of testing */
4149 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
4150 /* Enum values, see field(s): */
4151 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */
4153 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */
4154 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
4157 /***********************************/
4158 /* MC_CMD_CSR_READ32
4159 * Read 32bit words from the indirect memory map.
4161 #define MC_CMD_CSR_READ32 0xc
4162 #undef MC_CMD_0xc_PRIVILEGE_CTG
4164 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4166 /* MC_CMD_CSR_READ32_IN msgrequest */
4167 #define MC_CMD_CSR_READ32_IN_LEN 12
4169 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
4170 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4
4171 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
4173 /* MC_CMD_CSR_READ32_OUT msgresponse */
4174 #define MC_CMD_CSR_READ32_OUT_LENMIN 4
4175 #define MC_CMD_CSR_READ32_OUT_LENMAX 252
4176 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
4177 /* The last dword is the status, not a value read */
4178 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
4179 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
4180 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
4181 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
4184 /***********************************/
4185 /* MC_CMD_CSR_WRITE32
4186 * Write 32bit dwords to the indirect memory map.
4188 #define MC_CMD_CSR_WRITE32 0xd
4189 #undef MC_CMD_0xd_PRIVILEGE_CTG
4191 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4193 /* MC_CMD_CSR_WRITE32_IN msgrequest */
4194 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12
4195 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252
4196 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
4198 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
4199 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
4200 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
4201 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
4202 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
4203 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
4205 /* MC_CMD_CSR_WRITE32_OUT msgresponse */
4206 #define MC_CMD_CSR_WRITE32_OUT_LEN 4
4207 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
4210 /***********************************/
4212 * These commands are used for HP related features. They are grouped under one
4213 * MCDI command to avoid creating too many MCDI commands.
4215 #define MC_CMD_HP 0x54
4216 #undef MC_CMD_0x54_PRIVILEGE_CTG
4218 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4220 /* MC_CMD_HP_IN msgrequest */
4221 #define MC_CMD_HP_IN_LEN 16
4222 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
4223 * the specified address with the specified interval.When address is NULL,
4224 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
4225 * state / 2: (debug) Show temperature reported by one of the supported
4228 #define MC_CMD_HP_IN_SUBCMD_OFST 0
4229 /* enum: OCSD (Option Card Sensor Data) sub-command. */
4230 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0
4231 /* enum: Last known valid HP sub-command. */
4232 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0
4233 /* The address to the array of sensor fields. (Or NULL to use a sub-command.)
4235 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
4236 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8
4237 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
4238 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
4239 /* The requested update interval, in seconds. (Or the sub-command if ADDR is
4242 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12
4244 /* MC_CMD_HP_OUT msgresponse */
4245 #define MC_CMD_HP_OUT_LEN 4
4246 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
4247 /* enum: OCSD stopped for this card. */
4248 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1
4249 /* enum: OCSD was successfully started with the address provided. */
4250 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2
4251 /* enum: OCSD was already started for this card. */
4252 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
4255 /***********************************/
4257 * Get stack information.
4259 #define MC_CMD_STACKINFO 0xf
4260 #undef MC_CMD_0xf_PRIVILEGE_CTG
4262 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4264 /* MC_CMD_STACKINFO_IN msgrequest */
4265 #define MC_CMD_STACKINFO_IN_LEN 0
4267 /* MC_CMD_STACKINFO_OUT msgresponse */
4268 #define MC_CMD_STACKINFO_OUT_LENMIN 12
4269 #define MC_CMD_STACKINFO_OUT_LENMAX 252
4270 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
4271 /* (thread ptr, stack size, free space) for each thread in system */
4272 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
4273 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
4274 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
4275 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
4278 /***********************************/
4280 * MDIO register read.
4282 #define MC_CMD_MDIO_READ 0x10
4283 #undef MC_CMD_0x10_PRIVILEGE_CTG
4285 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4287 /* MC_CMD_MDIO_READ_IN msgrequest */
4288 #define MC_CMD_MDIO_READ_IN_LEN 16
4289 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for
4292 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0
4293 /* enum: Internal. */
4294 #define MC_CMD_MDIO_BUS_INTERNAL 0x0
4295 /* enum: External. */
4296 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1
4298 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
4299 /* Device Address or clause 22. */
4300 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
4301 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
4302 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
4304 #define MC_CMD_MDIO_CLAUSE22 0x20
4306 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12
4308 /* MC_CMD_MDIO_READ_OUT msgresponse */
4309 #define MC_CMD_MDIO_READ_OUT_LEN 8
4311 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
4312 /* Status the MDIO commands return the raw status bits from the MDIO block. A
4313 * "good" transaction should have the DONE bit set and all other bits clear.
4315 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
4317 #define MC_CMD_MDIO_STATUS_GOOD 0x8
4320 /***********************************/
4321 /* MC_CMD_MDIO_WRITE
4322 * MDIO register write.
4324 #define MC_CMD_MDIO_WRITE 0x11
4325 #undef MC_CMD_0x11_PRIVILEGE_CTG
4327 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4329 /* MC_CMD_MDIO_WRITE_IN msgrequest */
4330 #define MC_CMD_MDIO_WRITE_IN_LEN 20
4331 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for
4334 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
4335 /* enum: Internal. */
4336 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
4337 /* enum: External. */
4338 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
4340 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
4341 /* Device Address or clause 22. */
4342 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
4343 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
4344 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
4346 /* MC_CMD_MDIO_CLAUSE22 0x20 */
4348 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
4350 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
4352 /* MC_CMD_MDIO_WRITE_OUT msgresponse */
4353 #define MC_CMD_MDIO_WRITE_OUT_LEN 4
4354 /* Status; the MDIO commands return the raw status bits from the MDIO block. A
4355 * "good" transaction should have the DONE bit set and all other bits clear.
4357 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
4359 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */
4362 /***********************************/
4364 * Write DBI register(s).
4366 #define MC_CMD_DBI_WRITE 0x12
4367 #undef MC_CMD_0x12_PRIVILEGE_CTG
4369 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4371 /* MC_CMD_DBI_WRITE_IN msgrequest */
4372 #define MC_CMD_DBI_WRITE_IN_LENMIN 12
4373 #define MC_CMD_DBI_WRITE_IN_LENMAX 252
4374 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
4375 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
4376 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.
4378 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
4379 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
4380 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
4381 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
4383 /* MC_CMD_DBI_WRITE_OUT msgresponse */
4384 #define MC_CMD_DBI_WRITE_OUT_LEN 0
4386 /* MC_CMD_DBIWROP_TYPEDEF structuredef */
4387 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12
4388 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
4389 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
4390 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
4391 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
4392 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16
4393 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16
4394 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15
4395 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
4396 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14
4397 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
4398 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32
4399 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32
4400 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
4401 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
4402 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32
4405 /***********************************/
4406 /* MC_CMD_PORT_READ32
4407 * Read a 32-bit register from the indirect port register map. The port to
4408 * access is implied by the Shared memory channel used.
4410 #define MC_CMD_PORT_READ32 0x14
4412 /* MC_CMD_PORT_READ32_IN msgrequest */
4413 #define MC_CMD_PORT_READ32_IN_LEN 4
4415 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
4417 /* MC_CMD_PORT_READ32_OUT msgresponse */
4418 #define MC_CMD_PORT_READ32_OUT_LEN 8
4420 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
4422 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
4425 /***********************************/
4426 /* MC_CMD_PORT_WRITE32
4427 * Write a 32-bit register to the indirect port register map. The port to
4428 * access is implied by the Shared memory channel used.
4430 #define MC_CMD_PORT_WRITE32 0x15
4432 /* MC_CMD_PORT_WRITE32_IN msgrequest */
4433 #define MC_CMD_PORT_WRITE32_IN_LEN 8
4435 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
4437 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
4439 /* MC_CMD_PORT_WRITE32_OUT msgresponse */
4440 #define MC_CMD_PORT_WRITE32_OUT_LEN 4
4442 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
4445 /***********************************/
4446 /* MC_CMD_PORT_READ128
4447 * Read a 128-bit register from the indirect port register map. The port to
4448 * access is implied by the Shared memory channel used.
4450 #define MC_CMD_PORT_READ128 0x16
4452 /* MC_CMD_PORT_READ128_IN msgrequest */
4453 #define MC_CMD_PORT_READ128_IN_LEN 4
4455 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
4457 /* MC_CMD_PORT_READ128_OUT msgresponse */
4458 #define MC_CMD_PORT_READ128_OUT_LEN 20
4460 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
4461 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
4463 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
4466 /***********************************/
4467 /* MC_CMD_PORT_WRITE128
4468 * Write a 128-bit register to the indirect port register map. The port to
4469 * access is implied by the Shared memory channel used.
4471 #define MC_CMD_PORT_WRITE128 0x17
4473 /* MC_CMD_PORT_WRITE128_IN msgrequest */
4474 #define MC_CMD_PORT_WRITE128_IN_LEN 20
4476 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
4478 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
4479 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16
4481 /* MC_CMD_PORT_WRITE128_OUT msgresponse */
4482 #define MC_CMD_PORT_WRITE128_OUT_LEN 4
4484 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
4486 /* MC_CMD_CAPABILITIES structuredef */
4487 #define MC_CMD_CAPABILITIES_LEN 4
4488 /* Small buf table. */
4489 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
4490 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1
4491 /* Turbo mode (for Maranello). */
4492 #define MC_CMD_CAPABILITIES_TURBO_LBN 1
4493 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1
4494 /* Turbo mode active (for Maranello). */
4495 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2
4496 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1
4498 #define MC_CMD_CAPABILITIES_PTP_LBN 3
4499 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1
4501 #define MC_CMD_CAPABILITIES_AOE_LBN 4
4502 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1
4503 /* AOE mode active. */
4504 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5
4505 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1
4506 /* AOE mode active. */
4507 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6
4508 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1
4509 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7
4510 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25
4513 /***********************************/
4514 /* MC_CMD_GET_BOARD_CFG
4515 * Returns the MC firmware configuration structure.
4517 #define MC_CMD_GET_BOARD_CFG 0x18
4518 #undef MC_CMD_0x18_PRIVILEGE_CTG
4520 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4522 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */
4523 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0
4525 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
4526 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
4527 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
4528 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
4529 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
4530 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
4531 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
4532 /* See MC_CMD_CAPABILITIES */
4533 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
4534 /* See MC_CMD_CAPABILITIES */
4535 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
4536 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
4537 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
4538 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
4539 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
4540 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
4541 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
4542 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
4543 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
4544 /* This field contains a 16-bit value for each of the types of NVRAM area. The
4545 * values are defined in the firmware/mc/platform/.c file for a specific board
4546 * type, but otherwise have no meaning to the MC; they are used by the driver
4547 * to manage selection of appropriate firmware updates.
4549 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
4550 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
4551 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
4552 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
4555 /***********************************/
4557 * Read DBI register(s) -- extended functionality
4559 #define MC_CMD_DBI_READX 0x19
4560 #undef MC_CMD_0x19_PRIVILEGE_CTG
4562 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4564 /* MC_CMD_DBI_READX_IN msgrequest */
4565 #define MC_CMD_DBI_READX_IN_LENMIN 8
4566 #define MC_CMD_DBI_READX_IN_LENMAX 248
4567 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
4568 /* Each Read op consists of an address (offset 0), VF/CS2) */
4569 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
4570 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
4571 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
4572 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
4573 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
4574 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
4576 /* MC_CMD_DBI_READX_OUT msgresponse */
4577 #define MC_CMD_DBI_READX_OUT_LENMIN 4
4578 #define MC_CMD_DBI_READX_OUT_LENMAX 252
4579 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
4581 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
4582 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
4583 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
4584 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
4586 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */
4587 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8
4588 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
4589 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
4590 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32
4591 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
4592 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16
4593 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16
4594 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15
4595 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
4596 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14
4597 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
4598 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32
4599 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32
4602 /***********************************/
4603 /* MC_CMD_SET_RAND_SEED
4604 * Set the 16byte seed for the MC pseudo-random generator.
4606 #define MC_CMD_SET_RAND_SEED 0x1a
4607 #undef MC_CMD_0x1a_PRIVILEGE_CTG
4609 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4611 /* MC_CMD_SET_RAND_SEED_IN msgrequest */
4612 #define MC_CMD_SET_RAND_SEED_IN_LEN 16
4614 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
4615 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16
4617 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */
4618 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0
4621 /***********************************/
4622 /* MC_CMD_LTSSM_HIST
4623 * Retrieve the history of the LTSSM, if the build supports it.
4625 #define MC_CMD_LTSSM_HIST 0x1b
4627 /* MC_CMD_LTSSM_HIST_IN msgrequest */
4628 #define MC_CMD_LTSSM_HIST_IN_LEN 0
4630 /* MC_CMD_LTSSM_HIST_OUT msgresponse */
4631 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
4632 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252
4633 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
4634 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */
4635 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
4636 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
4637 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
4638 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
4641 /***********************************/
4642 /* MC_CMD_DRV_ATTACH
4643 * Inform MCPU that this port is managed on the host (i.e. driver active). For
4644 * Huntington, also request the preferred datapath firmware to use if possible
4645 * (it may not be possible for this request to be fulfilled; the driver must
4646 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which
4647 * features are actually available). The FIRMWARE_ID field is ignored by older
4650 #define MC_CMD_DRV_ATTACH 0x1c
4651 #undef MC_CMD_0x1c_PRIVILEGE_CTG
4653 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4655 /* MC_CMD_DRV_ATTACH_IN msgrequest */
4656 #define MC_CMD_DRV_ATTACH_IN_LEN 12
4657 /* new state to set if UPDATE=1 */
4658 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
4659 #define MC_CMD_DRV_ATTACH_LBN 0
4660 #define MC_CMD_DRV_ATTACH_WIDTH 1
4661 #define MC_CMD_DRV_PREBOOT_LBN 1
4662 #define MC_CMD_DRV_PREBOOT_WIDTH 1
4663 /* 1 to set new state, or 0 to just report the existing state */
4664 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
4665 /* preferred datapath firmware (for Huntington; ignored for Siena) */
4666 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8
4667 /* enum: Prefer to use full featured firmware */
4668 #define MC_CMD_FW_FULL_FEATURED 0x0
4669 /* enum: Prefer to use firmware with fewer features but lower latency */
4670 #define MC_CMD_FW_LOW_LATENCY 0x1
4671 /* enum: Prefer to use firmware for SolarCapture packed stream mode */
4672 #define MC_CMD_FW_PACKED_STREAM 0x2
4673 /* enum: Prefer to use firmware with fewer features and simpler TX event
4674 * batching but higher TX packet rate
4676 #define MC_CMD_FW_HIGH_TX_RATE 0x3
4677 /* enum: Reserved value */
4678 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
4679 /* enum: Only this option is allowed for non-admin functions */
4680 #define MC_CMD_FW_DONT_CARE 0xffffffff
4682 /* MC_CMD_DRV_ATTACH_OUT msgresponse */
4683 #define MC_CMD_DRV_ATTACH_OUT_LEN 4
4684 /* previous or existing state, see the bitmask at NEW_STATE */
4685 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
4687 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */
4688 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8
4689 /* previous or existing state, see the bitmask at NEW_STATE */
4690 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
4691 /* Flags associated with this function */
4692 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
4693 /* enum: Labels the lowest-numbered function visible to the OS */
4694 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
4695 /* enum: The function can control the link state of the physical port it is
4698 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
4699 /* enum: The function can perform privileged operations */
4700 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
4701 /* enum: The function does not have an active port associated with it. The port
4702 * refers to the Sorrento external FPGA port.
4704 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
4707 /***********************************/
4709 * Route UART output to circular buffer in shared memory instead.
4711 #define MC_CMD_SHMUART 0x1f
4713 /* MC_CMD_SHMUART_IN msgrequest */
4714 #define MC_CMD_SHMUART_IN_LEN 4
4716 #define MC_CMD_SHMUART_IN_FLAG_OFST 0
4718 /* MC_CMD_SHMUART_OUT msgresponse */
4719 #define MC_CMD_SHMUART_OUT_LEN 0
4722 /***********************************/
4723 /* MC_CMD_PORT_RESET
4724 * Generic per-port reset. There is no equivalent for per-board reset. Locks
4725 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
4726 * use MC_CMD_ENTITY_RESET instead.
4728 #define MC_CMD_PORT_RESET 0x20
4729 #undef MC_CMD_0x20_PRIVILEGE_CTG
4731 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4733 /* MC_CMD_PORT_RESET_IN msgrequest */
4734 #define MC_CMD_PORT_RESET_IN_LEN 0
4736 /* MC_CMD_PORT_RESET_OUT msgresponse */
4737 #define MC_CMD_PORT_RESET_OUT_LEN 0
4740 /***********************************/
4741 /* MC_CMD_ENTITY_RESET
4742 * Generic per-resource reset. There is no equivalent for per-board reset.
4743 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
4744 * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
4746 #define MC_CMD_ENTITY_RESET 0x20
4747 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
4749 /* MC_CMD_ENTITY_RESET_IN msgrequest */
4750 #define MC_CMD_ENTITY_RESET_IN_LEN 4
4751 /* Optional flags field. Omitting this will perform a "legacy" reset action
4754 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
4755 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
4756 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
4758 /* MC_CMD_ENTITY_RESET_OUT msgresponse */
4759 #define MC_CMD_ENTITY_RESET_OUT_LEN 0
4762 /***********************************/
4763 /* MC_CMD_PCIE_CREDITS
4764 * Read instantaneous and minimum flow control thresholds.
4766 #define MC_CMD_PCIE_CREDITS 0x21
4768 /* MC_CMD_PCIE_CREDITS_IN msgrequest */
4769 #define MC_CMD_PCIE_CREDITS_IN_LEN 8
4770 /* poll period. 0 is disabled */
4771 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
4772 /* wipe statistics */
4773 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
4775 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */
4776 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16
4777 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
4778 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
4779 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
4780 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
4781 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
4782 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
4783 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
4784 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
4785 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
4786 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
4787 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
4788 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
4789 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
4790 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
4791 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
4792 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2
4795 /***********************************/
4796 /* MC_CMD_RXD_MONITOR
4797 * Get histogram of RX queue fill level.
4799 #define MC_CMD_RXD_MONITOR 0x22
4801 /* MC_CMD_RXD_MONITOR_IN msgrequest */
4802 #define MC_CMD_RXD_MONITOR_IN_LEN 12
4803 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
4804 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
4805 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
4807 /* MC_CMD_RXD_MONITOR_OUT msgresponse */
4808 #define MC_CMD_RXD_MONITOR_OUT_LEN 80
4809 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
4810 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
4811 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
4812 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
4813 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
4814 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
4815 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
4816 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
4817 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
4818 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
4819 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
4820 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
4821 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
4822 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
4823 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
4824 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
4825 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
4826 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
4827 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
4828 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
4831 /***********************************/
4833 * Copy the given ASCII string out onto UART and/or out of the network port.
4835 #define MC_CMD_PUTS 0x23
4836 #undef MC_CMD_0x23_PRIVILEGE_CTG
4838 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4840 /* MC_CMD_PUTS_IN msgrequest */
4841 #define MC_CMD_PUTS_IN_LENMIN 13
4842 #define MC_CMD_PUTS_IN_LENMAX 252
4843 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
4844 #define MC_CMD_PUTS_IN_DEST_OFST 0
4845 #define MC_CMD_PUTS_IN_UART_LBN 0
4846 #define MC_CMD_PUTS_IN_UART_WIDTH 1
4847 #define MC_CMD_PUTS_IN_PORT_LBN 1
4848 #define MC_CMD_PUTS_IN_PORT_WIDTH 1
4849 #define MC_CMD_PUTS_IN_DHOST_OFST 4
4850 #define MC_CMD_PUTS_IN_DHOST_LEN 6
4851 #define MC_CMD_PUTS_IN_STRING_OFST 12
4852 #define MC_CMD_PUTS_IN_STRING_LEN 1
4853 #define MC_CMD_PUTS_IN_STRING_MINNUM 1
4854 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240
4856 /* MC_CMD_PUTS_OUT msgresponse */
4857 #define MC_CMD_PUTS_OUT_LEN 0
4860 /***********************************/
4861 /* MC_CMD_GET_PHY_CFG
4862 * Report PHY configuration. This guarantees to succeed even if the PHY is in a
4863 * 'zombie' state. Locks required: None
4865 #define MC_CMD_GET_PHY_CFG 0x24
4866 #undef MC_CMD_0x24_PRIVILEGE_CTG
4868 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4870 /* MC_CMD_GET_PHY_CFG_IN msgrequest */
4871 #define MC_CMD_GET_PHY_CFG_IN_LEN 0
4873 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */
4874 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72
4876 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
4877 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
4878 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
4879 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
4880 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
4881 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
4882 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
4883 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
4884 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
4885 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
4886 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
4887 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
4888 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
4889 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
4890 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
4892 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
4893 /* Bitmask of supported capabilities */
4894 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
4895 #define MC_CMD_PHY_CAP_10HDX_LBN 1
4896 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1
4897 #define MC_CMD_PHY_CAP_10FDX_LBN 2
4898 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1
4899 #define MC_CMD_PHY_CAP_100HDX_LBN 3
4900 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1
4901 #define MC_CMD_PHY_CAP_100FDX_LBN 4
4902 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1
4903 #define MC_CMD_PHY_CAP_1000HDX_LBN 5
4904 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
4905 #define MC_CMD_PHY_CAP_1000FDX_LBN 6
4906 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
4907 #define MC_CMD_PHY_CAP_10000FDX_LBN 7
4908 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
4909 #define MC_CMD_PHY_CAP_PAUSE_LBN 8
4910 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
4911 #define MC_CMD_PHY_CAP_ASYM_LBN 9
4912 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1
4913 #define MC_CMD_PHY_CAP_AN_LBN 10
4914 #define MC_CMD_PHY_CAP_AN_WIDTH 1
4915 #define MC_CMD_PHY_CAP_40000FDX_LBN 11
4916 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1
4917 #define MC_CMD_PHY_CAP_DDM_LBN 12
4918 #define MC_CMD_PHY_CAP_DDM_WIDTH 1
4920 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
4922 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
4924 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
4926 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
4927 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
4929 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
4931 #define MC_CMD_MEDIA_XAUI 0x1
4933 #define MC_CMD_MEDIA_CX4 0x2
4935 #define MC_CMD_MEDIA_KX4 0x3
4936 /* enum: XFP Far. */
4937 #define MC_CMD_MEDIA_XFP 0x4
4939 #define MC_CMD_MEDIA_SFP_PLUS 0x5
4940 /* enum: 10GBaseT. */
4941 #define MC_CMD_MEDIA_BASE_T 0x6
4943 #define MC_CMD_MEDIA_QSFP_PLUS 0x7
4944 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
4945 /* enum: Native clause 22 */
4946 #define MC_CMD_MMD_CLAUSE22 0x0
4947 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
4948 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
4949 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
4950 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
4951 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
4952 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
4953 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
4954 /* enum: Clause22 proxied over clause45 by PHY. */
4955 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
4956 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
4957 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
4958 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
4959 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
4962 /***********************************/
4963 /* MC_CMD_START_BIST
4964 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST
4965 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
4967 #define MC_CMD_START_BIST 0x25
4968 #undef MC_CMD_0x25_PRIVILEGE_CTG
4970 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4972 /* MC_CMD_START_BIST_IN msgrequest */
4973 #define MC_CMD_START_BIST_IN_LEN 4
4975 #define MC_CMD_START_BIST_IN_TYPE_OFST 0
4976 /* enum: Run the PHY's short cable BIST. */
4977 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
4978 /* enum: Run the PHY's long cable BIST. */
4979 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2
4980 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */
4981 #define MC_CMD_BPX_SERDES_BIST 0x3
4982 /* enum: Run the MC loopback tests. */
4983 #define MC_CMD_MC_LOOPBACK_BIST 0x4
4984 /* enum: Run the PHY's standard BIST. */
4985 #define MC_CMD_PHY_BIST 0x5
4986 /* enum: Run MC RAM test. */
4987 #define MC_CMD_MC_MEM_BIST 0x6
4988 /* enum: Run Port RAM test. */
4989 #define MC_CMD_PORT_MEM_BIST 0x7
4990 /* enum: Run register test. */
4991 #define MC_CMD_REG_BIST 0x8
4993 /* MC_CMD_START_BIST_OUT msgresponse */
4994 #define MC_CMD_START_BIST_OUT_LEN 0
4997 /***********************************/
4999 * Poll for BIST completion. Returns a single status code, and optionally some
5000 * PHY specific bist output. The driver should only consume the BIST output
5001 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't
5002 * successfully parse the BIST output, it should still respect the pass/Fail in
5003 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
5004 * EACCES (if PHY_LOCK is not held).
5006 #define MC_CMD_POLL_BIST 0x26
5007 #undef MC_CMD_0x26_PRIVILEGE_CTG
5009 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5011 /* MC_CMD_POLL_BIST_IN msgrequest */
5012 #define MC_CMD_POLL_BIST_IN_LEN 0
5014 /* MC_CMD_POLL_BIST_OUT msgresponse */
5015 #define MC_CMD_POLL_BIST_OUT_LEN 8
5017 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
5018 /* enum: Running. */
5019 #define MC_CMD_POLL_BIST_RUNNING 0x1
5021 #define MC_CMD_POLL_BIST_PASSED 0x2
5023 #define MC_CMD_POLL_BIST_FAILED 0x3
5024 /* enum: Timed-out. */
5025 #define MC_CMD_POLL_BIST_TIMEOUT 0x4
5026 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
5028 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
5029 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
5031 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5032 /* Enum values, see field(s): */
5033 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
5034 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
5035 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
5036 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
5037 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
5038 /* Status of each channel A */
5039 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
5041 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
5043 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
5044 /* enum: Intra-pair short. */
5045 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
5046 /* enum: Inter-pair short. */
5047 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
5049 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
5050 /* Status of each channel B */
5051 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
5052 /* Enum values, see field(s): */
5053 /* CABLE_STATUS_A */
5054 /* Status of each channel C */
5055 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
5056 /* Enum values, see field(s): */
5057 /* CABLE_STATUS_A */
5058 /* Status of each channel D */
5059 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
5060 /* Enum values, see field(s): */
5061 /* CABLE_STATUS_A */
5063 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
5064 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
5066 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5067 /* Enum values, see field(s): */
5068 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
5069 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
5070 /* enum: Complete. */
5071 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
5072 /* enum: Bus switch off I2C write. */
5073 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
5074 /* enum: Bus switch off I2C no access IO exp. */
5075 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
5076 /* enum: Bus switch off I2C no access module. */
5077 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
5078 /* enum: IO exp I2C configure. */
5079 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
5080 /* enum: Bus switch I2C no cross talk. */
5081 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
5082 /* enum: Module presence. */
5083 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
5084 /* enum: Module ID I2C access. */
5085 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
5086 /* enum: Module ID sane value. */
5087 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
5089 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */
5090 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36
5092 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5093 /* Enum values, see field(s): */
5094 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
5095 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
5096 /* enum: Test has completed. */
5097 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
5098 /* enum: RAM test - walk ones. */
5099 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
5100 /* enum: RAM test - walk zeros. */
5101 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
5102 /* enum: RAM test - walking inversions zeros/ones. */
5103 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
5104 /* enum: RAM test - walking inversions checkerboard. */
5105 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
5106 /* enum: Register test - set / clear individual bits. */
5107 #define MC_CMD_POLL_BIST_MEM_REG 0x5
5108 /* enum: ECC error detected. */
5109 #define MC_CMD_POLL_BIST_MEM_ECC 0x6
5110 /* Failure address, only valid if result is POLL_BIST_FAILED */
5111 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8
5112 /* Bus or address space to which the failure address corresponds */
5113 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12
5114 /* enum: MC MIPS bus. */
5115 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
5116 /* enum: CSR IREG bus. */
5117 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
5118 /* enum: RX0 DPCPU bus. */
5119 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
5120 /* enum: TX0 DPCPU bus. */
5121 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
5122 /* enum: TX1 DPCPU bus. */
5123 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
5124 /* enum: RX0 DICPU bus. */
5125 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
5126 /* enum: TX DICPU bus. */
5127 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
5128 /* enum: RX1 DPCPU bus. */
5129 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
5130 /* enum: RX1 DICPU bus. */
5131 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
5132 /* Pattern written to RAM / register */
5133 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16
5134 /* Actual value read from RAM / register */
5135 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20
5136 /* ECC error mask */
5137 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24
5138 /* ECC parity error mask */
5139 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28
5140 /* ECC fatal error mask */
5141 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32
5144 /***********************************/
5145 /* MC_CMD_FLUSH_RX_QUEUES
5146 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ
5147 * flushes should be initiated via this MCDI operation, rather than via
5148 * directly writing FLUSH_CMD.
5150 * The flush is completed (either done/fail) asynchronously (after this command
5151 * returns). The driver must still wait for flush done/failure events as usual.
5153 #define MC_CMD_FLUSH_RX_QUEUES 0x27
5155 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
5156 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
5157 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
5158 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
5159 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
5160 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
5161 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
5162 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
5164 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
5165 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
5168 /***********************************/
5169 /* MC_CMD_GET_LOOPBACK_MODES
5170 * Returns a bitmask of loopback modes available at each speed.
5172 #define MC_CMD_GET_LOOPBACK_MODES 0x28
5173 #undef MC_CMD_0x28_PRIVILEGE_CTG
5175 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5177 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
5178 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
5180 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
5181 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40
5182 /* Supported loopbacks. */
5183 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
5184 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
5185 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
5186 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
5188 #define MC_CMD_LOOPBACK_NONE 0x0
5190 #define MC_CMD_LOOPBACK_DATA 0x1
5192 #define MC_CMD_LOOPBACK_GMAC 0x2
5194 #define MC_CMD_LOOPBACK_XGMII 0x3
5196 #define MC_CMD_LOOPBACK_XGXS 0x4
5198 #define MC_CMD_LOOPBACK_XAUI 0x5
5200 #define MC_CMD_LOOPBACK_GMII 0x6
5202 #define MC_CMD_LOOPBACK_SGMII 0x7
5204 #define MC_CMD_LOOPBACK_XGBR 0x8
5206 #define MC_CMD_LOOPBACK_XFI 0x9
5207 /* enum: XAUI Far. */
5208 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa
5209 /* enum: GMII Far. */
5210 #define MC_CMD_LOOPBACK_GMII_FAR 0xb
5211 /* enum: SGMII Far. */
5212 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc
5213 /* enum: XFI Far. */
5214 #define MC_CMD_LOOPBACK_XFI_FAR 0xd
5216 #define MC_CMD_LOOPBACK_GPHY 0xe
5218 #define MC_CMD_LOOPBACK_PHYXS 0xf
5220 #define MC_CMD_LOOPBACK_PCS 0x10
5221 /* enum: PMA-PMD. */
5222 #define MC_CMD_LOOPBACK_PMAPMD 0x11
5223 /* enum: Cross-Port. */
5224 #define MC_CMD_LOOPBACK_XPORT 0x12
5225 /* enum: XGMII-Wireside. */
5226 #define MC_CMD_LOOPBACK_XGMII_WS 0x13
5227 /* enum: XAUI Wireside. */
5228 #define MC_CMD_LOOPBACK_XAUI_WS 0x14
5229 /* enum: XAUI Wireside Far. */
5230 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
5231 /* enum: XAUI Wireside near. */
5232 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
5233 /* enum: GMII Wireside. */
5234 #define MC_CMD_LOOPBACK_GMII_WS 0x17
5235 /* enum: XFI Wireside. */
5236 #define MC_CMD_LOOPBACK_XFI_WS 0x18
5237 /* enum: XFI Wireside Far. */
5238 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
5239 /* enum: PhyXS Wireside. */
5240 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
5241 /* enum: PMA lanes MAC-Serdes. */
5242 #define MC_CMD_LOOPBACK_PMA_INT 0x1b
5243 /* enum: KR Serdes Parallel (Encoder). */
5244 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c
5245 /* enum: KR Serdes Serial. */
5246 #define MC_CMD_LOOPBACK_SD_FAR 0x1d
5247 /* enum: PMA lanes MAC-Serdes Wireside. */
5248 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
5249 /* enum: KR Serdes Parallel Wireside (Full PCS). */
5250 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
5251 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
5252 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
5253 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
5254 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
5255 /* enum: KR Serdes Serial Wireside. */
5256 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22
5257 /* enum: Near side of AOE Siena side port */
5258 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
5259 /* enum: Medford Wireside datapath loopback */
5260 #define MC_CMD_LOOPBACK_DATA_WS 0x24
5261 /* enum: Force link up without setting up any physical loopback (snapper use
5264 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
5265 /* Supported loopbacks. */
5266 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
5267 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
5268 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
5269 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
5270 /* Enum values, see field(s): */
5272 /* Supported loopbacks. */
5273 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
5274 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
5275 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
5276 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
5277 /* Enum values, see field(s): */
5279 /* Supported loopbacks. */
5280 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
5281 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
5282 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
5283 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
5284 /* Enum values, see field(s): */
5286 /* Supported loopbacks. */
5287 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
5288 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
5289 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
5290 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
5291 /* Enum values, see field(s): */
5295 /***********************************/
5297 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
5300 #define MC_CMD_GET_LINK 0x29
5301 #undef MC_CMD_0x29_PRIVILEGE_CTG
5303 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5305 /* MC_CMD_GET_LINK_IN msgrequest */
5306 #define MC_CMD_GET_LINK_IN_LEN 0
5308 /* MC_CMD_GET_LINK_OUT msgresponse */
5309 #define MC_CMD_GET_LINK_OUT_LEN 28
5310 /* near-side advertised capabilities */
5311 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0
5312 /* link-partner advertised capabilities */
5313 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
5314 /* Autonegotiated speed in mbit/s. The link may still be down even if this
5317 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
5318 /* Current loopback setting. */
5319 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
5320 /* Enum values, see field(s): */
5321 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
5322 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
5323 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
5324 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
5325 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
5326 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
5327 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
5328 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
5329 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
5330 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
5331 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
5332 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
5333 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
5334 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
5335 /* This returns the negotiated flow control value. */
5336 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
5337 /* Enum values, see field(s): */
5338 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
5339 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
5340 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
5341 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
5342 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
5343 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
5344 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
5345 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
5346 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
5347 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
5350 /***********************************/
5352 * Write the unified MAC/PHY link configuration. Locks required: None. Return
5353 * code: 0, EINVAL, ETIME
5355 #define MC_CMD_SET_LINK 0x2a
5356 #undef MC_CMD_0x2a_PRIVILEGE_CTG
5358 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
5360 /* MC_CMD_SET_LINK_IN msgrequest */
5361 #define MC_CMD_SET_LINK_IN_LEN 16
5363 #define MC_CMD_SET_LINK_IN_CAP_OFST 0
5365 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
5366 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
5367 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
5368 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
5369 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
5370 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2
5371 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
5372 /* Loopback mode. */
5373 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
5374 /* Enum values, see field(s): */
5375 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
5376 /* A loopback speed of "0" is supported, and means (choose any available
5379 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
5381 /* MC_CMD_SET_LINK_OUT msgresponse */
5382 #define MC_CMD_SET_LINK_OUT_LEN 0
5385 /***********************************/
5386 /* MC_CMD_SET_ID_LED
5387 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
5389 #define MC_CMD_SET_ID_LED 0x2b
5390 #undef MC_CMD_0x2b_PRIVILEGE_CTG
5392 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
5394 /* MC_CMD_SET_ID_LED_IN msgrequest */
5395 #define MC_CMD_SET_ID_LED_IN_LEN 4
5396 /* Set LED state. */
5397 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
5398 #define MC_CMD_LED_OFF 0x0 /* enum */
5399 #define MC_CMD_LED_ON 0x1 /* enum */
5400 #define MC_CMD_LED_DEFAULT 0x2 /* enum */
5402 /* MC_CMD_SET_ID_LED_OUT msgresponse */
5403 #define MC_CMD_SET_ID_LED_OUT_LEN 0
5406 /***********************************/
5408 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
5410 #define MC_CMD_SET_MAC 0x2c
5411 #undef MC_CMD_0x2c_PRIVILEGE_CTG
5413 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5415 /* MC_CMD_SET_MAC_IN msgrequest */
5416 #define MC_CMD_SET_MAC_IN_LEN 28
5417 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
5418 * EtherII, VLAN, bug16011 padding).
5420 #define MC_CMD_SET_MAC_IN_MTU_OFST 0
5421 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
5422 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8
5423 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8
5424 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
5425 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
5426 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16
5427 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
5428 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
5429 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
5430 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
5431 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20
5432 /* enum: Flow control is off. */
5433 #define MC_CMD_FCNTL_OFF 0x0
5434 /* enum: Respond to flow control. */
5435 #define MC_CMD_FCNTL_RESPOND 0x1
5436 /* enum: Respond to and Issue flow control. */
5437 #define MC_CMD_FCNTL_BIDIR 0x2
5438 /* enum: Auto neg flow control. */
5439 #define MC_CMD_FCNTL_AUTO 0x3
5440 /* enum: Priority flow control (eftest builds only). */
5441 #define MC_CMD_FCNTL_QBB 0x4
5442 /* enum: Issue flow control. */
5443 #define MC_CMD_FCNTL_GENERATE 0x5
5444 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24
5445 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
5446 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1
5448 /* MC_CMD_SET_MAC_EXT_IN msgrequest */
5449 #define MC_CMD_SET_MAC_EXT_IN_LEN 32
5450 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
5451 * EtherII, VLAN, bug16011 padding).
5453 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
5454 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
5455 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
5456 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
5457 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
5458 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
5459 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
5460 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
5461 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
5462 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
5463 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
5464 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20
5465 /* enum: Flow control is off. */
5466 /* MC_CMD_FCNTL_OFF 0x0 */
5467 /* enum: Respond to flow control. */
5468 /* MC_CMD_FCNTL_RESPOND 0x1 */
5469 /* enum: Respond to and Issue flow control. */
5470 /* MC_CMD_FCNTL_BIDIR 0x2 */
5471 /* enum: Auto neg flow control. */
5472 /* MC_CMD_FCNTL_AUTO 0x3 */
5473 /* enum: Priority flow control (eftest builds only). */
5474 /* MC_CMD_FCNTL_QBB 0x4 */
5475 /* enum: Issue flow control. */
5476 /* MC_CMD_FCNTL_GENERATE 0x5 */
5477 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24
5478 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
5479 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
5480 /* Select which parameters to configure. A parameter will only be modified if
5481 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
5482 * capabilities then this field is ignored (and all flags are assumed to be
5485 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28
5486 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
5487 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
5488 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
5489 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
5490 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2
5491 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
5492 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3
5493 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
5494 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
5495 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
5497 /* MC_CMD_SET_MAC_OUT msgresponse */
5498 #define MC_CMD_SET_MAC_OUT_LEN 0
5500 /* MC_CMD_SET_MAC_V2_OUT msgresponse */
5501 #define MC_CMD_SET_MAC_V2_OUT_LEN 4
5502 /* MTU as configured after processing the request. See comment at
5503 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL
5506 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
5509 /***********************************/
5511 * Get generic PHY statistics. This call returns the statistics for a generic
5512 * PHY in a sparse array (indexed by the enumerate). Each value is represented
5513 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
5514 * statistics may be read from the message response. If DMA_ADDR != 0, then the
5515 * statistics are dmad to that (page-aligned location). Locks required: None.
5518 #define MC_CMD_PHY_STATS 0x2d
5519 #undef MC_CMD_0x2d_PRIVILEGE_CTG
5521 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
5523 /* MC_CMD_PHY_STATS_IN msgrequest */
5524 #define MC_CMD_PHY_STATS_IN_LEN 8
5526 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
5527 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
5528 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
5529 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
5531 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
5532 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
5534 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
5535 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
5536 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
5537 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
5538 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
5540 #define MC_CMD_OUI 0x0
5541 /* enum: PMA-PMD Link Up. */
5542 #define MC_CMD_PMA_PMD_LINK_UP 0x1
5543 /* enum: PMA-PMD RX Fault. */
5544 #define MC_CMD_PMA_PMD_RX_FAULT 0x2
5545 /* enum: PMA-PMD TX Fault. */
5546 #define MC_CMD_PMA_PMD_TX_FAULT 0x3
5547 /* enum: PMA-PMD Signal */
5548 #define MC_CMD_PMA_PMD_SIGNAL 0x4
5549 /* enum: PMA-PMD SNR A. */
5550 #define MC_CMD_PMA_PMD_SNR_A 0x5
5551 /* enum: PMA-PMD SNR B. */
5552 #define MC_CMD_PMA_PMD_SNR_B 0x6
5553 /* enum: PMA-PMD SNR C. */
5554 #define MC_CMD_PMA_PMD_SNR_C 0x7
5555 /* enum: PMA-PMD SNR D. */
5556 #define MC_CMD_PMA_PMD_SNR_D 0x8
5557 /* enum: PCS Link Up. */
5558 #define MC_CMD_PCS_LINK_UP 0x9
5559 /* enum: PCS RX Fault. */
5560 #define MC_CMD_PCS_RX_FAULT 0xa
5561 /* enum: PCS TX Fault. */
5562 #define MC_CMD_PCS_TX_FAULT 0xb
5563 /* enum: PCS BER. */
5564 #define MC_CMD_PCS_BER 0xc
5565 /* enum: PCS Block Errors. */
5566 #define MC_CMD_PCS_BLOCK_ERRORS 0xd
5567 /* enum: PhyXS Link Up. */
5568 #define MC_CMD_PHYXS_LINK_UP 0xe
5569 /* enum: PhyXS RX Fault. */
5570 #define MC_CMD_PHYXS_RX_FAULT 0xf
5571 /* enum: PhyXS TX Fault. */
5572 #define MC_CMD_PHYXS_TX_FAULT 0x10
5573 /* enum: PhyXS Align. */
5574 #define MC_CMD_PHYXS_ALIGN 0x11
5575 /* enum: PhyXS Sync. */
5576 #define MC_CMD_PHYXS_SYNC 0x12
5577 /* enum: AN link-up. */
5578 #define MC_CMD_AN_LINK_UP 0x13
5579 /* enum: AN Complete. */
5580 #define MC_CMD_AN_COMPLETE 0x14
5581 /* enum: AN 10GBaseT Status. */
5582 #define MC_CMD_AN_10GBT_STATUS 0x15
5583 /* enum: Clause 22 Link-Up. */
5584 #define MC_CMD_CL22_LINK_UP 0x16
5585 /* enum: (Last entry) */
5586 #define MC_CMD_PHY_NSTATS 0x17
5589 /***********************************/
5591 * Get generic MAC statistics. This call returns unified statistics maintained
5592 * by the MC as it switches between the GMAC and XMAC. The MC will write out
5593 * all supported stats. The driver should zero initialise the buffer to
5594 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
5595 * performed, and the statistics may be read from the message response. If
5596 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
5597 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no
5598 * effect. Returns: 0, ETIME
5600 #define MC_CMD_MAC_STATS 0x2e
5601 #undef MC_CMD_0x2e_PRIVILEGE_CTG
5603 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5605 /* MC_CMD_MAC_STATS_IN msgrequest */
5606 #define MC_CMD_MAC_STATS_IN_LEN 20
5608 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
5609 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
5610 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
5611 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
5612 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8
5613 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0
5614 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
5615 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
5616 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
5617 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
5618 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
5619 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
5620 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
5621 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
5622 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
5623 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
5624 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
5625 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
5626 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
5627 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
5628 /* port id so vadapter stats can be provided */
5629 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16
5631 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
5632 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
5634 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
5635 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
5636 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
5637 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
5638 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
5639 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
5640 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
5641 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
5642 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
5643 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
5644 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
5645 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
5646 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
5647 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
5648 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
5649 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
5650 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
5651 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
5652 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
5653 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
5654 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
5655 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
5656 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
5657 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
5658 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
5659 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
5660 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
5661 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
5662 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
5663 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
5664 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
5665 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
5666 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
5667 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
5668 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
5669 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
5670 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
5671 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
5672 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
5673 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
5674 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
5675 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
5676 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
5677 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
5678 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
5679 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
5680 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
5681 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
5682 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
5683 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
5684 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
5685 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
5686 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
5687 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
5688 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
5689 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
5690 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
5691 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
5692 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
5693 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
5694 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
5695 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
5696 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
5697 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
5698 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
5699 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
5700 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
5701 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
5702 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
5705 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
5706 /* enum: PM discard_bb_overflow counter. Valid for EF10 with
5707 * PM_AND_RXDP_COUNTERS capability only.
5709 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
5710 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
5713 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
5714 /* enum: PM discard_vfifo_full counter. Valid for EF10 with
5715 * PM_AND_RXDP_COUNTERS capability only.
5717 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
5718 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
5721 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40
5722 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
5725 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41
5726 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
5729 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
5730 /* enum: RXDP counter: Number of packets dropped due to the queue being
5731 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
5733 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
5734 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
5735 * with PM_AND_RXDP_COUNTERS capability only.
5737 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
5738 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
5739 * PM_AND_RXDP_COUNTERS capability only.
5741 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
5742 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.
5743 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
5745 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
5746 /* enum: RXDP counter: Number of times the DPCPU waited for an existing
5747 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
5749 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
5750 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
5751 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
5752 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
5753 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
5754 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
5755 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
5756 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
5757 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
5758 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
5759 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
5760 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
5761 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
5762 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
5763 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
5764 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
5765 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
5766 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
5767 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
5768 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
5769 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
5770 /* enum: Start of GMAC stats buffer space, for Siena only. */
5771 #define MC_CMD_GMAC_DMABUF_START 0x40
5772 /* enum: End of GMAC stats buffer space, for Siena only. */
5773 #define MC_CMD_GMAC_DMABUF_END 0x5f
5774 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */
5775 #define MC_CMD_MAC_NSTATS 0x61 /* enum */
5778 /***********************************/
5782 #define MC_CMD_SRIOV 0x30
5784 /* MC_CMD_SRIOV_IN msgrequest */
5785 #define MC_CMD_SRIOV_IN_LEN 12
5786 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0
5787 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
5788 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
5790 /* MC_CMD_SRIOV_OUT msgresponse */
5791 #define MC_CMD_SRIOV_OUT_LEN 8
5792 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
5793 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
5795 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
5796 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
5797 /* this is only used for the first record */
5798 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
5799 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
5800 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
5801 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
5802 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
5803 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
5804 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
5805 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
5806 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
5807 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
5808 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
5809 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
5810 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
5811 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
5812 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
5813 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
5814 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
5815 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
5816 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
5817 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
5818 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
5819 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
5820 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
5821 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
5822 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32
5825 /***********************************/
5827 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data
5828 * embedded directly in the command.
5830 * A common pattern is for a client to use generation counts to signal a dma
5831 * update of a datastructure. To facilitate this, this MCDI operation can
5832 * contain multiple requests which are executed in strict order. Requests take
5833 * the form of duplicating the entire MCDI request continuously (including the
5834 * requests record, which is ignored in all but the first structure)
5836 * The source data can either come from a DMA from the host, or it can be
5837 * embedded within the request directly, thereby eliminating a DMA read. To
5838 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
5839 * ADDR_LO=offset, and inserts the data at %offset from the start of the
5840 * payload. It's the callers responsibility to ensure that the embedded data
5841 * doesn't overlap the records.
5843 * Returns: 0, EINVAL (invalid RID)
5845 #define MC_CMD_MEMCPY 0x31
5847 /* MC_CMD_MEMCPY_IN msgrequest */
5848 #define MC_CMD_MEMCPY_IN_LENMIN 32
5849 #define MC_CMD_MEMCPY_IN_LENMAX 224
5850 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
5851 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */
5852 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0
5853 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32
5854 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
5855 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
5857 /* MC_CMD_MEMCPY_OUT msgresponse */
5858 #define MC_CMD_MEMCPY_OUT_LEN 0
5861 /***********************************/
5862 /* MC_CMD_WOL_FILTER_SET
5865 #define MC_CMD_WOL_FILTER_SET 0x32
5866 #undef MC_CMD_0x32_PRIVILEGE_CTG
5868 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
5870 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */
5871 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192
5872 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
5873 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
5874 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
5875 /* A type value of 1 is unused. */
5876 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
5878 #define MC_CMD_WOL_TYPE_MAGIC 0x0
5879 /* enum: MS Windows Magic */
5880 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
5881 /* enum: IPv4 Syn */
5882 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
5883 /* enum: IPv6 Syn */
5884 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
5886 #define MC_CMD_WOL_TYPE_BITMAP 0x5
5888 #define MC_CMD_WOL_TYPE_LINK 0x6
5889 /* enum: (Above this for future use) */
5890 #define MC_CMD_WOL_TYPE_MAX 0x7
5891 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
5892 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
5893 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
5895 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
5896 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
5897 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5898 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5899 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
5900 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
5901 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
5902 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
5904 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
5905 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
5906 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5907 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5908 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
5909 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
5910 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
5911 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
5912 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
5913 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
5915 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
5916 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
5917 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5918 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5919 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
5920 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
5921 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
5922 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
5923 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
5924 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
5925 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
5926 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
5928 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
5929 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
5930 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5931 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5932 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
5933 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
5934 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
5935 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
5936 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
5937 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
5938 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
5939 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
5940 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
5941 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
5943 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
5944 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
5945 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5946 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5947 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
5948 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
5949 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
5950 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
5951 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
5953 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
5954 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
5955 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
5958 /***********************************/
5959 /* MC_CMD_WOL_FILTER_REMOVE
5960 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
5962 #define MC_CMD_WOL_FILTER_REMOVE 0x33
5963 #undef MC_CMD_0x33_PRIVILEGE_CTG
5965 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
5967 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
5968 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
5969 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
5971 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
5972 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
5975 /***********************************/
5976 /* MC_CMD_WOL_FILTER_RESET
5977 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
5980 #define MC_CMD_WOL_FILTER_RESET 0x34
5981 #undef MC_CMD_0x34_PRIVILEGE_CTG
5983 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
5985 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
5986 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
5987 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
5988 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
5989 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
5991 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
5992 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
5995 /***********************************/
5996 /* MC_CMD_SET_MCAST_HASH
5997 * Set the MCAST hash value without otherwise reconfiguring the MAC
5999 #define MC_CMD_SET_MCAST_HASH 0x35
6001 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */
6002 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32
6003 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
6004 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
6005 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
6006 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16
6008 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
6009 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
6012 /***********************************/
6013 /* MC_CMD_NVRAM_TYPES
6014 * Return bitfield indicating available types of virtual NVRAM partitions.
6015 * Locks required: none. Returns: 0
6017 #define MC_CMD_NVRAM_TYPES 0x36
6018 #undef MC_CMD_0x36_PRIVILEGE_CTG
6020 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6022 /* MC_CMD_NVRAM_TYPES_IN msgrequest */
6023 #define MC_CMD_NVRAM_TYPES_IN_LEN 0
6025 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */
6026 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4
6027 /* Bit mask of supported types. */
6028 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
6029 /* enum: Disabled callisto. */
6030 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
6031 /* enum: MC firmware. */
6032 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1
6033 /* enum: MC backup firmware. */
6034 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
6035 /* enum: Static configuration Port0. */
6036 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
6037 /* enum: Static configuration Port1. */
6038 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
6039 /* enum: Dynamic configuration Port0. */
6040 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
6041 /* enum: Dynamic configuration Port1. */
6042 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
6043 /* enum: Expansion Rom. */
6044 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
6045 /* enum: Expansion Rom Configuration Port0. */
6046 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
6047 /* enum: Expansion Rom Configuration Port1. */
6048 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
6049 /* enum: Phy Configuration Port0. */
6050 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
6051 /* enum: Phy Configuration Port1. */
6052 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
6054 #define MC_CMD_NVRAM_TYPE_LOG 0xc
6055 /* enum: FPGA image. */
6056 #define MC_CMD_NVRAM_TYPE_FPGA 0xd
6057 /* enum: FPGA backup image */
6058 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
6059 /* enum: FC firmware. */
6060 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf
6061 /* enum: FC backup firmware. */
6062 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
6063 /* enum: CPLD image. */
6064 #define MC_CMD_NVRAM_TYPE_CPLD 0x11
6065 /* enum: Licensing information. */
6066 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12
6068 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
6069 /* enum: Additional flash on FPGA. */
6070 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
6073 /***********************************/
6074 /* MC_CMD_NVRAM_INFO
6075 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
6076 * EINVAL (bad type).
6078 #define MC_CMD_NVRAM_INFO 0x37
6079 #undef MC_CMD_0x37_PRIVILEGE_CTG
6081 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6083 /* MC_CMD_NVRAM_INFO_IN msgrequest */
6084 #define MC_CMD_NVRAM_INFO_IN_LEN 4
6085 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
6086 /* Enum values, see field(s): */
6087 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
6089 /* MC_CMD_NVRAM_INFO_OUT msgresponse */
6090 #define MC_CMD_NVRAM_INFO_OUT_LEN 24
6091 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
6092 /* Enum values, see field(s): */
6093 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
6094 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
6095 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
6096 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
6097 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
6098 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
6099 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
6100 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
6101 #define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6
6102 #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1
6103 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7
6104 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
6105 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
6106 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
6108 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */
6109 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28
6110 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
6111 /* Enum values, see field(s): */
6112 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
6113 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
6114 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8
6115 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12
6116 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
6117 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
6118 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
6119 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
6120 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7
6121 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1
6122 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16
6123 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20
6124 /* Writes must be multiples of this size. Added to support the MUM on Sorrento.
6126 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24
6129 /***********************************/
6130 /* MC_CMD_NVRAM_UPDATE_START
6131 * Start a group of update operations on a virtual NVRAM partition. Locks
6132 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
6133 * PHY_LOCK required and not held).
6135 #define MC_CMD_NVRAM_UPDATE_START 0x38
6136 #undef MC_CMD_0x38_PRIVILEGE_CTG
6138 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6140 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */
6141 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
6142 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
6143 /* Enum values, see field(s): */
6144 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
6146 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
6147 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
6150 /***********************************/
6151 /* MC_CMD_NVRAM_READ
6152 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if
6153 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
6154 * PHY_LOCK required and not held)
6156 #define MC_CMD_NVRAM_READ 0x39
6157 #undef MC_CMD_0x39_PRIVILEGE_CTG
6159 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6161 /* MC_CMD_NVRAM_READ_IN msgrequest */
6162 #define MC_CMD_NVRAM_READ_IN_LEN 12
6163 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
6164 /* Enum values, see field(s): */
6165 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
6166 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
6167 /* amount to read in bytes */
6168 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
6170 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */
6171 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16
6172 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
6173 /* Enum values, see field(s): */
6174 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
6175 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
6176 /* amount to read in bytes */
6177 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8
6178 /* Optional control info. If a partition is stored with an A/B versioning
6179 * scheme (i.e. in more than one physical partition in NVRAM) the host can set
6180 * this to control which underlying physical partition is used to read data
6181 * from. This allows it to perform a read-modify-write-verify with the write
6182 * lock continuously held by calling NVRAM_UPDATE_START, reading the old
6183 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then
6184 * verifying by reading with MODE=TARGET_BACKUP.
6186 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12
6187 /* enum: Same as omitting MODE: caller sees data in current partition unless it
6188 * holds the write lock in which case it sees data in the partition it is
6191 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
6192 /* enum: Read from the current partition of an A/B pair, even if holding the
6195 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
6196 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B
6199 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
6201 /* MC_CMD_NVRAM_READ_OUT msgresponse */
6202 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1
6203 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252
6204 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
6205 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
6206 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
6207 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
6208 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
6211 /***********************************/
6212 /* MC_CMD_NVRAM_WRITE
6213 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if
6214 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
6215 * PHY_LOCK required and not held)
6217 #define MC_CMD_NVRAM_WRITE 0x3a
6218 #undef MC_CMD_0x3a_PRIVILEGE_CTG
6220 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6222 /* MC_CMD_NVRAM_WRITE_IN msgrequest */
6223 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13
6224 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252
6225 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
6226 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
6227 /* Enum values, see field(s): */
6228 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
6229 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
6230 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
6231 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
6232 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
6233 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
6234 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
6236 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */
6237 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0
6240 /***********************************/
6241 /* MC_CMD_NVRAM_ERASE
6242 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if
6243 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
6244 * PHY_LOCK required and not held)
6246 #define MC_CMD_NVRAM_ERASE 0x3b
6247 #undef MC_CMD_0x3b_PRIVILEGE_CTG
6249 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6251 /* MC_CMD_NVRAM_ERASE_IN msgrequest */
6252 #define MC_CMD_NVRAM_ERASE_IN_LEN 12
6253 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
6254 /* Enum values, see field(s): */
6255 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
6256 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
6257 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
6259 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */
6260 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0
6263 /***********************************/
6264 /* MC_CMD_NVRAM_UPDATE_FINISH
6265 * Finish a group of update operations on a virtual NVRAM partition. Locks
6266 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad
6267 * type/offset/length), EACCES (if PHY_LOCK required and not held)
6269 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
6270 #undef MC_CMD_0x3c_PRIVILEGE_CTG
6272 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6274 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */
6275 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
6276 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
6277 /* Enum values, see field(s): */
6278 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
6279 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
6281 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */
6282 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
6285 /***********************************/
6289 * The AFTER_ASSERTION flag is intended to be used when the driver notices an
6290 * assertion failure (at which point it is expected to perform a complete tear
6291 * down and reinitialise), to allow both ports to reset the MC once in an
6294 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
6295 * which means that they will automatically reboot out of the assertion
6296 * handler, so this is in practise an optional operation. It is still
6297 * recommended that drivers execute this to support custom firmwares with
6298 * REBOOT_ON_ASSERT=0.
6300 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
6303 #define MC_CMD_REBOOT 0x3d
6304 #undef MC_CMD_0x3d_PRIVILEGE_CTG
6306 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6308 /* MC_CMD_REBOOT_IN msgrequest */
6309 #define MC_CMD_REBOOT_IN_LEN 4
6310 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0
6311 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
6313 /* MC_CMD_REBOOT_OUT msgresponse */
6314 #define MC_CMD_REBOOT_OUT_LEN 0
6317 /***********************************/
6319 * Request scheduler info. Locks required: NONE. Returns: An array of
6320 * (timeslice,maximum overrun), one for each thread, in ascending order of
6323 #define MC_CMD_SCHEDINFO 0x3e
6324 #undef MC_CMD_0x3e_PRIVILEGE_CTG
6326 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6328 /* MC_CMD_SCHEDINFO_IN msgrequest */
6329 #define MC_CMD_SCHEDINFO_IN_LEN 0
6331 /* MC_CMD_SCHEDINFO_OUT msgresponse */
6332 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4
6333 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252
6334 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
6335 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
6336 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
6337 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
6338 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
6341 /***********************************/
6342 /* MC_CMD_REBOOT_MODE
6343 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot
6344 * mode to the specified value. Returns the old mode.
6346 #define MC_CMD_REBOOT_MODE 0x3f
6347 #undef MC_CMD_0x3f_PRIVILEGE_CTG
6349 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6351 /* MC_CMD_REBOOT_MODE_IN msgrequest */
6352 #define MC_CMD_REBOOT_MODE_IN_LEN 4
6353 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
6355 #define MC_CMD_REBOOT_MODE_NORMAL 0x0
6356 /* enum: Power-on Reset. */
6357 #define MC_CMD_REBOOT_MODE_POR 0x2
6358 /* enum: Snapper. */
6359 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3
6360 /* enum: snapper fake POR */
6361 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
6362 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7
6363 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
6365 /* MC_CMD_REBOOT_MODE_OUT msgresponse */
6366 #define MC_CMD_REBOOT_MODE_OUT_LEN 4
6367 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
6370 /***********************************/
6371 /* MC_CMD_SENSOR_INFO
6372 * Returns information about every available sensor.
6374 * Each sensor has a single (16bit) value, and a corresponding state. The
6375 * mapping between value and state is nominally determined by the MC, but may
6376 * be implemented using up to 2 ranges per sensor.
6378 * This call returns a mask (32bit) of the sensors that are supported by this
6379 * platform, then an array of sensor information structures, in order of sensor
6380 * type (but without gaps for unimplemented sensors). Each structure defines
6381 * the ranges for the corresponding sensor. An unused range is indicated by
6382 * equal limit values. If one range is used, a value outside that range results
6383 * in STATE_FATAL. If two ranges are used, a value outside the second range
6384 * results in STATE_FATAL while a value outside the first and inside the second
6385 * range results in STATE_WARNING.
6387 * Sensor masks and sensor information arrays are organised into pages. For
6388 * backward compatibility, older host software can only use sensors in page 0.
6389 * Bit 32 in the sensor mask was previously unused, and is no reserved for use
6390 * as the next page flag.
6392 * If the request does not contain a PAGE value then firmware will only return
6393 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
6395 * If the request contains a PAGE value then firmware responds with the sensor
6396 * mask and sensor information array for that page of sensors. In this case bit
6397 * 31 in the mask is set if another page exists.
6399 * Locks required: None Returns: 0
6401 #define MC_CMD_SENSOR_INFO 0x41
6402 #undef MC_CMD_0x41_PRIVILEGE_CTG
6404 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6406 /* MC_CMD_SENSOR_INFO_IN msgrequest */
6407 #define MC_CMD_SENSOR_INFO_IN_LEN 0
6409 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */
6410 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
6411 /* Which page of sensors to report.
6413 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
6415 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
6417 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
6419 /* MC_CMD_SENSOR_INFO_OUT msgresponse */
6420 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4
6421 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252
6422 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
6423 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
6424 /* enum: Controller temperature: degC */
6425 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
6426 /* enum: Phy common temperature: degC */
6427 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
6428 /* enum: Controller cooling: bool */
6429 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
6430 /* enum: Phy 0 temperature: degC */
6431 #define MC_CMD_SENSOR_PHY0_TEMP 0x3
6432 /* enum: Phy 0 cooling: bool */
6433 #define MC_CMD_SENSOR_PHY0_COOLING 0x4
6434 /* enum: Phy 1 temperature: degC */
6435 #define MC_CMD_SENSOR_PHY1_TEMP 0x5
6436 /* enum: Phy 1 cooling: bool */
6437 #define MC_CMD_SENSOR_PHY1_COOLING 0x6
6438 /* enum: 1.0v power: mV */
6439 #define MC_CMD_SENSOR_IN_1V0 0x7
6440 /* enum: 1.2v power: mV */
6441 #define MC_CMD_SENSOR_IN_1V2 0x8
6442 /* enum: 1.8v power: mV */
6443 #define MC_CMD_SENSOR_IN_1V8 0x9
6444 /* enum: 2.5v power: mV */
6445 #define MC_CMD_SENSOR_IN_2V5 0xa
6446 /* enum: 3.3v power: mV */
6447 #define MC_CMD_SENSOR_IN_3V3 0xb
6448 /* enum: 12v power: mV */
6449 #define MC_CMD_SENSOR_IN_12V0 0xc
6450 /* enum: 1.2v analogue power: mV */
6451 #define MC_CMD_SENSOR_IN_1V2A 0xd
6452 /* enum: reference voltage: mV */
6453 #define MC_CMD_SENSOR_IN_VREF 0xe
6454 /* enum: AOE FPGA power: mV */
6455 #define MC_CMD_SENSOR_OUT_VAOE 0xf
6456 /* enum: AOE FPGA temperature: degC */
6457 #define MC_CMD_SENSOR_AOE_TEMP 0x10
6458 /* enum: AOE FPGA PSU temperature: degC */
6459 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
6460 /* enum: AOE PSU temperature: degC */
6461 #define MC_CMD_SENSOR_PSU_TEMP 0x12
6462 /* enum: Fan 0 speed: RPM */
6463 #define MC_CMD_SENSOR_FAN_0 0x13
6464 /* enum: Fan 1 speed: RPM */
6465 #define MC_CMD_SENSOR_FAN_1 0x14
6466 /* enum: Fan 2 speed: RPM */
6467 #define MC_CMD_SENSOR_FAN_2 0x15
6468 /* enum: Fan 3 speed: RPM */
6469 #define MC_CMD_SENSOR_FAN_3 0x16
6470 /* enum: Fan 4 speed: RPM */
6471 #define MC_CMD_SENSOR_FAN_4 0x17
6472 /* enum: AOE FPGA input power: mV */
6473 #define MC_CMD_SENSOR_IN_VAOE 0x18
6474 /* enum: AOE FPGA current: mA */
6475 #define MC_CMD_SENSOR_OUT_IAOE 0x19
6476 /* enum: AOE FPGA input current: mA */
6477 #define MC_CMD_SENSOR_IN_IAOE 0x1a
6478 /* enum: NIC power consumption: W */
6479 #define MC_CMD_SENSOR_NIC_POWER 0x1b
6480 /* enum: 0.9v power voltage: mV */
6481 #define MC_CMD_SENSOR_IN_0V9 0x1c
6482 /* enum: 0.9v power current: mA */
6483 #define MC_CMD_SENSOR_IN_I0V9 0x1d
6484 /* enum: 1.2v power current: mA */
6485 #define MC_CMD_SENSOR_IN_I1V2 0x1e
6486 /* enum: Not a sensor: reserved for the next page flag */
6487 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
6488 /* enum: 0.9v power voltage (at ADC): mV */
6489 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20
6490 /* enum: Controller temperature 2: degC */
6491 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
6492 /* enum: Voltage regulator internal temperature: degC */
6493 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
6494 /* enum: 0.9V voltage regulator temperature: degC */
6495 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
6496 /* enum: 1.2V voltage regulator temperature: degC */
6497 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
6498 /* enum: controller internal temperature sensor voltage (internal ADC): mV */
6499 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
6500 /* enum: controller internal temperature (internal ADC): degC */
6501 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
6502 /* enum: controller internal temperature sensor voltage (external ADC): mV */
6503 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
6504 /* enum: controller internal temperature (external ADC): degC */
6505 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
6506 /* enum: ambient temperature: degC */
6507 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
6508 /* enum: air flow: bool */
6509 #define MC_CMD_SENSOR_AIRFLOW 0x2a
6510 /* enum: voltage between VSS08D and VSS08D at CSR: mV */
6511 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
6512 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
6513 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
6514 /* enum: Hotpoint temperature: degC */
6515 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
6516 /* enum: Port 0 PHY power switch over-current: bool */
6517 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
6518 /* enum: Port 1 PHY power switch over-current: bool */
6519 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
6520 /* enum: Mop-up microcontroller reference voltage (millivolts) */
6521 #define MC_CMD_SENSOR_MUM_VCC 0x30
6522 /* enum: 0.9v power phase A voltage: mV */
6523 #define MC_CMD_SENSOR_IN_0V9_A 0x31
6524 /* enum: 0.9v power phase A current: mA */
6525 #define MC_CMD_SENSOR_IN_I0V9_A 0x32
6526 /* enum: 0.9V voltage regulator phase A temperature: degC */
6527 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
6528 /* enum: 0.9v power phase B voltage: mV */
6529 #define MC_CMD_SENSOR_IN_0V9_B 0x34
6530 /* enum: 0.9v power phase B current: mA */
6531 #define MC_CMD_SENSOR_IN_I0V9_B 0x35
6532 /* enum: 0.9V voltage regulator phase B temperature: degC */
6533 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
6534 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
6535 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
6536 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */
6537 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
6538 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
6539 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
6540 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */
6541 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
6542 /* enum: CCOM RTS temperature: degC */
6543 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
6544 /* enum: Not a sensor: reserved for the next page flag */
6545 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
6546 /* enum: controller internal temperature sensor voltage on master core
6547 * (internal ADC): mV
6549 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
6550 /* enum: controller internal temperature on master core (internal ADC): degC */
6551 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
6552 /* enum: controller internal temperature sensor voltage on master core
6553 * (external ADC): mV
6555 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
6556 /* enum: controller internal temperature on master core (external ADC): degC */
6557 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
6558 /* enum: controller internal temperature on slave core sensor voltage (internal
6561 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
6562 /* enum: controller internal temperature on slave core (internal ADC): degC */
6563 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
6564 /* enum: controller internal temperature on slave core sensor voltage (external
6567 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
6568 /* enum: controller internal temperature on slave core (external ADC): degC */
6569 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
6570 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */
6571 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49
6572 /* enum: Temperature of SODIMM 0 (if installed): degC */
6573 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
6574 /* enum: Temperature of SODIMM 1 (if installed): degC */
6575 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
6576 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
6577 #define MC_CMD_SENSOR_PHY0_VCC 0x4c
6578 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
6579 #define MC_CMD_SENSOR_PHY1_VCC 0x4d
6580 /* enum: Controller die temperature (TDIODE): degC */
6581 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
6582 /* enum: Board temperature (front): degC */
6583 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
6584 /* enum: Board temperature (back): degC */
6585 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
6586 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
6587 #define MC_CMD_SENSOR_ENTRY_OFST 4
6588 #define MC_CMD_SENSOR_ENTRY_LEN 8
6589 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4
6590 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8
6591 #define MC_CMD_SENSOR_ENTRY_MINNUM 0
6592 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31
6594 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */
6595 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
6596 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
6597 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
6598 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
6599 /* Enum values, see field(s): */
6600 /* MC_CMD_SENSOR_INFO_OUT */
6601 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31
6602 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
6603 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
6604 /* MC_CMD_SENSOR_ENTRY_OFST 4 */
6605 /* MC_CMD_SENSOR_ENTRY_LEN 8 */
6606 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
6607 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
6608 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
6609 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
6611 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
6612 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
6613 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
6614 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
6615 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
6616 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
6617 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
6618 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
6619 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
6620 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
6621 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
6622 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
6623 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
6624 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
6625 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
6626 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
6627 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
6628 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
6631 /***********************************/
6632 /* MC_CMD_READ_SENSORS
6633 * Returns the current reading from each sensor. DMAs an array of sensor
6634 * readings, in order of sensor type (but without gaps for unimplemented
6635 * sensors), into host memory. Each array element is a
6636 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.
6638 * If the request does not contain the LENGTH field then only sensors 0 to 30
6639 * are reported, to avoid DMA buffer overflow in older host software. If the
6640 * sensor reading require more space than the LENGTH allows, then return
6643 * The MC will send a SENSOREVT event every time any sensor changes state. The
6644 * driver is responsible for ensuring that it doesn't miss any events. The
6645 * board will function normally if all sensors are in STATE_OK or
6646 * STATE_WARNING. Otherwise the board should not be expected to function.
6648 #define MC_CMD_READ_SENSORS 0x42
6649 #undef MC_CMD_0x42_PRIVILEGE_CTG
6651 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6653 /* MC_CMD_READ_SENSORS_IN msgrequest */
6654 #define MC_CMD_READ_SENSORS_IN_LEN 8
6655 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
6656 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
6657 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
6658 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
6659 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
6661 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
6662 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12
6663 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
6664 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
6665 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
6666 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
6667 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
6668 /* Size in bytes of host buffer. */
6669 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
6671 /* MC_CMD_READ_SENSORS_OUT msgresponse */
6672 #define MC_CMD_READ_SENSORS_OUT_LEN 0
6674 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */
6675 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
6677 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
6678 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
6679 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
6680 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
6681 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
6682 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
6683 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
6684 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
6686 #define MC_CMD_SENSOR_STATE_OK 0x0
6687 /* enum: Breached warning threshold. */
6688 #define MC_CMD_SENSOR_STATE_WARNING 0x1
6689 /* enum: Breached fatal threshold. */
6690 #define MC_CMD_SENSOR_STATE_FATAL 0x2
6691 /* enum: Fault with sensor. */
6692 #define MC_CMD_SENSOR_STATE_BROKEN 0x3
6693 /* enum: Sensor is working but does not currently have a reading. */
6694 #define MC_CMD_SENSOR_STATE_NO_READING 0x4
6695 /* enum: Sensor initialisation failed. */
6696 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
6697 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
6698 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
6699 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3
6700 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
6701 /* Enum values, see field(s): */
6702 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
6703 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24
6704 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8
6707 /***********************************/
6708 /* MC_CMD_GET_PHY_STATE
6709 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot
6710 * (e.g. due to missing or corrupted firmware). Locks required: None. Return
6713 #define MC_CMD_GET_PHY_STATE 0x43
6714 #undef MC_CMD_0x43_PRIVILEGE_CTG
6716 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6718 /* MC_CMD_GET_PHY_STATE_IN msgrequest */
6719 #define MC_CMD_GET_PHY_STATE_IN_LEN 0
6721 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */
6722 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4
6723 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
6725 #define MC_CMD_PHY_STATE_OK 0x1
6727 #define MC_CMD_PHY_STATE_ZOMBIE 0x2
6730 /***********************************/
6731 /* MC_CMD_SETUP_8021QBB
6732 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
6733 * disable 802.Qbb for a given priority.
6735 #define MC_CMD_SETUP_8021QBB 0x44
6737 /* MC_CMD_SETUP_8021QBB_IN msgrequest */
6738 #define MC_CMD_SETUP_8021QBB_IN_LEN 32
6739 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
6740 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32
6742 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */
6743 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0
6746 /***********************************/
6747 /* MC_CMD_WOL_FILTER_GET
6748 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
6750 #define MC_CMD_WOL_FILTER_GET 0x45
6751 #undef MC_CMD_0x45_PRIVILEGE_CTG
6753 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
6755 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */
6756 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0
6758 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
6759 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
6760 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
6763 /***********************************/
6764 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
6765 * Add a protocol offload to NIC for lights-out state. Locks required: None.
6766 * Returns: 0, ENOSYS
6768 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
6769 #undef MC_CMD_0x46_PRIVILEGE_CTG
6771 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK
6773 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
6774 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
6775 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
6776 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
6777 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
6778 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
6779 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
6780 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
6781 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
6782 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
6783 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
6785 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
6786 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
6787 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
6788 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
6789 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
6790 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
6792 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
6793 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
6794 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
6795 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
6796 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
6797 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
6798 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
6799 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
6800 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16
6802 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
6803 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
6804 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
6807 /***********************************/
6808 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
6809 * Remove a protocol offload from NIC for lights-out state. Locks required:
6810 * None. Returns: 0, ENOSYS
6812 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
6813 #undef MC_CMD_0x47_PRIVILEGE_CTG
6815 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK
6817 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
6818 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
6819 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
6820 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
6822 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
6823 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
6826 /***********************************/
6827 /* MC_CMD_MAC_RESET_RESTORE
6828 * Restore MAC after block reset. Locks required: None. Returns: 0.
6830 #define MC_CMD_MAC_RESET_RESTORE 0x48
6832 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
6833 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
6835 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
6836 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
6839 /***********************************/
6840 /* MC_CMD_TESTASSERT
6841 * Deliberately trigger an assert-detonation in the firmware for testing
6842 * purposes (i.e. to allow tests that the driver copes gracefully). Locks
6843 * required: None Returns: 0
6845 #define MC_CMD_TESTASSERT 0x49
6846 #undef MC_CMD_0x49_PRIVILEGE_CTG
6848 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6850 /* MC_CMD_TESTASSERT_IN msgrequest */
6851 #define MC_CMD_TESTASSERT_IN_LEN 0
6853 /* MC_CMD_TESTASSERT_OUT msgresponse */
6854 #define MC_CMD_TESTASSERT_OUT_LEN 0
6857 /***********************************/
6858 /* MC_CMD_WORKAROUND
6859 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't
6860 * understand the given workaround number - which should not be treated as a
6861 * hard error by client code. This op does not imply any semantics about each
6862 * workaround, that's between the driver and the mcfw on a per-workaround
6863 * basis. Locks required: None. Returns: 0, EINVAL .
6865 #define MC_CMD_WORKAROUND 0x4a
6866 #undef MC_CMD_0x4a_PRIVILEGE_CTG
6868 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6870 /* MC_CMD_WORKAROUND_IN msgrequest */
6871 #define MC_CMD_WORKAROUND_IN_LEN 8
6872 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */
6873 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
6874 /* enum: Bug 17230 work around. */
6875 #define MC_CMD_WORKAROUND_BUG17230 0x1
6876 /* enum: Bug 35388 work around (unsafe EVQ writes). */
6877 #define MC_CMD_WORKAROUND_BUG35388 0x2
6878 /* enum: Bug35017 workaround (A64 tables must be identity map) */
6879 #define MC_CMD_WORKAROUND_BUG35017 0x3
6880 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
6881 #define MC_CMD_WORKAROUND_BUG41750 0x4
6882 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
6883 * - before adding code that queries this workaround, remember that there's
6884 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
6885 * and will hence (incorrectly) report that the bug doesn't exist.
6887 #define MC_CMD_WORKAROUND_BUG42008 0x5
6888 /* enum: Bug 26807 features present in firmware (multicast filter chaining)
6889 * This feature cannot be turned on/off while there are any filters already
6890 * present. The behaviour in such case depends on the acting client's privilege
6891 * level. If the client has the admin privilege, then all functions that have
6892 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise
6893 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.
6895 #define MC_CMD_WORKAROUND_BUG26807 0x6
6896 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
6897 #define MC_CMD_WORKAROUND_BUG61265 0x7
6898 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
6901 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
6903 /* MC_CMD_WORKAROUND_OUT msgresponse */
6904 #define MC_CMD_WORKAROUND_OUT_LEN 0
6906 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used
6907 * when (TYPE == MC_CMD_WORKAROUND_BUG26807)
6909 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4
6910 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
6911 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
6912 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
6915 /***********************************/
6916 /* MC_CMD_GET_PHY_MEDIA_INFO
6917 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
6918 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG
6919 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the
6920 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1
6921 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
6922 * Anything else: currently undefined. Locks required: None. Return code: 0.
6924 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
6925 #undef MC_CMD_0x4b_PRIVILEGE_CTG
6927 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6929 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
6930 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
6931 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
6933 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
6934 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
6935 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
6936 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
6938 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
6939 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
6940 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
6941 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
6942 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
6945 /***********************************/
6946 /* MC_CMD_NVRAM_TEST
6947 * Test a particular NVRAM partition for valid contents (where "valid" depends
6948 * on the type of partition).
6950 #define MC_CMD_NVRAM_TEST 0x4c
6951 #undef MC_CMD_0x4c_PRIVILEGE_CTG
6953 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6955 /* MC_CMD_NVRAM_TEST_IN msgrequest */
6956 #define MC_CMD_NVRAM_TEST_IN_LEN 4
6957 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
6958 /* Enum values, see field(s): */
6959 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
6961 /* MC_CMD_NVRAM_TEST_OUT msgresponse */
6962 #define MC_CMD_NVRAM_TEST_OUT_LEN 4
6963 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
6965 #define MC_CMD_NVRAM_TEST_PASS 0x0
6967 #define MC_CMD_NVRAM_TEST_FAIL 0x1
6968 /* enum: Not supported. */
6969 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
6972 /***********************************/
6973 /* MC_CMD_MRSFP_TWEAK
6974 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.
6975 * I2C I/O expander bits are always read; if equaliser parameters are supplied,
6976 * they are configured first. Locks required: None. Return code: 0, EINVAL.
6978 #define MC_CMD_MRSFP_TWEAK 0x4d
6980 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
6981 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
6982 /* 0-6 low->high de-emph. */
6983 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
6984 /* 0-8 low->high ref.V */
6985 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
6986 /* 0-8 0-8 low->high boost */
6987 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
6988 /* 0-8 low->high ref.V */
6989 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
6991 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
6992 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
6994 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
6995 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12
6997 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
6999 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
7001 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
7003 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
7005 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
7008 /***********************************/
7009 /* MC_CMD_SENSOR_SET_LIMS
7010 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
7011 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out
7014 #define MC_CMD_SENSOR_SET_LIMS 0x4e
7015 #undef MC_CMD_0x4e_PRIVILEGE_CTG
7017 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7019 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
7020 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
7021 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
7022 /* Enum values, see field(s): */
7023 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
7024 /* interpretation is is sensor-specific. */
7025 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
7026 /* interpretation is is sensor-specific. */
7027 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
7028 /* interpretation is is sensor-specific. */
7029 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
7030 /* interpretation is is sensor-specific. */
7031 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
7033 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
7034 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
7037 /***********************************/
7038 /* MC_CMD_GET_RESOURCE_LIMITS
7040 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f
7042 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
7043 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
7045 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
7046 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
7047 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
7048 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
7049 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
7050 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
7053 /***********************************/
7054 /* MC_CMD_NVRAM_PARTITIONS
7055 * Reads the list of available virtual NVRAM partition types. Locks required:
7056 * none. Returns: 0, EINVAL (bad type).
7058 #define MC_CMD_NVRAM_PARTITIONS 0x51
7059 #undef MC_CMD_0x51_PRIVILEGE_CTG
7061 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7063 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */
7064 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
7066 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */
7067 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
7068 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
7069 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
7070 /* total number of partitions */
7071 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
7072 /* type ID code for each of NUM_PARTITIONS partitions */
7073 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
7074 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
7075 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
7076 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62
7079 /***********************************/
7080 /* MC_CMD_NVRAM_METADATA
7081 * Reads soft metadata for a virtual NVRAM partition type. Locks required:
7082 * none. Returns: 0, EINVAL (bad type).
7084 #define MC_CMD_NVRAM_METADATA 0x52
7085 #undef MC_CMD_0x52_PRIVILEGE_CTG
7087 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7089 /* MC_CMD_NVRAM_METADATA_IN msgrequest */
7090 #define MC_CMD_NVRAM_METADATA_IN_LEN 4
7091 /* Partition type ID code */
7092 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
7094 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */
7095 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20
7096 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
7097 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
7098 /* Partition type ID code */
7099 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
7100 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
7101 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
7102 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
7103 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
7104 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
7105 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2
7106 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
7107 /* Subtype ID code for content of this partition */
7108 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8
7109 /* 1st component of W.X.Y.Z version number for content of this partition */
7110 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12
7111 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2
7112 /* 2nd component of W.X.Y.Z version number for content of this partition */
7113 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14
7114 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2
7115 /* 3rd component of W.X.Y.Z version number for content of this partition */
7116 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16
7117 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2
7118 /* 4th component of W.X.Y.Z version number for content of this partition */
7119 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18
7120 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2
7121 /* Zero-terminated string describing the content of this partition */
7122 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20
7123 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
7124 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
7125 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232
7128 /***********************************/
7129 /* MC_CMD_GET_MAC_ADDRESSES
7130 * Returns the base MAC, count and stride for the requesting function
7132 #define MC_CMD_GET_MAC_ADDRESSES 0x55
7133 #undef MC_CMD_0x55_PRIVILEGE_CTG
7135 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7137 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */
7138 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
7140 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */
7141 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16
7142 /* Base MAC address */
7143 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
7144 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6
7146 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6
7147 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2
7148 /* Number of allocated MAC addresses */
7149 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8
7150 /* Spacing of allocated MAC addresses */
7151 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12
7154 /***********************************/
7156 * Perform a CLP related operation
7158 #define MC_CMD_CLP 0x56
7159 #undef MC_CMD_0x56_PRIVILEGE_CTG
7161 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7163 /* MC_CMD_CLP_IN msgrequest */
7164 #define MC_CMD_CLP_IN_LEN 4
7166 #define MC_CMD_CLP_IN_OP_OFST 0
7167 /* enum: Return to factory default settings */
7168 #define MC_CMD_CLP_OP_DEFAULT 0x1
7169 /* enum: Set MAC address */
7170 #define MC_CMD_CLP_OP_SET_MAC 0x2
7171 /* enum: Get MAC address */
7172 #define MC_CMD_CLP_OP_GET_MAC 0x3
7173 /* enum: Set UEFI/GPXE boot mode */
7174 #define MC_CMD_CLP_OP_SET_BOOT 0x4
7175 /* enum: Get UEFI/GPXE boot mode */
7176 #define MC_CMD_CLP_OP_GET_BOOT 0x5
7178 /* MC_CMD_CLP_OUT msgresponse */
7179 #define MC_CMD_CLP_OUT_LEN 0
7181 /* MC_CMD_CLP_IN_DEFAULT msgrequest */
7182 #define MC_CMD_CLP_IN_DEFAULT_LEN 4
7183 /* MC_CMD_CLP_IN_OP_OFST 0 */
7185 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */
7186 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0
7188 /* MC_CMD_CLP_IN_SET_MAC msgrequest */
7189 #define MC_CMD_CLP_IN_SET_MAC_LEN 12
7190 /* MC_CMD_CLP_IN_OP_OFST 0 */
7191 /* MAC address assigned to port */
7192 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
7193 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6
7195 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10
7196 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2
7198 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */
7199 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0
7201 /* MC_CMD_CLP_IN_GET_MAC msgrequest */
7202 #define MC_CMD_CLP_IN_GET_MAC_LEN 4
7203 /* MC_CMD_CLP_IN_OP_OFST 0 */
7205 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */
7206 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8
7207 /* MAC address assigned to port */
7208 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
7209 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6
7211 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6
7212 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2
7214 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */
7215 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5
7216 /* MC_CMD_CLP_IN_OP_OFST 0 */
7218 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
7219 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1
7221 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */
7222 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0
7224 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */
7225 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4
7226 /* MC_CMD_CLP_IN_OP_OFST 0 */
7228 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */
7229 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4
7231 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
7232 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1
7234 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1
7235 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3
7238 /***********************************/
7240 * Perform a MUM operation
7242 #define MC_CMD_MUM 0x57
7243 #undef MC_CMD_0x57_PRIVILEGE_CTG
7245 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7247 /* MC_CMD_MUM_IN msgrequest */
7248 #define MC_CMD_MUM_IN_LEN 4
7249 #define MC_CMD_MUM_IN_OP_HDR_OFST 0
7250 #define MC_CMD_MUM_IN_OP_LBN 0
7251 #define MC_CMD_MUM_IN_OP_WIDTH 8
7252 /* enum: NULL MCDI command to MUM */
7253 #define MC_CMD_MUM_OP_NULL 0x1
7254 /* enum: Get MUM version */
7255 #define MC_CMD_MUM_OP_GET_VERSION 0x2
7256 /* enum: Issue raw I2C command to MUM */
7257 #define MC_CMD_MUM_OP_RAW_CMD 0x3
7258 /* enum: Read from registers on devices connected to MUM. */
7259 #define MC_CMD_MUM_OP_READ 0x4
7260 /* enum: Write to registers on devices connected to MUM. */
7261 #define MC_CMD_MUM_OP_WRITE 0x5
7262 /* enum: Control UART logging. */
7263 #define MC_CMD_MUM_OP_LOG 0x6
7264 /* enum: Operations on MUM GPIO lines */
7265 #define MC_CMD_MUM_OP_GPIO 0x7
7266 /* enum: Get sensor readings from MUM */
7267 #define MC_CMD_MUM_OP_READ_SENSORS 0x8
7268 /* enum: Initiate clock programming on the MUM */
7269 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9
7270 /* enum: Initiate FPGA load from flash on the MUM */
7271 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa
7272 /* enum: Request sensor reading from MUM ADC resulting from earlier request via
7275 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb
7276 /* enum: Send commands relating to the QSFP ports via the MUM for PHY
7279 #define MC_CMD_MUM_OP_QSFP 0xc
7280 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage
7283 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd
7285 /* MC_CMD_MUM_IN_NULL msgrequest */
7286 #define MC_CMD_MUM_IN_NULL_LEN 4
7287 /* MUM cmd header */
7288 #define MC_CMD_MUM_IN_CMD_OFST 0
7290 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */
7291 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4
7292 /* MUM cmd header */
7293 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7295 /* MC_CMD_MUM_IN_READ msgrequest */
7296 #define MC_CMD_MUM_IN_READ_LEN 16
7297 /* MUM cmd header */
7298 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7299 /* ID of (device connected to MUM) to read from registers of */
7300 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4
7301 /* enum: Hittite HMC1035 clock generator on Sorrento board */
7302 #define MC_CMD_MUM_DEV_HITTITE 0x1
7303 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
7304 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2
7305 /* 32-bit address to read from */
7306 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8
7307 /* Number of words to read. */
7308 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12
7310 /* MC_CMD_MUM_IN_WRITE msgrequest */
7311 #define MC_CMD_MUM_IN_WRITE_LENMIN 16
7312 #define MC_CMD_MUM_IN_WRITE_LENMAX 252
7313 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
7314 /* MUM cmd header */
7315 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7316 /* ID of (device connected to MUM) to write to registers of */
7317 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4
7318 /* enum: Hittite HMC1035 clock generator on Sorrento board */
7319 /* MC_CMD_MUM_DEV_HITTITE 0x1 */
7320 /* 32-bit address to write to */
7321 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8
7322 /* Words to write */
7323 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12
7324 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
7325 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1
7326 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60
7328 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */
7329 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17
7330 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252
7331 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))
7332 /* MUM cmd header */
7333 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7334 /* MUM I2C cmd code */
7335 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4
7336 /* Number of bytes to write */
7337 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8
7338 /* Number of bytes to read */
7339 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12
7340 /* Bytes to write */
7341 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16
7342 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1
7343 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1
7344 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236
7346 /* MC_CMD_MUM_IN_LOG msgrequest */
7347 #define MC_CMD_MUM_IN_LOG_LEN 8
7348 /* MUM cmd header */
7349 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7350 #define MC_CMD_MUM_IN_LOG_OP_OFST 4
7351 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
7353 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */
7354 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12
7355 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7356 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */
7357 /* Enable/disable debug output to UART */
7358 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8
7360 /* MC_CMD_MUM_IN_GPIO msgrequest */
7361 #define MC_CMD_MUM_IN_GPIO_LEN 8
7362 /* MUM cmd header */
7363 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7364 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4
7365 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
7366 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8
7367 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
7368 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
7369 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
7370 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
7371 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
7372 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */
7374 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */
7375 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8
7376 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7377 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4
7379 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */
7380 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16
7381 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7382 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4
7383 /* The first 32-bit word to be written to the GPIO OUT register. */
7384 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8
7385 /* The second 32-bit word to be written to the GPIO OUT register. */
7386 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12
7388 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */
7389 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8
7390 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7391 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4
7393 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */
7394 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16
7395 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7396 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4
7397 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */
7398 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8
7399 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */
7400 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12
7402 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */
7403 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8
7404 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7405 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4
7407 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */
7408 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8
7409 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7410 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
7411 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8
7412 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8
7413 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
7414 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
7415 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
7416 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
7417 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16
7418 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8
7420 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */
7421 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8
7422 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7423 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4
7425 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */
7426 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8
7427 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7428 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
7429 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24
7430 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8
7432 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */
7433 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8
7434 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7435 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
7436 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24
7437 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8
7439 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */
7440 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8
7441 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7442 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
7443 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24
7444 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8
7446 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */
7447 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8
7448 /* MUM cmd header */
7449 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7450 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
7451 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
7452 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8
7453 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8
7454 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8
7456 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */
7457 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12
7458 /* MUM cmd header */
7459 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7460 /* Bit-mask of clocks to be programmed */
7461 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4
7462 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
7463 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
7464 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
7465 /* Control flags for clock programming */
7466 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8
7467 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
7468 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1
7469 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1
7470 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1
7471 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2
7472 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1
7474 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */
7475 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8
7476 /* MUM cmd header */
7477 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7478 /* Enable/Disable FPGA config from flash */
7479 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4
7481 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */
7482 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4
7483 /* MUM cmd header */
7484 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7486 /* MC_CMD_MUM_IN_QSFP msgrequest */
7487 #define MC_CMD_MUM_IN_QSFP_LEN 12
7488 /* MUM cmd header */
7489 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7490 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4
7491 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
7492 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
7493 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
7494 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
7495 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
7496 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
7497 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
7498 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
7499 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8
7501 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */
7502 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16
7503 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7504 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4
7505 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8
7506 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12
7508 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */
7509 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24
7510 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7511 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4
7512 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8
7513 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12
7514 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16
7515 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20
7517 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */
7518 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12
7519 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7520 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4
7521 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8
7523 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */
7524 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16
7525 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7526 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4
7527 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8
7528 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12
7530 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */
7531 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12
7532 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7533 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4
7534 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8
7536 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */
7537 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12
7538 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7539 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4
7540 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8
7542 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */
7543 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4
7544 /* MUM cmd header */
7545 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7547 /* MC_CMD_MUM_OUT msgresponse */
7548 #define MC_CMD_MUM_OUT_LEN 0
7550 /* MC_CMD_MUM_OUT_NULL msgresponse */
7551 #define MC_CMD_MUM_OUT_NULL_LEN 0
7553 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */
7554 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12
7555 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0
7556 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
7557 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8
7558 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
7559 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8
7561 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */
7562 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
7563 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252
7564 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
7566 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
7567 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1
7568 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1
7569 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252
7571 /* MC_CMD_MUM_OUT_READ msgresponse */
7572 #define MC_CMD_MUM_OUT_READ_LENMIN 4
7573 #define MC_CMD_MUM_OUT_READ_LENMAX 252
7574 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
7575 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
7576 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
7577 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1
7578 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63
7580 /* MC_CMD_MUM_OUT_WRITE msgresponse */
7581 #define MC_CMD_MUM_OUT_WRITE_LEN 0
7583 /* MC_CMD_MUM_OUT_LOG msgresponse */
7584 #define MC_CMD_MUM_OUT_LOG_LEN 0
7586 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */
7587 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0
7589 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */
7590 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8
7591 /* The first 32-bit word read from the GPIO IN register. */
7592 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0
7593 /* The second 32-bit word read from the GPIO IN register. */
7594 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4
7596 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */
7597 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0
7599 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */
7600 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8
7601 /* The first 32-bit word read from the GPIO OUT register. */
7602 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0
7603 /* The second 32-bit word read from the GPIO OUT register. */
7604 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4
7606 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */
7607 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0
7609 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */
7610 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8
7611 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0
7612 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4
7614 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */
7615 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4
7616 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0
7618 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */
7619 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0
7621 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */
7622 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0
7624 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */
7625 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0
7627 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */
7628 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
7629 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252
7630 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
7631 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
7632 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
7633 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1
7634 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63
7635 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
7636 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16
7637 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16
7638 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8
7639 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24
7640 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8
7642 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */
7643 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4
7644 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0
7646 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */
7647 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0
7649 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */
7650 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4
7651 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0
7653 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */
7654 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0
7656 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */
7657 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8
7658 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0
7659 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
7660 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
7661 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1
7662 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1
7663 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1
7665 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */
7666 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4
7667 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0
7669 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */
7670 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5
7671 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252
7672 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
7674 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
7675 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4
7676 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1
7677 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1
7678 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248
7680 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */
7681 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8
7682 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0
7683 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4
7685 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */
7686 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4
7687 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0
7689 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */
7690 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24
7691 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248
7692 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))
7693 /* Discrete (soldered) DDR resistor strap info */
7694 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
7695 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
7696 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16
7697 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16
7698 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16
7699 /* Number of SODIMM info records */
7700 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4
7701 /* Array of SODIMM info records */
7702 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8
7703 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8
7704 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8
7705 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12
7706 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2
7707 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30
7708 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
7709 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8
7710 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */
7711 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0
7712 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */
7713 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
7714 /* enum: Total number of SODIMM banks */
7715 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
7716 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8
7717 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8
7718 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16
7719 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
7720 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20
7721 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
7722 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
7723 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
7724 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
7725 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
7726 /* enum: Values 5-15 are reserved for future usage */
7727 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
7728 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24
7729 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8
7730 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32
7731 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16
7732 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48
7733 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
7734 /* enum: No module present */
7735 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0
7736 /* enum: Module present supported and powered on */
7737 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1
7738 /* enum: Module present but bad type */
7739 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2
7740 /* enum: Module present but incompatible voltage */
7741 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3
7742 /* enum: Module present but unknown SPD */
7743 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4
7744 /* enum: Module present but slot cannot support it */
7745 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5
7746 /* enum: Modules may or may not be present, but cannot establish contact by I2C
7748 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
7749 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52
7750 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12
7752 /* MC_CMD_RESOURCE_SPECIFIER enum */
7754 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
7756 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe
7758 /* EVB_PORT_ID structuredef */
7759 #define EVB_PORT_ID_LEN 4
7760 #define EVB_PORT_ID_PORT_ID_OFST 0
7761 /* enum: An invalid port handle. */
7762 #define EVB_PORT_ID_NULL 0x0
7763 /* enum: The port assigned to this function.. */
7764 #define EVB_PORT_ID_ASSIGNED 0x1000000
7765 /* enum: External network port 0 */
7766 #define EVB_PORT_ID_MAC0 0x2000000
7767 /* enum: External network port 1 */
7768 #define EVB_PORT_ID_MAC1 0x2000001
7769 /* enum: External network port 2 */
7770 #define EVB_PORT_ID_MAC2 0x2000002
7771 /* enum: External network port 3 */
7772 #define EVB_PORT_ID_MAC3 0x2000003
7773 #define EVB_PORT_ID_PORT_ID_LBN 0
7774 #define EVB_PORT_ID_PORT_ID_WIDTH 32
7776 /* EVB_VLAN_TAG structuredef */
7777 #define EVB_VLAN_TAG_LEN 2
7778 /* The VLAN tag value */
7779 #define EVB_VLAN_TAG_VLAN_ID_LBN 0
7780 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12
7781 #define EVB_VLAN_TAG_MODE_LBN 12
7782 #define EVB_VLAN_TAG_MODE_WIDTH 4
7783 /* enum: Insert the VLAN. */
7784 #define EVB_VLAN_TAG_INSERT 0x0
7785 /* enum: Replace the VLAN if already present. */
7786 #define EVB_VLAN_TAG_REPLACE 0x1
7788 /* BUFTBL_ENTRY structuredef */
7789 #define BUFTBL_ENTRY_LEN 12
7791 #define BUFTBL_ENTRY_OID_OFST 0
7792 #define BUFTBL_ENTRY_OID_LEN 2
7793 #define BUFTBL_ENTRY_OID_LBN 0
7794 #define BUFTBL_ENTRY_OID_WIDTH 16
7795 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */
7796 #define BUFTBL_ENTRY_PGSZ_OFST 2
7797 #define BUFTBL_ENTRY_PGSZ_LEN 2
7798 #define BUFTBL_ENTRY_PGSZ_LBN 16
7799 #define BUFTBL_ENTRY_PGSZ_WIDTH 16
7800 /* the raw 64-bit address field from the SMC, not adjusted for page size */
7801 #define BUFTBL_ENTRY_RAWADDR_OFST 4
7802 #define BUFTBL_ENTRY_RAWADDR_LEN 8
7803 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
7804 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8
7805 #define BUFTBL_ENTRY_RAWADDR_LBN 32
7806 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64
7808 /* NVRAM_PARTITION_TYPE structuredef */
7809 #define NVRAM_PARTITION_TYPE_LEN 2
7810 #define NVRAM_PARTITION_TYPE_ID_OFST 0
7811 #define NVRAM_PARTITION_TYPE_ID_LEN 2
7812 /* enum: Primary MC firmware partition */
7813 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
7814 /* enum: Secondary MC firmware partition */
7815 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
7816 /* enum: Expansion ROM partition */
7817 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
7818 /* enum: Static configuration TLV partition */
7819 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
7820 /* enum: Dynamic configuration TLV partition */
7821 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
7822 /* enum: Expansion ROM configuration data for port 0 */
7823 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
7824 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
7825 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
7826 /* enum: Expansion ROM configuration data for port 1 */
7827 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
7828 /* enum: Expansion ROM configuration data for port 2 */
7829 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
7830 /* enum: Expansion ROM configuration data for port 3 */
7831 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
7832 /* enum: Non-volatile log output partition */
7833 #define NVRAM_PARTITION_TYPE_LOG 0x700
7834 /* enum: Non-volatile log output of second core on dual-core device */
7835 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
7836 /* enum: Device state dump output partition */
7837 #define NVRAM_PARTITION_TYPE_DUMP 0x800
7838 /* enum: Application license key storage partition */
7839 #define NVRAM_PARTITION_TYPE_LICENSE 0x900
7840 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
7841 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
7842 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
7843 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
7844 /* enum: Primary FPGA partition */
7845 #define NVRAM_PARTITION_TYPE_FPGA 0xb00
7846 /* enum: Secondary FPGA partition */
7847 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
7848 /* enum: FC firmware partition */
7849 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
7850 /* enum: FC License partition */
7851 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
7852 /* enum: Non-volatile log output partition for FC */
7853 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
7854 /* enum: MUM firmware partition */
7855 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
7856 /* enum: MUM Non-volatile log output partition. */
7857 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
7858 /* enum: MUM Application table partition. */
7859 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
7860 /* enum: MUM boot rom partition. */
7861 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
7862 /* enum: MUM production signatures & calibration rom partition. */
7863 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
7864 /* enum: MUM user signatures & calibration rom partition. */
7865 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
7866 /* enum: MUM fuses and lockbits partition. */
7867 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
7868 /* enum: UEFI expansion ROM if separate from PXE */
7869 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
7870 /* enum: Spare partition 0 */
7871 #define NVRAM_PARTITION_TYPE_SPARE_0 0x1000
7872 /* enum: Spare partition 1 */
7873 #define NVRAM_PARTITION_TYPE_SPARE_1 0x1100
7874 /* enum: Spare partition 2 */
7875 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
7876 /* enum: Manufacturing partition. Used during manufacture to pass information
7877 * between XJTAG and Manftest.
7879 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
7880 /* enum: Spare partition 4 */
7881 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
7882 /* enum: Spare partition 5 */
7883 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
7884 /* enum: Start of reserved value range (firmware may use for any purpose) */
7885 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
7886 /* enum: End of reserved value range (firmware may use for any purpose) */
7887 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
7888 /* enum: Recovery partition map (provided if real map is missing or corrupt) */
7889 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
7890 /* enum: Partition map (real map as stored in flash) */
7891 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
7892 #define NVRAM_PARTITION_TYPE_ID_LBN 0
7893 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16
7895 /* LICENSED_APP_ID structuredef */
7896 #define LICENSED_APP_ID_LEN 4
7897 #define LICENSED_APP_ID_ID_OFST 0
7898 /* enum: OpenOnload */
7899 #define LICENSED_APP_ID_ONLOAD 0x1
7900 /* enum: PTP timestamping */
7901 #define LICENSED_APP_ID_PTP 0x2
7902 /* enum: SolarCapture Pro */
7903 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
7904 /* enum: SolarSecure filter engine */
7905 #define LICENSED_APP_ID_SOLARSECURE 0x8
7906 /* enum: Performance monitor */
7907 #define LICENSED_APP_ID_PERF_MONITOR 0x10
7908 /* enum: SolarCapture Live */
7909 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
7910 /* enum: Capture SolarSystem */
7911 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
7912 /* enum: Network Access Control */
7913 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
7914 /* enum: TCP Direct */
7915 #define LICENSED_APP_ID_TCP_DIRECT 0x100
7916 #define LICENSED_APP_ID_ID_LBN 0
7917 #define LICENSED_APP_ID_ID_WIDTH 32
7919 /* LICENSED_FEATURES structuredef */
7920 #define LICENSED_FEATURES_LEN 8
7921 /* Bitmask of licensed firmware features */
7922 #define LICENSED_FEATURES_MASK_OFST 0
7923 #define LICENSED_FEATURES_MASK_LEN 8
7924 #define LICENSED_FEATURES_MASK_LO_OFST 0
7925 #define LICENSED_FEATURES_MASK_HI_OFST 4
7926 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
7927 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
7928 #define LICENSED_FEATURES_PIO_LBN 1
7929 #define LICENSED_FEATURES_PIO_WIDTH 1
7930 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2
7931 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1
7932 #define LICENSED_FEATURES_CLOCK_LBN 3
7933 #define LICENSED_FEATURES_CLOCK_WIDTH 1
7934 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
7935 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1
7936 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5
7937 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1
7938 #define LICENSED_FEATURES_RX_SNIFF_LBN 6
7939 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1
7940 #define LICENSED_FEATURES_TX_SNIFF_LBN 7
7941 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1
7942 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8
7943 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1
7944 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9
7945 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
7946 #define LICENSED_FEATURES_MASK_LBN 0
7947 #define LICENSED_FEATURES_MASK_WIDTH 64
7949 /* LICENSED_V3_APPS structuredef */
7950 #define LICENSED_V3_APPS_LEN 8
7951 /* Bitmask of licensed applications */
7952 #define LICENSED_V3_APPS_MASK_OFST 0
7953 #define LICENSED_V3_APPS_MASK_LEN 8
7954 #define LICENSED_V3_APPS_MASK_LO_OFST 0
7955 #define LICENSED_V3_APPS_MASK_HI_OFST 4
7956 #define LICENSED_V3_APPS_ONLOAD_LBN 0
7957 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1
7958 #define LICENSED_V3_APPS_PTP_LBN 1
7959 #define LICENSED_V3_APPS_PTP_WIDTH 1
7960 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2
7961 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1
7962 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3
7963 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1
7964 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4
7965 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1
7966 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5
7967 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1
7968 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6
7969 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1
7970 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7
7971 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1
7972 #define LICENSED_V3_APPS_TCP_DIRECT_LBN 8
7973 #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1
7974 #define LICENSED_V3_APPS_LOW_LATENCY_LBN 9
7975 #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1
7976 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10
7977 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1
7978 #define LICENSED_V3_APPS_MASK_LBN 0
7979 #define LICENSED_V3_APPS_MASK_WIDTH 64
7981 /* LICENSED_V3_FEATURES structuredef */
7982 #define LICENSED_V3_FEATURES_LEN 8
7983 /* Bitmask of licensed firmware features */
7984 #define LICENSED_V3_FEATURES_MASK_OFST 0
7985 #define LICENSED_V3_FEATURES_MASK_LEN 8
7986 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0
7987 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4
7988 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
7989 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
7990 #define LICENSED_V3_FEATURES_PIO_LBN 1
7991 #define LICENSED_V3_FEATURES_PIO_WIDTH 1
7992 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2
7993 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1
7994 #define LICENSED_V3_FEATURES_CLOCK_LBN 3
7995 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1
7996 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
7997 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1
7998 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5
7999 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1
8000 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6
8001 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1
8002 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7
8003 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1
8004 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8
8005 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1
8006 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9
8007 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
8008 #define LICENSED_V3_FEATURES_MASK_LBN 0
8009 #define LICENSED_V3_FEATURES_MASK_WIDTH 64
8011 /* TX_TIMESTAMP_EVENT structuredef */
8012 #define TX_TIMESTAMP_EVENT_LEN 6
8013 /* lower 16 bits of timestamp data */
8014 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
8015 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2
8016 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
8017 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16
8018 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp
8020 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3
8021 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1
8022 /* enum: This is a TX completion event, not a timestamp */
8023 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
8024 /* enum: This is the low part of a TX timestamp event */
8025 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
8026 /* enum: This is the high part of a TX timestamp event */
8027 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
8028 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24
8029 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8
8030 /* upper 16 bits of timestamp data */
8031 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
8032 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2
8033 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32
8034 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16
8036 /* RSS_MODE structuredef */
8037 #define RSS_MODE_LEN 1
8038 /* The RSS mode for a particular packet type is a value from 0 - 15 which can
8039 * be considered as 4 bits selecting which fields are included in the hash. (A
8040 * value 0 effectively disables RSS spreading for the packet type.) The YAML
8041 * generation tools require this structure to be a whole number of bytes wide,
8042 * but only 4 bits are relevant.
8044 #define RSS_MODE_HASH_SELECTOR_OFST 0
8045 #define RSS_MODE_HASH_SELECTOR_LEN 1
8046 #define RSS_MODE_HASH_SRC_ADDR_LBN 0
8047 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1
8048 #define RSS_MODE_HASH_DST_ADDR_LBN 1
8049 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1
8050 #define RSS_MODE_HASH_SRC_PORT_LBN 2
8051 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1
8052 #define RSS_MODE_HASH_DST_PORT_LBN 3
8053 #define RSS_MODE_HASH_DST_PORT_WIDTH 1
8054 #define RSS_MODE_HASH_SELECTOR_LBN 0
8055 #define RSS_MODE_HASH_SELECTOR_WIDTH 8
8058 /***********************************/
8060 * Get a dump of the MCPU registers
8062 #define MC_CMD_READ_REGS 0x50
8063 #undef MC_CMD_0x50_PRIVILEGE_CTG
8065 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8067 /* MC_CMD_READ_REGS_IN msgrequest */
8068 #define MC_CMD_READ_REGS_IN_LEN 0
8070 /* MC_CMD_READ_REGS_OUT msgresponse */
8071 #define MC_CMD_READ_REGS_OUT_LEN 308
8072 /* Whether the corresponding register entry contains a valid value */
8073 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0
8074 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16
8075 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
8078 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16
8079 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4
8080 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73
8083 /***********************************/
8085 * Set up an event queue according to the supplied parameters. The IN arguments
8086 * end with an address for each 4k of host memory required to back the EVQ.
8088 #define MC_CMD_INIT_EVQ 0x80
8089 #undef MC_CMD_0x80_PRIVILEGE_CTG
8091 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8093 /* MC_CMD_INIT_EVQ_IN msgrequest */
8094 #define MC_CMD_INIT_EVQ_IN_LENMIN 44
8095 #define MC_CMD_INIT_EVQ_IN_LENMAX 548
8096 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
8097 /* Size, in entries */
8098 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
8099 /* Desired instance. Must be set to a specific instance, which is a function
8100 * local queue index.
8102 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
8103 /* The initial timer value. The load value is ignored if the timer mode is DIS.
8105 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
8106 /* The reload value is ignored in one-shot modes */
8107 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
8109 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
8110 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
8111 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
8112 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
8113 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
8114 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2
8115 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
8116 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3
8117 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
8118 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
8119 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
8120 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5
8121 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
8122 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6
8123 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1
8124 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
8125 /* enum: Disabled */
8126 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
8127 /* enum: Immediate */
8128 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
8129 /* enum: Triggered */
8130 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
8131 /* enum: Hold-off */
8132 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
8133 /* Target EVQ for wakeups if in wakeup mode. */
8134 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
8135 /* Target interrupt if in interrupting mode (note union with target EVQ). Use
8136 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
8139 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
8140 /* Event Counter Mode. */
8141 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28
8142 /* enum: Disabled */
8143 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
8144 /* enum: Disabled */
8145 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
8146 /* enum: Disabled */
8147 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
8148 /* enum: Disabled */
8149 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
8150 /* Event queue packet count threshold. */
8151 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32
8152 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8153 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
8154 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
8155 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
8156 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
8157 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
8158 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
8160 /* MC_CMD_INIT_EVQ_OUT msgresponse */
8161 #define MC_CMD_INIT_EVQ_OUT_LEN 4
8162 /* Only valid if INTRFLAG was true */
8163 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
8165 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */
8166 #define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44
8167 #define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548
8168 #define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))
8169 /* Size, in entries */
8170 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
8171 /* Desired instance. Must be set to a specific instance, which is a function
8172 * local queue index.
8174 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
8175 /* The initial timer value. The load value is ignored if the timer mode is DIS.
8177 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8
8178 /* The reload value is ignored in one-shot modes */
8179 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12
8181 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16
8182 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
8183 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1
8184 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1
8185 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1
8186 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2
8187 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1
8188 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3
8189 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1
8190 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
8191 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1
8192 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5
8193 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1
8194 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6
8195 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1
8196 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7
8197 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
8198 /* enum: All initialisation flags specified by host. */
8199 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
8200 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
8201 * over-ridden by firmware based on licenses and firmware variant in order to
8202 * provide the lowest latency achievable. See
8203 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
8205 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
8206 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
8207 * over-ridden by firmware based on licenses and firmware variant in order to
8208 * provide the best throughput achievable. See
8209 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
8211 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
8212 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
8213 * firmware based on licenses and firmware variant. See
8214 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
8216 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
8217 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20
8218 /* enum: Disabled */
8219 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
8220 /* enum: Immediate */
8221 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
8222 /* enum: Triggered */
8223 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
8224 /* enum: Hold-off */
8225 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
8226 /* Target EVQ for wakeups if in wakeup mode. */
8227 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24
8228 /* Target interrupt if in interrupting mode (note union with target EVQ). Use
8229 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
8232 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24
8233 /* Event Counter Mode. */
8234 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28
8235 /* enum: Disabled */
8236 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
8237 /* enum: Disabled */
8238 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
8239 /* enum: Disabled */
8240 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
8241 /* enum: Disabled */
8242 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
8243 /* Event queue packet count threshold. */
8244 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32
8245 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8246 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36
8247 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8
8248 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36
8249 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
8250 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
8251 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
8253 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */
8254 #define MC_CMD_INIT_EVQ_V2_OUT_LEN 8
8255 /* Only valid if INTRFLAG was true */
8256 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
8257 /* Actual configuration applied on the card */
8258 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
8259 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
8260 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1
8261 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1
8262 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1
8263 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2
8264 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1
8265 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3
8266 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
8268 /* QUEUE_CRC_MODE structuredef */
8269 #define QUEUE_CRC_MODE_LEN 1
8270 #define QUEUE_CRC_MODE_MODE_LBN 0
8271 #define QUEUE_CRC_MODE_MODE_WIDTH 4
8273 #define QUEUE_CRC_MODE_NONE 0x0
8274 /* enum: CRC Fiber channel over ethernet. */
8275 #define QUEUE_CRC_MODE_FCOE 0x1
8276 /* enum: CRC (digest) iSCSI header only. */
8277 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2
8278 /* enum: CRC (digest) iSCSI header and payload. */
8279 #define QUEUE_CRC_MODE_ISCSI 0x3
8280 /* enum: CRC Fiber channel over IP over ethernet. */
8281 #define QUEUE_CRC_MODE_FCOIPOE 0x4
8282 /* enum: CRC MPA. */
8283 #define QUEUE_CRC_MODE_MPA 0x5
8284 #define QUEUE_CRC_MODE_SPARE_LBN 4
8285 #define QUEUE_CRC_MODE_SPARE_WIDTH 4
8288 /***********************************/
8290 * set up a receive queue according to the supplied parameters. The IN
8291 * arguments end with an address for each 4k of host memory required to back
8294 #define MC_CMD_INIT_RXQ 0x81
8295 #undef MC_CMD_0x81_PRIVILEGE_CTG
8297 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8299 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version
8302 #define MC_CMD_INIT_RXQ_IN_LENMIN 36
8303 #define MC_CMD_INIT_RXQ_IN_LENMAX 252
8304 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
8305 /* Size, in entries */
8306 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
8307 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ
8309 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
8310 /* The value to put in the event data. Check hardware spec. for valid range. */
8311 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
8312 /* Desired instance. Must be set to a specific instance, which is a function
8313 * local queue index.
8315 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
8316 /* There will be more flags here. */
8317 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
8318 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
8319 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
8320 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
8321 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
8322 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2
8323 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
8324 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
8325 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
8326 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7
8327 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
8328 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8
8329 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
8330 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9
8331 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
8332 #define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10
8333 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1
8334 /* Owner ID to use if in buffer mode (zero if physical) */
8335 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
8336 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
8337 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24
8338 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8339 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
8340 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
8341 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
8342 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
8343 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
8344 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
8346 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode
8349 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544
8350 /* Size, in entries */
8351 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
8352 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ
8354 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
8355 /* The value to put in the event data. Check hardware spec. for valid range. */
8356 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
8357 /* Desired instance. Must be set to a specific instance, which is a function
8358 * local queue index.
8360 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12
8361 /* There will be more flags here. */
8362 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16
8363 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
8364 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
8365 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1
8366 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1
8367 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2
8368 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
8369 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3
8370 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
8371 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7
8372 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1
8373 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8
8374 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1
8375 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9
8376 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1
8377 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10
8378 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
8379 /* enum: One packet per descriptor (for normal networking) */
8380 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
8381 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */
8382 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
8383 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14
8384 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
8385 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
8386 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
8387 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
8388 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
8389 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
8390 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
8391 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
8392 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
8393 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
8394 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19
8395 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
8396 /* Owner ID to use if in buffer mode (zero if physical) */
8397 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20
8398 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
8399 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24
8400 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8401 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28
8402 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8
8403 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28
8404 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32
8405 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64
8406 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
8407 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
8409 /* MC_CMD_INIT_RXQ_OUT msgresponse */
8410 #define MC_CMD_INIT_RXQ_OUT_LEN 0
8412 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */
8413 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
8416 /***********************************/
8419 #define MC_CMD_INIT_TXQ 0x82
8420 #undef MC_CMD_0x82_PRIVILEGE_CTG
8422 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8424 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version
8427 #define MC_CMD_INIT_TXQ_IN_LENMIN 36
8428 #define MC_CMD_INIT_TXQ_IN_LENMAX 252
8429 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
8430 /* Size, in entries */
8431 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
8432 /* The EVQ to send events to. This is an index originally specified to
8435 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
8436 /* The value to put in the event data. Check hardware spec. for valid range. */
8437 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
8438 /* Desired instance. Must be set to a specific instance, which is a function
8439 * local queue index.
8441 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
8442 /* There will be more flags here. */
8443 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
8444 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
8445 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
8446 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
8447 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
8448 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
8449 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
8450 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
8451 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
8452 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
8453 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
8454 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8
8455 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
8456 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9
8457 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
8458 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
8459 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
8460 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
8461 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
8462 /* Owner ID to use if in buffer mode (zero if physical) */
8463 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
8464 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
8465 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24
8466 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8467 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
8468 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
8469 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
8470 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
8471 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
8472 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
8474 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode
8477 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544
8478 /* Size, in entries */
8479 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
8480 /* The EVQ to send events to. This is an index originally specified to
8483 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
8484 /* The value to put in the event data. Check hardware spec. for valid range. */
8485 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8
8486 /* Desired instance. Must be set to a specific instance, which is a function
8487 * local queue index.
8489 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12
8490 /* There will be more flags here. */
8491 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16
8492 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
8493 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
8494 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1
8495 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1
8496 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2
8497 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
8498 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3
8499 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
8500 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
8501 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
8502 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8
8503 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
8504 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9
8505 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1
8506 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
8507 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
8508 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
8509 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
8510 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12
8511 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1
8512 /* Owner ID to use if in buffer mode (zero if physical) */
8513 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20
8514 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
8515 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24
8516 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8517 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28
8518 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8
8519 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28
8520 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
8521 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1
8522 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
8523 /* Flags related to Qbb flow control mode. */
8524 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540
8525 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
8526 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1
8527 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1
8528 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3
8530 /* MC_CMD_INIT_TXQ_OUT msgresponse */
8531 #define MC_CMD_INIT_TXQ_OUT_LEN 0
8534 /***********************************/
8538 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first
8539 * or the operation will fail with EBUSY
8541 #define MC_CMD_FINI_EVQ 0x83
8542 #undef MC_CMD_0x83_PRIVILEGE_CTG
8544 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8546 /* MC_CMD_FINI_EVQ_IN msgrequest */
8547 #define MC_CMD_FINI_EVQ_IN_LEN 4
8548 /* Instance of EVQ to destroy. Should be the same instance as that previously
8549 * passed to INIT_EVQ
8551 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
8553 /* MC_CMD_FINI_EVQ_OUT msgresponse */
8554 #define MC_CMD_FINI_EVQ_OUT_LEN 0
8557 /***********************************/
8561 #define MC_CMD_FINI_RXQ 0x84
8562 #undef MC_CMD_0x84_PRIVILEGE_CTG
8564 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8566 /* MC_CMD_FINI_RXQ_IN msgrequest */
8567 #define MC_CMD_FINI_RXQ_IN_LEN 4
8568 /* Instance of RXQ to destroy */
8569 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
8571 /* MC_CMD_FINI_RXQ_OUT msgresponse */
8572 #define MC_CMD_FINI_RXQ_OUT_LEN 0
8575 /***********************************/
8579 #define MC_CMD_FINI_TXQ 0x85
8580 #undef MC_CMD_0x85_PRIVILEGE_CTG
8582 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8584 /* MC_CMD_FINI_TXQ_IN msgrequest */
8585 #define MC_CMD_FINI_TXQ_IN_LEN 4
8586 /* Instance of TXQ to destroy */
8587 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
8589 /* MC_CMD_FINI_TXQ_OUT msgresponse */
8590 #define MC_CMD_FINI_TXQ_OUT_LEN 0
8593 /***********************************/
8594 /* MC_CMD_DRIVER_EVENT
8595 * Generate an event on an EVQ belonging to the function issuing the command.
8597 #define MC_CMD_DRIVER_EVENT 0x86
8598 #undef MC_CMD_0x86_PRIVILEGE_CTG
8600 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8602 /* MC_CMD_DRIVER_EVENT_IN msgrequest */
8603 #define MC_CMD_DRIVER_EVENT_IN_LEN 12
8604 /* Handle of target EVQ */
8605 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
8606 /* Bits 0 - 63 of event */
8607 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
8608 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
8609 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
8610 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
8612 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */
8613 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0
8616 /***********************************/
8618 * Execute an arbitrary MCDI command on behalf of a different function, subject
8619 * to security restrictions. The command to be proxied follows immediately
8620 * afterward in the host buffer (or on the UART). This command supercedes
8621 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
8623 #define MC_CMD_PROXY_CMD 0x5b
8624 #undef MC_CMD_0x5b_PRIVILEGE_CTG
8626 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8628 /* MC_CMD_PROXY_CMD_IN msgrequest */
8629 #define MC_CMD_PROXY_CMD_IN_LEN 4
8630 /* The handle of the target function. */
8631 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
8632 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
8633 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16
8634 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16
8635 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16
8636 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
8638 /* MC_CMD_PROXY_CMD_OUT msgresponse */
8639 #define MC_CMD_PROXY_CMD_OUT_LEN 0
8641 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to
8642 * manage proxied requests
8644 #define MC_PROXY_STATUS_BUFFER_LEN 16
8645 /* Handle allocated by the firmware for this proxy transaction */
8646 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0
8647 /* enum: An invalid handle. */
8648 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0
8649 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0
8650 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32
8651 /* The requesting physical function number */
8652 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4
8653 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2
8654 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32
8655 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16
8656 /* The requesting virtual function number. Set to VF_NULL if the target is a
8659 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6
8660 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2
8661 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48
8662 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16
8663 /* The target function RID. */
8664 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8
8665 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2
8666 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64
8667 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16
8668 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */
8669 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10
8670 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2
8671 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80
8672 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16
8673 /* If a request is authorized rather than carried out by the host, this is the
8674 * elevated privilege mask granted to the requesting function.
8676 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12
8677 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96
8678 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32
8681 /***********************************/
8682 /* MC_CMD_PROXY_CONFIGURE
8683 * Enable/disable authorization of MCDI requests from unprivileged functions by
8684 * a designated admin function
8686 #define MC_CMD_PROXY_CONFIGURE 0x58
8687 #undef MC_CMD_0x58_PRIVILEGE_CTG
8689 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8691 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */
8692 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108
8693 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0
8694 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0
8695 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1
8696 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
8697 * of blocks, each of the size REQUEST_BLOCK_SIZE.
8699 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4
8700 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8
8701 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4
8702 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8
8703 /* Must be a power of 2 */
8704 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12
8705 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
8706 * of blocks, each of the size REPLY_BLOCK_SIZE.
8708 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16
8709 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8
8710 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16
8711 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20
8712 /* Must be a power of 2 */
8713 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24
8714 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
8715 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if
8716 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.
8718 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28
8719 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8
8720 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28
8721 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32
8722 /* Must be a power of 2, or zero if this buffer is not provided */
8723 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36
8724 /* Applies to all three buffers */
8725 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40
8726 /* A bit mask defining which MCDI operations may be proxied */
8727 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44
8728 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64
8730 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */
8731 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112
8732 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0
8733 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0
8734 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1
8735 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
8736 * of blocks, each of the size REQUEST_BLOCK_SIZE.
8738 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4
8739 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8
8740 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4
8741 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8
8742 /* Must be a power of 2 */
8743 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12
8744 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
8745 * of blocks, each of the size REPLY_BLOCK_SIZE.
8747 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16
8748 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8
8749 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16
8750 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20
8751 /* Must be a power of 2 */
8752 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24
8753 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
8754 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if
8755 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.
8757 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28
8758 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8
8759 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28
8760 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32
8761 /* Must be a power of 2, or zero if this buffer is not provided */
8762 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36
8763 /* Applies to all three buffers */
8764 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40
8765 /* A bit mask defining which MCDI operations may be proxied */
8766 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44
8767 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64
8768 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108
8770 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */
8771 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0
8774 /***********************************/
8775 /* MC_CMD_PROXY_COMPLETE
8776 * Tells FW that a requested proxy operation has either been completed (by
8777 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the
8778 * function that enabled proxying/authorization (by using
8779 * MC_CMD_PROXY_CONFIGURE).
8781 #define MC_CMD_PROXY_COMPLETE 0x5f
8782 #undef MC_CMD_0x5f_PRIVILEGE_CTG
8784 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8786 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */
8787 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12
8788 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0
8789 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4
8790 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply
8791 * is stored in the REPLY_BUFF.
8793 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0
8794 /* enum: The operation has been authorized. The originating function may now
8797 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1
8798 /* enum: The operation has been declined. */
8799 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2
8800 /* enum: The authorization failed because the relevant application did not
8803 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3
8804 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8
8806 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */
8807 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0
8810 /***********************************/
8811 /* MC_CMD_ALLOC_BUFTBL_CHUNK
8812 * Allocate a set of buffer table entries using the specified owner ID. This
8813 * operation allocates the required buffer table entries (and fails if it
8814 * cannot do so). The buffer table entries will initially be zeroed.
8816 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
8817 #undef MC_CMD_0x87_PRIVILEGE_CTG
8819 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
8821 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */
8822 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8
8823 /* Owner ID to use */
8824 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
8825 /* Size of buffer table pages to use, in bytes (note that only a few values are
8826 * legal on any specific hardware).
8828 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
8830 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */
8831 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12
8832 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
8833 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
8834 /* Buffer table IDs for use in DMA descriptors. */
8835 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8
8838 /***********************************/
8839 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES
8840 * Reprogram a set of buffer table entries in the specified chunk.
8842 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
8843 #undef MC_CMD_0x88_PRIVILEGE_CTG
8845 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
8847 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */
8848 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20
8849 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268
8850 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
8851 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
8853 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
8855 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8
8856 /* Buffer table entry address */
8857 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
8858 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
8859 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
8860 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
8861 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
8862 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32
8864 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */
8865 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
8868 /***********************************/
8869 /* MC_CMD_FREE_BUFTBL_CHUNK
8871 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89
8872 #undef MC_CMD_0x89_PRIVILEGE_CTG
8874 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
8876 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */
8877 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
8878 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
8880 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */
8881 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
8883 /* PORT_CONFIG_ENTRY structuredef */
8884 #define PORT_CONFIG_ENTRY_LEN 16
8885 /* External port number (label) */
8886 #define PORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0
8887 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1
8888 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0
8889 #define PORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8
8890 /* Port core location */
8891 #define PORT_CONFIG_ENTRY_CORE_OFST 1
8892 #define PORT_CONFIG_ENTRY_CORE_LEN 1
8893 #define PORT_CONFIG_ENTRY_STANDALONE 0x0 /* enum */
8894 #define PORT_CONFIG_ENTRY_MASTER 0x1 /* enum */
8895 #define PORT_CONFIG_ENTRY_SLAVE 0x2 /* enum */
8896 #define PORT_CONFIG_ENTRY_CORE_LBN 8
8897 #define PORT_CONFIG_ENTRY_CORE_WIDTH 8
8898 /* Internal number (HW resource) relative to the core */
8899 #define PORT_CONFIG_ENTRY_INT_NUMBER_OFST 2
8900 #define PORT_CONFIG_ENTRY_INT_NUMBER_LEN 1
8901 #define PORT_CONFIG_ENTRY_INT_NUMBER_LBN 16
8902 #define PORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8
8904 #define PORT_CONFIG_ENTRY_RSVD_OFST 3
8905 #define PORT_CONFIG_ENTRY_RSVD_LEN 1
8906 #define PORT_CONFIG_ENTRY_RSVD_LBN 24
8907 #define PORT_CONFIG_ENTRY_RSVD_WIDTH 8
8908 /* Bitmask of KR lanes used by the port */
8909 #define PORT_CONFIG_ENTRY_LANES_OFST 4
8910 #define PORT_CONFIG_ENTRY_LANES_LBN 32
8911 #define PORT_CONFIG_ENTRY_LANES_WIDTH 32
8912 /* Port capabilities (MC_CMD_PHY_CAP_*) */
8913 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8
8914 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64
8915 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32
8916 /* Reserved (align to 16 bytes) */
8917 #define PORT_CONFIG_ENTRY_RSVD2_OFST 12
8918 #define PORT_CONFIG_ENTRY_RSVD2_LBN 96
8919 #define PORT_CONFIG_ENTRY_RSVD2_WIDTH 32
8922 /***********************************/
8924 * Multiplexed MCDI call for filter operations
8926 #define MC_CMD_FILTER_OP 0x8a
8927 #undef MC_CMD_0x8a_PRIVILEGE_CTG
8929 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8931 /* MC_CMD_FILTER_OP_IN msgrequest */
8932 #define MC_CMD_FILTER_OP_IN_LEN 108
8933 /* identifies the type of operation requested */
8934 #define MC_CMD_FILTER_OP_IN_OP_OFST 0
8935 /* enum: single-recipient filter insert */
8936 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
8937 /* enum: single-recipient filter remove */
8938 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
8939 /* enum: multi-recipient filter subscribe */
8940 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
8941 /* enum: multi-recipient filter unsubscribe */
8942 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
8943 /* enum: replace one recipient with another (warning - the filter handle may
8946 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
8947 /* filter handle (for remove / unsubscribe operations) */
8948 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
8949 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
8950 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
8951 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
8952 /* The port ID associated with the v-adaptor which should contain this filter.
8954 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
8955 /* fields to include in match criteria */
8956 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16
8957 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
8958 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
8959 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
8960 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
8961 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
8962 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
8963 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
8964 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
8965 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
8966 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
8967 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
8968 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
8969 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
8970 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
8971 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
8972 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
8973 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
8974 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
8975 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
8976 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
8977 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
8978 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
8979 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
8980 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
8981 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
8982 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
8983 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
8984 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
8985 /* receive destination */
8986 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20
8987 /* enum: drop packets */
8988 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
8989 /* enum: receive to host */
8990 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
8991 /* enum: receive to MC */
8992 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
8993 /* enum: loop back to TXDP 0 */
8994 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
8995 /* enum: loop back to TXDP 1 */
8996 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
8997 /* receive queue handle (for multiple queue modes, this is the base queue) */
8998 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24
9000 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28
9001 /* enum: receive to just the specified queue */
9002 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
9003 /* enum: receive to multiple queues using RSS context */
9004 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
9005 /* enum: receive to multiple queues using .1p mapping */
9006 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
9007 /* enum: install a filter entry that will never match; for test purposes only
9009 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
9010 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
9011 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
9012 * MC_CMD_DOT1P_MAPPING_ALLOC.
9014 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32
9015 /* transmit domain (reserved; set to 0) */
9016 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36
9017 /* transmit destination (either set the MAC and/or PM bits for explicit
9018 * control, or set this field to TX_DEST_DEFAULT for sensible default
9021 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40
9022 /* enum: request default behaviour (based on filter type) */
9023 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
9024 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
9025 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
9026 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
9027 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
9028 /* source MAC address to match (as bytes in network order) */
9029 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44
9030 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
9031 /* source port to match (as bytes in network order) */
9032 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50
9033 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
9034 /* destination MAC address to match (as bytes in network order) */
9035 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52
9036 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
9037 /* destination port to match (as bytes in network order) */
9038 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58
9039 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
9040 /* Ethernet type to match (as bytes in network order) */
9041 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60
9042 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
9043 /* Inner VLAN tag to match (as bytes in network order) */
9044 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62
9045 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
9046 /* Outer VLAN tag to match (as bytes in network order) */
9047 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64
9048 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
9049 /* IP protocol to match (in low byte; set high byte to 0) */
9050 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66
9051 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
9052 /* Firmware defined register 0 to match (reserved; set to 0) */
9053 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68
9054 /* Firmware defined register 1 to match (reserved; set to 0) */
9055 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72
9056 /* source IP address to match (as bytes in network order; set last 12 bytes to
9057 * 0 for IPv4 address)
9059 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76
9060 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
9061 /* destination IP address to match (as bytes in network order; set last 12
9062 * bytes to 0 for IPv4 address)
9064 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92
9065 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
9067 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to
9068 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is
9069 * supported on Medford only).
9071 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172
9072 /* identifies the type of operation requested */
9073 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
9074 /* Enum values, see field(s): */
9075 /* MC_CMD_FILTER_OP_IN/OP */
9076 /* filter handle (for remove / unsubscribe operations) */
9077 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
9078 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8
9079 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
9080 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8
9081 /* The port ID associated with the v-adaptor which should contain this filter.
9083 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12
9084 /* fields to include in match criteria */
9085 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16
9086 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
9087 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1
9088 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1
9089 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1
9090 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2
9091 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1
9092 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3
9093 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1
9094 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
9095 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1
9096 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5
9097 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1
9098 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6
9099 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1
9100 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7
9101 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1
9102 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8
9103 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1
9104 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9
9105 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1
9106 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10
9107 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1
9108 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11
9109 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1
9110 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12
9111 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1
9112 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13
9113 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1
9114 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14
9115 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
9116 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15
9117 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
9118 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16
9119 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1
9120 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17
9121 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1
9122 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
9123 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
9124 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19
9125 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
9126 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
9127 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
9128 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21
9129 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
9130 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22
9131 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1
9132 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23
9133 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1
9134 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
9135 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
9136 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
9137 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
9138 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
9139 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
9140 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
9141 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
9142 /* receive destination */
9143 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20
9144 /* enum: drop packets */
9145 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
9146 /* enum: receive to host */
9147 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
9148 /* enum: receive to MC */
9149 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
9150 /* enum: loop back to TXDP 0 */
9151 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
9152 /* enum: loop back to TXDP 1 */
9153 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
9154 /* receive queue handle (for multiple queue modes, this is the base queue) */
9155 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24
9157 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28
9158 /* enum: receive to just the specified queue */
9159 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
9160 /* enum: receive to multiple queues using RSS context */
9161 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
9162 /* enum: receive to multiple queues using .1p mapping */
9163 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
9164 /* enum: install a filter entry that will never match; for test purposes only
9166 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
9167 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
9168 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
9169 * MC_CMD_DOT1P_MAPPING_ALLOC.
9171 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32
9172 /* transmit domain (reserved; set to 0) */
9173 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36
9174 /* transmit destination (either set the MAC and/or PM bits for explicit
9175 * control, or set this field to TX_DEST_DEFAULT for sensible default
9178 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40
9179 /* enum: request default behaviour (based on filter type) */
9180 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
9181 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
9182 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
9183 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
9184 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1
9185 /* source MAC address to match (as bytes in network order) */
9186 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44
9187 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6
9188 /* source port to match (as bytes in network order) */
9189 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50
9190 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2
9191 /* destination MAC address to match (as bytes in network order) */
9192 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52
9193 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6
9194 /* destination port to match (as bytes in network order) */
9195 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58
9196 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2
9197 /* Ethernet type to match (as bytes in network order) */
9198 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60
9199 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2
9200 /* Inner VLAN tag to match (as bytes in network order) */
9201 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62
9202 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2
9203 /* Outer VLAN tag to match (as bytes in network order) */
9204 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64
9205 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2
9206 /* IP protocol to match (in low byte; set high byte to 0) */
9207 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66
9208 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2
9209 /* Firmware defined register 0 to match (reserved; set to 0) */
9210 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68
9211 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
9212 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
9213 * VXLAN/NVGRE, or 1 for Geneve)
9215 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72
9216 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
9217 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24
9218 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24
9219 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8
9220 /* enum: Match VXLAN traffic with this VNI */
9221 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
9222 /* enum: Match Geneve traffic with this VNI */
9223 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
9224 /* enum: Reserved for experimental development use */
9225 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
9226 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
9227 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24
9228 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24
9229 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8
9230 /* enum: Match NVGRE traffic with this VSID */
9231 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
9232 /* source IP address to match (as bytes in network order; set last 12 bytes to
9233 * 0 for IPv4 address)
9235 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76
9236 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16
9237 /* destination IP address to match (as bytes in network order; set last 12
9238 * bytes to 0 for IPv4 address)
9240 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92
9241 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16
9242 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
9245 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108
9246 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6
9247 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
9248 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114
9249 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2
9250 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
9253 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116
9254 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6
9255 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network
9258 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122
9259 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2
9260 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
9262 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124
9263 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2
9264 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
9266 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126
9267 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2
9268 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
9270 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128
9271 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2
9272 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
9275 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130
9276 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2
9277 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
9280 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132
9281 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
9284 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136
9285 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
9286 * order; set last 12 bytes to 0 for IPv4 address)
9288 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140
9289 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16
9290 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
9291 * order; set last 12 bytes to 0 for IPv4 address)
9293 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156
9294 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16
9296 /* MC_CMD_FILTER_OP_OUT msgresponse */
9297 #define MC_CMD_FILTER_OP_OUT_LEN 12
9298 /* identifies the type of operation requested */
9299 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0
9300 /* Enum values, see field(s): */
9301 /* MC_CMD_FILTER_OP_IN/OP */
9302 /* Returned filter handle (for insert / subscribe operations). Note that these
9303 * handles should be considered opaque to the host, although a value of
9304 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
9306 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
9307 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
9308 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
9309 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
9310 /* enum: guaranteed invalid filter handle (low 32 bits) */
9311 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
9312 /* enum: guaranteed invalid filter handle (high 32 bits) */
9313 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
9315 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */
9316 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12
9317 /* identifies the type of operation requested */
9318 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
9319 /* Enum values, see field(s): */
9320 /* MC_CMD_FILTER_OP_EXT_IN/OP */
9321 /* Returned filter handle (for insert / subscribe operations). Note that these
9322 * handles should be considered opaque to the host, although a value of
9323 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
9325 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
9326 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8
9327 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
9328 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8
9329 /* Enum values, see field(s): */
9330 /* MC_CMD_FILTER_OP_OUT/HANDLE */
9333 /***********************************/
9334 /* MC_CMD_GET_PARSER_DISP_INFO
9335 * Get information related to the parser-dispatcher subsystem
9337 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4
9338 #undef MC_CMD_0xe4_PRIVILEGE_CTG
9340 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9342 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */
9343 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
9344 /* identifies the type of operation requested */
9345 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
9346 /* enum: read the list of supported RX filter matches */
9347 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
9348 /* enum: read flags indicating restrictions on filter insertion for the calling
9351 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
9352 /* enum: read properties relating to security rules (Medford-only; for use by
9353 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
9355 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
9356 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE
9357 * encapsulated frames, which follow a different match sequence to normal
9358 * frames (Medford only)
9360 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
9362 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
9363 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
9364 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252
9365 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
9366 /* identifies the type of operation requested */
9367 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
9368 /* Enum values, see field(s): */
9369 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
9370 /* number of supported match types */
9371 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
9372 /* array of supported match types (valid MATCH_FIELDS values for
9373 * MC_CMD_FILTER_OP) sorted in decreasing priority order
9375 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8
9376 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
9377 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
9378 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61
9380 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */
9381 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8
9382 /* identifies the type of operation requested */
9383 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
9384 /* Enum values, see field(s): */
9385 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
9386 /* bitfield of filter insertion restrictions */
9387 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
9388 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
9389 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1
9391 /* MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT msgresponse:
9392 * GET_PARSER_DISP_INFO response format for OP_GET_SECURITY_RULE_INFO.
9393 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
9394 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
9395 * been used in any released code and may change during development. This note
9396 * will be removed once it is regarded as stable.
9398 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36
9399 /* identifies the type of operation requested */
9400 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0
9401 /* Enum values, see field(s): */
9402 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
9403 /* a version number representing the set of rule lookups that are implemented
9404 * by the currently running firmware
9406 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4
9407 /* enum: implements lookup sequences described in SF-114946-SW draft C */
9408 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0
9409 /* the number of nodes in the subnet map */
9410 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8
9411 /* the number of entries in one subnet map node */
9412 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12
9413 /* minimum valid value for a subnet ID in a subnet map leaf */
9414 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16
9415 /* maximum valid value for a subnet ID in a subnet map leaf */
9416 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20
9417 /* the number of entries in the local and remote port range maps */
9418 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24
9419 /* minimum valid value for a portrange ID in a port range map leaf */
9420 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28
9421 /* maximum valid value for a portrange ID in a port range map leaf */
9422 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32
9425 /***********************************/
9426 /* MC_CMD_PARSER_DISP_RW
9427 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.
9428 * Please note that this interface is only of use to debug tools which have
9429 * knowledge of firmware and hardware data structures; nothing here is intended
9430 * for use by normal driver code.
9432 #define MC_CMD_PARSER_DISP_RW 0xe5
9433 #undef MC_CMD_0xe5_PRIVILEGE_CTG
9435 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9437 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */
9438 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32
9439 /* identifies the target of the operation */
9440 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0
9441 /* enum: RX dispatcher CPU */
9442 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
9443 /* enum: TX dispatcher CPU */
9444 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
9445 /* enum: Lookup engine (with original metadata format) */
9446 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
9447 /* enum: Lookup engine (with requested metadata format) */
9448 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3
9449 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */
9450 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0
9451 /* enum: RX1 dispatcher CPU (only valid for Medford) */
9452 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4
9453 /* enum: Miscellaneous other state (only valid for Medford) */
9454 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5
9455 /* identifies the type of operation requested */
9456 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4
9457 /* enum: read a word of DICPU DMEM or a LUE entry */
9458 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0
9459 /* enum: write a word of DICPU DMEM or a LUE entry */
9460 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
9461 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */
9462 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
9463 /* data memory address (DICPU targets) or LUE index (LUE targets) */
9464 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8
9465 /* selector (for MISC_STATE target) */
9466 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8
9467 /* enum: Port to datapath mapping */
9468 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1
9469 /* value to write (for DMEM writes) */
9470 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12
9471 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */
9472 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12
9473 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */
9474 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16
9475 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */
9476 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12
9477 /* value to write (for LUE writes) */
9478 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12
9479 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20
9481 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */
9482 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52
9483 /* value read (for DMEM reads) */
9484 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0
9485 /* value read (for LUE reads) */
9486 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0
9487 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20
9488 /* up to 8 32-bit words of additional soft state from the LUE manager (the
9489 * exact content is firmware-dependent and intended only for debug use)
9491 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20
9492 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32
9493 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */
9494 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0
9495 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4
9496 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4
9497 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */
9498 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */
9501 /***********************************/
9502 /* MC_CMD_GET_PF_COUNT
9503 * Get number of PFs on the device.
9505 #define MC_CMD_GET_PF_COUNT 0xb6
9506 #undef MC_CMD_0xb6_PRIVILEGE_CTG
9508 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9510 /* MC_CMD_GET_PF_COUNT_IN msgrequest */
9511 #define MC_CMD_GET_PF_COUNT_IN_LEN 0
9513 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */
9514 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1
9515 /* Identifies the number of PFs on the device. */
9516 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
9517 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1
9520 /***********************************/
9521 /* MC_CMD_SET_PF_COUNT
9522 * Set number of PFs on the device.
9524 #define MC_CMD_SET_PF_COUNT 0xb7
9526 /* MC_CMD_SET_PF_COUNT_IN msgrequest */
9527 #define MC_CMD_SET_PF_COUNT_IN_LEN 4
9528 /* New number of PFs on the device. */
9529 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
9531 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */
9532 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0
9535 /***********************************/
9536 /* MC_CMD_GET_PORT_ASSIGNMENT
9537 * Get port assignment for current PCI function.
9539 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
9540 #undef MC_CMD_0xb8_PRIVILEGE_CTG
9542 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9544 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
9545 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
9547 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
9548 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
9549 /* Identifies the port assignment for this function. */
9550 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
9553 /***********************************/
9554 /* MC_CMD_SET_PORT_ASSIGNMENT
9555 * Set port assignment for current PCI function.
9557 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
9558 #undef MC_CMD_0xb9_PRIVILEGE_CTG
9560 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9562 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */
9563 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
9564 /* Identifies the port assignment for this function. */
9565 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
9567 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */
9568 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
9571 /***********************************/
9573 * Allocate VIs for current PCI function.
9575 #define MC_CMD_ALLOC_VIS 0x8b
9576 #undef MC_CMD_0x8b_PRIVILEGE_CTG
9578 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9580 /* MC_CMD_ALLOC_VIS_IN msgrequest */
9581 #define MC_CMD_ALLOC_VIS_IN_LEN 8
9582 /* The minimum number of VIs that is acceptable */
9583 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
9584 /* The maximum number of VIs that would be useful */
9585 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
9587 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
9588 * Use extended version in new code.
9590 #define MC_CMD_ALLOC_VIS_OUT_LEN 8
9591 /* The number of VIs allocated on this function */
9592 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
9593 /* The base absolute VI number allocated to this function. Required to
9594 * correctly interpret wakeup events.
9596 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
9598 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */
9599 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12
9600 /* The number of VIs allocated on this function */
9601 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
9602 /* The base absolute VI number allocated to this function. Required to
9603 * correctly interpret wakeup events.
9605 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
9606 /* Function's port vi_shift value (always 0 on Huntington) */
9607 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8
9610 /***********************************/
9612 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,
9615 #define MC_CMD_FREE_VIS 0x8c
9616 #undef MC_CMD_0x8c_PRIVILEGE_CTG
9618 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9620 /* MC_CMD_FREE_VIS_IN msgrequest */
9621 #define MC_CMD_FREE_VIS_IN_LEN 0
9623 /* MC_CMD_FREE_VIS_OUT msgresponse */
9624 #define MC_CMD_FREE_VIS_OUT_LEN 0
9627 /***********************************/
9628 /* MC_CMD_GET_SRIOV_CFG
9629 * Get SRIOV config for this PF.
9631 #define MC_CMD_GET_SRIOV_CFG 0xba
9632 #undef MC_CMD_0xba_PRIVILEGE_CTG
9634 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9636 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */
9637 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
9639 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */
9640 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20
9641 /* Number of VFs currently enabled. */
9642 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
9643 /* Max number of VFs before sriov stride and offset may need to be changed. */
9644 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
9645 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
9646 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
9647 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
9648 /* RID offset of first VF from PF. */
9649 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12
9650 /* RID offset of each subsequent VF from the previous. */
9651 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16
9654 /***********************************/
9655 /* MC_CMD_SET_SRIOV_CFG
9656 * Set SRIOV config for this PF.
9658 #define MC_CMD_SET_SRIOV_CFG 0xbb
9659 #undef MC_CMD_0xbb_PRIVILEGE_CTG
9661 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9663 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */
9664 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20
9665 /* Number of VFs currently enabled. */
9666 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
9667 /* Max number of VFs before sriov stride and offset may need to be changed. */
9668 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
9669 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8
9670 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
9671 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
9672 /* RID offset of first VF from PF, or 0 for no change, or
9673 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.
9675 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12
9676 /* RID offset of each subsequent VF from the previous, 0 for no change, or
9677 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.
9679 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16
9681 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */
9682 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
9685 /***********************************/
9686 /* MC_CMD_GET_VI_ALLOC_INFO
9687 * Get information about number of VI's and base VI number allocated to this
9690 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d
9691 #undef MC_CMD_0x8d_PRIVILEGE_CTG
9693 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9695 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */
9696 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
9698 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */
9699 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12
9700 /* The number of VIs allocated on this function */
9701 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
9702 /* The base absolute VI number allocated to this function. Required to
9703 * correctly interpret wakeup events.
9705 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
9706 /* Function's port vi_shift value (always 0 on Huntington) */
9707 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8
9710 /***********************************/
9711 /* MC_CMD_DUMP_VI_STATE
9712 * For CmdClient use. Dump pertinent information on a specific absolute VI.
9714 #define MC_CMD_DUMP_VI_STATE 0x8e
9715 #undef MC_CMD_0x8e_PRIVILEGE_CTG
9717 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9719 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */
9720 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4
9721 /* The VI number to query. */
9722 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
9724 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */
9725 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96
9726 /* The PF part of the function owning this VI. */
9727 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
9728 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2
9729 /* The VF part of the function owning this VI. */
9730 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2
9731 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2
9732 /* Base of VIs allocated to this function. */
9733 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
9734 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2
9735 /* Count of VIs allocated to the owner function. */
9736 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6
9737 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2
9738 /* Base interrupt vector allocated to this function. */
9739 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8
9740 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2
9741 /* Number of interrupt vectors allocated to this function. */
9742 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10
9743 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2
9744 /* Raw evq ptr table data. */
9745 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12
9746 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8
9747 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12
9748 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16
9749 /* Raw evq timer table data. */
9750 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20
9751 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8
9752 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20
9753 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24
9754 /* Combined metadata field. */
9755 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
9756 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
9757 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16
9758 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16
9759 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8
9760 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24
9761 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8
9762 /* TXDPCPU raw table data for queue. */
9763 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32
9764 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8
9765 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32
9766 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36
9767 /* TXDPCPU raw table data for queue. */
9768 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40
9769 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8
9770 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40
9771 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44
9772 /* TXDPCPU raw table data for queue. */
9773 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48
9774 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8
9775 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48
9776 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52
9777 /* Combined metadata field. */
9778 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56
9779 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
9780 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
9781 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
9782 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
9783 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
9784 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16
9785 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8
9786 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24
9787 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8
9788 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32
9789 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8
9790 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40
9791 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24
9792 /* RXDPCPU raw table data for queue. */
9793 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64
9794 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8
9795 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64
9796 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68
9797 /* RXDPCPU raw table data for queue. */
9798 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72
9799 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8
9800 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72
9801 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76
9802 /* Reserved, currently 0. */
9803 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80
9804 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8
9805 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80
9806 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84
9807 /* Combined metadata field. */
9808 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88
9809 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
9810 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
9811 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
9812 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
9813 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
9814 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16
9815 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8
9816 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24
9817 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8
9818 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
9819 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
9822 /***********************************/
9823 /* MC_CMD_ALLOC_PIOBUF
9824 * Allocate a push I/O buffer for later use with a tx queue.
9826 #define MC_CMD_ALLOC_PIOBUF 0x8f
9827 #undef MC_CMD_0x8f_PRIVILEGE_CTG
9829 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
9831 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */
9832 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
9834 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */
9835 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
9836 /* Handle for allocated push I/O buffer. */
9837 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
9840 /***********************************/
9841 /* MC_CMD_FREE_PIOBUF
9842 * Free a push I/O buffer.
9844 #define MC_CMD_FREE_PIOBUF 0x90
9845 #undef MC_CMD_0x90_PRIVILEGE_CTG
9847 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
9849 /* MC_CMD_FREE_PIOBUF_IN msgrequest */
9850 #define MC_CMD_FREE_PIOBUF_IN_LEN 4
9851 /* Handle for allocated push I/O buffer. */
9852 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
9854 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */
9855 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0
9858 /***********************************/
9859 /* MC_CMD_GET_VI_TLP_PROCESSING
9860 * Get TLP steering and ordering information for a VI.
9862 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
9863 #undef MC_CMD_0xb0_PRIVILEGE_CTG
9865 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9867 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */
9868 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
9869 /* VI number to get information for. */
9870 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
9872 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */
9873 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4
9874 /* Transaction processing steering hint 1 for use with the Rx Queue. */
9875 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0
9876 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1
9877 /* Transaction processing steering hint 2 for use with the Ev Queue. */
9878 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1
9879 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1
9880 /* Use Relaxed ordering model for TLPs on this VI. */
9881 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16
9882 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1
9883 /* Use ID based ordering for TLPs on this VI. */
9884 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17
9885 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1
9886 /* Set no snoop bit for TLPs on this VI. */
9887 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18
9888 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1
9889 /* Enable TPH for TLPs on this VI. */
9890 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19
9891 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1
9892 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
9895 /***********************************/
9896 /* MC_CMD_SET_VI_TLP_PROCESSING
9897 * Set TLP steering and ordering information for a VI.
9899 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
9900 #undef MC_CMD_0xb1_PRIVILEGE_CTG
9902 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9904 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */
9905 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8
9906 /* VI number to set information for. */
9907 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
9908 /* Transaction processing steering hint 1 for use with the Rx Queue. */
9909 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4
9910 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1
9911 /* Transaction processing steering hint 2 for use with the Ev Queue. */
9912 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5
9913 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1
9914 /* Use Relaxed ordering model for TLPs on this VI. */
9915 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48
9916 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1
9917 /* Use ID based ordering for TLPs on this VI. */
9918 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49
9919 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1
9920 /* Set the no snoop bit for TLPs on this VI. */
9921 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50
9922 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1
9923 /* Enable TPH for TLPs on this VI. */
9924 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51
9925 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1
9926 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
9928 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */
9929 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
9932 /***********************************/
9933 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS
9934 * Get global PCIe steering and transaction processing configuration.
9936 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
9937 #undef MC_CMD_0xbc_PRIVILEGE_CTG
9939 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9941 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */
9942 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4
9943 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
9945 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
9947 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
9949 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
9950 /* enum: TPH Type. */
9951 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
9953 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
9954 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8
9955 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0
9956 /* Enum values, see field(s): */
9957 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
9958 /* Amalgamated TLP info word. */
9959 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4
9960 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
9961 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
9962 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
9963 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31
9964 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
9965 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
9966 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1
9967 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1
9968 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2
9969 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1
9970 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3
9971 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
9972 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
9973 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28
9974 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
9975 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
9976 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1
9977 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1
9978 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2
9979 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
9980 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3
9981 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29
9982 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
9983 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
9984 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2
9985 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2
9986 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4
9987 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2
9988 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6
9989 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2
9990 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8
9991 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2
9992 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9
9993 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23
9996 /***********************************/
9997 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS
9998 * Set global PCIe steering and transaction processing configuration.
10000 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
10001 #undef MC_CMD_0xbd_PRIVILEGE_CTG
10003 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
10005 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */
10006 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8
10007 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
10008 /* Enum values, see field(s): */
10009 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
10010 /* Amalgamated TLP info word. */
10011 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4
10012 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0
10013 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1
10014 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0
10015 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1
10016 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1
10017 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1
10018 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2
10019 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1
10020 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3
10021 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1
10022 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0
10023 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1
10024 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1
10025 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1
10026 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2
10027 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1
10028 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0
10029 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
10030 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2
10031 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2
10032 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4
10033 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2
10034 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6
10035 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2
10036 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8
10037 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2
10038 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10
10039 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22
10041 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
10042 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
10045 /***********************************/
10046 /* MC_CMD_SATELLITE_DOWNLOAD
10047 * Download a new set of images to the satellite CPUs from the host.
10049 #define MC_CMD_SATELLITE_DOWNLOAD 0x91
10050 #undef MC_CMD_0x91_PRIVILEGE_CTG
10052 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN
10054 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs
10055 * are subtle, and so downloads must proceed in a number of phases.
10057 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
10059 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
10060 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should
10061 * be a checksum (a simple 32-bit sum) of the transferred data. An individual
10062 * download may be aborted using CHUNK_ID_ABORT.
10064 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),
10065 * similar to PHASE_IMEMS.
10067 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
10069 * After any error (a requested abort is not considered to be an error) the
10070 * sequence must be restarted from PHASE_RESET.
10072 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20
10073 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252
10074 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
10075 /* Download phase. (Note: the IDLE phase is used internally and is never valid
10076 * in a command from the host.)
10078 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0
10079 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
10080 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
10081 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
10082 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
10083 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
10084 /* Target for download. (These match the blob numbers defined in
10085 * mc_flash_layout.h.)
10087 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4
10088 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10089 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
10090 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10091 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
10092 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10093 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
10094 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10095 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
10096 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10097 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
10098 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10099 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
10100 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10101 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
10102 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10103 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
10104 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10105 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
10106 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10107 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
10108 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10109 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
10110 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
10111 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
10112 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
10113 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
10114 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
10115 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
10116 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
10117 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
10118 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
10119 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
10120 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
10121 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
10122 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */
10123 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8
10124 /* enum: Last chunk, containing checksum rather than data */
10125 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
10126 /* enum: Abort download of this item */
10127 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
10128 /* Length of this chunk in bytes */
10129 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12
10130 /* Data for this chunk */
10131 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16
10132 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4
10133 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1
10134 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59
10136 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */
10137 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8
10138 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
10139 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0
10140 /* Extra status information */
10141 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4
10142 /* enum: Code download OK, completed. */
10143 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
10144 /* enum: Code download aborted as requested. */
10145 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
10146 /* enum: Code download OK so far, send next chunk. */
10147 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
10148 /* enum: Download phases out of sequence */
10149 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
10150 /* enum: Bad target for this phase */
10151 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
10152 /* enum: Chunk ID out of sequence */
10153 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
10154 /* enum: Chunk length zero or too large */
10155 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
10156 /* enum: Checksum was incorrect */
10157 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300
10160 /***********************************/
10161 /* MC_CMD_GET_CAPABILITIES
10162 * Get device capabilities.
10164 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to
10165 * reference inherent device capabilities as opposed to current NVRAM config.
10167 #define MC_CMD_GET_CAPABILITIES 0xbe
10168 #undef MC_CMD_0xbe_PRIVILEGE_CTG
10170 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10172 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */
10173 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0
10175 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */
10176 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20
10177 /* First word of flags. */
10178 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
10179 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3
10180 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1
10181 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
10182 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1
10183 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5
10184 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1
10185 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
10186 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
10187 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7
10188 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
10189 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8
10190 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
10191 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9
10192 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1
10193 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
10194 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
10195 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
10196 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
10197 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
10198 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
10199 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13
10200 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
10201 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14
10202 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1
10203 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
10204 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
10205 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16
10206 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1
10207 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17
10208 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1
10209 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18
10210 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1
10211 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19
10212 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
10213 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20
10214 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
10215 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21
10216 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
10217 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22
10218 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
10219 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23
10220 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
10221 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24
10222 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
10223 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25
10224 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
10225 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26
10226 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
10227 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27
10228 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
10229 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28
10230 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1
10231 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
10232 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
10233 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30
10234 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1
10235 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31
10236 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1
10237 /* RxDPCPU firmware id. */
10238 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
10239 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2
10240 /* enum: Standard RXDP firmware */
10241 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
10242 /* enum: Low latency RXDP firmware */
10243 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
10244 /* enum: Packed stream RXDP firmware */
10245 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
10246 /* enum: BIST RXDP firmware */
10247 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
10248 /* enum: RXDP Test firmware image 1 */
10249 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
10250 /* enum: RXDP Test firmware image 2 */
10251 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
10252 /* enum: RXDP Test firmware image 3 */
10253 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
10254 /* enum: RXDP Test firmware image 4 */
10255 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
10256 /* enum: RXDP Test firmware image 5 */
10257 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
10258 /* enum: RXDP Test firmware image 6 */
10259 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
10260 /* enum: RXDP Test firmware image 7 */
10261 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
10262 /* enum: RXDP Test firmware image 8 */
10263 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
10264 /* enum: RXDP Test firmware image 9 */
10265 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
10266 /* TxDPCPU firmware id. */
10267 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6
10268 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2
10269 /* enum: Standard TXDP firmware */
10270 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
10271 /* enum: Low latency TXDP firmware */
10272 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
10273 /* enum: High packet rate TXDP firmware */
10274 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
10275 /* enum: BIST TXDP firmware */
10276 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
10277 /* enum: TXDP Test firmware image 1 */
10278 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
10279 /* enum: TXDP Test firmware image 2 */
10280 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
10281 /* enum: TXDP CSR bus test firmware */
10282 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
10283 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8
10284 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2
10285 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
10286 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12
10287 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12
10288 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
10289 /* enum: reserved value - do not use (may indicate alternative interpretation
10290 * of REV field in future)
10292 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
10293 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
10294 * development only)
10296 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
10297 /* enum: RX PD firmware with approximately Siena-compatible behaviour
10298 * (Huntington development only)
10300 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
10301 /* enum: Virtual switching (full feature) RX PD production firmware */
10302 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
10303 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
10304 * (Huntington development only)
10306 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10307 /* enum: Low latency RX PD production firmware */
10308 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
10309 /* enum: Packed stream RX PD production firmware */
10310 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
10311 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
10312 * tests (Medford development only)
10314 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
10315 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10316 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10317 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
10318 * encapsulations (Medford development only)
10320 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
10321 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10
10322 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2
10323 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
10324 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12
10325 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12
10326 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
10327 /* enum: reserved value - do not use (may indicate alternative interpretation
10328 * of REV field in future)
10330 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
10331 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
10332 * development only)
10334 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
10335 /* enum: TX PD firmware with approximately Siena-compatible behaviour
10336 * (Huntington development only)
10338 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
10339 /* enum: Virtual switching (full feature) TX PD production firmware */
10340 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
10341 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
10342 * (Huntington development only)
10344 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10345 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10346 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10347 * tests (Medford development only)
10349 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10350 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10351 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10352 /* Hardware capabilities of NIC */
10353 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12
10354 /* Licensed capabilities */
10355 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16
10357 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */
10358 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
10360 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */
10361 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72
10362 /* First word of flags. */
10363 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
10364 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3
10365 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1
10366 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
10367 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1
10368 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5
10369 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1
10370 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
10371 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
10372 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7
10373 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
10374 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8
10375 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
10376 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9
10377 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1
10378 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
10379 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
10380 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
10381 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
10382 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
10383 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
10384 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13
10385 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
10386 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14
10387 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1
10388 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
10389 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
10390 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16
10391 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1
10392 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17
10393 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1
10394 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18
10395 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1
10396 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19
10397 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1
10398 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20
10399 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1
10400 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21
10401 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1
10402 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22
10403 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1
10404 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23
10405 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1
10406 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24
10407 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1
10408 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25
10409 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1
10410 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26
10411 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1
10412 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27
10413 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
10414 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28
10415 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1
10416 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
10417 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
10418 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30
10419 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1
10420 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31
10421 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1
10422 /* RxDPCPU firmware id. */
10423 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
10424 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2
10425 /* enum: Standard RXDP firmware */
10426 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
10427 /* enum: Low latency RXDP firmware */
10428 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
10429 /* enum: Packed stream RXDP firmware */
10430 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
10431 /* enum: BIST RXDP firmware */
10432 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
10433 /* enum: RXDP Test firmware image 1 */
10434 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
10435 /* enum: RXDP Test firmware image 2 */
10436 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
10437 /* enum: RXDP Test firmware image 3 */
10438 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
10439 /* enum: RXDP Test firmware image 4 */
10440 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
10441 /* enum: RXDP Test firmware image 5 */
10442 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
10443 /* enum: RXDP Test firmware image 6 */
10444 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
10445 /* enum: RXDP Test firmware image 7 */
10446 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
10447 /* enum: RXDP Test firmware image 8 */
10448 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
10449 /* enum: RXDP Test firmware image 9 */
10450 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
10451 /* TxDPCPU firmware id. */
10452 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6
10453 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2
10454 /* enum: Standard TXDP firmware */
10455 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
10456 /* enum: Low latency TXDP firmware */
10457 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
10458 /* enum: High packet rate TXDP firmware */
10459 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
10460 /* enum: BIST TXDP firmware */
10461 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
10462 /* enum: TXDP Test firmware image 1 */
10463 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
10464 /* enum: TXDP Test firmware image 2 */
10465 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
10466 /* enum: TXDP CSR bus test firmware */
10467 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
10468 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8
10469 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2
10470 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
10471 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12
10472 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12
10473 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
10474 /* enum: reserved value - do not use (may indicate alternative interpretation
10475 * of REV field in future)
10477 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
10478 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
10479 * development only)
10481 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
10482 /* enum: RX PD firmware with approximately Siena-compatible behaviour
10483 * (Huntington development only)
10485 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
10486 /* enum: Virtual switching (full feature) RX PD production firmware */
10487 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
10488 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
10489 * (Huntington development only)
10491 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10492 /* enum: Low latency RX PD production firmware */
10493 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
10494 /* enum: Packed stream RX PD production firmware */
10495 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
10496 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
10497 * tests (Medford development only)
10499 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
10500 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10501 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10502 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
10503 * encapsulations (Medford development only)
10505 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
10506 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10
10507 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2
10508 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
10509 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12
10510 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12
10511 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
10512 /* enum: reserved value - do not use (may indicate alternative interpretation
10513 * of REV field in future)
10515 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
10516 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
10517 * development only)
10519 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
10520 /* enum: TX PD firmware with approximately Siena-compatible behaviour
10521 * (Huntington development only)
10523 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
10524 /* enum: Virtual switching (full feature) TX PD production firmware */
10525 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
10526 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
10527 * (Huntington development only)
10529 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10530 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10531 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10532 * tests (Medford development only)
10534 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10535 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10536 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10537 /* Hardware capabilities of NIC */
10538 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12
10539 /* Licensed capabilities */
10540 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16
10541 /* Second word of flags. Not present on older firmware (check the length). */
10542 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20
10543 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
10544 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1
10545 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1
10546 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1
10547 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2
10548 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1
10549 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3
10550 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1
10551 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
10552 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1
10553 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5
10554 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
10555 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
10556 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
10557 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7
10558 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1
10559 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
10560 * on older firmware (check the length).
10562 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
10563 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
10564 /* One byte per PF containing the number of the external port assigned to this
10565 * PF, indexed by PF number. Special values indicate that a PF is either not
10566 * present or not assigned.
10568 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
10569 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
10570 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
10571 /* enum: The caller is not permitted to access information on this PF. */
10572 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
10573 /* enum: PF does not exist. */
10574 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
10575 /* enum: PF does exist but is not assigned to any external port. */
10576 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
10577 /* enum: This value indicates that PF is assigned, but it cannot be expressed
10578 * in this field. It is intended for a possible future situation where a more
10579 * complex scheme of PFs to ports mapping is being used. The future driver
10580 * should look for a new field supporting the new scheme. The current/old
10581 * driver should treat this value as PF_NOT_ASSIGNED.
10583 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
10584 /* One byte per PF containing the number of its VFs, indexed by PF number. A
10585 * special value indicates that a PF is not present.
10587 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42
10588 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1
10589 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16
10590 /* enum: The caller is not permitted to access information on this PF. */
10591 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
10592 /* enum: PF does not exist. */
10593 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
10594 /* Number of VIs available for each external port */
10595 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58
10596 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2
10597 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
10598 /* Size of RX descriptor cache expressed as binary logarithm The actual size
10599 * equals (2 ^ RX_DESC_CACHE_SIZE)
10601 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66
10602 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1
10603 /* Size of TX descriptor cache expressed as binary logarithm The actual size
10604 * equals (2 ^ TX_DESC_CACHE_SIZE)
10606 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67
10607 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1
10608 /* Total number of available PIO buffers */
10609 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68
10610 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2
10611 /* Size of a single PIO buffer */
10612 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70
10613 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2
10616 /***********************************/
10618 * Encapsulation for a v2 extended command
10620 #define MC_CMD_V2_EXTN 0x7f
10622 /* MC_CMD_V2_EXTN_IN msgrequest */
10623 #define MC_CMD_V2_EXTN_IN_LEN 4
10624 /* the extended command number */
10625 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
10626 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
10627 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
10628 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
10629 /* the actual length of the encapsulated command (which is not in the v1
10632 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
10633 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
10634 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
10635 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6
10638 /***********************************/
10639 /* MC_CMD_TCM_BUCKET_ALLOC
10640 * Allocate a pacer bucket (for qau rp or a snapper test)
10642 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2
10643 #undef MC_CMD_0xb2_PRIVILEGE_CTG
10645 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10647 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */
10648 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
10650 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */
10651 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
10652 /* the bucket id */
10653 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
10656 /***********************************/
10657 /* MC_CMD_TCM_BUCKET_FREE
10658 * Free a pacer bucket
10660 #define MC_CMD_TCM_BUCKET_FREE 0xb3
10661 #undef MC_CMD_0xb3_PRIVILEGE_CTG
10663 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10665 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */
10666 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
10667 /* the bucket id */
10668 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
10670 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */
10671 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
10674 /***********************************/
10675 /* MC_CMD_TCM_BUCKET_INIT
10676 * Initialise pacer bucket with a given rate
10678 #define MC_CMD_TCM_BUCKET_INIT 0xb4
10679 #undef MC_CMD_0xb4_PRIVILEGE_CTG
10681 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10683 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */
10684 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8
10685 /* the bucket id */
10686 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
10687 /* the rate in mbps */
10688 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
10690 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */
10691 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12
10692 /* the bucket id */
10693 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0
10694 /* the rate in mbps */
10695 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4
10696 /* the desired maximum fill level */
10697 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8
10699 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */
10700 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
10703 /***********************************/
10704 /* MC_CMD_TCM_TXQ_INIT
10705 * Initialise txq in pacer with given options or set options
10707 #define MC_CMD_TCM_TXQ_INIT 0xb5
10708 #undef MC_CMD_0xb5_PRIVILEGE_CTG
10710 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10712 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */
10713 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28
10715 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
10716 /* the static priority associated with the txq */
10717 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
10718 /* bitmask of the priority queues this txq is inserted into when inserted. */
10719 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8
10720 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0
10721 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
10722 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1
10723 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1
10724 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2
10725 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1
10726 /* the reaction point (RP) bucket */
10727 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12
10728 /* an already reserved bucket (typically set to bucket associated with outer
10731 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16
10732 /* an already reserved bucket (typically set to bucket associated with inner
10735 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20
10736 /* the min bucket (typically for ETS/minimum bandwidth) */
10737 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24
10739 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */
10740 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32
10742 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0
10743 /* the static priority associated with the txq */
10744 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4
10745 /* bitmask of the priority queues this txq is inserted into when inserted. */
10746 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8
10747 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0
10748 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
10749 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1
10750 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1
10751 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2
10752 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1
10753 /* the reaction point (RP) bucket */
10754 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12
10755 /* an already reserved bucket (typically set to bucket associated with outer
10758 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16
10759 /* an already reserved bucket (typically set to bucket associated with inner
10762 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20
10763 /* the min bucket (typically for ETS/minimum bandwidth) */
10764 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24
10765 /* the static priority associated with the txq */
10766 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28
10768 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */
10769 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
10772 /***********************************/
10773 /* MC_CMD_LINK_PIOBUF
10774 * Link a push I/O buffer to a TxQ
10776 #define MC_CMD_LINK_PIOBUF 0x92
10777 #undef MC_CMD_0x92_PRIVILEGE_CTG
10779 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
10781 /* MC_CMD_LINK_PIOBUF_IN msgrequest */
10782 #define MC_CMD_LINK_PIOBUF_IN_LEN 8
10783 /* Handle for allocated push I/O buffer. */
10784 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
10785 /* Function Local Instance (VI) number. */
10786 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
10788 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */
10789 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0
10792 /***********************************/
10793 /* MC_CMD_UNLINK_PIOBUF
10794 * Unlink a push I/O buffer from a TxQ
10796 #define MC_CMD_UNLINK_PIOBUF 0x93
10797 #undef MC_CMD_0x93_PRIVILEGE_CTG
10799 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
10801 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */
10802 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
10803 /* Function Local Instance (VI) number. */
10804 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
10806 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */
10807 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
10810 /***********************************/
10811 /* MC_CMD_VSWITCH_ALLOC
10812 * allocate and initialise a v-switch.
10814 #define MC_CMD_VSWITCH_ALLOC 0x94
10815 #undef MC_CMD_0x94_PRIVILEGE_CTG
10817 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10819 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */
10820 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16
10821 /* The port to connect to the v-switch's upstream port. */
10822 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
10823 /* The type of v-switch to create. */
10824 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
10826 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
10828 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
10829 /* enum: VEPA (obsolete) */
10830 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
10832 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
10833 /* enum: Snapper specific; semantics TBD */
10834 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
10835 /* Flags controlling v-port creation */
10836 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8
10837 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
10838 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
10839 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
10840 * this must be one or greated, and the attached v-ports must have exactly this
10841 * number of tags. For other v-switch types, this must be zero of greater, and
10842 * is an upper limit on the number of VLAN tags for attached v-ports. An error
10843 * will be returned if existing configuration means we can't support attached
10844 * v-ports with this number of tags.
10846 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
10848 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */
10849 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
10852 /***********************************/
10853 /* MC_CMD_VSWITCH_FREE
10854 * de-allocate a v-switch.
10856 #define MC_CMD_VSWITCH_FREE 0x95
10857 #undef MC_CMD_0x95_PRIVILEGE_CTG
10859 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10861 /* MC_CMD_VSWITCH_FREE_IN msgrequest */
10862 #define MC_CMD_VSWITCH_FREE_IN_LEN 4
10863 /* The port to which the v-switch is connected. */
10864 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
10866 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */
10867 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0
10870 /***********************************/
10871 /* MC_CMD_VSWITCH_QUERY
10872 * read some config of v-switch. For now this command is an empty placeholder.
10873 * It may be used to check if a v-switch is connected to a given EVB port (if
10874 * not, then the command returns ENOENT).
10876 #define MC_CMD_VSWITCH_QUERY 0x63
10877 #undef MC_CMD_0x63_PRIVILEGE_CTG
10879 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10881 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */
10882 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4
10883 /* The port to which the v-switch is connected. */
10884 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
10886 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */
10887 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0
10890 /***********************************/
10891 /* MC_CMD_VPORT_ALLOC
10892 * allocate a v-port.
10894 #define MC_CMD_VPORT_ALLOC 0x96
10895 #undef MC_CMD_0x96_PRIVILEGE_CTG
10897 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10899 /* MC_CMD_VPORT_ALLOC_IN msgrequest */
10900 #define MC_CMD_VPORT_ALLOC_IN_LEN 20
10901 /* The port to which the v-switch is connected. */
10902 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
10903 /* The type of the new v-port. */
10904 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
10905 /* enum: VLAN (obsolete) */
10906 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
10907 /* enum: VEB (obsolete) */
10908 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
10909 /* enum: VEPA (obsolete) */
10910 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
10911 /* enum: A normal v-port receives packets which match a specified MAC and/or
10914 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
10915 /* enum: An expansion v-port packets traffic which don't match any other
10918 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
10919 /* enum: An test v-port receives packets which match any filters installed by
10920 * its downstream components.
10922 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
10923 /* Flags controlling v-port creation */
10924 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8
10925 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
10926 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
10927 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1
10928 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1
10929 /* The number of VLAN tags to insert/remove. An error will be returned if
10930 * incompatible with the number of VLAN tags specified for the upstream
10933 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
10934 /* The actual VLAN tags to insert/remove */
10935 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16
10936 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
10937 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16
10938 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16
10939 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16
10941 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */
10942 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4
10943 /* The handle of the new v-port */
10944 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
10947 /***********************************/
10948 /* MC_CMD_VPORT_FREE
10949 * de-allocate a v-port.
10951 #define MC_CMD_VPORT_FREE 0x97
10952 #undef MC_CMD_0x97_PRIVILEGE_CTG
10954 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10956 /* MC_CMD_VPORT_FREE_IN msgrequest */
10957 #define MC_CMD_VPORT_FREE_IN_LEN 4
10958 /* The handle of the v-port */
10959 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
10961 /* MC_CMD_VPORT_FREE_OUT msgresponse */
10962 #define MC_CMD_VPORT_FREE_OUT_LEN 0
10965 /***********************************/
10966 /* MC_CMD_VADAPTOR_ALLOC
10967 * allocate a v-adaptor.
10969 #define MC_CMD_VADAPTOR_ALLOC 0x98
10970 #undef MC_CMD_0x98_PRIVILEGE_CTG
10972 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10974 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */
10975 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30
10976 /* The port to connect to the v-adaptor's port. */
10977 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
10978 /* Flags controlling v-adaptor creation */
10979 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8
10980 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
10981 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
10982 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1
10983 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
10984 /* The number of VLAN tags to strip on receive */
10985 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12
10986 /* The number of VLAN tags to transparently insert/remove. */
10987 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16
10988 /* The actual VLAN tags to insert/remove */
10989 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20
10990 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
10991 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16
10992 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16
10993 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16
10994 /* The MAC address to assign to this v-adaptor */
10995 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24
10996 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6
10997 /* enum: Derive the MAC address from the upstream port */
10998 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
11000 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */
11001 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
11004 /***********************************/
11005 /* MC_CMD_VADAPTOR_FREE
11006 * de-allocate a v-adaptor.
11008 #define MC_CMD_VADAPTOR_FREE 0x99
11009 #undef MC_CMD_0x99_PRIVILEGE_CTG
11011 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11013 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */
11014 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4
11015 /* The port to which the v-adaptor is connected. */
11016 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
11018 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */
11019 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
11022 /***********************************/
11023 /* MC_CMD_VADAPTOR_SET_MAC
11024 * assign a new MAC address to a v-adaptor.
11026 #define MC_CMD_VADAPTOR_SET_MAC 0x5d
11027 #undef MC_CMD_0x5d_PRIVILEGE_CTG
11029 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11031 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */
11032 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10
11033 /* The port to which the v-adaptor is connected. */
11034 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
11035 /* The new MAC address to assign to this v-adaptor */
11036 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
11037 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6
11039 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */
11040 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
11043 /***********************************/
11044 /* MC_CMD_VADAPTOR_GET_MAC
11045 * read the MAC address assigned to a v-adaptor.
11047 #define MC_CMD_VADAPTOR_GET_MAC 0x5e
11048 #undef MC_CMD_0x5e_PRIVILEGE_CTG
11050 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11052 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */
11053 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4
11054 /* The port to which the v-adaptor is connected. */
11055 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
11057 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */
11058 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6
11059 /* The MAC address assigned to this v-adaptor */
11060 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0
11061 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6
11064 /***********************************/
11065 /* MC_CMD_VADAPTOR_QUERY
11066 * read some config of v-adaptor.
11068 #define MC_CMD_VADAPTOR_QUERY 0x61
11069 #undef MC_CMD_0x61_PRIVILEGE_CTG
11071 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11073 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */
11074 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4
11075 /* The port to which the v-adaptor is connected. */
11076 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
11078 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */
11079 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12
11080 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
11081 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
11082 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
11083 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
11084 /* The number of VLAN tags that may still be added */
11085 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8
11088 /***********************************/
11089 /* MC_CMD_EVB_PORT_ASSIGN
11090 * assign a port to a PCI function.
11092 #define MC_CMD_EVB_PORT_ASSIGN 0x9a
11093 #undef MC_CMD_0x9a_PRIVILEGE_CTG
11095 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11097 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */
11098 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8
11099 /* The port to assign. */
11100 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
11101 /* The target function to modify. */
11102 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
11103 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
11104 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16
11105 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16
11106 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16
11108 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */
11109 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
11112 /***********************************/
11113 /* MC_CMD_RDWR_A64_REGIONS
11114 * Assign the 64 bit region addresses.
11116 #define MC_CMD_RDWR_A64_REGIONS 0x9b
11117 #undef MC_CMD_0x9b_PRIVILEGE_CTG
11119 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11121 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */
11122 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17
11123 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
11124 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
11125 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8
11126 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12
11127 /* Write enable bits 0-3, set to write, clear to read. */
11128 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128
11129 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
11130 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16
11131 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1
11133 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included
11134 * regardless of state of write bits in the request.
11136 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16
11137 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
11138 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
11139 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8
11140 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12
11143 /***********************************/
11144 /* MC_CMD_ONLOAD_STACK_ALLOC
11145 * Allocate an Onload stack ID.
11147 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
11148 #undef MC_CMD_0x9c_PRIVILEGE_CTG
11150 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11152 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */
11153 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
11154 /* The handle of the owning upstream port */
11155 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11157 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */
11158 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
11159 /* The handle of the new Onload stack */
11160 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
11163 /***********************************/
11164 /* MC_CMD_ONLOAD_STACK_FREE
11165 * Free an Onload stack ID.
11167 #define MC_CMD_ONLOAD_STACK_FREE 0x9d
11168 #undef MC_CMD_0x9d_PRIVILEGE_CTG
11170 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11172 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */
11173 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
11174 /* The handle of the Onload stack */
11175 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
11177 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */
11178 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
11181 /***********************************/
11182 /* MC_CMD_RSS_CONTEXT_ALLOC
11183 * Allocate an RSS context.
11185 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
11186 #undef MC_CMD_0x9e_PRIVILEGE_CTG
11188 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11190 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */
11191 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12
11192 /* The handle of the owning upstream port */
11193 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11194 /* The type of context to allocate */
11195 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
11196 /* enum: Allocate a context for exclusive use. The key and indirection table
11197 * must be explicitly configured.
11199 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
11200 /* enum: Allocate a context for shared use; this will spread across a range of
11201 * queues, but the key and indirection table are pre-configured and may not be
11202 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
11204 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
11205 /* Number of queues spanned by this context, in the range 1-64; valid offsets
11206 * in the indirection table will be in the range 0 to NUM_QUEUES-1.
11208 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8
11210 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */
11211 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
11212 /* The handle of the new RSS context. This should be considered opaque to the
11213 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
11216 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
11217 /* enum: guaranteed invalid RSS context handle value */
11218 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
11221 /***********************************/
11222 /* MC_CMD_RSS_CONTEXT_FREE
11223 * Free an RSS context.
11225 #define MC_CMD_RSS_CONTEXT_FREE 0x9f
11226 #undef MC_CMD_0x9f_PRIVILEGE_CTG
11228 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11230 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */
11231 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
11232 /* The handle of the RSS context */
11233 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
11235 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */
11236 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
11239 /***********************************/
11240 /* MC_CMD_RSS_CONTEXT_SET_KEY
11241 * Set the Toeplitz hash key for an RSS context.
11243 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
11244 #undef MC_CMD_0xa0_PRIVILEGE_CTG
11246 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11248 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */
11249 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44
11250 /* The handle of the RSS context */
11251 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
11252 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
11253 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
11254 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40
11256 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */
11257 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
11260 /***********************************/
11261 /* MC_CMD_RSS_CONTEXT_GET_KEY
11262 * Get the Toeplitz hash key for an RSS context.
11264 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
11265 #undef MC_CMD_0xa1_PRIVILEGE_CTG
11267 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11269 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */
11270 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
11271 /* The handle of the RSS context */
11272 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
11274 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */
11275 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44
11276 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
11277 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
11278 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40
11281 /***********************************/
11282 /* MC_CMD_RSS_CONTEXT_SET_TABLE
11283 * Set the indirection table for an RSS context.
11285 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
11286 #undef MC_CMD_0xa2_PRIVILEGE_CTG
11288 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11290 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */
11291 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132
11292 /* The handle of the RSS context */
11293 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
11294 /* The 128-byte indirection table (1 byte per entry) */
11295 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
11296 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128
11298 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */
11299 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
11302 /***********************************/
11303 /* MC_CMD_RSS_CONTEXT_GET_TABLE
11304 * Get the indirection table for an RSS context.
11306 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
11307 #undef MC_CMD_0xa3_PRIVILEGE_CTG
11309 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11311 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */
11312 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
11313 /* The handle of the RSS context */
11314 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
11316 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */
11317 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132
11318 /* The 128-byte indirection table (1 byte per entry) */
11319 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
11320 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128
11323 /***********************************/
11324 /* MC_CMD_RSS_CONTEXT_SET_FLAGS
11325 * Set various control flags for an RSS context.
11327 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
11328 #undef MC_CMD_0xe1_PRIVILEGE_CTG
11330 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11332 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */
11333 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8
11334 /* The handle of the RSS context */
11335 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
11336 /* Hash control flags. The _EN bits are always supported, but new modes are
11337 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES:
11338 * in this case, the MODE fields may be set to non-zero values, and will take
11339 * effect regardless of the settings of the _EN flags. See the RSS_MODE
11340 * structure for the meaning of the mode bits. Drivers must check the
11341 * capability before trying to set any _MODE fields, as older firmware will
11342 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
11343 * the case where all the _MODE flags are zero, the _EN flags take effect,
11344 * providing backward compatibility for existing drivers. (Setting all _MODE
11345 * *and* all _EN flags to zero is valid, to disable RSS spreading for that
11346 * particular packet type.)
11348 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
11349 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
11350 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
11351 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
11352 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
11353 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2
11354 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
11355 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3
11356 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
11357 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
11358 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
11359 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8
11360 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
11361 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12
11362 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
11363 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16
11364 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
11365 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20
11366 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
11367 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24
11368 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
11369 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28
11370 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
11372 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */
11373 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
11376 /***********************************/
11377 /* MC_CMD_RSS_CONTEXT_GET_FLAGS
11378 * Get various control flags for an RSS context.
11380 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
11381 #undef MC_CMD_0xe2_PRIVILEGE_CTG
11383 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11385 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */
11386 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
11387 /* The handle of the RSS context */
11388 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
11390 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */
11391 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8
11392 /* Hash control flags. If all _MODE bits are zero (which will always be true
11393 * for older firmware which does not report the ADDITIONAL_RSS_MODES
11394 * capability), the _EN bits report the state. If any _MODE bits are non-zero
11395 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES)
11396 * then the _EN bits should be disregarded, although the _MODE flags are
11397 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
11398 * context and in the case where the _EN flags were used in the SET. This
11399 * provides backward compatibility: old drivers will not be attempting to
11400 * derive any meaning from the _MODE bits (and can never set them to any value
11401 * not representable by the _EN bits); new drivers can always determine the
11402 * mode by looking only at the _MODE bits; the value returned by a GET can
11403 * always be used for a SET regardless of old/new driver vs. old/new firmware.
11405 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
11406 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
11407 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
11408 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
11409 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
11410 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2
11411 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
11412 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3
11413 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
11414 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
11415 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
11416 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8
11417 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
11418 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12
11419 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
11420 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16
11421 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
11422 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20
11423 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
11424 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24
11425 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
11426 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28
11427 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
11430 /***********************************/
11431 /* MC_CMD_DOT1P_MAPPING_ALLOC
11432 * Allocate a .1p mapping.
11434 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
11435 #undef MC_CMD_0xa4_PRIVILEGE_CTG
11437 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11439 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */
11440 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8
11441 /* The handle of the owning upstream port */
11442 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11443 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed
11444 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
11445 * referenced RSS contexts must span no more than this number.
11447 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4
11449 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */
11450 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4
11451 /* The handle of the new .1p mapping. This should be considered opaque to the
11452 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
11455 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0
11456 /* enum: guaranteed invalid .1p mapping handle value */
11457 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff
11460 /***********************************/
11461 /* MC_CMD_DOT1P_MAPPING_FREE
11462 * Free a .1p mapping.
11464 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5
11465 #undef MC_CMD_0xa5_PRIVILEGE_CTG
11467 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11469 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */
11470 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4
11471 /* The handle of the .1p mapping */
11472 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0
11474 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */
11475 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0
11478 /***********************************/
11479 /* MC_CMD_DOT1P_MAPPING_SET_TABLE
11480 * Set the mapping table for a .1p mapping.
11482 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
11483 #undef MC_CMD_0xa6_PRIVILEGE_CTG
11485 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11487 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */
11488 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36
11489 /* The handle of the .1p mapping */
11490 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
11491 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
11494 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4
11495 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32
11497 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */
11498 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0
11501 /***********************************/
11502 /* MC_CMD_DOT1P_MAPPING_GET_TABLE
11503 * Get the mapping table for a .1p mapping.
11505 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
11506 #undef MC_CMD_0xa7_PRIVILEGE_CTG
11508 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11510 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */
11511 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4
11512 /* The handle of the .1p mapping */
11513 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
11515 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */
11516 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36
11517 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
11520 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4
11521 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32
11524 /***********************************/
11525 /* MC_CMD_GET_VECTOR_CFG
11526 * Get Interrupt Vector config for this PF.
11528 #define MC_CMD_GET_VECTOR_CFG 0xbf
11529 #undef MC_CMD_0xbf_PRIVILEGE_CTG
11531 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11533 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */
11534 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0
11536 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */
11537 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12
11538 /* Base absolute interrupt vector number. */
11539 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
11540 /* Number of interrupt vectors allocate to this PF. */
11541 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
11542 /* Number of interrupt vectors to allocate per VF. */
11543 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8
11546 /***********************************/
11547 /* MC_CMD_SET_VECTOR_CFG
11548 * Set Interrupt Vector config for this PF.
11550 #define MC_CMD_SET_VECTOR_CFG 0xc0
11551 #undef MC_CMD_0xc0_PRIVILEGE_CTG
11553 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11555 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */
11556 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12
11557 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to
11558 * let the system find a suitable base.
11560 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
11561 /* Number of interrupt vectors allocate to this PF. */
11562 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
11563 /* Number of interrupt vectors to allocate per VF. */
11564 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8
11566 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */
11567 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
11570 /***********************************/
11571 /* MC_CMD_VPORT_ADD_MAC_ADDRESS
11572 * Add a MAC address to a v-port
11574 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
11575 #undef MC_CMD_0xa8_PRIVILEGE_CTG
11577 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11579 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */
11580 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10
11581 /* The handle of the v-port */
11582 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
11583 /* MAC address to add */
11584 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
11585 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6
11587 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */
11588 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
11591 /***********************************/
11592 /* MC_CMD_VPORT_DEL_MAC_ADDRESS
11593 * Delete a MAC address from a v-port
11595 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
11596 #undef MC_CMD_0xa9_PRIVILEGE_CTG
11598 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11600 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */
11601 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10
11602 /* The handle of the v-port */
11603 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
11604 /* MAC address to add */
11605 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
11606 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6
11608 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */
11609 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
11612 /***********************************/
11613 /* MC_CMD_VPORT_GET_MAC_ADDRESSES
11614 * Delete a MAC address from a v-port
11616 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
11617 #undef MC_CMD_0xaa_PRIVILEGE_CTG
11619 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11621 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */
11622 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
11623 /* The handle of the v-port */
11624 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
11626 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */
11627 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
11628 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250
11629 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
11630 /* The number of MAC addresses returned */
11631 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
11632 /* Array of MAC addresses */
11633 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
11634 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6
11635 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
11636 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41
11639 /***********************************/
11640 /* MC_CMD_VPORT_RECONFIGURE
11641 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
11642 * has already been passed to another function (v-port's user), then that
11643 * function will be reset before applying the changes.
11645 #define MC_CMD_VPORT_RECONFIGURE 0xeb
11646 #undef MC_CMD_0xeb_PRIVILEGE_CTG
11648 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11650 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */
11651 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44
11652 /* The handle of the v-port */
11653 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
11654 /* Flags requesting what should be changed. */
11655 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
11656 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
11657 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1
11658 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1
11659 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1
11660 /* The number of VLAN tags to insert/remove. An error will be returned if
11661 * incompatible with the number of VLAN tags specified for the upstream
11664 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8
11665 /* The actual VLAN tags to insert/remove */
11666 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12
11667 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
11668 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16
11669 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16
11670 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16
11671 /* The number of MAC addresses to add */
11672 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16
11673 /* MAC addresses to add */
11674 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20
11675 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6
11676 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
11678 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */
11679 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
11680 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
11681 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
11682 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1
11685 /***********************************/
11686 /* MC_CMD_EVB_PORT_QUERY
11687 * read some config of v-port.
11689 #define MC_CMD_EVB_PORT_QUERY 0x62
11690 #undef MC_CMD_0x62_PRIVILEGE_CTG
11692 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11694 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */
11695 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4
11696 /* The handle of the v-port */
11697 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0
11699 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */
11700 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8
11701 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
11702 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0
11703 /* The number of VLAN tags that may be used on a v-adaptor connected to this
11706 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4
11709 /***********************************/
11710 /* MC_CMD_DUMP_BUFTBL_ENTRIES
11711 * Dump buffer table entries, mainly for command client debug use. Dumps
11712 * absolute entries, and does not use chunk handles. All entries must be in
11713 * range, and used for q page mapping, Although the latter restriction may be
11714 * lifted in future.
11716 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
11717 #undef MC_CMD_0xab_PRIVILEGE_CTG
11719 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11721 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */
11722 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8
11723 /* Index of the first buffer table entry. */
11724 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0
11725 /* Number of buffer table entries to dump. */
11726 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4
11728 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */
11729 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12
11730 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252
11731 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
11732 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */
11733 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
11734 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12
11735 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1
11736 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21
11739 /***********************************/
11740 /* MC_CMD_SET_RXDP_CONFIG
11741 * Set global RXDP configuration settings
11743 #define MC_CMD_SET_RXDP_CONFIG 0xc1
11744 #undef MC_CMD_0xc1_PRIVILEGE_CTG
11746 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11748 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */
11749 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4
11750 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0
11751 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0
11752 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1
11753 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1
11754 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2
11755 /* enum: pad to 64 bytes */
11756 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0
11757 /* enum: pad to 128 bytes (Medford only) */
11758 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1
11759 /* enum: pad to 256 bytes (Medford only) */
11760 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2
11762 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */
11763 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0
11766 /***********************************/
11767 /* MC_CMD_GET_RXDP_CONFIG
11768 * Get global RXDP configuration settings
11770 #define MC_CMD_GET_RXDP_CONFIG 0xc2
11771 #undef MC_CMD_0xc2_PRIVILEGE_CTG
11773 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11775 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */
11776 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0
11778 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */
11779 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4
11780 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0
11781 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0
11782 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1
11783 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1
11784 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2
11785 /* Enum values, see field(s): */
11786 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */
11789 /***********************************/
11790 /* MC_CMD_GET_CLOCK
11791 * Return the system and PDCPU clock frequencies.
11793 #define MC_CMD_GET_CLOCK 0xac
11794 #undef MC_CMD_0xac_PRIVILEGE_CTG
11796 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11798 /* MC_CMD_GET_CLOCK_IN msgrequest */
11799 #define MC_CMD_GET_CLOCK_IN_LEN 0
11801 /* MC_CMD_GET_CLOCK_OUT msgresponse */
11802 #define MC_CMD_GET_CLOCK_OUT_LEN 8
11803 /* System frequency, MHz */
11804 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
11805 /* DPCPU frequency, MHz */
11806 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
11809 /***********************************/
11810 /* MC_CMD_SET_CLOCK
11811 * Control the system and DPCPU clock frequencies. Changes are lost reboot.
11813 #define MC_CMD_SET_CLOCK 0xad
11814 #undef MC_CMD_0xad_PRIVILEGE_CTG
11816 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11818 /* MC_CMD_SET_CLOCK_IN msgrequest */
11819 #define MC_CMD_SET_CLOCK_IN_LEN 28
11820 /* Requested frequency in MHz for system clock domain */
11821 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0
11822 /* enum: Leave the system clock domain frequency unchanged */
11823 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0
11824 /* Requested frequency in MHz for inter-core clock domain */
11825 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4
11826 /* enum: Leave the inter-core clock domain frequency unchanged */
11827 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0
11828 /* Requested frequency in MHz for DPCPU clock domain */
11829 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8
11830 /* enum: Leave the DPCPU clock domain frequency unchanged */
11831 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0
11832 /* Requested frequency in MHz for PCS clock domain */
11833 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12
11834 /* enum: Leave the PCS clock domain frequency unchanged */
11835 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0
11836 /* Requested frequency in MHz for MC clock domain */
11837 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16
11838 /* enum: Leave the MC clock domain frequency unchanged */
11839 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0
11840 /* Requested frequency in MHz for rmon clock domain */
11841 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20
11842 /* enum: Leave the rmon clock domain frequency unchanged */
11843 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0
11844 /* Requested frequency in MHz for vswitch clock domain */
11845 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24
11846 /* enum: Leave the vswitch clock domain frequency unchanged */
11847 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0
11849 /* MC_CMD_SET_CLOCK_OUT msgresponse */
11850 #define MC_CMD_SET_CLOCK_OUT_LEN 28
11851 /* Resulting system frequency in MHz */
11852 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0
11853 /* enum: The system clock domain doesn't exist */
11854 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0
11855 /* Resulting inter-core frequency in MHz */
11856 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4
11857 /* enum: The inter-core clock domain doesn't exist / isn't used */
11858 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0
11859 /* Resulting DPCPU frequency in MHz */
11860 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8
11861 /* enum: The dpcpu clock domain doesn't exist */
11862 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0
11863 /* Resulting PCS frequency in MHz */
11864 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12
11865 /* enum: The PCS clock domain doesn't exist / isn't controlled */
11866 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0
11867 /* Resulting MC frequency in MHz */
11868 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16
11869 /* enum: The MC clock domain doesn't exist / isn't controlled */
11870 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0
11871 /* Resulting rmon frequency in MHz */
11872 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20
11873 /* enum: The rmon clock domain doesn't exist / isn't controlled */
11874 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0
11875 /* Resulting vswitch frequency in MHz */
11876 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24
11877 /* enum: The vswitch clock domain doesn't exist / isn't controlled */
11878 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0
11881 /***********************************/
11882 /* MC_CMD_DPCPU_RPC
11883 * Send an arbitrary DPCPU message.
11885 #define MC_CMD_DPCPU_RPC 0xae
11886 #undef MC_CMD_0xae_PRIVILEGE_CTG
11888 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11890 /* MC_CMD_DPCPU_RPC_IN msgrequest */
11891 #define MC_CMD_DPCPU_RPC_IN_LEN 36
11892 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0
11893 /* enum: RxDPCPU0 */
11894 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0
11895 /* enum: TxDPCPU0 */
11896 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
11897 /* enum: TxDPCPU1 */
11898 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
11899 /* enum: RxDPCPU1 (Medford only) */
11900 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3
11901 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of
11904 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80
11905 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of
11908 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81
11909 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be
11910 * initialised to zero
11912 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4
11913 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32
11914 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8
11915 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8
11916 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
11917 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
11918 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
11919 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
11920 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
11921 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
11922 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
11923 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
11924 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
11925 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16
11926 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16
11927 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16
11928 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16
11929 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48
11930 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16
11931 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16
11932 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240
11933 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16
11934 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16
11935 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
11936 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
11937 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
11938 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
11939 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
11940 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48
11941 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16
11942 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64
11943 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16
11944 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80
11945 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16
11946 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16
11947 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16
11948 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
11949 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
11950 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
11951 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64
11952 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16
11953 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12
11954 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24
11955 /* Register data to write. Only valid in write/write-read. */
11956 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16
11957 /* Register address. */
11958 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20
11960 /* MC_CMD_DPCPU_RPC_OUT msgresponse */
11961 #define MC_CMD_DPCPU_RPC_OUT_LEN 36
11962 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0
11964 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4
11965 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32
11966 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32
11967 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16
11968 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48
11969 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16
11970 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12
11971 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24
11972 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12
11973 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16
11974 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20
11975 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24
11978 /***********************************/
11979 /* MC_CMD_TRIGGER_INTERRUPT
11980 * Trigger an interrupt by prodding the BIU.
11982 #define MC_CMD_TRIGGER_INTERRUPT 0xe3
11983 #undef MC_CMD_0xe3_PRIVILEGE_CTG
11985 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11987 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */
11988 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
11989 /* Interrupt level relative to base for function. */
11990 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
11992 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */
11993 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
11996 /***********************************/
11997 /* MC_CMD_SHMBOOT_OP
11998 * Special operations to support (for now) shmboot.
12000 #define MC_CMD_SHMBOOT_OP 0xe6
12001 #undef MC_CMD_0xe6_PRIVILEGE_CTG
12003 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12005 /* MC_CMD_SHMBOOT_OP_IN msgrequest */
12006 #define MC_CMD_SHMBOOT_OP_IN_LEN 4
12007 /* Identifies the operation to perform */
12008 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0
12009 /* enum: Copy slave_data section to the slave core. (Greenport only) */
12010 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0
12012 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */
12013 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0
12016 /***********************************/
12017 /* MC_CMD_CAP_BLK_READ
12018 * Read multiple 64bit words from capture block memory
12020 #define MC_CMD_CAP_BLK_READ 0xe7
12021 #undef MC_CMD_0xe7_PRIVILEGE_CTG
12023 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12025 /* MC_CMD_CAP_BLK_READ_IN msgrequest */
12026 #define MC_CMD_CAP_BLK_READ_IN_LEN 12
12027 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0
12028 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4
12029 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8
12031 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */
12032 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8
12033 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248
12034 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))
12035 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
12036 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8
12037 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
12038 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
12039 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
12040 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31
12043 /***********************************/
12045 * Take a dump of the DUT state
12047 #define MC_CMD_DUMP_DO 0xe8
12048 #undef MC_CMD_0xe8_PRIVILEGE_CTG
12050 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12052 /* MC_CMD_DUMP_DO_IN msgrequest */
12053 #define MC_CMD_DUMP_DO_IN_LEN 52
12054 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0
12055 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
12056 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
12057 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
12058 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
12059 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
12060 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
12061 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
12062 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
12063 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
12064 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
12065 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
12066 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
12067 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
12068 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
12069 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
12070 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
12071 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
12072 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
12073 /* enum: The uart port this command was received over (if using a uart
12076 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
12077 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
12078 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28
12079 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
12080 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
12081 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
12082 /* Enum values, see field(s): */
12083 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
12084 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
12085 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
12086 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
12087 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
12088 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
12089 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
12090 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
12091 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
12092 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
12094 /* MC_CMD_DUMP_DO_OUT msgresponse */
12095 #define MC_CMD_DUMP_DO_OUT_LEN 4
12096 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
12099 /***********************************/
12100 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED
12101 * Configure unsolicited dumps
12103 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
12104 #undef MC_CMD_0xe9_PRIVILEGE_CTG
12106 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12108 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */
12109 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52
12110 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
12111 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
12112 /* Enum values, see field(s): */
12113 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */
12114 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
12115 /* Enum values, see field(s): */
12116 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
12117 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
12118 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
12119 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
12120 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
12121 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
12122 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
12123 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
12124 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
12125 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
12126 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28
12127 /* Enum values, see field(s): */
12128 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */
12129 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
12130 /* Enum values, see field(s): */
12131 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
12132 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
12133 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
12134 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
12135 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
12136 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
12137 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
12138 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
12139 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
12140 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
12143 /***********************************/
12145 * Adjusts power supply parameters. This is a warranty-voiding operation.
12146 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if
12147 * the parameter is out of range.
12149 #define MC_CMD_SET_PSU 0xea
12150 #undef MC_CMD_0xea_PRIVILEGE_CTG
12152 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12154 /* MC_CMD_SET_PSU_IN msgrequest */
12155 #define MC_CMD_SET_PSU_IN_LEN 12
12156 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0
12157 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
12158 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4
12159 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
12160 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
12161 /* desired value, eg voltage in mV */
12162 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8
12164 /* MC_CMD_SET_PSU_OUT msgresponse */
12165 #define MC_CMD_SET_PSU_OUT_LEN 0
12168 /***********************************/
12169 /* MC_CMD_GET_FUNCTION_INFO
12170 * Get function information. PF and VF number.
12172 #define MC_CMD_GET_FUNCTION_INFO 0xec
12173 #undef MC_CMD_0xec_PRIVILEGE_CTG
12175 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12177 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */
12178 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
12180 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */
12181 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8
12182 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
12183 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
12186 /***********************************/
12187 /* MC_CMD_ENABLE_OFFLINE_BIST
12188 * Enters offline BIST mode. All queues are torn down, chip enters quiescent
12189 * mode, calling function gets exclusive MCDI ownership. The only way out is
12192 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed
12193 #undef MC_CMD_0xed_PRIVILEGE_CTG
12195 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12197 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */
12198 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
12200 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */
12201 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
12204 /***********************************/
12205 /* MC_CMD_UART_SEND_DATA
12206 * Send checksummed[sic] block of data over the uart. Response is a placeholder
12207 * should we wish to make this reliable; currently requests are fire-and-
12210 #define MC_CMD_UART_SEND_DATA 0xee
12211 #undef MC_CMD_0xee_PRIVILEGE_CTG
12213 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12215 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */
12216 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16
12217 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252
12218 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))
12219 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */
12220 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0
12221 /* Offset at which to write the data */
12222 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4
12223 /* Length of data */
12224 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8
12225 /* Reserved for future use */
12226 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12
12227 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16
12228 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1
12229 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0
12230 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236
12232 /* MC_CMD_UART_SEND_DATA_IN msgresponse */
12233 #define MC_CMD_UART_SEND_DATA_IN_LEN 0
12236 /***********************************/
12237 /* MC_CMD_UART_RECV_DATA
12238 * Request checksummed[sic] block of data over the uart. Only a placeholder,
12239 * subject to change and not currently implemented.
12241 #define MC_CMD_UART_RECV_DATA 0xef
12242 #undef MC_CMD_0xef_PRIVILEGE_CTG
12244 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12246 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */
12247 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16
12248 /* CRC32 over OFFSET, LENGTH, RESERVED */
12249 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0
12250 /* Offset from which to read the data */
12251 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4
12252 /* Length of data */
12253 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8
12254 /* Reserved for future use */
12255 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12
12257 /* MC_CMD_UART_RECV_DATA_IN msgresponse */
12258 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16
12259 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252
12260 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))
12261 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */
12262 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0
12263 /* Offset at which to write the data */
12264 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4
12265 /* Length of data */
12266 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8
12267 /* Reserved for future use */
12268 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12
12269 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16
12270 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1
12271 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0
12272 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236
12275 /***********************************/
12276 /* MC_CMD_READ_FUSES
12277 * Read data programmed into the device One-Time-Programmable (OTP) Fuses
12279 #define MC_CMD_READ_FUSES 0xf0
12280 #undef MC_CMD_0xf0_PRIVILEGE_CTG
12282 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12284 /* MC_CMD_READ_FUSES_IN msgrequest */
12285 #define MC_CMD_READ_FUSES_IN_LEN 8
12286 /* Offset in OTP to read */
12287 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
12288 /* Length of data to read in bytes */
12289 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
12291 /* MC_CMD_READ_FUSES_OUT msgresponse */
12292 #define MC_CMD_READ_FUSES_OUT_LENMIN 4
12293 #define MC_CMD_READ_FUSES_OUT_LENMAX 252
12294 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
12295 /* Length of returned OTP data in bytes */
12296 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
12297 /* Returned data */
12298 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4
12299 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1
12300 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
12301 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248
12304 /***********************************/
12306 * Get or set KR Serdes RXEQ and TX Driver settings
12308 #define MC_CMD_KR_TUNE 0xf1
12309 #undef MC_CMD_0xf1_PRIVILEGE_CTG
12311 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12313 /* MC_CMD_KR_TUNE_IN msgrequest */
12314 #define MC_CMD_KR_TUNE_IN_LENMIN 4
12315 #define MC_CMD_KR_TUNE_IN_LENMAX 252
12316 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
12317 /* Requested operation */
12318 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
12319 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
12320 /* enum: Get current RXEQ settings */
12321 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
12322 /* enum: Override RXEQ settings */
12323 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
12324 /* enum: Get current TX Driver settings */
12325 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
12326 /* enum: Override TX Driver settings */
12327 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
12328 /* enum: Force KR Serdes reset / recalibration */
12329 #define MC_CMD_KR_TUNE_IN_RECAL 0x4
12330 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid
12333 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
12334 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The
12335 * caller should call this command repeatedly after starting eye plot, until no
12336 * more data is returned.
12338 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
12339 /* enum: Read Figure Of Merit (eye quality, higher is better). */
12340 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7
12341 /* Align the arguments to 32 bits */
12342 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
12343 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3
12344 /* Arguments specific to the operation */
12345 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
12346 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
12347 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
12348 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62
12350 /* MC_CMD_KR_TUNE_OUT msgresponse */
12351 #define MC_CMD_KR_TUNE_OUT_LEN 0
12353 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */
12354 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
12355 /* Requested operation */
12356 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
12357 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1
12358 /* Align the arguments to 32 bits */
12359 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
12360 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
12362 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */
12363 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
12364 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252
12365 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
12366 /* RXEQ Parameter */
12367 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
12368 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
12369 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
12370 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
12371 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
12372 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
12373 /* enum: Attenuation (0-15, Huntington) */
12374 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
12375 /* enum: CTLE Boost (0-15, Huntington) */
12376 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
12377 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
12378 * positive, Medford - 0-31)
12380 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
12381 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
12382 * positive, Medford - 0-31)
12384 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
12385 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
12386 * positive, Medford - 0-16)
12388 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
12389 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
12390 * positive, Medford - 0-16)
12392 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
12393 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
12394 * positive, Medford - 0-16)
12396 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
12397 /* enum: Edge DFE DLEV (0-128 for Medford) */
12398 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
12399 /* enum: Variable Gain Amplifier (0-15, Medford) */
12400 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
12401 /* enum: CTLE EQ Capacitor (0-15, Medford) */
12402 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
12403 /* enum: CTLE EQ Resistor (0-7, Medford) */
12404 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
12405 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
12406 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3
12407 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
12408 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
12409 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
12410 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
12411 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
12412 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11
12413 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
12414 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
12415 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
12416 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16
12417 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
12418 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
12419 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
12421 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */
12422 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8
12423 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252
12424 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
12425 /* Requested operation */
12426 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
12427 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
12428 /* Align the arguments to 32 bits */
12429 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
12430 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
12431 /* RXEQ Parameter */
12432 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
12433 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
12434 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
12435 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
12436 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
12437 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
12438 /* Enum values, see field(s): */
12439 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */
12440 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
12441 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3
12442 /* Enum values, see field(s): */
12443 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */
12444 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11
12445 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
12446 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12
12447 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
12448 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
12449 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
12450 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
12451 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
12453 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */
12454 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
12456 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */
12457 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4
12458 /* Requested operation */
12459 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0
12460 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1
12461 /* Align the arguments to 32 bits */
12462 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
12463 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
12465 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */
12466 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
12467 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252
12468 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
12469 /* TXEQ Parameter */
12470 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
12471 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
12472 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
12473 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
12474 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
12475 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
12476 /* enum: TX Amplitude (Huntington, Medford) */
12477 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
12478 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
12479 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
12480 /* enum: De-Emphasis Tap1 Fine */
12481 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
12482 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
12483 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
12484 /* enum: De-Emphasis Tap2 Fine (Huntington) */
12485 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
12486 /* enum: Pre-Emphasis Magnitude (Huntington) */
12487 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
12488 /* enum: Pre-Emphasis Fine (Huntington) */
12489 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
12490 /* enum: TX Slew Rate Coarse control (Huntington) */
12491 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
12492 /* enum: TX Slew Rate Fine control (Huntington) */
12493 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
12494 /* enum: TX Termination Impedance control (Huntington) */
12495 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
12496 /* enum: TX Amplitude Fine control (Medford) */
12497 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
12498 /* enum: Pre-shoot Tap (Medford) */
12499 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
12500 /* enum: De-emphasis Tap (Medford) */
12501 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
12502 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
12503 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3
12504 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
12505 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
12506 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
12507 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
12508 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
12509 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11
12510 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5
12511 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16
12512 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
12513 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24
12514 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8
12516 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */
12517 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8
12518 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252
12519 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
12520 /* Requested operation */
12521 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
12522 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1
12523 /* Align the arguments to 32 bits */
12524 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
12525 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
12526 /* TXEQ Parameter */
12527 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4
12528 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
12529 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1
12530 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62
12531 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
12532 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8
12533 /* Enum values, see field(s): */
12534 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */
12535 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8
12536 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3
12537 /* Enum values, see field(s): */
12538 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */
12539 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11
12540 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5
12541 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16
12542 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
12543 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24
12544 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8
12546 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */
12547 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0
12549 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */
12550 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4
12551 /* Requested operation */
12552 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
12553 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1
12554 /* Align the arguments to 32 bits */
12555 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1
12556 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3
12558 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */
12559 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
12561 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */
12562 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8
12563 /* Requested operation */
12564 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
12565 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
12566 /* Align the arguments to 32 bits */
12567 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
12568 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
12569 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
12571 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */
12572 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0
12574 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */
12575 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4
12576 /* Requested operation */
12577 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
12578 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
12579 /* Align the arguments to 32 bits */
12580 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
12581 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
12583 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */
12584 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
12585 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
12586 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
12587 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
12588 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
12589 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
12590 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
12592 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */
12593 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8
12594 /* Requested operation */
12595 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0
12596 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1
12597 /* Align the arguments to 32 bits */
12598 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1
12599 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3
12600 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
12602 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */
12603 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4
12604 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0
12607 /***********************************/
12608 /* MC_CMD_PCIE_TUNE
12609 * Get or set PCIE Serdes RXEQ and TX Driver settings
12611 #define MC_CMD_PCIE_TUNE 0xf2
12612 #undef MC_CMD_0xf2_PRIVILEGE_CTG
12614 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12616 /* MC_CMD_PCIE_TUNE_IN msgrequest */
12617 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4
12618 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252
12619 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
12620 /* Requested operation */
12621 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
12622 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
12623 /* enum: Get current RXEQ settings */
12624 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
12625 /* enum: Override RXEQ settings */
12626 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
12627 /* enum: Get current TX Driver settings */
12628 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
12629 /* enum: Override TX Driver settings */
12630 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
12631 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */
12632 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5
12633 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The
12634 * caller should call this command repeatedly after starting eye plot, until no
12635 * more data is returned.
12637 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6
12638 /* Align the arguments to 32 bits */
12639 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1
12640 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3
12641 /* Arguments specific to the operation */
12642 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4
12643 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4
12644 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0
12645 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62
12647 /* MC_CMD_PCIE_TUNE_OUT msgresponse */
12648 #define MC_CMD_PCIE_TUNE_OUT_LEN 0
12650 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */
12651 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4
12652 /* Requested operation */
12653 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
12654 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
12655 /* Align the arguments to 32 bits */
12656 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
12657 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
12659 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */
12660 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4
12661 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252
12662 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
12663 /* RXEQ Parameter */
12664 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
12665 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
12666 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
12667 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
12668 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
12669 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
12670 /* enum: Attenuation (0-15) */
12671 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
12672 /* enum: CTLE Boost (0-15) */
12673 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
12674 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
12675 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
12676 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
12677 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
12678 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
12679 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
12680 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
12681 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
12682 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
12683 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
12684 /* enum: DFE DLev */
12685 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7
12686 /* enum: Figure of Merit */
12687 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8
12688 /* enum: CTLE EQ Capacitor (HF Gain) */
12689 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
12690 /* enum: CTLE EQ Resistor (DC Gain) */
12691 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
12692 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
12693 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5
12694 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
12695 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
12696 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
12697 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
12698 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
12699 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
12700 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
12701 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
12702 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */
12703 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */
12704 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */
12705 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */
12706 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */
12707 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */
12708 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
12709 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
12710 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
12711 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13
12712 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
12713 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14
12714 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10
12715 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
12716 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
12718 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */
12719 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8
12720 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252
12721 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
12722 /* Requested operation */
12723 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0
12724 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1
12725 /* Align the arguments to 32 bits */
12726 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1
12727 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3
12728 /* RXEQ Parameter */
12729 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4
12730 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4
12731 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
12732 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
12733 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
12734 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
12735 /* Enum values, see field(s): */
12736 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */
12737 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
12738 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5
12739 /* Enum values, see field(s): */
12740 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
12741 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13
12742 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
12743 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14
12744 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2
12745 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
12746 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
12747 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
12748 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
12750 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */
12751 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0
12753 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */
12754 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4
12755 /* Requested operation */
12756 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
12757 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
12758 /* Align the arguments to 32 bits */
12759 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
12760 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
12762 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */
12763 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4
12764 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252
12765 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
12766 /* RXEQ Parameter */
12767 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
12768 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
12769 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
12770 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
12771 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
12772 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
12773 /* enum: TxMargin (PIPE) */
12774 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
12775 /* enum: TxSwing (PIPE) */
12776 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
12777 /* enum: De-emphasis coefficient C(-1) (PIPE) */
12778 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
12779 /* enum: De-emphasis coefficient C(0) (PIPE) */
12780 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
12781 /* enum: De-emphasis coefficient C(+1) (PIPE) */
12782 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
12783 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
12784 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
12785 /* Enum values, see field(s): */
12786 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
12787 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12
12788 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12
12789 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24
12790 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
12792 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */
12793 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8
12794 /* Requested operation */
12795 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
12796 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
12797 /* Align the arguments to 32 bits */
12798 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
12799 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
12800 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
12802 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */
12803 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0
12805 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */
12806 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4
12807 /* Requested operation */
12808 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
12809 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
12810 /* Align the arguments to 32 bits */
12811 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
12812 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
12814 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */
12815 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
12816 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
12817 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
12818 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
12819 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
12820 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
12821 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
12824 /***********************************/
12825 /* MC_CMD_LICENSING
12826 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
12827 * - not used for V3 licensing
12829 #define MC_CMD_LICENSING 0xf3
12830 #undef MC_CMD_0xf3_PRIVILEGE_CTG
12832 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12834 /* MC_CMD_LICENSING_IN msgrequest */
12835 #define MC_CMD_LICENSING_IN_LEN 4
12836 /* identifies the type of operation requested */
12837 #define MC_CMD_LICENSING_IN_OP_OFST 0
12838 /* enum: re-read and apply licenses after a license key partition update; note
12839 * that this operation returns a zero-length response
12841 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
12842 /* enum: report counts of installed licenses */
12843 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
12845 /* MC_CMD_LICENSING_OUT msgresponse */
12846 #define MC_CMD_LICENSING_OUT_LEN 28
12847 /* count of application keys which are valid */
12848 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
12849 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with
12850 * MC_CMD_FC_OP_LICENSE)
12852 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
12853 /* count of application keys which are invalid due to being blacklisted */
12854 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8
12855 /* count of application keys which are invalid due to being unverifiable */
12856 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12
12857 /* count of application keys which are invalid due to being for the wrong node
12859 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16
12860 /* licensing state (for diagnostics; the exact meaning of the bits in this
12861 * field are private to the firmware)
12863 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20
12864 /* licensing subsystem self-test report (for manftest) */
12865 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24
12866 /* enum: licensing subsystem self-test failed */
12867 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
12868 /* enum: licensing subsystem self-test passed */
12869 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
12872 /***********************************/
12873 /* MC_CMD_LICENSING_V3
12874 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
12875 * - V3 licensing (Medford)
12877 #define MC_CMD_LICENSING_V3 0xd0
12878 #undef MC_CMD_0xd0_PRIVILEGE_CTG
12880 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12882 /* MC_CMD_LICENSING_V3_IN msgrequest */
12883 #define MC_CMD_LICENSING_V3_IN_LEN 4
12884 /* identifies the type of operation requested */
12885 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0
12886 /* enum: re-read and apply licenses after a license key partition update; note
12887 * that this operation returns a zero-length response
12889 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
12890 /* enum: report counts of installed licenses */
12891 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
12893 /* MC_CMD_LICENSING_V3_OUT msgresponse */
12894 #define MC_CMD_LICENSING_V3_OUT_LEN 88
12895 /* count of keys which are valid */
12896 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
12897 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with
12898 * MC_CMD_FC_OP_LICENSE)
12900 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
12901 /* count of keys which are invalid due to being unverifiable */
12902 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8
12903 /* count of keys which are invalid due to being for the wrong node */
12904 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12
12905 /* licensing state (for diagnostics; the exact meaning of the bits in this
12906 * field are private to the firmware)
12908 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16
12909 /* licensing subsystem self-test report (for manftest) */
12910 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20
12911 /* enum: licensing subsystem self-test failed */
12912 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
12913 /* enum: licensing subsystem self-test passed */
12914 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
12915 /* bitmask of licensed applications */
12916 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24
12917 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8
12918 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24
12919 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28
12920 /* reserved for future use */
12921 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32
12922 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24
12923 /* bitmask of licensed features */
12924 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56
12925 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8
12926 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56
12927 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60
12928 /* reserved for future use */
12929 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64
12930 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24
12933 /***********************************/
12934 /* MC_CMD_LICENSING_GET_ID_V3
12935 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license
12936 * partition - V3 licensing (Medford)
12938 #define MC_CMD_LICENSING_GET_ID_V3 0xd1
12939 #undef MC_CMD_0xd1_PRIVILEGE_CTG
12941 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12943 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */
12944 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0
12946 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */
12947 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8
12948 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252
12949 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))
12950 /* type of license (eg 3) */
12951 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
12952 /* length of the license ID (in bytes) */
12953 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4
12954 /* the unique license ID of the adapter */
12955 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8
12956 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1
12957 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0
12958 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244
12961 /***********************************/
12962 /* MC_CMD_MC2MC_PROXY
12963 * Execute an arbitrary MCDI command on the slave MC of a dual-core device.
12964 * This will fail on a single-core system.
12966 #define MC_CMD_MC2MC_PROXY 0xf4
12967 #undef MC_CMD_0xf4_PRIVILEGE_CTG
12969 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12971 /* MC_CMD_MC2MC_PROXY_IN msgrequest */
12972 #define MC_CMD_MC2MC_PROXY_IN_LEN 0
12974 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */
12975 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0
12978 /***********************************/
12979 /* MC_CMD_GET_LICENSED_APP_STATE
12980 * Query the state of an individual licensed application. (Note that the actual
12981 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation
12982 * or a reboot of the MC.) Not used for V3 licensing
12984 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5
12985 #undef MC_CMD_0xf5_PRIVILEGE_CTG
12987 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12989 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */
12990 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
12991 /* application ID to query (LICENSED_APP_ID_xxx) */
12992 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
12994 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */
12995 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
12996 /* state of this application */
12997 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
12998 /* enum: no (or invalid) license is present for the application */
12999 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
13000 /* enum: a valid license is present for the application */
13001 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
13004 /***********************************/
13005 /* MC_CMD_GET_LICENSED_V3_APP_STATE
13006 * Query the state of an individual licensed application. (Note that the actual
13007 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
13008 * operation or a reboot of the MC.) Used for V3 licensing (Medford)
13010 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
13011 #undef MC_CMD_0xd2_PRIVILEGE_CTG
13013 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13015 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */
13016 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8
13017 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit
13020 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
13021 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8
13022 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
13023 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
13025 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */
13026 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
13027 /* state of this application */
13028 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0
13029 /* enum: no (or invalid) license is present for the application */
13030 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
13031 /* enum: a valid license is present for the application */
13032 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1
13035 /***********************************/
13036 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES
13037 * Query the state of an one or more licensed features. (Note that the actual
13038 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
13039 * operation or a reboot of the MC.) Used for V3 licensing (Medford)
13041 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
13042 #undef MC_CMD_0xd3_PRIVILEGE_CTG
13044 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13046 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */
13047 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8
13048 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or
13051 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
13052 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8
13053 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
13054 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
13056 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */
13057 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8
13058 /* states of these features - bit set for licensed, clear for not licensed */
13059 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
13060 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8
13061 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
13062 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
13065 /***********************************/
13066 /* MC_CMD_LICENSED_APP_OP
13067 * Perform an action for an individual licensed application - not used for V3
13070 #define MC_CMD_LICENSED_APP_OP 0xf6
13071 #undef MC_CMD_0xf6_PRIVILEGE_CTG
13073 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13075 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */
13076 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8
13077 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252
13078 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
13079 /* application ID */
13080 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
13081 /* the type of operation requested */
13082 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
13083 /* enum: validate application */
13084 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
13085 /* enum: mask application */
13086 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
13087 /* arguments specific to this particular operation */
13088 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8
13089 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
13090 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
13091 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61
13093 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */
13094 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
13095 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252
13096 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
13097 /* result specific to this particular operation */
13098 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
13099 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
13100 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
13101 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63
13103 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */
13104 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72
13105 /* application ID */
13106 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0
13107 /* the type of operation requested */
13108 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4
13109 /* validation challenge */
13110 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8
13111 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64
13113 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */
13114 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68
13115 /* feature expiry (time_t) */
13116 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0
13117 /* validation response */
13118 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4
13119 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64
13121 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */
13122 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12
13123 /* application ID */
13124 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0
13125 /* the type of operation requested */
13126 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4
13128 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8
13130 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */
13131 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0
13134 /***********************************/
13135 /* MC_CMD_LICENSED_V3_VALIDATE_APP
13136 * Perform validation for an individual licensed application - V3 licensing
13139 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
13140 #undef MC_CMD_0xd4_PRIVILEGE_CTG
13142 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13144 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */
13145 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 62
13146 /* challenge for validation (384 bits) */
13147 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0
13148 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48
13149 /* application ID expressed as a single bit mask */
13150 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48
13151 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8
13152 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48
13153 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52
13154 /* MAC address of the calling client MC_CMD_ERR_EPERM is returned if the
13155 * calling client is not allowed to use this MAC address.
13157 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_MACADDR_OFST 56
13158 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_MACADDR_LEN 6
13160 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */
13161 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 104
13162 /* validation response to challenge in the form of ECDSA signature consisting
13163 * of two 384-bit integers, r and s, in big-endian order. The signature signs a
13164 * SHA-384 digest of a message constructed from the concatenation of the input
13165 * message and the remaining fields of this output message, e.g. challenge[48
13166 * bytes] ... expiry_time[4 bytes] ...
13168 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0
13169 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96
13170 /* application expiry time */
13171 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96
13172 /* application expiry units */
13173 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100
13174 /* enum: expiry units are accounting units */
13175 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
13176 /* enum: expiry units are calendar days */
13177 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
13180 /***********************************/
13181 /* MC_CMD_LICENSED_V3_MASK_FEATURES
13182 * Mask features - V3 licensing (Medford)
13184 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
13185 #undef MC_CMD_0xd5_PRIVILEGE_CTG
13187 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13189 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */
13190 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12
13191 /* mask to be applied to features to be changed */
13192 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
13193 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8
13194 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
13195 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
13196 /* whether to turn on or turn off the masked features */
13197 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8
13198 /* enum: turn the features off */
13199 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
13200 /* enum: turn the features back on */
13201 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1
13203 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */
13204 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0
13207 /***********************************/
13208 /* MC_CMD_LICENSING_V3_TEMPORARY
13209 * Perform operations to support installation of a single temporary license in
13210 * the adapter, in addition to those found in the licensing partition. See
13211 * SF-116124-SW for an overview of how this could be used. The license is
13212 * stored in MC persistent data and so will survive a MC reboot, but will be
13213 * erased when the adapter is power cycled
13215 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
13216 #undef MC_CMD_0xd6_PRIVILEGE_CTG
13218 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13220 /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */
13221 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4
13222 /* operation code */
13223 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0
13224 /* enum: install a new license, overwriting any existing temporary license.
13225 * This is an asynchronous operation owing to the time taken to validate an
13228 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
13229 /* enum: clear the license immediately rather than waiting for the next power
13232 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
13233 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET
13236 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2
13238 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */
13239 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164
13240 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0
13241 /* ECDSA license and signature */
13242 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4
13243 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160
13245 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */
13246 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4
13247 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0
13249 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */
13250 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4
13251 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0
13253 /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */
13254 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12
13256 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0
13257 /* enum: finished validating and installing license */
13258 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
13259 /* enum: license validation and installation in progress */
13260 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
13261 /* enum: licensing error. More specific error messages are not provided to
13262 * avoid exposing details of the licensing system to the client
13264 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
13265 /* bitmask of licensed features */
13266 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
13267 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8
13268 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
13269 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8
13272 /***********************************/
13273 /* MC_CMD_SET_PORT_SNIFF_CONFIG
13274 * Configure RX port sniffing for the physical port associated with the calling
13275 * function. Only a privileged function may change the port sniffing
13276 * configuration. A copy of all traffic delivered to the host (non-promiscuous
13277 * mode) or all traffic arriving at the port (promiscuous mode) may be
13278 * delivered to a specific queue, or a set of queues with RSS.
13280 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
13281 #undef MC_CMD_0xf7_PRIVILEGE_CTG
13283 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13285 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */
13286 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16
13287 /* configuration flags */
13288 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
13289 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
13290 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
13291 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1
13292 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1
13293 /* receive queue handle (for RSS mode, this is the base queue) */
13294 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
13296 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
13297 /* enum: receive to just the specified queue */
13298 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
13299 /* enum: receive to multiple queues using RSS context */
13300 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
13301 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
13302 * that these handles should be considered opaque to the host, although a value
13303 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
13305 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12
13307 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */
13308 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0
13311 /***********************************/
13312 /* MC_CMD_GET_PORT_SNIFF_CONFIG
13313 * Obtain the current RX port sniffing configuration for the physical port
13314 * associated with the calling function. Only a privileged function may read
13315 * the configuration.
13317 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
13318 #undef MC_CMD_0xf8_PRIVILEGE_CTG
13320 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13322 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */
13323 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0
13325 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */
13326 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16
13327 /* configuration flags */
13328 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
13329 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
13330 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
13331 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1
13332 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1
13333 /* receiving queue handle (for RSS mode, this is the base queue) */
13334 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
13336 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
13337 /* enum: receiving to just the specified queue */
13338 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
13339 /* enum: receiving to multiple queues using RSS context */
13340 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
13341 /* RSS context (for RX_MODE_RSS) */
13342 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
13345 /***********************************/
13346 /* MC_CMD_SET_PARSER_DISP_CONFIG
13347 * Change configuration related to the parser-dispatcher subsystem.
13349 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
13350 #undef MC_CMD_0xf9_PRIVILEGE_CTG
13352 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13354 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */
13355 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12
13356 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252
13357 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
13358 /* the type of configuration setting to change */
13359 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
13360 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible
13361 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.)
13363 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
13364 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the
13365 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single
13368 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
13369 /* handle for the entity to update: queue handle, EVB port ID, etc. depending
13370 * on the type of configuration setting being changed
13372 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
13373 /* new value: the details depend on the type of configuration setting being
13376 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8
13377 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
13378 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1
13379 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61
13381 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */
13382 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
13385 /***********************************/
13386 /* MC_CMD_GET_PARSER_DISP_CONFIG
13387 * Read configuration related to the parser-dispatcher subsystem.
13389 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
13390 #undef MC_CMD_0xfa_PRIVILEGE_CTG
13392 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13394 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */
13395 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8
13396 /* the type of configuration setting to read */
13397 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
13398 /* Enum values, see field(s): */
13399 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */
13400 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on
13401 * the type of configuration setting being read
13403 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
13405 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */
13406 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4
13407 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252
13408 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
13409 /* current value: the details depend on the type of configuration setting being
13412 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0
13413 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4
13414 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1
13415 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63
13418 /***********************************/
13419 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG
13420 * Configure TX port sniffing for the physical port associated with the calling
13421 * function. Only a privileged function may change the port sniffing
13422 * configuration. A copy of all traffic transmitted through the port may be
13423 * delivered to a specific queue, or a set of queues with RSS. Note that these
13424 * packets are delivered with transmit timestamps in the packet prefix, not
13425 * receive timestamps, so it is likely that the queue(s) will need to be
13426 * dedicated as TX sniff receivers.
13428 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
13429 #undef MC_CMD_0xfb_PRIVILEGE_CTG
13431 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13433 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
13434 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16
13435 /* configuration flags */
13436 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
13437 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
13438 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
13439 /* receive queue handle (for RSS mode, this is the base queue) */
13440 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
13442 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
13443 /* enum: receive to just the specified queue */
13444 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
13445 /* enum: receive to multiple queues using RSS context */
13446 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
13447 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
13448 * that these handles should be considered opaque to the host, although a value
13449 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
13451 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12
13453 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */
13454 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0
13457 /***********************************/
13458 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG
13459 * Obtain the current TX port sniffing configuration for the physical port
13460 * associated with the calling function. Only a privileged function may read
13461 * the configuration.
13463 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
13464 #undef MC_CMD_0xfc_PRIVILEGE_CTG
13466 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13468 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
13469 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0
13471 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */
13472 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16
13473 /* configuration flags */
13474 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
13475 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
13476 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
13477 /* receiving queue handle (for RSS mode, this is the base queue) */
13478 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
13480 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
13481 /* enum: receiving to just the specified queue */
13482 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
13483 /* enum: receiving to multiple queues using RSS context */
13484 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
13485 /* RSS context (for RX_MODE_RSS) */
13486 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
13489 /***********************************/
13490 /* MC_CMD_RMON_STATS_RX_ERRORS
13491 * Per queue rx error stats.
13493 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
13494 #undef MC_CMD_0xfe_PRIVILEGE_CTG
13496 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13498 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */
13499 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8
13500 /* The rx queue to get stats for. */
13501 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0
13502 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4
13503 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0
13504 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1
13506 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */
13507 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16
13508 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0
13509 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4
13510 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8
13511 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12
13514 /***********************************/
13515 /* MC_CMD_GET_PCIE_RESOURCE_INFO
13516 * Find out about available PCIE resources
13518 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
13520 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */
13521 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0
13523 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */
13524 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28
13525 /* The maximum number of PFs the device can expose */
13526 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0
13527 /* The maximum number of VFs the device can expose in total */
13528 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4
13529 /* The maximum number of MSI-X vectors the device can provide in total */
13530 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8
13531 /* the number of MSI-X vectors the device will allocate by default to each PF
13533 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12
13534 /* the number of MSI-X vectors the device will allocate by default to each VF
13536 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16
13537 /* the maximum number of MSI-X vectors the device can allocate to any one PF */
13538 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20
13539 /* the maximum number of MSI-X vectors the device can allocate to any one VF */
13540 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24
13543 /***********************************/
13544 /* MC_CMD_GET_PORT_MODES
13545 * Find out about available port modes
13547 #define MC_CMD_GET_PORT_MODES 0xff
13548 #undef MC_CMD_0xff_PRIVILEGE_CTG
13550 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13552 /* MC_CMD_GET_PORT_MODES_IN msgrequest */
13553 #define MC_CMD_GET_PORT_MODES_IN_LEN 0
13555 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */
13556 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12
13557 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */
13558 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0
13559 /* Default (canonical) board mode */
13560 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4
13561 /* Current board mode */
13562 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8
13565 /***********************************/
13567 * Sample voltages on the ATB
13569 #define MC_CMD_READ_ATB 0x100
13570 #undef MC_CMD_0x100_PRIVILEGE_CTG
13572 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13574 /* MC_CMD_READ_ATB_IN msgrequest */
13575 #define MC_CMD_READ_ATB_IN_LEN 16
13576 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0
13577 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */
13578 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */
13579 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */
13580 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4
13581 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8
13582 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12
13584 /* MC_CMD_READ_ATB_OUT msgresponse */
13585 #define MC_CMD_READ_ATB_OUT_LEN 4
13586 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0
13589 /***********************************/
13590 /* MC_CMD_GET_WORKAROUNDS
13591 * Read the list of all implemented and all currently enabled workarounds. The
13592 * enums here must correspond with those in MC_CMD_WORKAROUND.
13594 #define MC_CMD_GET_WORKAROUNDS 0x59
13595 #undef MC_CMD_0x59_PRIVILEGE_CTG
13597 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13599 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */
13600 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8
13601 /* Each workaround is represented by a single bit according to the enums below.
13603 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
13604 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
13605 /* enum: Bug 17230 work around. */
13606 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
13607 /* enum: Bug 35388 work around (unsafe EVQ writes). */
13608 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
13609 /* enum: Bug35017 workaround (A64 tables must be identity map) */
13610 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
13611 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
13612 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
13613 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
13614 * - before adding code that queries this workaround, remember that there's
13615 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
13616 * and will hence (incorrectly) report that the bug doesn't exist.
13618 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
13619 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */
13620 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
13621 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
13622 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
13625 /***********************************/
13626 /* MC_CMD_PRIVILEGE_MASK
13627 * Read/set privileges of an arbitrary PCIe function
13629 #define MC_CMD_PRIVILEGE_MASK 0x5a
13630 #undef MC_CMD_0x5a_PRIVILEGE_CTG
13632 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13634 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */
13635 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8
13636 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
13639 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
13640 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
13641 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16
13642 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16
13643 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16
13644 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
13645 /* New privilege mask to be set. The mask will only be changed if the MSB is
13648 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
13649 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
13650 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
13651 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
13652 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
13653 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
13654 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */
13655 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
13656 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
13657 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
13658 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
13659 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
13660 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
13661 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC
13664 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
13665 /* enum: Privilege that allows a Function to change the MAC address configured
13666 * in its associated vAdapter/vPort.
13668 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
13669 /* enum: Privilege that allows a Function to install filters that specify VLANs
13670 * that are not in the permit list for the associated vPort. This privilege is
13671 * primarily to support ESX where vPorts are created that restrict traffic to
13672 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT.
13674 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
13675 /* enum: Set this bit to indicate that a new privilege mask is to be set,
13676 * otherwise the command will only read the existing mask.
13678 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
13680 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */
13681 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
13682 /* For an admin function, always all the privileges are reported. */
13683 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
13686 /***********************************/
13687 /* MC_CMD_LINK_STATE_MODE
13688 * Read/set link state mode of a VF
13690 #define MC_CMD_LINK_STATE_MODE 0x5c
13691 #undef MC_CMD_0x5c_PRIVILEGE_CTG
13693 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13695 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */
13696 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8
13697 /* The target function to have its link state mode read or set, must be a VF
13698 * e.g. VF 1,3 = 0x00030001
13700 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
13701 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
13702 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16
13703 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16
13704 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16
13705 /* New link state mode to be set */
13706 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
13707 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
13708 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
13709 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
13710 /* enum: Use this value to just read the existing setting without modifying it.
13712 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
13714 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */
13715 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
13716 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
13719 /***********************************/
13720 /* MC_CMD_GET_SNAPSHOT_LENGTH
13721 * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH
13722 * parameter to MC_CMD_INIT_RXQ.
13724 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
13725 #undef MC_CMD_0x101_PRIVILEGE_CTG
13727 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13729 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */
13730 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0
13732 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */
13733 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8
13734 /* Minimum acceptable snapshot length. */
13735 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0
13736 /* Maximum acceptable snapshot length. */
13737 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4
13740 /***********************************/
13741 /* MC_CMD_FUSE_DIAGS
13742 * Additional fuse diagnostics
13744 #define MC_CMD_FUSE_DIAGS 0x102
13745 #undef MC_CMD_0x102_PRIVILEGE_CTG
13747 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13749 /* MC_CMD_FUSE_DIAGS_IN msgrequest */
13750 #define MC_CMD_FUSE_DIAGS_IN_LEN 0
13752 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */
13753 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48
13754 /* Total number of mismatched bits between pairs in area 0 */
13755 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0
13756 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */
13757 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4
13758 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */
13759 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8
13760 /* Checksum of data after logical OR of pairs in area 0 */
13761 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12
13762 /* Total number of mismatched bits between pairs in area 1 */
13763 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16
13764 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */
13765 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20
13766 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */
13767 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24
13768 /* Checksum of data after logical OR of pairs in area 1 */
13769 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28
13770 /* Total number of mismatched bits between pairs in area 2 */
13771 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32
13772 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */
13773 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36
13774 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */
13775 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40
13776 /* Checksum of data after logical OR of pairs in area 2 */
13777 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44
13780 /***********************************/
13781 /* MC_CMD_PRIVILEGE_MODIFY
13782 * Modify the privileges of a set of PCIe functions. Note that this operation
13783 * only effects non-admin functions unless the admin privilege itself is
13784 * included in one of the masks provided.
13786 #define MC_CMD_PRIVILEGE_MODIFY 0x60
13787 #undef MC_CMD_0x60_PRIVILEGE_CTG
13789 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13791 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */
13792 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16
13793 /* The groups of functions to have their privilege masks modified. */
13794 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0
13795 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
13796 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
13797 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
13798 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
13799 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
13800 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
13801 /* For VFS_OF_PF specify the PF, for ONE specify the target function */
13802 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
13803 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0
13804 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16
13805 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16
13806 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16
13807 /* Privileges to be added to the target functions. For privilege definitions
13808 * refer to the command MC_CMD_PRIVILEGE_MASK
13810 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8
13811 /* Privileges to be removed from the target functions. For privilege
13812 * definitions refer to the command MC_CMD_PRIVILEGE_MASK
13814 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12
13816 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */
13817 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0
13820 /***********************************/
13821 /* MC_CMD_XPM_READ_BYTES
13824 #define MC_CMD_XPM_READ_BYTES 0x103
13825 #undef MC_CMD_0x103_PRIVILEGE_CTG
13827 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13829 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */
13830 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8
13831 /* Start address (byte) */
13832 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0
13833 /* Count (bytes) */
13834 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4
13836 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */
13837 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0
13838 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252
13839 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
13841 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0
13842 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1
13843 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0
13844 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252
13847 /***********************************/
13848 /* MC_CMD_XPM_WRITE_BYTES
13851 #define MC_CMD_XPM_WRITE_BYTES 0x104
13852 #undef MC_CMD_0x104_PRIVILEGE_CTG
13854 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13856 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */
13857 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8
13858 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252
13859 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num))
13860 /* Start address (byte) */
13861 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0
13862 /* Count (bytes) */
13863 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4
13865 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8
13866 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1
13867 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0
13868 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244
13870 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */
13871 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0
13874 /***********************************/
13875 /* MC_CMD_XPM_READ_SECTOR
13878 #define MC_CMD_XPM_READ_SECTOR 0x105
13879 #undef MC_CMD_0x105_PRIVILEGE_CTG
13881 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13883 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */
13884 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8
13886 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0
13888 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4
13890 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */
13891 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4
13892 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36
13893 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))
13895 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0
13896 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */
13897 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */
13898 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */
13899 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */
13901 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4
13902 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1
13903 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0
13904 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32
13907 /***********************************/
13908 /* MC_CMD_XPM_WRITE_SECTOR
13911 #define MC_CMD_XPM_WRITE_SECTOR 0x106
13912 #undef MC_CMD_0x106_PRIVILEGE_CTG
13914 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13916 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */
13917 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12
13918 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44
13919 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num))
13920 /* If writing fails due to an uncorrectable error, try up to RETRIES following
13921 * sectors (or until no more space available). If 0, only one write attempt is
13922 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair
13925 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0
13926 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1
13927 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1
13928 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3
13930 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4
13931 /* Enum values, see field(s): */
13932 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */
13934 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8
13936 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12
13937 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1
13938 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0
13939 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32
13941 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */
13942 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4
13943 /* New sector index */
13944 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0
13947 /***********************************/
13948 /* MC_CMD_XPM_INVALIDATE_SECTOR
13949 * Invalidate XPM sector
13951 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
13952 #undef MC_CMD_0x107_PRIVILEGE_CTG
13954 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13956 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */
13957 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4
13959 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0
13961 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */
13962 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0
13965 /***********************************/
13966 /* MC_CMD_XPM_BLANK_CHECK
13967 * Blank-check XPM memory and report bad locations
13969 #define MC_CMD_XPM_BLANK_CHECK 0x108
13970 #undef MC_CMD_0x108_PRIVILEGE_CTG
13972 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13974 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */
13975 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8
13976 /* Start address (byte) */
13977 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0
13978 /* Count (bytes) */
13979 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4
13981 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */
13982 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4
13983 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252
13984 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))
13985 /* Total number of bad (non-blank) locations */
13986 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0
13987 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit
13988 * into MCDI response)
13990 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4
13991 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2
13992 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0
13993 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124
13996 /***********************************/
13997 /* MC_CMD_XPM_REPAIR
13998 * Blank-check and repair XPM memory
14000 #define MC_CMD_XPM_REPAIR 0x109
14001 #undef MC_CMD_0x109_PRIVILEGE_CTG
14003 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14005 /* MC_CMD_XPM_REPAIR_IN msgrequest */
14006 #define MC_CMD_XPM_REPAIR_IN_LEN 8
14007 /* Start address (byte) */
14008 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0
14009 /* Count (bytes) */
14010 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4
14012 /* MC_CMD_XPM_REPAIR_OUT msgresponse */
14013 #define MC_CMD_XPM_REPAIR_OUT_LEN 0
14016 /***********************************/
14017 /* MC_CMD_XPM_DECODER_TEST
14018 * Test XPM memory address decoders for gross manufacturing defects. Can only
14019 * be performed on an unprogrammed part.
14021 #define MC_CMD_XPM_DECODER_TEST 0x10a
14022 #undef MC_CMD_0x10a_PRIVILEGE_CTG
14024 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14026 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */
14027 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0
14029 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */
14030 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0
14033 /***********************************/
14034 /* MC_CMD_XPM_WRITE_TEST
14035 * XPM memory write test. Test XPM write logic for gross manufacturing defects
14036 * by writing to a dedicated test row. There are 16 locations in the test row
14037 * and the test can only be performed on locations that have not been
14038 * previously used (i.e. can be run at most 16 times). The test will pick the
14039 * first available location to use, or fail with ENOSPC if none left.
14041 #define MC_CMD_XPM_WRITE_TEST 0x10b
14042 #undef MC_CMD_0x10b_PRIVILEGE_CTG
14044 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14046 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */
14047 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0
14049 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */
14050 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0
14053 /***********************************/
14054 /* MC_CMD_EXEC_SIGNED
14055 * Check the CMAC of the contents of IMEM and DMEM against the value supplied
14056 * and if correct begin execution from the start of IMEM. The caller supplies a
14057 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC
14058 * computation runs from the start of IMEM, and from the start of DMEM + 16k,
14059 * to match flash booting. The command will respond with EINVAL if the CMAC
14060 * does match, otherwise it will respond with success before it jumps to IMEM.
14062 #define MC_CMD_EXEC_SIGNED 0x10c
14063 #undef MC_CMD_0x10c_PRIVILEGE_CTG
14065 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14067 /* MC_CMD_EXEC_SIGNED_IN msgrequest */
14068 #define MC_CMD_EXEC_SIGNED_IN_LEN 28
14069 /* the length of code to include in the CMAC */
14070 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0
14071 /* the length of date to include in the CMAC */
14072 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4
14073 /* the XPM sector containing the key to use */
14074 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8
14075 /* the expected CMAC value */
14076 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12
14077 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16
14079 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */
14080 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0
14083 /***********************************/
14084 /* MC_CMD_PREPARE_SIGNED
14085 * Prepare to upload a signed image. This will scrub the specified length of
14086 * the data region, which must be at least as large as the DATALEN supplied to
14087 * MC_CMD_EXEC_SIGNED.
14089 #define MC_CMD_PREPARE_SIGNED 0x10d
14090 #undef MC_CMD_0x10d_PRIVILEGE_CTG
14092 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14094 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */
14095 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4
14096 /* the length of data area to clear */
14097 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0
14099 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */
14100 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0
14103 /***********************************/
14104 /* MC_CMD_SET_SECURITY_RULE
14105 * Set blacklist and/or whitelist action for a particular match criteria.
14106 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
14107 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
14108 * been used in any released code and may change during development. This note
14109 * will be removed once it is regarded as stable.
14111 #define MC_CMD_SET_SECURITY_RULE 0x10f
14112 #undef MC_CMD_0x10f_PRIVILEGE_CTG
14114 #define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14116 /* MC_CMD_SET_SECURITY_RULE_IN msgrequest */
14117 #define MC_CMD_SET_SECURITY_RULE_IN_LEN 92
14118 /* fields to include in match criteria */
14119 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0
14120 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0
14121 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_WIDTH 1
14122 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_LBN 1
14123 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_WIDTH 1
14124 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_LBN 2
14125 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_WIDTH 1
14126 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_LBN 3
14127 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_WIDTH 1
14128 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_LBN 4
14129 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_WIDTH 1
14130 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_LBN 5
14131 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_WIDTH 1
14132 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_LBN 6
14133 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_WIDTH 1
14134 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_LBN 7
14135 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_WIDTH 1
14136 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_LBN 8
14137 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_WIDTH 1
14138 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_LBN 9
14139 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_WIDTH 1
14140 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_LBN 10
14141 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_WIDTH 1
14142 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_LBN 11
14143 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_WIDTH 1
14144 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_LBN 12
14145 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_WIDTH 1
14146 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_LBN 13
14147 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_WIDTH 1
14148 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_LBN 14
14149 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_WIDTH 1
14150 /* remote MAC address to match (as bytes in network order) */
14151 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_OFST 4
14152 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_LEN 6
14153 /* remote port to match (as bytes in network order) */
14154 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_OFST 10
14155 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_LEN 2
14156 /* local MAC address to match (as bytes in network order) */
14157 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_OFST 12
14158 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_LEN 6
14159 /* local port to match (as bytes in network order) */
14160 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_OFST 18
14161 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_LEN 2
14162 /* Ethernet type to match (as bytes in network order) */
14163 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_OFST 20
14164 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_LEN 2
14165 /* Inner VLAN tag to match (as bytes in network order) */
14166 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_OFST 22
14167 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_LEN 2
14168 /* Outer VLAN tag to match (as bytes in network order) */
14169 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_OFST 24
14170 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_LEN 2
14171 /* IP protocol to match (in low byte; set high byte to 0) */
14172 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_OFST 26
14173 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_LEN 2
14174 /* Physical port to match (as little-endian 32-bit value) */
14175 #define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_OFST 28
14176 /* Reserved; set to 0 */
14177 #define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_OFST 32
14178 /* remote IP address to match (as bytes in network order; set last 12 bytes to
14179 * 0 for IPv4 address)
14181 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_OFST 36
14182 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_LEN 16
14183 /* local IP address to match (as bytes in network order; set last 12 bytes to 0
14184 * for IPv4 address)
14186 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_OFST 52
14187 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_LEN 16
14188 /* remote subnet ID to match (as little-endian 32-bit value); note that remote
14189 * subnets are matched by mapping the remote IP address to a "subnet ID" via a
14190 * data structure which must already have been configured using
14191 * MC_CMD_SUBNET_MAP_SET_NODE appropriately
14193 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_OFST 68
14194 /* remote portrange ID to match (as little-endian 32-bit value); note that
14195 * remote port ranges are matched by mapping the remote port to a "portrange
14196 * ID" via a data structure which must already have been configured using
14197 * MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE
14199 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_OFST 72
14200 /* local portrange ID to match (as little-endian 32-bit value); note that local
14201 * port ranges are matched by mapping the local port to a "portrange ID" via a
14202 * data structure which must already have been configured using
14203 * MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE
14205 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_OFST 76
14206 /* set the action for transmitted packets matching this rule */
14207 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_OFST 80
14208 /* enum: make no decision */
14209 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE 0x0
14210 /* enum: decide to accept the packet */
14211 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST 0x1
14212 /* enum: decide to drop the packet */
14213 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST 0x2
14214 /* enum: do not change the current TX action */
14215 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED 0xffffffff
14216 /* set the action for received packets matching this rule */
14217 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_OFST 84
14218 /* enum: make no decision */
14219 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE 0x0
14220 /* enum: decide to accept the packet */
14221 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST 0x1
14222 /* enum: decide to drop the packet */
14223 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST 0x2
14224 /* enum: do not change the current RX action */
14225 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED 0xffffffff
14226 /* counter ID to associate with this rule; IDs are allocated using
14227 * MC_CMD_SECURITY_RULE_COUNTER_ALLOC
14229 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_OFST 88
14230 /* enum: special value for the null counter ID */
14231 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE 0x0
14233 /* MC_CMD_SET_SECURITY_RULE_OUT msgresponse */
14234 #define MC_CMD_SET_SECURITY_RULE_OUT_LEN 28
14235 /* new reference count for uses of counter ID */
14236 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_OFST 0
14237 /* constructed match bits for this rule (as a tracing aid only) */
14238 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_OFST 4
14239 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_LEN 12
14240 /* constructed discriminator bits for this rule (as a tracing aid only) */
14241 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_OFST 16
14242 /* base location for probes for this rule (as a tracing aid only) */
14243 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_OFST 20
14244 /* step for probes for this rule (as a tracing aid only) */
14245 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_OFST 24
14248 /***********************************/
14249 /* MC_CMD_RESET_SECURITY_RULES
14250 * Reset all blacklist and whitelist actions for a particular physical port, or
14251 * all ports. (Medford-only; for use by SolarSecure apps, not directly by
14252 * drivers. See SF-114946-SW.) NOTE - this message definition is provisional.
14253 * It has not yet been used in any released code and may change during
14254 * development. This note will be removed once it is regarded as stable.
14256 #define MC_CMD_RESET_SECURITY_RULES 0x110
14257 #undef MC_CMD_0x110_PRIVILEGE_CTG
14259 #define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14261 /* MC_CMD_RESET_SECURITY_RULES_IN msgrequest */
14262 #define MC_CMD_RESET_SECURITY_RULES_IN_LEN 4
14263 /* index of physical port to reset (or ALL_PHYSICAL_PORTS to reset all) */
14264 #define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0
14265 /* enum: special value to reset all physical ports */
14266 #define MC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS 0xffffffff
14268 /* MC_CMD_RESET_SECURITY_RULES_OUT msgresponse */
14269 #define MC_CMD_RESET_SECURITY_RULES_OUT_LEN 0
14272 /***********************************/
14273 /* MC_CMD_GET_SECURITY_RULESET_VERSION
14274 * Return a large hash value representing a "version" of the complete set of
14275 * currently active blacklist / whitelist rules and associated data structures.
14276 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
14277 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
14278 * been used in any released code and may change during development. This note
14279 * will be removed once it is regarded as stable.
14281 #define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111
14282 #undef MC_CMD_0x111_PRIVILEGE_CTG
14284 #define MC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14286 /* MC_CMD_GET_SECURITY_RULESET_VERSION_IN msgrequest */
14287 #define MC_CMD_GET_SECURITY_RULESET_VERSION_IN_LEN 0
14289 /* MC_CMD_GET_SECURITY_RULESET_VERSION_OUT msgresponse */
14290 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMIN 1
14291 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMAX 252
14292 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num))
14293 /* Opaque hash value; length may vary depending on the hash scheme used */
14294 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_OFST 0
14295 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_LEN 1
14296 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MINNUM 1
14297 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MAXNUM 252
14300 /***********************************/
14301 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC
14302 * Allocate counters for use with blacklist / whitelist rules. (Medford-only;
14303 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.)
14304 * NOTE - this message definition is provisional. It has not yet been used in
14305 * any released code and may change during development. This note will be
14306 * removed once it is regarded as stable.
14308 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112
14309 #undef MC_CMD_0x112_PRIVILEGE_CTG
14311 #define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14313 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN msgrequest */
14314 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_LEN 4
14315 /* the number of new counter IDs to request */
14316 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_OFST 0
14318 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT msgresponse */
14319 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMIN 4
14320 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMAX 252
14321 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LEN(num) (4+4*(num))
14322 /* the number of new counter IDs allocated (may be less than the number
14323 * requested if resources are unavailable)
14325 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_OFST 0
14326 /* new counter ID(s) */
14327 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 4
14328 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4
14329 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 0
14330 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 62
14333 /***********************************/
14334 /* MC_CMD_SECURITY_RULE_COUNTER_FREE
14335 * Allocate counters for use with blacklist / whitelist rules. (Medford-only;
14336 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.)
14337 * NOTE - this message definition is provisional. It has not yet been used in
14338 * any released code and may change during development. This note will be
14339 * removed once it is regarded as stable.
14341 #define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113
14342 #undef MC_CMD_0x113_PRIVILEGE_CTG
14344 #define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14346 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_IN msgrequest */
14347 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMIN 4
14348 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMAX 252
14349 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num))
14350 /* the number of counter IDs to free */
14351 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0
14352 /* the counter ID(s) to free */
14353 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_OFST 4
14354 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_LEN 4
14355 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MINNUM 0
14356 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MAXNUM 62
14358 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT msgresponse */
14359 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT_LEN 0
14362 /***********************************/
14363 /* MC_CMD_SUBNET_MAP_SET_NODE
14364 * Atomically update a trie node in the map of subnets to subnet IDs. The
14365 * constants in the descriptions of the fields of this message may be retrieved
14366 * by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. (Medford-
14367 * only; for use by SolarSecure apps, not directly by drivers. See
14368 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
14369 * been used in any released code and may change during development. This note
14370 * will be removed once it is regarded as stable.
14372 #define MC_CMD_SUBNET_MAP_SET_NODE 0x114
14373 #undef MC_CMD_0x114_PRIVILEGE_CTG
14375 #define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14377 /* MC_CMD_SUBNET_MAP_SET_NODE_IN msgrequest */
14378 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMIN 6
14379 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMAX 252
14380 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num))
14381 /* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */
14382 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0
14383 /* SUBNET_MAP_NUM_ENTRIES_PER_NODE new entries; each entry is either a pointer
14384 * to the next node, expressed as an offset in the trie memory (i.e. node ID
14385 * multiplied by SUBNET_MAP_NUM_ENTRIES_PER_NODE), or a leaf value in the range
14386 * SUBNET_ID_MIN .. SUBNET_ID_MAX
14388 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_OFST 4
14389 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_LEN 2
14390 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MINNUM 1
14391 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MAXNUM 124
14393 /* MC_CMD_SUBNET_MAP_SET_NODE_OUT msgresponse */
14394 #define MC_CMD_SUBNET_MAP_SET_NODE_OUT_LEN 0
14396 /* PORTRANGE_TREE_ENTRY structuredef */
14397 #define PORTRANGE_TREE_ENTRY_LEN 4
14398 /* key for branch nodes (<= key takes left branch, > key takes right branch),
14399 * or magic value for leaf nodes
14401 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_OFST 0
14402 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LEN 2
14403 #define PORTRANGE_TREE_ENTRY_LEAF_NODE_KEY 0xffff /* enum */
14404 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LBN 0
14405 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_WIDTH 16
14406 /* final portrange ID for leaf nodes (don't care for branch nodes) */
14407 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_OFST 2
14408 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LEN 2
14409 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LBN 16
14410 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_WIDTH 16
14413 /***********************************/
14414 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE
14415 * Atomically update the entire tree mapping remote port ranges to portrange
14416 * IDs. The constants in the descriptions of the fields of this message may be
14417 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO.
14418 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
14419 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
14420 * been used in any released code and may change during development. This note
14421 * will be removed once it is regarded as stable.
14423 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115
14424 #undef MC_CMD_0x115_PRIVILEGE_CTG
14426 #define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14428 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN msgrequest */
14429 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4
14430 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252
14431 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num))
14432 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a
14433 * PORTRANGE_TREE_ENTRY
14435 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0
14436 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4
14437 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1
14438 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63
14440 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT msgresponse */
14441 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT_LEN 0
14444 /***********************************/
14445 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE
14446 * Atomically update the entire tree mapping remote port ranges to portrange
14447 * IDs. The constants in the descriptions of the fields of this message may be
14448 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO.
14449 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
14450 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
14451 * been used in any released code and may change during development. This note
14452 * will be removed once it is regarded as stable.
14454 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116
14455 #undef MC_CMD_0x116_PRIVILEGE_CTG
14457 #define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14459 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN msgrequest */
14460 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4
14461 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252
14462 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num))
14463 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a
14464 * PORTRANGE_TREE_ENTRY
14466 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0
14467 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4
14468 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1
14469 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63
14471 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT msgresponse */
14472 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT_LEN 0
14474 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */
14475 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
14476 /* UDP port (the standard ports are named below but any port may be used) */
14477 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
14478 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2
14479 /* enum: the IANA allocated UDP port for VXLAN */
14480 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
14481 /* enum: the IANA allocated UDP port for Geneve */
14482 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
14483 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
14484 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16
14485 /* tunnel encapsulation protocol (only those named below are supported) */
14486 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2
14487 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2
14488 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */
14489 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
14490 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */
14491 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
14492 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16
14493 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16
14496 /***********************************/
14497 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS
14498 * Configure UDP ports for tunnel encapsulation hardware acceleration. The
14499 * parser-dispatcher will attempt to parse traffic on these ports as tunnel
14500 * encapsulation PDUs and filter them using the tunnel encapsulation filter
14501 * chain rather than the standard filter chain. Note that this command can
14502 * cause all functions to see a reset. (Available on Medford only.)
14504 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
14505 #undef MC_CMD_0x117_PRIVILEGE_CTG
14507 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14509 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */
14510 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
14511 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68
14512 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
14514 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
14515 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2
14516 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
14517 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1
14518 /* The number of entries in the ENTRIES array */
14519 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2
14520 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2
14521 /* Entries defining the UDP port to protocol mapping, each laid out as a
14522 * TUNNEL_ENCAP_UDP_PORT_ENTRY
14524 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
14525 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
14526 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
14527 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16
14529 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */
14530 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2
14532 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
14533 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2
14534 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
14535 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1
14538 /***********************************/
14539 /* MC_CMD_RX_BALANCING
14540 * Configure a port upconverter to distribute the packets on both RX engines.
14541 * Packets are distributed based on a table with the destination vFIFO. The
14542 * index of the table is a hash of source and destination of IPV4 and VLAN
14545 #define MC_CMD_RX_BALANCING 0x118
14546 #undef MC_CMD_0x118_PRIVILEGE_CTG
14548 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14550 /* MC_CMD_RX_BALANCING_IN msgrequest */
14551 #define MC_CMD_RX_BALANCING_IN_LEN 16
14552 /* The RX port whose upconverter table will be modified */
14553 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0
14554 /* The VLAN priority associated to the table index and vFIFO */
14555 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4
14556 /* The resulting bit of SRC^DST for indexing the table */
14557 #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8
14558 /* The RX engine to which the vFIFO in the table entry will point to */
14559 #define MC_CMD_RX_BALANCING_IN_ENG_OFST 12
14561 /* MC_CMD_RX_BALANCING_OUT msgresponse */
14562 #define MC_CMD_RX_BALANCING_OUT_LEN 0
14565 /***********************************/
14567 * TSAN - TSAC binding communication protocol. Refer to SF-115479-TC for more
14568 * info in respect to the binding protocol. Note- This MCDI command is only
14569 * available over a TLS secure connection between the TSAN and TSAC, and is not
14570 * available to host software.
14572 #define MC_CMD_TSA_BIND 0x119
14573 #undef MC_CMD_0x119_PRIVILEGE_CTG
14575 #define MC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14577 /* MC_CMD_TSA_BIND_IN msgrequest: Protocol operation code */
14578 #define MC_CMD_TSA_BIND_IN_LEN 4
14579 #define MC_CMD_TSA_BIND_IN_OP_OFST 0
14580 /* enum: Retrieve the TSAN ID from a TSAN. TSAN ID is a unique identifier for
14581 * the network adapter. More specifically, TSAN ID equals the MAC address of
14582 * the network adapter. TSAN ID is used as part of the TSAN authentication
14583 * protocol. Refer to SF-114946-SW for more information.
14585 #define MC_CMD_TSA_BIND_OP_GET_ID 0x1
14586 /* enum: Get a binding ticket from the TSAN. The binding ticket is used as part
14587 * of the binding procedure to authorize the binding of an adapter to a TSAID.
14588 * Refer to SF-114946-SW for more information.
14590 #define MC_CMD_TSA_BIND_OP_GET_TICKET 0x2
14591 /* enum: Opcode associated with the propagation of a private key that TSAN uses
14592 * as part of post-binding authentication procedure. More specifically, TSAN
14593 * uses this key for a signing operation. TSAC uses the counterpart public key
14594 * to verify the signature. Note - The post-binding authentication occurs when
14595 * the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer to
14596 * SF-114946-SW for more information.
14598 #define MC_CMD_TSA_BIND_OP_SET_KEY 0x3
14599 /* enum: Request an unbinding operation. Note- TSAN clears the binding ticket
14600 * from the Nvram section.
14602 #define MC_CMD_TSA_BIND_OP_UNBIND 0x4
14604 /* MC_CMD_TSA_BIND_IN_GET_ID msgrequest */
14605 #define MC_CMD_TSA_BIND_IN_GET_ID_LEN 20
14606 /* The operation requested. */
14607 #define MC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0
14608 /* Cryptographic nonce that TSAC generates and sends to TSAN. TSAC generates
14609 * the nonce every time as part of the TSAN post-binding authentication
14610 * procedure when the TSAN-TSAC connection terminates and TSAN does need to re-
14611 * connect to the TSAC. Refer to SF-114946-SW for more information.
14613 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_OFST 4
14614 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_LEN 16
14616 /* MC_CMD_TSA_BIND_IN_GET_TICKET msgrequest */
14617 #define MC_CMD_TSA_BIND_IN_GET_TICKET_LEN 4
14618 /* The operation requested. */
14619 #define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_OFST 0
14621 /* MC_CMD_TSA_BIND_IN_SET_KEY msgrequest */
14622 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMIN 5
14623 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMAX 252
14624 #define MC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num))
14625 /* The operation requested. */
14626 #define MC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0
14627 /* This data blob contains the private key generated by the TSAC. TSAN uses
14628 * this key for a signing operation. Note- This private key is used in
14629 * conjunction with the post-binding TSAN authentication procedure that occurs
14630 * when the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer
14631 * to SF-114946-SW for more information.
14633 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_OFST 4
14634 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_LEN 1
14635 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MINNUM 1
14636 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MAXNUM 248
14638 /* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Asks for the un-binding procedure */
14639 #define MC_CMD_TSA_BIND_IN_UNBIND_LEN 10
14640 /* The operation requested. */
14641 #define MC_CMD_TSA_BIND_IN_UNBIND_OP_OFST 0
14642 /* TSAN unique identifier for the network adapter */
14643 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_OFST 4
14644 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_LEN 6
14646 /* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse */
14647 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMIN 11
14648 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252
14649 #define MC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (10+1*(num))
14650 /* The operation completion code. */
14651 #define MC_CMD_TSA_BIND_OUT_GET_ID_OP_OFST 0
14652 /* TSAN unique identifier for the network adapter */
14653 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_OFST 4
14654 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_LEN 6
14655 /* The signature data blob. The signature is computed against the message
14656 * formed by TSAN ID concatenated with the NONCE value. Refer to SF-115479-TC
14657 * for more information also in respect to the private keys that are used to
14658 * sign the message based on TSAN pre/post-binding authentication procedure.
14660 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_OFST 10
14661 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_LEN 1
14662 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MINNUM 1
14663 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MAXNUM 242
14665 /* MC_CMD_TSA_BIND_OUT_GET_TICKET msgresponse */
14666 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMIN 5
14667 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX 252
14668 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num))
14669 /* The operation completion code. */
14670 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_OFST 0
14671 /* The ticket represents the data blob construct that TSAN sends to TSAC as
14672 * part of the binding protocol. From the TSAN perspective the ticket is an
14673 * opaque construct. For more info refer to SF-115479-TC.
14675 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_OFST 4
14676 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_LEN 1
14677 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MINNUM 1
14678 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MAXNUM 248
14680 /* MC_CMD_TSA_BIND_OUT_SET_KEY msgresponse */
14681 #define MC_CMD_TSA_BIND_OUT_SET_KEY_LEN 4
14682 /* The operation completion code. */
14683 #define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_OFST 0
14685 /* MC_CMD_TSA_BIND_OUT_UNBIND msgresponse */
14686 #define MC_CMD_TSA_BIND_OUT_UNBIND_LEN 8
14687 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
14688 #define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_OFST 0
14689 /* Extra status information */
14690 #define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_OFST 4
14691 /* enum: Unbind successful. */
14692 #define MC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND 0x0
14693 /* enum: TSANID mismatch */
14694 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID 0x1
14695 /* enum: Unable to remove the binding ticket from persistent storage. */
14696 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET 0x2
14697 /* enum: TSAN is not bound to a binding ticket. */
14698 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND 0x3
14701 /***********************************/
14702 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE
14703 * Manage the persistent NVRAM cache of security rules created with
14704 * MC_CMD_SET_SECURITY_RULE. Note that the cache is not automatically updated
14705 * as rules are added or removed; the active ruleset must be explicitly
14706 * committed to the cache. The cache may also be explicitly invalidated,
14707 * without affecting the currently active ruleset. When the cache is valid, it
14708 * will be loaded at power on or MC reboot, instead of the default ruleset.
14709 * Rollback of the currently active ruleset to the cached version (when it is
14710 * valid) is also supported. (Medford-only; for use by SolarSecure apps, not
14711 * directly by drivers. See SF-114946-SW.) NOTE - this message definition is
14712 * provisional. It has not yet been used in any released code and may change
14713 * during development. This note will be removed once it is regarded as stable.
14715 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a
14716 #undef MC_CMD_0x11a_PRIVILEGE_CTG
14718 #define MC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14720 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN msgrequest */
14721 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_LEN 4
14722 /* the operation to perform */
14723 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_OFST 0
14724 /* enum: reports the ruleset version that is cached in persistent storage but
14725 * performs no other action
14727 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION 0x0
14728 /* enum: rolls back the active state to the cached version. (May fail with
14729 * ENOENT if there is no valid cached version.)
14731 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK 0x1
14732 /* enum: commits the active state to the persistent cache */
14733 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT 0x2
14734 /* enum: invalidates the persistent cache without affecting the active state */
14735 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE 0x3
14737 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT msgresponse */
14738 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMIN 5
14739 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMAX 252
14740 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LEN(num) (4+1*(num))
14741 /* indicates whether the persistent cache is valid (after completion of the
14742 * requested operation in the case of rollback, commit, or invalidate)
14744 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_OFST 0
14745 /* enum: persistent cache is invalid (the VERSION field will be empty in this
14748 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID 0x0
14749 /* enum: persistent cache is valid */
14750 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID 0x1
14751 /* cached ruleset version (after completion of the requested operation, in the
14752 * case of rollback, commit, or invalidate) as an opaque hash value in the same
14753 * form as MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION
14755 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_OFST 4
14756 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_LEN 1
14757 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MINNUM 1
14758 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MAXNUM 248
14761 /***********************************/
14762 /* MC_CMD_NVRAM_PRIVATE_APPEND
14763 * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST
14764 * if the tag is already present.
14766 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
14767 #undef MC_CMD_0x11c_PRIVILEGE_CTG
14769 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14771 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */
14772 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9
14773 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252
14774 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num))
14775 /* The tag to be appended */
14776 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0
14777 /* The length of the data */
14778 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4
14779 /* The data to be contained in the TLV structure */
14780 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8
14781 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1
14782 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1
14783 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244
14785 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */
14786 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0
14789 /***********************************/
14790 /* MC_CMD_XPM_VERIFY_CONTENTS
14791 * Verify that the contents of the XPM memory is correct (Medford only). This
14792 * is used during manufacture to check that the XPM memory has been programmed
14793 * correctly at ATE.
14795 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
14796 #undef MC_CMD_0x11b_PRIVILEGE_CTG
14798 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14800 /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */
14801 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4
14802 /* Data type to be checked */
14803 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0
14805 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */
14806 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12
14807 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252
14808 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num))
14809 /* Number of sectors found (test builds only) */
14810 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0
14811 /* Number of bytes found (test builds only) */
14812 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4
14813 /* Length of signature */
14814 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8
14816 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12
14817 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1
14818 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0
14819 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240
14822 /***********************************/
14823 /* MC_CMD_SET_EVQ_TMR
14824 * Update the timer load, timer reload and timer mode values for a given EVQ.
14825 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will
14826 * be rounded up to the granularity supported by the hardware, then truncated
14827 * to the range supported by the hardware. The resulting value after the
14828 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS
14829 * and TMR_RELOAD_ACT_NS).
14831 #define MC_CMD_SET_EVQ_TMR 0x120
14832 #undef MC_CMD_0x120_PRIVILEGE_CTG
14834 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14836 /* MC_CMD_SET_EVQ_TMR_IN msgrequest */
14837 #define MC_CMD_SET_EVQ_TMR_IN_LEN 16
14838 /* Function-relative queue instance */
14839 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0
14840 /* Requested value for timer load (in nanoseconds) */
14841 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4
14842 /* Requested value for timer reload (in nanoseconds) */
14843 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8
14844 /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */
14845 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12
14846 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
14847 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
14848 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
14849 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
14851 /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */
14852 #define MC_CMD_SET_EVQ_TMR_OUT_LEN 8
14853 /* Actual value for timer load (in nanoseconds) */
14854 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0
14855 /* Actual value for timer reload (in nanoseconds) */
14856 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4
14859 /***********************************/
14860 /* MC_CMD_GET_EVQ_TMR_PROPERTIES
14861 * Query properties about the event queue timers.
14863 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
14864 #undef MC_CMD_0x122_PRIVILEGE_CTG
14866 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14868 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */
14869 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0
14871 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */
14872 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36
14873 /* Reserved for future use. */
14874 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0
14875 /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in
14876 * nanoseconds) for each increment of the timer load/reload count. The
14877 * requested duration of a timer is this value multiplied by the timer
14878 * load/reload count.
14880 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4
14881 /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value
14882 * allowed for timer load/reload counts.
14884 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8
14885 /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a
14886 * multiple of this step size will be rounded in an implementation defined
14889 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12
14890 /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only
14891 * meaningful if MC_CMD_SET_EVQ_TMR is implemented.
14893 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16
14894 /* Timer durations requested via MCDI that are not a multiple of this step size
14895 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented.
14897 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20
14898 /* For timers updated using the bug35388 workaround, this is the time interval
14899 * (in nanoseconds) for each increment of the timer load/reload count. The
14900 * requested duration of a timer is this value multiplied by the timer
14901 * load/reload count. This field is only meaningful if the bug35388 workaround
14904 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24
14905 /* For timers updated using the bug35388 workaround, this is the maximum value
14906 * allowed for timer load/reload counts. This field is only meaningful if the
14907 * bug35388 workaround is enabled.
14909 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28
14910 /* For timers updated using the bug35388 workaround, timer load/reload counts
14911 * not a multiple of this step size will be rounded in an implementation
14912 * defined manner. This field is only meaningful if the bug35388 workaround is
14915 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32
14918 /***********************************/
14919 /* MC_CMD_ALLOCATE_TX_VFIFO_CP
14920 * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the
14921 * non used switch buffers.
14923 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
14924 #undef MC_CMD_0x11d_PRIVILEGE_CTG
14926 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14928 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */
14929 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20
14930 /* Desired instance. Must be set to a specific instance, which is a function
14931 * local queue index.
14933 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0
14934 /* Will the common pool be used as TX_vFIFO_ULL (1) */
14935 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4
14936 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */
14937 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */
14938 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0
14939 /* Number of buffers to reserve for the common pool */
14940 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8
14941 /* TX datapath to which the Common Pool is connected to. */
14942 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12
14943 /* enum: Extracts information from function */
14944 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
14945 /* Network port or RX Engine to which the common pool connects. */
14946 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16
14947 /* enum: Extracts information from function */
14948 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
14949 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */
14950 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */
14951 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */
14952 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */
14953 /* enum: To enable Switch loopback with Rx engine 0 */
14954 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4
14955 /* enum: To enable Switch loopback with Rx engine 1 */
14956 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5
14958 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */
14959 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4
14960 /* ID of the common pool allocated */
14961 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0
14964 /***********************************/
14965 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO
14966 * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the
14967 * previously allocated common pools.
14969 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
14970 #undef MC_CMD_0x11e_PRIVILEGE_CTG
14972 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14974 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */
14975 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20
14976 /* Common pool previously allocated to which the new vFIFO will be associated
14978 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0
14979 /* Port or RX engine to associate the vFIFO egress */
14980 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4
14981 /* enum: Extracts information from common pool */
14982 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
14983 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */
14984 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */
14985 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */
14986 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */
14987 /* enum: To enable Switch loopback with Rx engine 0 */
14988 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4
14989 /* enum: To enable Switch loopback with Rx engine 1 */
14990 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5
14991 /* Minimum number of buffers that the pool must have */
14992 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8
14993 /* enum: Do not check the space available */
14994 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0
14995 /* Will the vFIFO be used as TX_vFIFO_ULL */
14996 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12
14997 /* Network priority of the vFIFO,if applicable */
14998 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16
14999 /* enum: Search for the lowest unused priority */
15000 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1
15002 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */
15003 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8
15004 /* Short vFIFO ID */
15005 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0
15006 /* Network priority of the vFIFO */
15007 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4
15010 /***********************************/
15011 /* MC_CMD_TEARDOWN_TX_VFIFO_VF
15012 * This interface clears the configuration of the given vFIFO and leaves it
15013 * ready to be re-used.
15015 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
15016 #undef MC_CMD_0x11f_PRIVILEGE_CTG
15018 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15020 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */
15021 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4
15022 /* Short vFIFO ID */
15023 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0
15025 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */
15026 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0
15029 /***********************************/
15030 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP
15031 * This interface clears the configuration of the given common pool and leaves
15032 * it ready to be re-used.
15034 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
15035 #undef MC_CMD_0x121_PRIVILEGE_CTG
15037 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15039 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */
15040 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4
15041 /* Common pool ID given when pool allocated */
15042 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0
15044 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */
15045 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0
15047 #endif /* _SIENA_MC_DRIVER_PCOL_H */