2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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30 * policies, either expressed or implied, of the FreeBSD Project.
35 #ifndef _SYS_EFX_REGS_PCI_H
36 #define _SYS_EFX_REGS_PCI_H
43 * PC_VEND_ID_REG(16bit):
47 #define PCR_AZ_VEND_ID_REG 0x00000000
48 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
50 #define PCRF_AZ_VEND_ID_LBN 0
51 #define PCRF_AZ_VEND_ID_WIDTH 16
55 * PC_DEV_ID_REG(16bit):
59 #define PCR_AZ_DEV_ID_REG 0x00000002
60 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
62 #define PCRF_AZ_DEV_ID_LBN 0
63 #define PCRF_AZ_DEV_ID_WIDTH 16
71 #define PCR_AZ_CMD_REG 0x00000004
72 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
74 #define PCRF_AZ_INTX_DIS_LBN 10
75 #define PCRF_AZ_INTX_DIS_WIDTH 1
76 #define PCRF_AZ_FB2B_EN_LBN 9
77 #define PCRF_AZ_FB2B_EN_WIDTH 1
78 #define PCRF_AZ_SERR_EN_LBN 8
79 #define PCRF_AZ_SERR_EN_WIDTH 1
80 #define PCRF_AZ_IDSEL_CTL_LBN 7
81 #define PCRF_AZ_IDSEL_CTL_WIDTH 1
82 #define PCRF_AZ_PERR_EN_LBN 6
83 #define PCRF_AZ_PERR_EN_WIDTH 1
84 #define PCRF_AZ_VGA_PAL_SNP_LBN 5
85 #define PCRF_AZ_VGA_PAL_SNP_WIDTH 1
86 #define PCRF_AZ_MWI_EN_LBN 4
87 #define PCRF_AZ_MWI_EN_WIDTH 1
88 #define PCRF_AZ_SPEC_CYC_LBN 3
89 #define PCRF_AZ_SPEC_CYC_WIDTH 1
90 #define PCRF_AZ_MST_EN_LBN 2
91 #define PCRF_AZ_MST_EN_WIDTH 1
92 #define PCRF_AZ_MEM_EN_LBN 1
93 #define PCRF_AZ_MEM_EN_WIDTH 1
94 #define PCRF_AZ_IO_EN_LBN 0
95 #define PCRF_AZ_IO_EN_WIDTH 1
103 #define PCR_AZ_STAT_REG 0x00000006
104 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
106 #define PCRF_AZ_DET_PERR_LBN 15
107 #define PCRF_AZ_DET_PERR_WIDTH 1
108 #define PCRF_AZ_SIG_SERR_LBN 14
109 #define PCRF_AZ_SIG_SERR_WIDTH 1
110 #define PCRF_AZ_GOT_MABRT_LBN 13
111 #define PCRF_AZ_GOT_MABRT_WIDTH 1
112 #define PCRF_AZ_GOT_TABRT_LBN 12
113 #define PCRF_AZ_GOT_TABRT_WIDTH 1
114 #define PCRF_AZ_SIG_TABRT_LBN 11
115 #define PCRF_AZ_SIG_TABRT_WIDTH 1
116 #define PCRF_AZ_DEVSEL_TIM_LBN 9
117 #define PCRF_AZ_DEVSEL_TIM_WIDTH 2
118 #define PCRF_AZ_MDAT_PERR_LBN 8
119 #define PCRF_AZ_MDAT_PERR_WIDTH 1
120 #define PCRF_AZ_FB2B_CAP_LBN 7
121 #define PCRF_AZ_FB2B_CAP_WIDTH 1
122 #define PCRF_AZ_66MHZ_CAP_LBN 5
123 #define PCRF_AZ_66MHZ_CAP_WIDTH 1
124 #define PCRF_AZ_CAP_LIST_LBN 4
125 #define PCRF_AZ_CAP_LIST_WIDTH 1
126 #define PCRF_AZ_INTX_STAT_LBN 3
127 #define PCRF_AZ_INTX_STAT_WIDTH 1
131 * PC_REV_ID_REG(8bit):
132 * Class code & revision ID register
135 #define PCR_AZ_REV_ID_REG 0x00000008
136 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
138 #define PCRF_AZ_REV_ID_LBN 0
139 #define PCRF_AZ_REV_ID_WIDTH 8
144 * Class code register
147 #define PCR_AZ_CC_REG 0x00000009
148 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
150 #define PCRF_AZ_BASE_CC_LBN 16
151 #define PCRF_AZ_BASE_CC_WIDTH 8
152 #define PCRF_AZ_SUB_CC_LBN 8
153 #define PCRF_AZ_SUB_CC_WIDTH 8
154 #define PCRF_AZ_PROG_IF_LBN 0
155 #define PCRF_AZ_PROG_IF_WIDTH 8
159 * PC_CACHE_LSIZE_REG(8bit):
163 #define PCR_AZ_CACHE_LSIZE_REG 0x0000000c
164 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
166 #define PCRF_AZ_CACHE_LSIZE_LBN 0
167 #define PCRF_AZ_CACHE_LSIZE_WIDTH 8
171 * PC_MST_LAT_REG(8bit):
172 * Master latency timer register
175 #define PCR_AZ_MST_LAT_REG 0x0000000d
176 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
178 #define PCRF_AZ_MST_LAT_LBN 0
179 #define PCRF_AZ_MST_LAT_WIDTH 8
183 * PC_HDR_TYPE_REG(8bit):
184 * Header type register
187 #define PCR_AZ_HDR_TYPE_REG 0x0000000e
188 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
190 #define PCRF_AZ_MULT_FUNC_LBN 7
191 #define PCRF_AZ_MULT_FUNC_WIDTH 1
192 #define PCRF_AZ_TYPE_LBN 0
193 #define PCRF_AZ_TYPE_WIDTH 7
201 #define PCR_AZ_BIST_REG 0x0000000f
202 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
204 #define PCRF_AZ_BIST_LBN 0
205 #define PCRF_AZ_BIST_WIDTH 8
209 * PC_BAR0_REG(32bit):
210 * Primary function base address register 0
213 #define PCR_AZ_BAR0_REG 0x00000010
214 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
216 #define PCRF_AZ_BAR0_LBN 4
217 #define PCRF_AZ_BAR0_WIDTH 28
218 #define PCRF_AZ_BAR0_PREF_LBN 3
219 #define PCRF_AZ_BAR0_PREF_WIDTH 1
220 #define PCRF_AZ_BAR0_TYPE_LBN 1
221 #define PCRF_AZ_BAR0_TYPE_WIDTH 2
222 #define PCRF_AZ_BAR0_IOM_LBN 0
223 #define PCRF_AZ_BAR0_IOM_WIDTH 1
227 * PC_BAR1_REG(32bit):
228 * Primary function base address register 1, BAR1 is not implemented so read only.
231 #define PCR_DZ_BAR1_REG 0x00000014
232 /* hunta0=pci_f0_config */
234 #define PCRF_DZ_BAR1_LBN 0
235 #define PCRF_DZ_BAR1_WIDTH 32
239 * PC_BAR2_LO_REG(32bit):
240 * Primary function base address register 2 low bits
243 #define PCR_AZ_BAR2_LO_REG 0x00000018
244 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
246 #define PCRF_AZ_BAR2_LO_LBN 4
247 #define PCRF_AZ_BAR2_LO_WIDTH 28
248 #define PCRF_AZ_BAR2_PREF_LBN 3
249 #define PCRF_AZ_BAR2_PREF_WIDTH 1
250 #define PCRF_AZ_BAR2_TYPE_LBN 1
251 #define PCRF_AZ_BAR2_TYPE_WIDTH 2
252 #define PCRF_AZ_BAR2_IOM_LBN 0
253 #define PCRF_AZ_BAR2_IOM_WIDTH 1
257 * PC_BAR2_HI_REG(32bit):
258 * Primary function base address register 2 high bits
261 #define PCR_AZ_BAR2_HI_REG 0x0000001c
262 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
264 #define PCRF_AZ_BAR2_HI_LBN 0
265 #define PCRF_AZ_BAR2_HI_WIDTH 32
269 * PC_BAR4_LO_REG(32bit):
270 * Primary function base address register 2 low bits
273 #define PCR_CZ_BAR4_LO_REG 0x00000020
274 /* sienaa0,hunta0=pci_f0_config */
276 #define PCRF_CZ_BAR4_LO_LBN 4
277 #define PCRF_CZ_BAR4_LO_WIDTH 28
278 #define PCRF_CZ_BAR4_PREF_LBN 3
279 #define PCRF_CZ_BAR4_PREF_WIDTH 1
280 #define PCRF_CZ_BAR4_TYPE_LBN 1
281 #define PCRF_CZ_BAR4_TYPE_WIDTH 2
282 #define PCRF_CZ_BAR4_IOM_LBN 0
283 #define PCRF_CZ_BAR4_IOM_WIDTH 1
287 * PC_BAR4_HI_REG(32bit):
288 * Primary function base address register 2 high bits
291 #define PCR_CZ_BAR4_HI_REG 0x00000024
292 /* sienaa0,hunta0=pci_f0_config */
294 #define PCRF_CZ_BAR4_HI_LBN 0
295 #define PCRF_CZ_BAR4_HI_WIDTH 32
299 * PC_SS_VEND_ID_REG(16bit):
300 * Sub-system vendor ID register
303 #define PCR_AZ_SS_VEND_ID_REG 0x0000002c
304 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
306 #define PCRF_AZ_SS_VEND_ID_LBN 0
307 #define PCRF_AZ_SS_VEND_ID_WIDTH 16
311 * PC_SS_ID_REG(16bit):
312 * Sub-system ID register
315 #define PCR_AZ_SS_ID_REG 0x0000002e
316 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
318 #define PCRF_AZ_SS_ID_LBN 0
319 #define PCRF_AZ_SS_ID_WIDTH 16
323 * PC_EXPROM_BAR_REG(32bit):
324 * Expansion ROM base address register
327 #define PCR_AZ_EXPROM_BAR_REG 0x00000030
328 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
330 #define PCRF_AZ_EXPROM_BAR_LBN 11
331 #define PCRF_AZ_EXPROM_BAR_WIDTH 21
332 #define PCRF_AB_EXPROM_MIN_SIZE_LBN 2
333 #define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9
334 #define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1
335 #define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10
336 #define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1
337 #define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1
338 #define PCRF_AZ_EXPROM_EN_LBN 0
339 #define PCRF_AZ_EXPROM_EN_WIDTH 1
343 * PC_CAP_PTR_REG(8bit):
344 * Capability pointer register
347 #define PCR_AZ_CAP_PTR_REG 0x00000034
348 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
350 #define PCRF_AZ_CAP_PTR_LBN 0
351 #define PCRF_AZ_CAP_PTR_WIDTH 8
355 * PC_INT_LINE_REG(8bit):
356 * Interrupt line register
359 #define PCR_AZ_INT_LINE_REG 0x0000003c
360 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
362 #define PCRF_AZ_INT_LINE_LBN 0
363 #define PCRF_AZ_INT_LINE_WIDTH 8
367 * PC_INT_PIN_REG(8bit):
368 * Interrupt pin register
371 #define PCR_AZ_INT_PIN_REG 0x0000003d
372 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
374 #define PCRF_AZ_INT_PIN_LBN 0
375 #define PCRF_AZ_INT_PIN_WIDTH 8
376 #define PCFE_DZ_INTPIN_INTD 4
377 #define PCFE_DZ_INTPIN_INTC 3
378 #define PCFE_DZ_INTPIN_INTB 2
379 #define PCFE_DZ_INTPIN_INTA 1
383 * PC_PM_CAP_ID_REG(8bit):
384 * Power management capability ID
387 #define PCR_AZ_PM_CAP_ID_REG 0x00000040
388 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
390 #define PCRF_AZ_PM_CAP_ID_LBN 0
391 #define PCRF_AZ_PM_CAP_ID_WIDTH 8
395 * PC_PM_NXT_PTR_REG(8bit):
396 * Power management next item pointer
399 #define PCR_AZ_PM_NXT_PTR_REG 0x00000041
400 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
402 #define PCRF_AZ_PM_NXT_PTR_LBN 0
403 #define PCRF_AZ_PM_NXT_PTR_WIDTH 8
407 * PC_PM_CAP_REG(16bit):
408 * Power management capabilities register
411 #define PCR_AZ_PM_CAP_REG 0x00000042
412 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
414 #define PCRF_AZ_PM_PME_SUPT_LBN 11
415 #define PCRF_AZ_PM_PME_SUPT_WIDTH 5
416 #define PCRF_AZ_PM_D2_SUPT_LBN 10
417 #define PCRF_AZ_PM_D2_SUPT_WIDTH 1
418 #define PCRF_AZ_PM_D1_SUPT_LBN 9
419 #define PCRF_AZ_PM_D1_SUPT_WIDTH 1
420 #define PCRF_AZ_PM_AUX_CURR_LBN 6
421 #define PCRF_AZ_PM_AUX_CURR_WIDTH 3
422 #define PCRF_AZ_PM_DSI_LBN 5
423 #define PCRF_AZ_PM_DSI_WIDTH 1
424 #define PCRF_AZ_PM_PME_CLK_LBN 3
425 #define PCRF_AZ_PM_PME_CLK_WIDTH 1
426 #define PCRF_AZ_PM_PME_VER_LBN 0
427 #define PCRF_AZ_PM_PME_VER_WIDTH 3
431 * PC_PM_CS_REG(16bit):
432 * Power management control & status register
435 #define PCR_AZ_PM_CS_REG 0x00000044
436 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
438 #define PCRF_AZ_PM_PME_STAT_LBN 15
439 #define PCRF_AZ_PM_PME_STAT_WIDTH 1
440 #define PCRF_AZ_PM_DAT_SCALE_LBN 13
441 #define PCRF_AZ_PM_DAT_SCALE_WIDTH 2
442 #define PCRF_AZ_PM_DAT_SEL_LBN 9
443 #define PCRF_AZ_PM_DAT_SEL_WIDTH 4
444 #define PCRF_AZ_PM_PME_EN_LBN 8
445 #define PCRF_AZ_PM_PME_EN_WIDTH 1
446 #define PCRF_CZ_NO_SOFT_RESET_LBN 3
447 #define PCRF_CZ_NO_SOFT_RESET_WIDTH 1
448 #define PCRF_AZ_PM_PWR_ST_LBN 0
449 #define PCRF_AZ_PM_PWR_ST_WIDTH 2
453 * PC_MSI_CAP_ID_REG(8bit):
457 #define PCR_AZ_MSI_CAP_ID_REG 0x00000050
458 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
460 #define PCRF_AZ_MSI_CAP_ID_LBN 0
461 #define PCRF_AZ_MSI_CAP_ID_WIDTH 8
465 * PC_MSI_NXT_PTR_REG(8bit):
466 * MSI next item pointer
469 #define PCR_AZ_MSI_NXT_PTR_REG 0x00000051
470 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
472 #define PCRF_AZ_MSI_NXT_PTR_LBN 0
473 #define PCRF_AZ_MSI_NXT_PTR_WIDTH 8
477 * PC_MSI_CTL_REG(16bit):
478 * MSI control register
481 #define PCR_AZ_MSI_CTL_REG 0x00000052
482 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
484 #define PCRF_AZ_MSI_64_EN_LBN 7
485 #define PCRF_AZ_MSI_64_EN_WIDTH 1
486 #define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4
487 #define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3
488 #define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1
489 #define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3
490 #define PCRF_AZ_MSI_EN_LBN 0
491 #define PCRF_AZ_MSI_EN_WIDTH 1
495 * PC_MSI_ADR_LO_REG(32bit):
496 * MSI low 32 bits address register
499 #define PCR_AZ_MSI_ADR_LO_REG 0x00000054
500 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
502 #define PCRF_AZ_MSI_ADR_LO_LBN 2
503 #define PCRF_AZ_MSI_ADR_LO_WIDTH 30
507 * PC_MSI_ADR_HI_REG(32bit):
508 * MSI high 32 bits address register
511 #define PCR_AZ_MSI_ADR_HI_REG 0x00000058
512 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
514 #define PCRF_AZ_MSI_ADR_HI_LBN 0
515 #define PCRF_AZ_MSI_ADR_HI_WIDTH 32
519 * PC_MSI_DAT_REG(16bit):
523 #define PCR_AZ_MSI_DAT_REG 0x0000005c
524 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
526 #define PCRF_AZ_MSI_DAT_LBN 0
527 #define PCRF_AZ_MSI_DAT_WIDTH 16
531 * PC_PCIE_CAP_LIST_REG(16bit):
532 * PCIe capability list register
535 #define PCR_AB_PCIE_CAP_LIST_REG 0x00000060
536 /* falcona0,falconb0=pci_f0_config */
538 #define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070
539 /* sienaa0,hunta0=pci_f0_config */
541 #define PCRF_AZ_PCIE_NXT_PTR_LBN 8
542 #define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8
543 #define PCRF_AZ_PCIE_CAP_ID_LBN 0
544 #define PCRF_AZ_PCIE_CAP_ID_WIDTH 8
548 * PC_PCIE_CAP_REG(16bit):
549 * PCIe capability register
552 #define PCR_AB_PCIE_CAP_REG 0x00000062
553 /* falcona0,falconb0=pci_f0_config */
555 #define PCR_CZ_PCIE_CAP_REG 0x00000072
556 /* sienaa0,hunta0=pci_f0_config */
558 #define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9
559 #define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5
560 #define PCRF_AZ_PCIE_SLOT_IMP_LBN 8
561 #define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1
562 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4
563 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4
564 #define PCRF_AZ_PCIE_CAP_VER_LBN 0
565 #define PCRF_AZ_PCIE_CAP_VER_WIDTH 4
569 * PC_DEV_CAP_REG(32bit):
570 * PCIe device capabilities register
573 #define PCR_AB_DEV_CAP_REG 0x00000064
574 /* falcona0,falconb0=pci_f0_config */
576 #define PCR_CZ_DEV_CAP_REG 0x00000074
577 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */
579 #define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28
580 #define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1
581 #define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26
582 #define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2
583 #define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18
584 #define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8
585 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15
586 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1
587 #define PCRF_AB_PWR_IND_LBN 14
588 #define PCRF_AB_PWR_IND_WIDTH 1
589 #define PCRF_AB_ATTN_IND_LBN 13
590 #define PCRF_AB_ATTN_IND_WIDTH 1
591 #define PCRF_AB_ATTN_BUTTON_LBN 12
592 #define PCRF_AB_ATTN_BUTTON_WIDTH 1
593 #define PCRF_AZ_ENDPT_L1_LAT_LBN 9
594 #define PCRF_AZ_ENDPT_L1_LAT_WIDTH 3
595 #define PCRF_AZ_ENDPT_L0_LAT_LBN 6
596 #define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3
597 #define PCRF_AZ_TAG_FIELD_LBN 5
598 #define PCRF_AZ_TAG_FIELD_WIDTH 1
599 #define PCRF_AZ_PHAN_FUNC_LBN 3
600 #define PCRF_AZ_PHAN_FUNC_WIDTH 2
601 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0
602 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3
606 * PC_DEV_CTL_REG(16bit):
607 * PCIe device control register
610 #define PCR_AB_DEV_CTL_REG 0x00000068
611 /* falcona0,falconb0=pci_f0_config */
613 #define PCR_CZ_DEV_CTL_REG 0x00000078
614 /* sienaa0,hunta0=pci_f0_config */
616 #define PCRF_CZ_FN_LEVEL_RESET_LBN 15
617 #define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1
618 #define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12
619 #define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3
620 #define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5
621 #define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4
622 #define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3
623 #define PCFE_AZ_MAX_RD_REQ_SIZE_512 2
624 #define PCFE_AZ_MAX_RD_REQ_SIZE_256 1
625 #define PCFE_AZ_MAX_RD_REQ_SIZE_128 0
626 #define PCRF_AZ_EN_NO_SNOOP_LBN 11
627 #define PCRF_AZ_EN_NO_SNOOP_WIDTH 1
628 #define PCRF_AZ_AUX_PWR_PM_EN_LBN 10
629 #define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1
630 #define PCRF_AZ_PHAN_FUNC_EN_LBN 9
631 #define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1
632 #define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8
633 #define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1
634 #define PCRF_CZ_EXTENDED_TAG_EN_LBN 8
635 #define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1
636 #define PCRF_AZ_MAX_PAYL_SIZE_LBN 5
637 #define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3
638 #define PCFE_AZ_MAX_PAYL_SIZE_4096 5
639 #define PCFE_AZ_MAX_PAYL_SIZE_2048 4
640 #define PCFE_AZ_MAX_PAYL_SIZE_1024 3
641 #define PCFE_AZ_MAX_PAYL_SIZE_512 2
642 #define PCFE_AZ_MAX_PAYL_SIZE_256 1
643 #define PCFE_AZ_MAX_PAYL_SIZE_128 0
644 #define PCRF_AZ_EN_RELAX_ORDER_LBN 4
645 #define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1
646 #define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3
647 #define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1
648 #define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2
649 #define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1
650 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1
651 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1
652 #define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0
653 #define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1
657 * PC_DEV_STAT_REG(16bit):
658 * PCIe device status register
661 #define PCR_AB_DEV_STAT_REG 0x0000006a
662 /* falcona0,falconb0=pci_f0_config */
664 #define PCR_CZ_DEV_STAT_REG 0x0000007a
665 /* sienaa0,hunta0=pci_f0_config */
667 #define PCRF_AZ_TRNS_PEND_LBN 5
668 #define PCRF_AZ_TRNS_PEND_WIDTH 1
669 #define PCRF_AZ_AUX_PWR_DET_LBN 4
670 #define PCRF_AZ_AUX_PWR_DET_WIDTH 1
671 #define PCRF_AZ_UNSUP_REQ_DET_LBN 3
672 #define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1
673 #define PCRF_AZ_FATAL_ERR_DET_LBN 2
674 #define PCRF_AZ_FATAL_ERR_DET_WIDTH 1
675 #define PCRF_AZ_NONFATAL_ERR_DET_LBN 1
676 #define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1
677 #define PCRF_AZ_CORR_ERR_DET_LBN 0
678 #define PCRF_AZ_CORR_ERR_DET_WIDTH 1
682 * PC_LNK_CAP_REG(32bit):
683 * PCIe link capabilities register
686 #define PCR_AB_LNK_CAP_REG 0x0000006c
687 /* falcona0,falconb0=pci_f0_config */
689 #define PCR_CZ_LNK_CAP_REG 0x0000007c
690 /* sienaa0,hunta0=pci_f0_config */
692 #define PCRF_AZ_PORT_NUM_LBN 24
693 #define PCRF_AZ_PORT_NUM_WIDTH 8
694 #define PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22
695 #define PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1
696 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21
697 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1
698 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20
699 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1
700 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19
701 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1
702 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18
703 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1
704 #define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15
705 #define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3
706 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12
707 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3
708 #define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10
709 #define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2
710 #define PCRF_AZ_MAX_LNK_WIDTH_LBN 4
711 #define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6
712 #define PCRF_AZ_MAX_LNK_SP_LBN 0
713 #define PCRF_AZ_MAX_LNK_SP_WIDTH 4
717 * PC_LNK_CTL_REG(16bit):
718 * PCIe link control register
721 #define PCR_AB_LNK_CTL_REG 0x00000070
722 /* falcona0,falconb0=pci_f0_config */
724 #define PCR_CZ_LNK_CTL_REG 0x00000080
725 /* sienaa0,hunta0=pci_f0_config */
727 #define PCRF_AZ_EXT_SYNC_LBN 7
728 #define PCRF_AZ_EXT_SYNC_WIDTH 1
729 #define PCRF_AZ_COMM_CLK_CFG_LBN 6
730 #define PCRF_AZ_COMM_CLK_CFG_WIDTH 1
731 #define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5
732 #define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1
733 #define PCRF_CZ_LNK_RETRAIN_LBN 5
734 #define PCRF_CZ_LNK_RETRAIN_WIDTH 1
735 #define PCRF_AZ_LNK_DIS_LBN 4
736 #define PCRF_AZ_LNK_DIS_WIDTH 1
737 #define PCRF_AZ_RD_COM_BDRY_LBN 3
738 #define PCRF_AZ_RD_COM_BDRY_WIDTH 1
739 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0
740 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2
744 * PC_LNK_STAT_REG(16bit):
745 * PCIe link status register
748 #define PCR_AB_LNK_STAT_REG 0x00000072
749 /* falcona0,falconb0=pci_f0_config */
751 #define PCR_CZ_LNK_STAT_REG 0x00000082
752 /* sienaa0,hunta0=pci_f0_config */
754 #define PCRF_AZ_SLOT_CLK_CFG_LBN 12
755 #define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1
756 #define PCRF_AZ_LNK_TRAIN_LBN 11
757 #define PCRF_AZ_LNK_TRAIN_WIDTH 1
758 #define PCRF_AB_TRAIN_ERR_LBN 10
759 #define PCRF_AB_TRAIN_ERR_WIDTH 1
760 #define PCRF_AZ_LNK_WIDTH_LBN 4
761 #define PCRF_AZ_LNK_WIDTH_WIDTH 6
762 #define PCRF_AZ_LNK_SP_LBN 0
763 #define PCRF_AZ_LNK_SP_WIDTH 4
767 * PC_SLOT_CAP_REG(32bit):
768 * PCIe slot capabilities register
771 #define PCR_AB_SLOT_CAP_REG 0x00000074
772 /* falcona0,falconb0=pci_f0_config */
774 #define PCRF_AB_SLOT_NUM_LBN 19
775 #define PCRF_AB_SLOT_NUM_WIDTH 13
776 #define PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15
777 #define PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2
778 #define PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7
779 #define PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8
780 #define PCRF_AB_SLOT_HP_CAP_LBN 6
781 #define PCRF_AB_SLOT_HP_CAP_WIDTH 1
782 #define PCRF_AB_SLOT_HP_SURP_LBN 5
783 #define PCRF_AB_SLOT_HP_SURP_WIDTH 1
784 #define PCRF_AB_SLOT_PWR_IND_PRST_LBN 4
785 #define PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1
786 #define PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3
787 #define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1
788 #define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2
789 #define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1
790 #define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1
791 #define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1
792 #define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0
793 #define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1
797 * PC_SLOT_CTL_REG(16bit):
798 * PCIe slot control register
801 #define PCR_AB_SLOT_CTL_REG 0x00000078
802 /* falcona0,falconb0=pci_f0_config */
804 #define PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10
805 #define PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1
806 #define PCRF_AB_SLOT_PWR_IND_CTL_LBN 8
807 #define PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2
808 #define PCRF_AB_SLOT_ATT_IND_CTL_LBN 6
809 #define PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2
810 #define PCRF_AB_SLOT_HP_INT_EN_LBN 5
811 #define PCRF_AB_SLOT_HP_INT_EN_WIDTH 1
812 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4
813 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1
814 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3
815 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1
816 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2
817 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1
818 #define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1
819 #define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1
820 #define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0
821 #define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1
825 * PC_SLOT_STAT_REG(16bit):
826 * PCIe slot status register
829 #define PCR_AB_SLOT_STAT_REG 0x0000007a
830 /* falcona0,falconb0=pci_f0_config */
832 #define PCRF_AB_PRES_DET_ST_LBN 6
833 #define PCRF_AB_PRES_DET_ST_WIDTH 1
834 #define PCRF_AB_MRL_SENS_ST_LBN 5
835 #define PCRF_AB_MRL_SENS_ST_WIDTH 1
836 #define PCRF_AB_SLOT_PWR_IND_LBN 4
837 #define PCRF_AB_SLOT_PWR_IND_WIDTH 1
838 #define PCRF_AB_SLOT_ATTN_IND_LBN 3
839 #define PCRF_AB_SLOT_ATTN_IND_WIDTH 1
840 #define PCRF_AB_SLOT_MRL_SENS_LBN 2
841 #define PCRF_AB_SLOT_MRL_SENS_WIDTH 1
842 #define PCRF_AB_PWR_FLTDET_LBN 1
843 #define PCRF_AB_PWR_FLTDET_WIDTH 1
844 #define PCRF_AB_ATTN_BUTDET_LBN 0
845 #define PCRF_AB_ATTN_BUTDET_WIDTH 1
849 * PC_MSIX_CAP_ID_REG(8bit):
853 #define PCR_BB_MSIX_CAP_ID_REG 0x00000090
854 /* falconb0=pci_f0_config */
856 #define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0
857 /* sienaa0,hunta0=pci_f0_config */
859 #define PCRF_BZ_MSIX_CAP_ID_LBN 0
860 #define PCRF_BZ_MSIX_CAP_ID_WIDTH 8
864 * PC_MSIX_NXT_PTR_REG(8bit):
865 * MSIX Capability Next Capability Ptr
868 #define PCR_BB_MSIX_NXT_PTR_REG 0x00000091
869 /* falconb0=pci_f0_config */
871 #define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1
872 /* sienaa0,hunta0=pci_f0_config */
874 #define PCRF_BZ_MSIX_NXT_PTR_LBN 0
875 #define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8
879 * PC_MSIX_CTL_REG(16bit):
880 * MSIX control register
883 #define PCR_BB_MSIX_CTL_REG 0x00000092
884 /* falconb0=pci_f0_config */
886 #define PCR_CZ_MSIX_CTL_REG 0x000000b2
887 /* sienaa0,hunta0=pci_f0_config */
889 #define PCRF_BZ_MSIX_EN_LBN 15
890 #define PCRF_BZ_MSIX_EN_WIDTH 1
891 #define PCRF_BZ_MSIX_FUNC_MASK_LBN 14
892 #define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1
893 #define PCRF_BZ_MSIX_TBL_SIZE_LBN 0
894 #define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11
898 * PC_MSIX_TBL_BASE_REG(32bit):
899 * MSIX Capability Vector Table Base
902 #define PCR_BB_MSIX_TBL_BASE_REG 0x00000094
903 /* falconb0=pci_f0_config */
905 #define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4
906 /* sienaa0,hunta0=pci_f0_config */
908 #define PCRF_BZ_MSIX_TBL_OFF_LBN 3
909 #define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29
910 #define PCRF_BZ_MSIX_TBL_BIR_LBN 0
911 #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3
915 * PC_DEV_CAP2_REG(32bit):
916 * PCIe Device Capabilities 2
919 #define PCR_CZ_DEV_CAP2_REG 0x00000094
920 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */
922 #define PCRF_DZ_OBFF_SUPPORTED_LBN 18
923 #define PCRF_DZ_OBFF_SUPPORTED_WIDTH 2
924 #define PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12
925 #define PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2
926 #define PCRF_DZ_LTR_M_SUPPORTED_LBN 11
927 #define PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1
928 #define PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4
929 #define PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1
930 #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4
931 #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1
932 #define PCRF_CZ_CMPL_TIMEOUT_LBN 0
933 #define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4
934 #define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14
935 #define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13
936 #define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10
937 #define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9
938 #define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6
939 #define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5
940 #define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2
941 #define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1
942 #define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0
946 * PC_DEV_CTL2_REG(16bit):
947 * PCIe Device Control 2
950 #define PCR_CZ_DEV_CTL2_REG 0x00000098
951 /* sienaa0,hunta0=pci_f0_config */
953 #define PCRF_DZ_OBFF_ENABLE_LBN 13
954 #define PCRF_DZ_OBFF_ENABLE_WIDTH 2
955 #define PCRF_DZ_LTR_ENABLE_LBN 10
956 #define PCRF_DZ_LTR_ENABLE_WIDTH 1
957 #define PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9
958 #define PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1
959 #define PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8
960 #define PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1
961 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4
962 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1
963 #define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0
964 #define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4
968 * PC_MSIX_PBA_BASE_REG(32bit):
969 * MSIX Capability PBA Base
972 #define PCR_BB_MSIX_PBA_BASE_REG 0x00000098
973 /* falconb0=pci_f0_config */
975 #define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8
976 /* sienaa0,hunta0=pci_f0_config */
978 #define PCRF_BZ_MSIX_PBA_OFF_LBN 3
979 #define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29
980 #define PCRF_BZ_MSIX_PBA_BIR_LBN 0
981 #define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3
985 * PC_LNK_CAP2_REG(32bit):
986 * PCIe Link Capability 2
989 #define PCR_DZ_LNK_CAP2_REG 0x0000009c
990 /* hunta0=pci_f0_config */
992 #define PCRF_DZ_LNK_SPEED_SUP_LBN 1
993 #define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7
997 * PC_LNK_CTL2_REG(16bit):
998 * PCIe Link Control 2
1001 #define PCR_CZ_LNK_CTL2_REG 0x000000a0
1002 /* sienaa0,hunta0=pci_f0_config */
1004 #define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12
1005 #define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1
1006 #define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11
1007 #define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1
1008 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10
1009 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1
1010 #define PCRF_CZ_TRANSMIT_MARGIN_LBN 7
1011 #define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3
1012 #define PCRF_CZ_SELECT_DEEMPH_LBN 6
1013 #define PCRF_CZ_SELECT_DEEMPH_WIDTH 1
1014 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5
1015 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1
1016 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4
1017 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1
1018 #define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0
1019 #define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4
1020 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3
1021 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2
1022 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1
1026 * PC_LNK_STAT2_REG(16bit):
1027 * PCIe Link Status 2
1030 #define PCR_CZ_LNK_STAT2_REG 0x000000a2
1031 /* sienaa0,hunta0=pci_f0_config */
1033 #define PCRF_CZ_CURRENT_DEEMPH_LBN 0
1034 #define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1
1038 * PC_VPD_CAP_ID_REG(8bit):
1042 #define PCR_AB_VPD_CAP_ID_REG 0x000000b0
1043 /* falcona0,falconb0=pci_f0_config */
1045 #define PCRF_AB_VPD_CAP_ID_LBN 0
1046 #define PCRF_AB_VPD_CAP_ID_WIDTH 8
1050 * PC_VPD_NXT_PTR_REG(8bit):
1051 * VPD next item pointer
1054 #define PCR_AB_VPD_NXT_PTR_REG 0x000000b1
1055 /* falcona0,falconb0=pci_f0_config */
1057 #define PCRF_AB_VPD_NXT_PTR_LBN 0
1058 #define PCRF_AB_VPD_NXT_PTR_WIDTH 8
1062 * PC_VPD_ADDR_REG(16bit):
1063 * VPD address register
1066 #define PCR_AB_VPD_ADDR_REG 0x000000b2
1067 /* falcona0,falconb0=pci_f0_config */
1069 #define PCRF_AB_VPD_FLAG_LBN 15
1070 #define PCRF_AB_VPD_FLAG_WIDTH 1
1071 #define PCRF_AB_VPD_ADDR_LBN 0
1072 #define PCRF_AB_VPD_ADDR_WIDTH 15
1076 * PC_VPD_CAP_DATA_REG(32bit):
1077 * documentation to be written for sum_PC_VPD_CAP_DATA_REG
1080 #define PCR_AB_VPD_CAP_DATA_REG 0x000000b4
1081 /* falcona0,falconb0=pci_f0_config */
1083 #define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4
1084 /* sienaa0,hunta0=pci_f0_config */
1086 #define PCRF_AZ_VPD_DATA_LBN 0
1087 #define PCRF_AZ_VPD_DATA_WIDTH 32
1091 * PC_VPD_CAP_CTL_REG(8bit):
1092 * VPD control and capabilities register
1095 #define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0
1096 /* sienaa0,hunta0=pci_f0_config */
1098 #define PCRF_CZ_VPD_FLAG_LBN 31
1099 #define PCRF_CZ_VPD_FLAG_WIDTH 1
1100 #define PCRF_CZ_VPD_ADDR_LBN 16
1101 #define PCRF_CZ_VPD_ADDR_WIDTH 15
1102 #define PCRF_CZ_VPD_NXT_PTR_LBN 8
1103 #define PCRF_CZ_VPD_NXT_PTR_WIDTH 8
1104 #define PCRF_CZ_VPD_CAP_ID_LBN 0
1105 #define PCRF_CZ_VPD_CAP_ID_WIDTH 8
1109 * PC_AER_CAP_HDR_REG(32bit):
1110 * AER capability header register
1113 #define PCR_AZ_AER_CAP_HDR_REG 0x00000100
1114 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1116 #define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20
1117 #define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12
1118 #define PCRF_AZ_AERCAPHDR_VER_LBN 16
1119 #define PCRF_AZ_AERCAPHDR_VER_WIDTH 4
1120 #define PCRF_AZ_AERCAPHDR_ID_LBN 0
1121 #define PCRF_AZ_AERCAPHDR_ID_WIDTH 16
1125 * PC_AER_UNCORR_ERR_STAT_REG(32bit):
1126 * AER Uncorrectable error status register
1129 #define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104
1130 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1132 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20
1133 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1
1134 #define PCRF_AZ_ECRC_ERR_STAT_LBN 19
1135 #define PCRF_AZ_ECRC_ERR_STAT_WIDTH 1
1136 #define PCRF_AZ_MALF_TLP_STAT_LBN 18
1137 #define PCRF_AZ_MALF_TLP_STAT_WIDTH 1
1138 #define PCRF_AZ_RX_OVF_STAT_LBN 17
1139 #define PCRF_AZ_RX_OVF_STAT_WIDTH 1
1140 #define PCRF_AZ_UNEXP_COMP_STAT_LBN 16
1141 #define PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1
1142 #define PCRF_AZ_COMP_ABRT_STAT_LBN 15
1143 #define PCRF_AZ_COMP_ABRT_STAT_WIDTH 1
1144 #define PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14
1145 #define PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1
1146 #define PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13
1147 #define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1
1148 #define PCRF_AZ_PSON_TLP_STAT_LBN 12
1149 #define PCRF_AZ_PSON_TLP_STAT_WIDTH 1
1150 #define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4
1151 #define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1
1152 #define PCRF_AB_TRAIN_ERR_STAT_LBN 0
1153 #define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1
1157 * PC_AER_UNCORR_ERR_MASK_REG(32bit):
1158 * AER Uncorrectable error mask register
1161 #define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108
1162 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1164 #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24
1165 #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1
1166 #define PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22
1167 #define PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1
1168 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20
1169 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1
1170 #define PCRF_AZ_ECRC_ERR_MASK_LBN 19
1171 #define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1
1172 #define PCRF_AZ_MALF_TLP_MASK_LBN 18
1173 #define PCRF_AZ_MALF_TLP_MASK_WIDTH 1
1174 #define PCRF_AZ_RX_OVF_MASK_LBN 17
1175 #define PCRF_AZ_RX_OVF_MASK_WIDTH 1
1176 #define PCRF_AZ_UNEXP_COMP_MASK_LBN 16
1177 #define PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1
1178 #define PCRF_AZ_COMP_ABRT_MASK_LBN 15
1179 #define PCRF_AZ_COMP_ABRT_MASK_WIDTH 1
1180 #define PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14
1181 #define PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1
1182 #define PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13
1183 #define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1
1184 #define PCRF_AZ_PSON_TLP_MASK_LBN 12
1185 #define PCRF_AZ_PSON_TLP_MASK_WIDTH 1
1186 #define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4
1187 #define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1
1188 #define PCRF_AB_TRAIN_ERR_MASK_LBN 0
1189 #define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1
1193 * PC_AER_UNCORR_ERR_SEV_REG(32bit):
1194 * AER Uncorrectable error severity register
1197 #define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c
1198 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1200 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20
1201 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1
1202 #define PCRF_AZ_ECRC_ERR_SEV_LBN 19
1203 #define PCRF_AZ_ECRC_ERR_SEV_WIDTH 1
1204 #define PCRF_AZ_MALF_TLP_SEV_LBN 18
1205 #define PCRF_AZ_MALF_TLP_SEV_WIDTH 1
1206 #define PCRF_AZ_RX_OVF_SEV_LBN 17
1207 #define PCRF_AZ_RX_OVF_SEV_WIDTH 1
1208 #define PCRF_AZ_UNEXP_COMP_SEV_LBN 16
1209 #define PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1
1210 #define PCRF_AZ_COMP_ABRT_SEV_LBN 15
1211 #define PCRF_AZ_COMP_ABRT_SEV_WIDTH 1
1212 #define PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14
1213 #define PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1
1214 #define PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13
1215 #define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1
1216 #define PCRF_AZ_PSON_TLP_SEV_LBN 12
1217 #define PCRF_AZ_PSON_TLP_SEV_WIDTH 1
1218 #define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4
1219 #define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1
1220 #define PCRF_AB_TRAIN_ERR_SEV_LBN 0
1221 #define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1
1225 * PC_AER_CORR_ERR_STAT_REG(32bit):
1226 * AER Correctable error status register
1229 #define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110
1230 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1232 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13
1233 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1
1234 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12
1235 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1
1236 #define PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8
1237 #define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1
1238 #define PCRF_AZ_BAD_DLLP_STAT_LBN 7
1239 #define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1
1240 #define PCRF_AZ_BAD_TLP_STAT_LBN 6
1241 #define PCRF_AZ_BAD_TLP_STAT_WIDTH 1
1242 #define PCRF_AZ_RX_ERR_STAT_LBN 0
1243 #define PCRF_AZ_RX_ERR_STAT_WIDTH 1
1247 * PC_AER_CORR_ERR_MASK_REG(32bit):
1248 * AER Correctable error status register
1251 #define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114
1252 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1254 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13
1255 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1
1256 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12
1257 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1
1258 #define PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8
1259 #define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1
1260 #define PCRF_AZ_BAD_DLLP_MASK_LBN 7
1261 #define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1
1262 #define PCRF_AZ_BAD_TLP_MASK_LBN 6
1263 #define PCRF_AZ_BAD_TLP_MASK_WIDTH 1
1264 #define PCRF_AZ_RX_ERR_MASK_LBN 0
1265 #define PCRF_AZ_RX_ERR_MASK_WIDTH 1
1269 * PC_AER_CAP_CTL_REG(32bit):
1270 * AER capability and control register
1273 #define PCR_AZ_AER_CAP_CTL_REG 0x00000118
1274 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1276 #define PCRF_AZ_ECRC_CHK_EN_LBN 8
1277 #define PCRF_AZ_ECRC_CHK_EN_WIDTH 1
1278 #define PCRF_AZ_ECRC_CHK_CAP_LBN 7
1279 #define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1
1280 #define PCRF_AZ_ECRC_GEN_EN_LBN 6
1281 #define PCRF_AZ_ECRC_GEN_EN_WIDTH 1
1282 #define PCRF_AZ_ECRC_GEN_CAP_LBN 5
1283 #define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1
1284 #define PCRF_AZ_1ST_ERR_PTR_LBN 0
1285 #define PCRF_AZ_1ST_ERR_PTR_WIDTH 5
1289 * PC_AER_HDR_LOG_REG(128bit):
1290 * AER Header log register
1293 #define PCR_AZ_AER_HDR_LOG_REG 0x0000011c
1294 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1296 #define PCRF_AZ_HDR_LOG_LBN 0
1297 #define PCRF_AZ_HDR_LOG_WIDTH 128
1301 * PC_DEVSN_CAP_HDR_REG(32bit):
1302 * Device serial number capability header register
1305 #define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140
1306 /* sienaa0,hunta0=pci_f0_config */
1308 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20
1309 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12
1310 #define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16
1311 #define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4
1312 #define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0
1313 #define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16
1317 * PC_DEVSN_DWORD0_REG(32bit):
1318 * Device serial number DWORD0
1321 #define PCR_CZ_DEVSN_DWORD0_REG 0x00000144
1322 /* sienaa0,hunta0=pci_f0_config */
1324 #define PCRF_CZ_DEVSN_DWORD0_LBN 0
1325 #define PCRF_CZ_DEVSN_DWORD0_WIDTH 32
1329 * PC_DEVSN_DWORD1_REG(32bit):
1330 * Device serial number DWORD0
1333 #define PCR_CZ_DEVSN_DWORD1_REG 0x00000148
1334 /* sienaa0,hunta0=pci_f0_config */
1336 #define PCRF_CZ_DEVSN_DWORD1_LBN 0
1337 #define PCRF_CZ_DEVSN_DWORD1_WIDTH 32
1341 * PC_ARI_CAP_HDR_REG(32bit):
1342 * ARI capability header register
1345 #define PCR_CZ_ARI_CAP_HDR_REG 0x00000150
1346 /* sienaa0,hunta0=pci_f0_config */
1348 #define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20
1349 #define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12
1350 #define PCRF_CZ_ARICAPHDR_VER_LBN 16
1351 #define PCRF_CZ_ARICAPHDR_VER_WIDTH 4
1352 #define PCRF_CZ_ARICAPHDR_ID_LBN 0
1353 #define PCRF_CZ_ARICAPHDR_ID_WIDTH 16
1357 * PC_ARI_CAP_REG(16bit):
1361 #define PCR_CZ_ARI_CAP_REG 0x00000154
1362 /* sienaa0,hunta0=pci_f0_config */
1364 #define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8
1365 #define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8
1366 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1
1367 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1
1368 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0
1369 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1
1373 * PC_ARI_CTL_REG(16bit):
1377 #define PCR_CZ_ARI_CTL_REG 0x00000156
1378 /* sienaa0,hunta0=pci_f0_config */
1380 #define PCRF_CZ_ARI_FN_GRP_LBN 4
1381 #define PCRF_CZ_ARI_FN_GRP_WIDTH 3
1382 #define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1
1383 #define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1
1384 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0
1385 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1
1389 * PC_SEC_PCIE_CAP_REG(32bit):
1390 * Secondary PCIE Capability Register
1393 #define PCR_DZ_SEC_PCIE_CAP_REG 0x00000160
1394 /* hunta0=pci_f0_config */
1396 #define PCRF_DZ_SEC_NXT_PTR_LBN 20
1397 #define PCRF_DZ_SEC_NXT_PTR_WIDTH 12
1398 #define PCRF_DZ_SEC_VERSION_LBN 16
1399 #define PCRF_DZ_SEC_VERSION_WIDTH 4
1400 #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0
1401 #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16
1405 * PC_SRIOV_CAP_HDR_REG(32bit):
1406 * SRIOV capability header register
1409 #define PCR_CC_SRIOV_CAP_HDR_REG 0x00000160
1410 /* sienaa0=pci_f0_config */
1412 #define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180
1413 /* hunta0=pci_f0_config */
1415 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20
1416 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12
1417 #define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16
1418 #define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4
1419 #define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0
1420 #define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16
1424 * PC_SRIOV_CAP_REG(32bit):
1425 * SRIOV Capabilities
1428 #define PCR_CC_SRIOV_CAP_REG 0x00000164
1429 /* sienaa0=pci_f0_config */
1431 #define PCR_DZ_SRIOV_CAP_REG 0x00000184
1432 /* hunta0=pci_f0_config */
1434 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21
1435 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11
1436 #define PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1
1437 #define PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1
1438 #define PCRF_CZ_VF_MIGR_CAP_LBN 0
1439 #define PCRF_CZ_VF_MIGR_CAP_WIDTH 1
1443 * PC_LINK_CONTROL3_REG(32bit):
1447 #define PCR_DZ_LINK_CONTROL3_REG 0x00000164
1448 /* hunta0=pci_f0_config */
1450 #define PCRF_DZ_LINK_EQ_INT_EN_LBN 1
1451 #define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1
1452 #define PCRF_DZ_PERFORM_EQL_LBN 0
1453 #define PCRF_DZ_PERFORM_EQL_WIDTH 1
1457 * PC_LANE_ERROR_STAT_REG(32bit):
1458 * Lane Error Status Register.
1461 #define PCR_DZ_LANE_ERROR_STAT_REG 0x00000168
1462 /* hunta0=pci_f0_config */
1464 #define PCRF_DZ_LANE_STATUS_LBN 0
1465 #define PCRF_DZ_LANE_STATUS_WIDTH 8
1469 * PC_SRIOV_CTL_REG(16bit):
1473 #define PCR_CC_SRIOV_CTL_REG 0x00000168
1474 /* sienaa0=pci_f0_config */
1476 #define PCR_DZ_SRIOV_CTL_REG 0x00000188
1477 /* hunta0=pci_f0_config */
1479 #define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4
1480 #define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1
1481 #define PCRF_CZ_VF_MSE_LBN 3
1482 #define PCRF_CZ_VF_MSE_WIDTH 1
1483 #define PCRF_CZ_VF_MIGR_INT_EN_LBN 2
1484 #define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1
1485 #define PCRF_CZ_VF_MIGR_EN_LBN 1
1486 #define PCRF_CZ_VF_MIGR_EN_WIDTH 1
1487 #define PCRF_CZ_VF_EN_LBN 0
1488 #define PCRF_CZ_VF_EN_WIDTH 1
1492 * PC_SRIOV_STAT_REG(16bit):
1496 #define PCR_CC_SRIOV_STAT_REG 0x0000016a
1497 /* sienaa0=pci_f0_config */
1499 #define PCR_DZ_SRIOV_STAT_REG 0x0000018a
1500 /* hunta0=pci_f0_config */
1502 #define PCRF_CZ_VF_MIGR_STAT_LBN 0
1503 #define PCRF_CZ_VF_MIGR_STAT_WIDTH 1
1507 * PC_LANE01_EQU_CONTROL_REG(32bit):
1508 * Lanes 0,1 Equalization Control Register.
1511 #define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c
1512 /* hunta0=pci_f0_config */
1514 #define PCRF_DZ_LANE1_EQ_CTRL_LBN 16
1515 #define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16
1516 #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0
1517 #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16
1521 * PC_SRIOV_INITIALVFS_REG(16bit):
1525 #define PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c
1526 /* sienaa0=pci_f0_config */
1528 #define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c
1529 /* hunta0=pci_f0_config */
1531 #define PCRF_CZ_VF_INITIALVFS_LBN 0
1532 #define PCRF_CZ_VF_INITIALVFS_WIDTH 16
1536 * PC_SRIOV_TOTALVFS_REG(10bit):
1540 #define PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e
1541 /* sienaa0=pci_f0_config */
1543 #define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e
1544 /* hunta0=pci_f0_config */
1546 #define PCRF_CZ_VF_TOTALVFS_LBN 0
1547 #define PCRF_CZ_VF_TOTALVFS_WIDTH 16
1551 * PC_SRIOV_NUMVFS_REG(16bit):
1552 * SRIOV Number of VFs
1555 #define PCR_CC_SRIOV_NUMVFS_REG 0x00000170
1556 /* sienaa0=pci_f0_config */
1558 #define PCR_DZ_SRIOV_NUMVFS_REG 0x00000190
1559 /* hunta0=pci_f0_config */
1561 #define PCRF_CZ_VF_NUMVFS_LBN 0
1562 #define PCRF_CZ_VF_NUMVFS_WIDTH 16
1566 * PC_LANE23_EQU_CONTROL_REG(32bit):
1567 * Lanes 2,3 Equalization Control Register.
1570 #define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170
1571 /* hunta0=pci_f0_config */
1573 #define PCRF_DZ_LANE3_EQ_CTRL_LBN 16
1574 #define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16
1575 #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0
1576 #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16
1580 * PC_SRIOV_FN_DPND_LNK_REG(16bit):
1581 * SRIOV Function dependency link
1584 #define PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172
1585 /* sienaa0=pci_f0_config */
1587 #define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192
1588 /* hunta0=pci_f0_config */
1590 #define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0
1591 #define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8
1595 * PC_SRIOV_1STVF_OFFSET_REG(16bit):
1596 * SRIOV First VF Offset
1599 #define PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174
1600 /* sienaa0=pci_f0_config */
1602 #define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194
1603 /* hunta0=pci_f0_config */
1605 #define PCRF_CZ_VF_1STVF_OFFSET_LBN 0
1606 #define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16
1610 * PC_LANE45_EQU_CONTROL_REG(32bit):
1611 * Lanes 4,5 Equalization Control Register.
1614 #define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174
1615 /* hunta0=pci_f0_config */
1617 #define PCRF_DZ_LANE5_EQ_CTRL_LBN 16
1618 #define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16
1619 #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0
1620 #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16
1624 * PC_SRIOV_VFSTRIDE_REG(16bit):
1628 #define PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176
1629 /* sienaa0=pci_f0_config */
1631 #define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196
1632 /* hunta0=pci_f0_config */
1634 #define PCRF_CZ_VF_VFSTRIDE_LBN 0
1635 #define PCRF_CZ_VF_VFSTRIDE_WIDTH 16
1639 * PC_LANE67_EQU_CONTROL_REG(32bit):
1640 * Lanes 6,7 Equalization Control Register.
1643 #define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178
1644 /* hunta0=pci_f0_config */
1646 #define PCRF_DZ_LANE7_EQ_CTRL_LBN 16
1647 #define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16
1648 #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0
1649 #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16
1653 * PC_SRIOV_DEVID_REG(16bit):
1654 * SRIOV VF Device ID
1657 #define PCR_CC_SRIOV_DEVID_REG 0x0000017a
1658 /* sienaa0=pci_f0_config */
1660 #define PCR_DZ_SRIOV_DEVID_REG 0x0000019a
1661 /* hunta0=pci_f0_config */
1663 #define PCRF_CZ_VF_DEVID_LBN 0
1664 #define PCRF_CZ_VF_DEVID_WIDTH 16
1668 * PC_SRIOV_SUP_PAGESZ_REG(16bit):
1669 * SRIOV Supported Page Sizes
1672 #define PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c
1673 /* sienaa0=pci_f0_config */
1675 #define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c
1676 /* hunta0=pci_f0_config */
1678 #define PCRF_CZ_VF_SUP_PAGESZ_LBN 0
1679 #define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16
1683 * PC_SRIOV_SYS_PAGESZ_REG(32bit):
1684 * SRIOV System Page Size
1687 #define PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180
1688 /* sienaa0=pci_f0_config */
1690 #define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0
1691 /* hunta0=pci_f0_config */
1693 #define PCRF_CZ_VF_SYS_PAGESZ_LBN 0
1694 #define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16
1698 * PC_SRIOV_BAR0_REG(32bit):
1702 #define PCR_CC_SRIOV_BAR0_REG 0x00000184
1703 /* sienaa0=pci_f0_config */
1705 #define PCR_DZ_SRIOV_BAR0_REG 0x000001a4
1706 /* hunta0=pci_f0_config */
1708 #define PCRF_CC_VF_BAR_ADDRESS_LBN 0
1709 #define PCRF_CC_VF_BAR_ADDRESS_WIDTH 32
1710 #define PCRF_DZ_VF_BAR0_ADDRESS_LBN 4
1711 #define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28
1712 #define PCRF_DZ_VF_BAR0_PREF_LBN 3
1713 #define PCRF_DZ_VF_BAR0_PREF_WIDTH 1
1714 #define PCRF_DZ_VF_BAR0_TYPE_LBN 1
1715 #define PCRF_DZ_VF_BAR0_TYPE_WIDTH 2
1716 #define PCRF_DZ_VF_BAR0_IOM_LBN 0
1717 #define PCRF_DZ_VF_BAR0_IOM_WIDTH 1
1721 * PC_SRIOV_BAR1_REG(32bit):
1725 #define PCR_CC_SRIOV_BAR1_REG 0x00000188
1726 /* sienaa0=pci_f0_config */
1728 #define PCR_DZ_SRIOV_BAR1_REG 0x000001a8
1729 /* hunta0=pci_f0_config */
1731 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1732 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1733 #define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0
1734 #define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32
1738 * PC_SRIOV_BAR2_REG(32bit):
1742 #define PCR_CC_SRIOV_BAR2_REG 0x0000018c
1743 /* sienaa0=pci_f0_config */
1745 #define PCR_DZ_SRIOV_BAR2_REG 0x000001ac
1746 /* hunta0=pci_f0_config */
1748 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1749 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1750 #define PCRF_DZ_VF_BAR2_ADDRESS_LBN 4
1751 #define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28
1752 #define PCRF_DZ_VF_BAR2_PREF_LBN 3
1753 #define PCRF_DZ_VF_BAR2_PREF_WIDTH 1
1754 #define PCRF_DZ_VF_BAR2_TYPE_LBN 1
1755 #define PCRF_DZ_VF_BAR2_TYPE_WIDTH 2
1756 #define PCRF_DZ_VF_BAR2_IOM_LBN 0
1757 #define PCRF_DZ_VF_BAR2_IOM_WIDTH 1
1761 * PC_SRIOV_BAR3_REG(32bit):
1765 #define PCR_CC_SRIOV_BAR3_REG 0x00000190
1766 /* sienaa0=pci_f0_config */
1768 #define PCR_DZ_SRIOV_BAR3_REG 0x000001b0
1769 /* hunta0=pci_f0_config */
1771 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1772 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1773 #define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0
1774 #define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32
1778 * PC_SRIOV_BAR4_REG(32bit):
1782 #define PCR_CC_SRIOV_BAR4_REG 0x00000194
1783 /* sienaa0=pci_f0_config */
1785 #define PCR_DZ_SRIOV_BAR4_REG 0x000001b4
1786 /* hunta0=pci_f0_config */
1788 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1789 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1790 #define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0
1791 #define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32
1795 * PC_SRIOV_BAR5_REG(32bit):
1799 #define PCR_CC_SRIOV_BAR5_REG 0x00000198
1800 /* sienaa0=pci_f0_config */
1802 #define PCR_DZ_SRIOV_BAR5_REG 0x000001b8
1803 /* hunta0=pci_f0_config */
1805 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1806 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1807 #define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0
1808 #define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32
1812 * PC_SRIOV_RSVD_REG(16bit):
1816 #define PCR_DZ_SRIOV_RSVD_REG 0x00000198
1817 /* hunta0=pci_f0_config */
1819 #define PCRF_DZ_VF_RSVD_LBN 0
1820 #define PCRF_DZ_VF_RSVD_WIDTH 16
1824 * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit):
1825 * SRIOV VF Migration State Array Offset
1828 #define PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c
1829 /* sienaa0=pci_f0_config */
1831 #define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc
1832 /* hunta0=pci_f0_config */
1834 #define PCRF_CZ_VF_MIGR_OFFSET_LBN 3
1835 #define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29
1836 #define PCRF_CZ_VF_MIGR_BIR_LBN 0
1837 #define PCRF_CZ_VF_MIGR_BIR_WIDTH 3
1841 * PC_TPH_CAP_HDR_REG(32bit):
1842 * TPH Capability Header Register
1845 #define PCR_DZ_TPH_CAP_HDR_REG 0x000001c0
1846 /* hunta0=pci_f0_config */
1848 #define PCRF_DZ_TPH_NXT_PTR_LBN 20
1849 #define PCRF_DZ_TPH_NXT_PTR_WIDTH 12
1850 #define PCRF_DZ_TPH_VERSION_LBN 16
1851 #define PCRF_DZ_TPH_VERSION_WIDTH 4
1852 #define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0
1853 #define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16
1857 * PC_TPH_REQ_CAP_REG(32bit):
1858 * TPH Requester Capability Register
1861 #define PCR_DZ_TPH_REQ_CAP_REG 0x000001c4
1862 /* hunta0=pci_f0_config */
1864 #define PCRF_DZ_ST_TBLE_SIZE_LBN 16
1865 #define PCRF_DZ_ST_TBLE_SIZE_WIDTH 11
1866 #define PCRF_DZ_ST_TBLE_LOC_LBN 9
1867 #define PCRF_DZ_ST_TBLE_LOC_WIDTH 2
1868 #define PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8
1869 #define PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1
1870 #define PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2
1871 #define PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1
1872 #define PCRF_DZ_TPH_INT_MODE_SUP_LBN 1
1873 #define PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1
1874 #define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0
1875 #define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1
1879 * PC_TPH_REQ_CTL_REG(32bit):
1880 * TPH Requester Control Register
1883 #define PCR_DZ_TPH_REQ_CTL_REG 0x000001c8
1884 /* hunta0=pci_f0_config */
1886 #define PCRF_DZ_TPH_REQ_ENABLE_LBN 8
1887 #define PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2
1888 #define PCRF_DZ_TPH_ST_MODE_LBN 0
1889 #define PCRF_DZ_TPH_ST_MODE_WIDTH 3
1893 * PC_LTR_CAP_HDR_REG(32bit):
1894 * Latency Tolerance Reporting Cap Header Reg
1897 #define PCR_DZ_LTR_CAP_HDR_REG 0x00000290
1898 /* hunta0=pci_f0_config */
1900 #define PCRF_DZ_LTR_NXT_PTR_LBN 20
1901 #define PCRF_DZ_LTR_NXT_PTR_WIDTH 12
1902 #define PCRF_DZ_LTR_VERSION_LBN 16
1903 #define PCRF_DZ_LTR_VERSION_WIDTH 4
1904 #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0
1905 #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16
1909 * PC_LTR_MAX_SNOOP_REG(32bit):
1910 * LTR Maximum Snoop/No Snoop Register
1913 #define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294
1914 /* hunta0=pci_f0_config */
1916 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26
1917 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3
1918 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16
1919 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10
1920 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10
1921 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3
1922 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0
1923 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10
1927 * PC_ACK_LAT_TMR_REG(32bit):
1928 * ACK latency timer & replay timer register
1931 #define PCR_AC_ACK_LAT_TMR_REG 0x00000700
1932 /* falcona0,falconb0,sienaa0=pci_f0_config */
1934 #define PCRF_AC_RT_LBN 16
1935 #define PCRF_AC_RT_WIDTH 16
1936 #define PCRF_AC_ALT_LBN 0
1937 #define PCRF_AC_ALT_WIDTH 16
1941 * PC_OTHER_MSG_REG(32bit):
1942 * Other message register
1945 #define PCR_AC_OTHER_MSG_REG 0x00000704
1946 /* falcona0,falconb0,sienaa0=pci_f0_config */
1948 #define PCRF_AC_OM_CRPT3_LBN 24
1949 #define PCRF_AC_OM_CRPT3_WIDTH 8
1950 #define PCRF_AC_OM_CRPT2_LBN 16
1951 #define PCRF_AC_OM_CRPT2_WIDTH 8
1952 #define PCRF_AC_OM_CRPT1_LBN 8
1953 #define PCRF_AC_OM_CRPT1_WIDTH 8
1954 #define PCRF_AC_OM_CRPT0_LBN 0
1955 #define PCRF_AC_OM_CRPT0_WIDTH 8
1959 * PC_FORCE_LNK_REG(24bit):
1960 * Port force link register
1963 #define PCR_AC_FORCE_LNK_REG 0x00000708
1964 /* falcona0,falconb0,sienaa0=pci_f0_config */
1966 #define PCRF_AC_LFS_LBN 16
1967 #define PCRF_AC_LFS_WIDTH 6
1968 #define PCRF_AC_FL_LBN 15
1969 #define PCRF_AC_FL_WIDTH 1
1970 #define PCRF_AC_LN_LBN 0
1971 #define PCRF_AC_LN_WIDTH 8
1975 * PC_ACK_FREQ_REG(32bit):
1976 * ACK frequency register
1979 #define PCR_AC_ACK_FREQ_REG 0x0000070c
1980 /* falcona0,falconb0,sienaa0=pci_f0_config */
1982 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30
1983 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1
1984 #define PCRF_AC_L1_ENTR_LAT_LBN 27
1985 #define PCRF_AC_L1_ENTR_LAT_WIDTH 3
1986 #define PCRF_AC_L0_ENTR_LAT_LBN 24
1987 #define PCRF_AC_L0_ENTR_LAT_WIDTH 3
1988 #define PCRF_CC_COMM_NFTS_LBN 16
1989 #define PCRF_CC_COMM_NFTS_WIDTH 8
1990 #define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16
1991 #define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3
1992 #define PCRF_AC_MAX_FTS_LBN 8
1993 #define PCRF_AC_MAX_FTS_WIDTH 8
1994 #define PCRF_AC_ACK_FREQ_LBN 0
1995 #define PCRF_AC_ACK_FREQ_WIDTH 8
1999 * PC_PORT_LNK_CTL_REG(32bit):
2000 * Port link control register
2003 #define PCR_AC_PORT_LNK_CTL_REG 0x00000710
2004 /* falcona0,falconb0,sienaa0=pci_f0_config */
2006 #define PCRF_AB_LRE_LBN 27
2007 #define PCRF_AB_LRE_WIDTH 1
2008 #define PCRF_AB_ESYNC_LBN 26
2009 #define PCRF_AB_ESYNC_WIDTH 1
2010 #define PCRF_AB_CRPT_LBN 25
2011 #define PCRF_AB_CRPT_WIDTH 1
2012 #define PCRF_AB_XB_LBN 24
2013 #define PCRF_AB_XB_WIDTH 1
2014 #define PCRF_AC_LC_LBN 16
2015 #define PCRF_AC_LC_WIDTH 6
2016 #define PCRF_AC_LDR_LBN 8
2017 #define PCRF_AC_LDR_WIDTH 4
2018 #define PCRF_AC_FLM_LBN 7
2019 #define PCRF_AC_FLM_WIDTH 1
2020 #define PCRF_AC_LKD_LBN 6
2021 #define PCRF_AC_LKD_WIDTH 1
2022 #define PCRF_AC_DLE_LBN 5
2023 #define PCRF_AC_DLE_WIDTH 1
2024 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4
2025 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1
2026 #define PCRF_AC_RA_LBN 3
2027 #define PCRF_AC_RA_WIDTH 1
2028 #define PCRF_AC_LE_LBN 2
2029 #define PCRF_AC_LE_WIDTH 1
2030 #define PCRF_AC_SD_LBN 1
2031 #define PCRF_AC_SD_WIDTH 1
2032 #define PCRF_AC_OMR_LBN 0
2033 #define PCRF_AC_OMR_WIDTH 1
2037 * PC_LN_SKEW_REG(32bit):
2038 * Lane skew register
2041 #define PCR_AC_LN_SKEW_REG 0x00000714
2042 /* falcona0,falconb0,sienaa0=pci_f0_config */
2044 #define PCRF_AC_DIS_LBN 31
2045 #define PCRF_AC_DIS_WIDTH 1
2046 #define PCRF_AB_RST_LBN 30
2047 #define PCRF_AB_RST_WIDTH 1
2048 #define PCRF_AC_AD_LBN 25
2049 #define PCRF_AC_AD_WIDTH 1
2050 #define PCRF_AC_FCD_LBN 24
2051 #define PCRF_AC_FCD_WIDTH 1
2052 #define PCRF_AC_LS2_LBN 16
2053 #define PCRF_AC_LS2_WIDTH 8
2054 #define PCRF_AC_LS1_LBN 8
2055 #define PCRF_AC_LS1_WIDTH 8
2056 #define PCRF_AC_LS0_LBN 0
2057 #define PCRF_AC_LS0_WIDTH 8
2061 * PC_SYM_NUM_REG(16bit):
2062 * Symbol number register
2065 #define PCR_AC_SYM_NUM_REG 0x00000718
2066 /* falcona0,falconb0,sienaa0=pci_f0_config */
2068 #define PCRF_CC_MAX_FUNCTIONS_LBN 29
2069 #define PCRF_CC_MAX_FUNCTIONS_WIDTH 3
2070 #define PCRF_CC_FC_WATCHDOG_TMR_LBN 24
2071 #define PCRF_CC_FC_WATCHDOG_TMR_WIDTH 5
2072 #define PCRF_CC_ACK_NAK_TMR_MOD_LBN 19
2073 #define PCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5
2074 #define PCRF_CC_REPLAY_TMR_MOD_LBN 14
2075 #define PCRF_CC_REPLAY_TMR_MOD_WIDTH 5
2076 #define PCRF_AB_ES_LBN 12
2077 #define PCRF_AB_ES_WIDTH 3
2078 #define PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11
2079 #define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1
2080 #define PCRF_CC_NUM_SKP_SYMS_LBN 8
2081 #define PCRF_CC_NUM_SKP_SYMS_WIDTH 3
2082 #define PCRF_AB_TS2_LBN 4
2083 #define PCRF_AB_TS2_WIDTH 4
2084 #define PCRF_AC_TS1_LBN 0
2085 #define PCRF_AC_TS1_WIDTH 4
2089 * PC_SYM_TMR_FLT_MSK_REG(16bit):
2090 * Symbol timer and Filter Mask Register
2093 #define PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c
2094 /* sienaa0=pci_f0_config */
2096 #define PCRF_CC_DEFAULT_FLT_MSK1_LBN 16
2097 #define PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16
2098 #define PCRF_CC_FC_WDOG_TMR_DIS_LBN 15
2099 #define PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1
2100 #define PCRF_CC_SI1_LBN 8
2101 #define PCRF_CC_SI1_WIDTH 3
2102 #define PCRF_CC_SKIP_INT_VAL_LBN 0
2103 #define PCRF_CC_SKIP_INT_VAL_WIDTH 11
2104 #define PCRF_CC_SI0_LBN 0
2105 #define PCRF_CC_SI0_WIDTH 8
2109 * PC_SYM_TMR_REG(16bit):
2110 * Symbol timer register
2113 #define PCR_AB_SYM_TMR_REG 0x0000071c
2114 /* falcona0,falconb0=pci_f0_config */
2116 #define PCRF_AB_ET_LBN 11
2117 #define PCRF_AB_ET_WIDTH 4
2118 #define PCRF_AB_SI1_LBN 8
2119 #define PCRF_AB_SI1_WIDTH 3
2120 #define PCRF_AB_SI0_LBN 0
2121 #define PCRF_AB_SI0_WIDTH 8
2125 * PC_FLT_MSK_REG(32bit):
2126 * Filter Mask Register 2
2129 #define PCR_CC_FLT_MSK_REG 0x00000720
2130 /* sienaa0=pci_f0_config */
2132 #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0
2133 #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32
2137 * PC_PHY_STAT_REG(32bit):
2138 * PHY status register
2141 #define PCR_AB_PHY_STAT_REG 0x00000720
2142 /* falcona0,falconb0=pci_f0_config */
2144 #define PCR_CC_PHY_STAT_REG 0x00000810
2145 /* sienaa0=pci_f0_config */
2147 #define PCRF_AC_SSL_LBN 3
2148 #define PCRF_AC_SSL_WIDTH 1
2149 #define PCRF_AC_SSR_LBN 2
2150 #define PCRF_AC_SSR_WIDTH 1
2151 #define PCRF_AC_SSCL_LBN 1
2152 #define PCRF_AC_SSCL_WIDTH 1
2153 #define PCRF_AC_SSCD_LBN 0
2154 #define PCRF_AC_SSCD_WIDTH 1
2158 * PC_PHY_CTL_REG(32bit):
2159 * PHY control register
2162 #define PCR_AB_PHY_CTL_REG 0x00000724
2163 /* falcona0,falconb0=pci_f0_config */
2165 #define PCR_CC_PHY_CTL_REG 0x00000814
2166 /* sienaa0=pci_f0_config */
2168 #define PCRF_AC_BD_LBN 31
2169 #define PCRF_AC_BD_WIDTH 1
2170 #define PCRF_AC_CDS_LBN 30
2171 #define PCRF_AC_CDS_WIDTH 1
2172 #define PCRF_AC_DWRAP_LB_LBN 29
2173 #define PCRF_AC_DWRAP_LB_WIDTH 1
2174 #define PCRF_AC_EBD_LBN 28
2175 #define PCRF_AC_EBD_WIDTH 1
2176 #define PCRF_AC_SNR_LBN 27
2177 #define PCRF_AC_SNR_WIDTH 1
2178 #define PCRF_AC_RX_NOT_DET_LBN 2
2179 #define PCRF_AC_RX_NOT_DET_WIDTH 1
2180 #define PCRF_AC_FORCE_LOS_VAL_LBN 1
2181 #define PCRF_AC_FORCE_LOS_VAL_WIDTH 1
2182 #define PCRF_AC_FORCE_LOS_EN_LBN 0
2183 #define PCRF_AC_FORCE_LOS_EN_WIDTH 1
2187 * PC_DEBUG0_REG(32bit):
2191 #define PCR_AC_DEBUG0_REG 0x00000728
2192 /* falcona0,falconb0,sienaa0=pci_f0_config */
2194 #define PCRF_AC_CDI03_LBN 24
2195 #define PCRF_AC_CDI03_WIDTH 8
2196 #define PCRF_AC_CDI0_LBN 0
2197 #define PCRF_AC_CDI0_WIDTH 32
2198 #define PCRF_AC_CDI02_LBN 16
2199 #define PCRF_AC_CDI02_WIDTH 8
2200 #define PCRF_AC_CDI01_LBN 8
2201 #define PCRF_AC_CDI01_WIDTH 8
2202 #define PCRF_AC_CDI00_LBN 0
2203 #define PCRF_AC_CDI00_WIDTH 8
2207 * PC_DEBUG1_REG(32bit):
2211 #define PCR_AC_DEBUG1_REG 0x0000072c
2212 /* falcona0,falconb0,sienaa0=pci_f0_config */
2214 #define PCRF_AC_CDI13_LBN 24
2215 #define PCRF_AC_CDI13_WIDTH 8
2216 #define PCRF_AC_CDI1_LBN 0
2217 #define PCRF_AC_CDI1_WIDTH 32
2218 #define PCRF_AC_CDI12_LBN 16
2219 #define PCRF_AC_CDI12_WIDTH 8
2220 #define PCRF_AC_CDI11_LBN 8
2221 #define PCRF_AC_CDI11_WIDTH 8
2222 #define PCRF_AC_CDI10_LBN 0
2223 #define PCRF_AC_CDI10_WIDTH 8
2227 * PC_XPFCC_STAT_REG(24bit):
2228 * documentation to be written for sum_PC_XPFCC_STAT_REG
2231 #define PCR_AC_XPFCC_STAT_REG 0x00000730
2232 /* falcona0,falconb0,sienaa0=pci_f0_config */
2234 #define PCRF_AC_XPDC_LBN 12
2235 #define PCRF_AC_XPDC_WIDTH 8
2236 #define PCRF_AC_XPHC_LBN 0
2237 #define PCRF_AC_XPHC_WIDTH 12
2241 * PC_XNPFCC_STAT_REG(24bit):
2242 * documentation to be written for sum_PC_XNPFCC_STAT_REG
2245 #define PCR_AC_XNPFCC_STAT_REG 0x00000734
2246 /* falcona0,falconb0,sienaa0=pci_f0_config */
2248 #define PCRF_AC_XNPDC_LBN 12
2249 #define PCRF_AC_XNPDC_WIDTH 8
2250 #define PCRF_AC_XNPHC_LBN 0
2251 #define PCRF_AC_XNPHC_WIDTH 12
2255 * PC_XCFCC_STAT_REG(24bit):
2256 * documentation to be written for sum_PC_XCFCC_STAT_REG
2259 #define PCR_AC_XCFCC_STAT_REG 0x00000738
2260 /* falcona0,falconb0,sienaa0=pci_f0_config */
2262 #define PCRF_AC_XCDC_LBN 12
2263 #define PCRF_AC_XCDC_WIDTH 8
2264 #define PCRF_AC_XCHC_LBN 0
2265 #define PCRF_AC_XCHC_WIDTH 12
2269 * PC_Q_STAT_REG(8bit):
2270 * documentation to be written for sum_PC_Q_STAT_REG
2273 #define PCR_AC_Q_STAT_REG 0x0000073c
2274 /* falcona0,falconb0,sienaa0=pci_f0_config */
2276 #define PCRF_AC_RQNE_LBN 2
2277 #define PCRF_AC_RQNE_WIDTH 1
2278 #define PCRF_AC_XRNE_LBN 1
2279 #define PCRF_AC_XRNE_WIDTH 1
2280 #define PCRF_AC_RCNR_LBN 0
2281 #define PCRF_AC_RCNR_WIDTH 1
2285 * PC_VC_XMIT_ARB1_REG(32bit):
2286 * VC Transmit Arbitration Register 1
2289 #define PCR_CC_VC_XMIT_ARB1_REG 0x00000740
2290 /* sienaa0=pci_f0_config */
2295 * PC_VC_XMIT_ARB2_REG(32bit):
2296 * VC Transmit Arbitration Register 2
2299 #define PCR_CC_VC_XMIT_ARB2_REG 0x00000744
2300 /* sienaa0=pci_f0_config */
2305 * PC_VC0_P_RQ_CTL_REG(32bit):
2306 * VC0 Posted Receive Queue Control
2309 #define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748
2310 /* sienaa0=pci_f0_config */
2315 * PC_VC0_NP_RQ_CTL_REG(32bit):
2316 * VC0 Non-Posted Receive Queue Control
2319 #define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c
2320 /* sienaa0=pci_f0_config */
2325 * PC_VC0_C_RQ_CTL_REG(32bit):
2326 * VC0 Completion Receive Queue Control
2329 #define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750
2330 /* sienaa0=pci_f0_config */
2335 * PC_GEN2_REG(32bit):
2339 #define PCR_CC_GEN2_REG 0x0000080c
2340 /* sienaa0=pci_f0_config */
2342 #define PCRF_CC_SET_DE_EMPHASIS_LBN 20
2343 #define PCRF_CC_SET_DE_EMPHASIS_WIDTH 1
2344 #define PCRF_CC_CFG_TX_COMPLIANCE_LBN 19
2345 #define PCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1
2346 #define PCRF_CC_CFG_TX_SWING_LBN 18
2347 #define PCRF_CC_CFG_TX_SWING_WIDTH 1
2348 #define PCRF_CC_DIR_SPEED_CHANGE_LBN 17
2349 #define PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1
2350 #define PCRF_CC_LANE_ENABLE_LBN 8
2351 #define PCRF_CC_LANE_ENABLE_WIDTH 9
2352 #define PCRF_CC_NUM_FTS_LBN 0
2353 #define PCRF_CC_NUM_FTS_WIDTH 8
2360 #endif /* _SYS_EFX_REGS_PCI_H */