2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
42 static __checkReturn efx_rc_t
50 #if EFSYS_OPT_RX_SCATTER
51 static __checkReturn efx_rc_t
52 siena_rx_scatter_enable(
54 __in unsigned int buf_size);
55 #endif /* EFSYS_OPT_RX_SCATTER */
57 #if EFSYS_OPT_RX_SCALE
58 static __checkReturn efx_rc_t
59 siena_rx_scale_mode_set(
61 __in efx_rx_hash_alg_t alg,
62 __in efx_rx_hash_type_t type,
63 __in boolean_t insert);
65 static __checkReturn efx_rc_t
66 siena_rx_scale_key_set(
68 __in_ecount(n) uint8_t *key,
71 static __checkReturn efx_rc_t
72 siena_rx_scale_tbl_set(
74 __in_ecount(n) unsigned int *table,
77 static __checkReturn uint32_t
80 __in efx_rx_hash_alg_t func,
81 __in uint8_t *buffer);
83 #endif /* EFSYS_OPT_RX_SCALE */
85 static __checkReturn efx_rc_t
86 siena_rx_prefix_pktlen(
89 __out uint16_t *lengthp);
94 __in_ecount(n) efsys_dma_addr_t *addrp,
97 __in unsigned int completed,
98 __in unsigned int added);
103 __in unsigned int added,
104 __inout unsigned int *pushedp);
106 static __checkReturn efx_rc_t
108 __in efx_rxq_t *erp);
112 __in efx_rxq_t *erp);
114 static __checkReturn efx_rc_t
117 __in unsigned int index,
118 __in unsigned int label,
119 __in efx_rxq_type_t type,
120 __in efsys_mem_t *esmp,
124 __in efx_rxq_t *erp);
128 __in efx_rxq_t *erp);
130 #endif /* EFSYS_OPT_SIENA */
134 static const efx_rx_ops_t __efx_rx_siena_ops = {
135 siena_rx_init, /* erxo_init */
136 siena_rx_fini, /* erxo_fini */
137 #if EFSYS_OPT_RX_SCATTER
138 siena_rx_scatter_enable, /* erxo_scatter_enable */
140 #if EFSYS_OPT_RX_SCALE
141 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
142 siena_rx_scale_key_set, /* erxo_scale_key_set */
143 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
144 siena_rx_prefix_hash, /* erxo_prefix_hash */
146 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
147 siena_rx_qpost, /* erxo_qpost */
148 siena_rx_qpush, /* erxo_qpush */
149 siena_rx_qflush, /* erxo_qflush */
150 siena_rx_qenable, /* erxo_qenable */
151 siena_rx_qcreate, /* erxo_qcreate */
152 siena_rx_qdestroy, /* erxo_qdestroy */
154 #endif /* EFSYS_OPT_SIENA */
156 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
157 static const efx_rx_ops_t __efx_rx_ef10_ops = {
158 ef10_rx_init, /* erxo_init */
159 ef10_rx_fini, /* erxo_fini */
160 #if EFSYS_OPT_RX_SCATTER
161 ef10_rx_scatter_enable, /* erxo_scatter_enable */
163 #if EFSYS_OPT_RX_SCALE
164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash, /* erxo_prefix_hash */
169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
170 ef10_rx_qpost, /* erxo_qpost */
171 ef10_rx_qpush, /* erxo_qpush */
172 ef10_rx_qflush, /* erxo_qflush */
173 ef10_rx_qenable, /* erxo_qenable */
174 ef10_rx_qcreate, /* erxo_qcreate */
175 ef10_rx_qdestroy, /* erxo_qdestroy */
177 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
180 __checkReturn efx_rc_t
182 __inout efx_nic_t *enp)
184 const efx_rx_ops_t *erxop;
187 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
188 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
190 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
195 if (enp->en_mod_flags & EFX_MOD_RX) {
200 switch (enp->en_family) {
202 case EFX_FAMILY_SIENA:
203 erxop = &__efx_rx_siena_ops;
205 #endif /* EFSYS_OPT_SIENA */
207 #if EFSYS_OPT_HUNTINGTON
208 case EFX_FAMILY_HUNTINGTON:
209 erxop = &__efx_rx_ef10_ops;
211 #endif /* EFSYS_OPT_HUNTINGTON */
213 #if EFSYS_OPT_MEDFORD
214 case EFX_FAMILY_MEDFORD:
215 erxop = &__efx_rx_ef10_ops;
217 #endif /* EFSYS_OPT_MEDFORD */
225 if ((rc = erxop->erxo_init(enp)) != 0)
228 enp->en_erxop = erxop;
229 enp->en_mod_flags |= EFX_MOD_RX;
239 EFSYS_PROBE1(fail1, efx_rc_t, rc);
241 enp->en_erxop = NULL;
242 enp->en_mod_flags &= ~EFX_MOD_RX;
250 const efx_rx_ops_t *erxop = enp->en_erxop;
252 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
253 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
254 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
255 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
257 erxop->erxo_fini(enp);
259 enp->en_erxop = NULL;
260 enp->en_mod_flags &= ~EFX_MOD_RX;
263 #if EFSYS_OPT_RX_SCATTER
264 __checkReturn efx_rc_t
265 efx_rx_scatter_enable(
267 __in unsigned int buf_size)
269 const efx_rx_ops_t *erxop = enp->en_erxop;
272 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
273 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
275 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
281 EFSYS_PROBE1(fail1, efx_rc_t, rc);
284 #endif /* EFSYS_OPT_RX_SCATTER */
286 #if EFSYS_OPT_RX_SCALE
287 __checkReturn efx_rc_t
288 efx_rx_hash_support_get(
290 __out efx_rx_hash_support_t *supportp)
294 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
295 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
297 if (supportp == NULL) {
302 /* Report if resources are available to insert RX hash value */
303 *supportp = enp->en_hash_support;
308 EFSYS_PROBE1(fail1, efx_rc_t, rc);
313 __checkReturn efx_rc_t
314 efx_rx_scale_support_get(
316 __out efx_rx_scale_support_t *supportp)
320 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
321 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
323 if (supportp == NULL) {
328 /* Report if resources are available to support RSS */
329 *supportp = enp->en_rss_support;
334 EFSYS_PROBE1(fail1, efx_rc_t, rc);
339 __checkReturn efx_rc_t
340 efx_rx_scale_mode_set(
342 __in efx_rx_hash_alg_t alg,
343 __in efx_rx_hash_type_t type,
344 __in boolean_t insert)
346 const efx_rx_ops_t *erxop = enp->en_erxop;
349 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
350 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
352 if (erxop->erxo_scale_mode_set != NULL) {
353 if ((rc = erxop->erxo_scale_mode_set(enp, alg,
361 EFSYS_PROBE1(fail1, efx_rc_t, rc);
364 #endif /* EFSYS_OPT_RX_SCALE */
366 #if EFSYS_OPT_RX_SCALE
367 __checkReturn efx_rc_t
368 efx_rx_scale_key_set(
370 __in_ecount(n) uint8_t *key,
373 const efx_rx_ops_t *erxop = enp->en_erxop;
376 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
377 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
379 if ((rc = erxop->erxo_scale_key_set(enp, key, n)) != 0)
385 EFSYS_PROBE1(fail1, efx_rc_t, rc);
389 #endif /* EFSYS_OPT_RX_SCALE */
391 #if EFSYS_OPT_RX_SCALE
392 __checkReturn efx_rc_t
393 efx_rx_scale_tbl_set(
395 __in_ecount(n) unsigned int *table,
398 const efx_rx_ops_t *erxop = enp->en_erxop;
401 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
402 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
404 if ((rc = erxop->erxo_scale_tbl_set(enp, table, n)) != 0)
410 EFSYS_PROBE1(fail1, efx_rc_t, rc);
414 #endif /* EFSYS_OPT_RX_SCALE */
419 __in_ecount(n) efsys_dma_addr_t *addrp,
422 __in unsigned int completed,
423 __in unsigned int added)
425 efx_nic_t *enp = erp->er_enp;
426 const efx_rx_ops_t *erxop = enp->en_erxop;
428 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
430 erxop->erxo_qpost(erp, addrp, size, n, completed, added);
436 __in unsigned int added,
437 __inout unsigned int *pushedp)
439 efx_nic_t *enp = erp->er_enp;
440 const efx_rx_ops_t *erxop = enp->en_erxop;
442 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
444 erxop->erxo_qpush(erp, added, pushedp);
447 __checkReturn efx_rc_t
451 efx_nic_t *enp = erp->er_enp;
452 const efx_rx_ops_t *erxop = enp->en_erxop;
455 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
457 if ((rc = erxop->erxo_qflush(erp)) != 0)
463 EFSYS_PROBE1(fail1, efx_rc_t, rc);
472 efx_nic_t *enp = erp->er_enp;
473 const efx_rx_ops_t *erxop = enp->en_erxop;
475 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
477 erxop->erxo_qenable(erp);
480 __checkReturn efx_rc_t
483 __in unsigned int index,
484 __in unsigned int label,
485 __in efx_rxq_type_t type,
486 __in efsys_mem_t *esmp,
490 __deref_out efx_rxq_t **erpp)
492 const efx_rx_ops_t *erxop = enp->en_erxop;
496 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
497 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
499 /* Allocate an RXQ object */
500 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
507 erp->er_magic = EFX_RXQ_MAGIC;
509 erp->er_index = index;
510 erp->er_mask = n - 1;
513 if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id,
525 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
527 EFSYS_PROBE1(fail1, efx_rc_t, rc);
536 efx_nic_t *enp = erp->er_enp;
537 const efx_rx_ops_t *erxop = enp->en_erxop;
539 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
541 erxop->erxo_qdestroy(erp);
544 __checkReturn efx_rc_t
545 efx_pseudo_hdr_pkt_length_get(
547 __in uint8_t *buffer,
548 __out uint16_t *lengthp)
550 efx_nic_t *enp = erp->er_enp;
551 const efx_rx_ops_t *erxop = enp->en_erxop;
553 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
555 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
558 #if EFSYS_OPT_RX_SCALE
559 __checkReturn uint32_t
560 efx_pseudo_hdr_hash_get(
562 __in efx_rx_hash_alg_t func,
563 __in uint8_t *buffer)
565 efx_nic_t *enp = erp->er_enp;
566 const efx_rx_ops_t *erxop = enp->en_erxop;
568 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
570 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
571 return (erxop->erxo_prefix_hash(enp, func, buffer));
573 #endif /* EFSYS_OPT_RX_SCALE */
577 static __checkReturn efx_rc_t
584 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
586 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
587 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
588 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
589 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
590 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
591 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
592 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
594 /* Zero the RSS table */
595 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
597 EFX_ZERO_OWORD(oword);
598 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
599 index, &oword, B_TRUE);
602 #if EFSYS_OPT_RX_SCALE
603 /* The RSS key and indirection table are writable. */
604 enp->en_rss_support = EFX_RX_SCALE_EXCLUSIVE;
606 /* Hardware can insert RX hash with/without RSS */
607 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
608 #endif /* EFSYS_OPT_RX_SCALE */
613 #if EFSYS_OPT_RX_SCATTER
614 static __checkReturn efx_rc_t
615 siena_rx_scatter_enable(
617 __in unsigned int buf_size)
623 nbuf32 = buf_size / 32;
625 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
626 ((buf_size % 32) != 0)) {
631 if (enp->en_rx_qcount > 0) {
636 /* Set scatter buffer size */
637 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
638 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
639 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
641 /* Enable scatter for packets not matching a filter */
642 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
643 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
644 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
651 EFSYS_PROBE1(fail1, efx_rc_t, rc);
655 #endif /* EFSYS_OPT_RX_SCATTER */
658 #define EFX_RX_LFSR_HASH(_enp, _insert) \
662 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
663 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
664 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
665 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
666 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
667 (_insert) ? 1 : 0); \
668 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
670 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
671 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
673 EFX_SET_OWORD_FIELD(oword, \
674 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
675 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
679 _NOTE(CONSTANTCONDITION) \
682 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
686 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
687 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
688 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
690 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
692 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
693 (_insert) ? 1 : 0); \
694 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
696 _NOTE(CONSTANTCONDITION) \
699 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
703 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
704 EFX_SET_OWORD_FIELD(oword, \
705 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
706 EFX_SET_OWORD_FIELD(oword, \
707 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
708 EFX_SET_OWORD_FIELD(oword, \
709 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
710 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
714 _NOTE(CONSTANTCONDITION) \
718 #if EFSYS_OPT_RX_SCALE
720 static __checkReturn efx_rc_t
721 siena_rx_scale_mode_set(
723 __in efx_rx_hash_alg_t alg,
724 __in efx_rx_hash_type_t type,
725 __in boolean_t insert)
730 case EFX_RX_HASHALG_LFSR:
731 EFX_RX_LFSR_HASH(enp, insert);
734 case EFX_RX_HASHALG_TOEPLITZ:
735 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
736 type & EFX_RX_HASH_IPV4,
737 type & EFX_RX_HASH_TCPIPV4);
739 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
740 type & EFX_RX_HASH_IPV6,
741 type & EFX_RX_HASH_TCPIPV6,
758 EFSYS_PROBE1(fail1, efx_rc_t, rc);
760 EFX_RX_LFSR_HASH(enp, B_FALSE);
766 #if EFSYS_OPT_RX_SCALE
767 static __checkReturn efx_rc_t
768 siena_rx_scale_key_set(
770 __in_ecount(n) uint8_t *key,
780 /* Write Toeplitz IPv4 hash key */
781 EFX_ZERO_OWORD(oword);
782 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
783 offset > 0 && byte < n;
785 oword.eo_u8[offset - 1] = key[byte++];
787 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
791 /* Verify Toeplitz IPv4 hash key */
792 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
793 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
794 offset > 0 && byte < n;
796 if (oword.eo_u8[offset - 1] != key[byte++]) {
802 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
807 /* Write Toeplitz IPv6 hash key 3 */
808 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
809 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
810 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
811 offset > 0 && byte < n;
813 oword.eo_u8[offset - 1] = key[byte++];
815 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
817 /* Write Toeplitz IPv6 hash key 2 */
818 EFX_ZERO_OWORD(oword);
819 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
820 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
821 offset > 0 && byte < n;
823 oword.eo_u8[offset - 1] = key[byte++];
825 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
827 /* Write Toeplitz IPv6 hash key 1 */
828 EFX_ZERO_OWORD(oword);
829 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
830 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
831 offset > 0 && byte < n;
833 oword.eo_u8[offset - 1] = key[byte++];
835 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
839 /* Verify Toeplitz IPv6 hash key 3 */
840 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
841 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
842 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
843 offset > 0 && byte < n;
845 if (oword.eo_u8[offset - 1] != key[byte++]) {
851 /* Verify Toeplitz IPv6 hash key 2 */
852 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
853 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
854 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
855 offset > 0 && byte < n;
857 if (oword.eo_u8[offset - 1] != key[byte++]) {
863 /* Verify Toeplitz IPv6 hash key 1 */
864 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
865 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
866 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
867 offset > 0 && byte < n;
869 if (oword.eo_u8[offset - 1] != key[byte++]) {
885 EFSYS_PROBE1(fail1, efx_rc_t, rc);
891 #if EFSYS_OPT_RX_SCALE
892 static __checkReturn efx_rc_t
893 siena_rx_scale_tbl_set(
895 __in_ecount(n) unsigned int *table,
902 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
903 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
905 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
910 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
913 /* Calculate the entry to place in the table */
914 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
916 EFSYS_PROBE2(table, int, index, uint32_t, byte);
918 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
920 /* Write the table */
921 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
922 index, &oword, B_TRUE);
925 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
928 /* Determine if we're starting a new batch */
929 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
932 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
933 index, &oword, B_TRUE);
935 /* Verify the entry */
936 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
947 EFSYS_PROBE1(fail1, efx_rc_t, rc);
954 * Falcon/Siena pseudo-header
955 * --------------------------
957 * Receive packets are prefixed by an optional 16 byte pseudo-header.
958 * The pseudo-header is a byte array of one of the forms:
960 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
961 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
962 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
965 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
966 * LL.LL LFSR hash (16-bit big-endian)
969 #if EFSYS_OPT_RX_SCALE
970 static __checkReturn uint32_t
971 siena_rx_prefix_hash(
973 __in efx_rx_hash_alg_t func,
974 __in uint8_t *buffer)
976 _NOTE(ARGUNUSED(enp))
979 case EFX_RX_HASHALG_TOEPLITZ:
980 return ((buffer[12] << 24) |
985 case EFX_RX_HASHALG_LFSR:
986 return ((buffer[14] << 8) | buffer[15]);
993 #endif /* EFSYS_OPT_RX_SCALE */
995 static __checkReturn efx_rc_t
996 siena_rx_prefix_pktlen(
998 __in uint8_t *buffer,
999 __out uint16_t *lengthp)
1001 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1003 /* Not supported by Falcon/Siena hardware */
1011 __in efx_rxq_t *erp,
1012 __in_ecount(n) efsys_dma_addr_t *addrp,
1014 __in unsigned int n,
1015 __in unsigned int completed,
1016 __in unsigned int added)
1020 unsigned int offset;
1023 /* The client driver must not overfill the queue */
1024 EFSYS_ASSERT3U(added - completed + n, <=,
1025 EFX_RXQ_LIMIT(erp->er_mask + 1));
1027 id = added & (erp->er_mask);
1028 for (i = 0; i < n; i++) {
1029 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1030 unsigned int, id, efsys_dma_addr_t, addrp[i],
1033 EFX_POPULATE_QWORD_3(qword,
1034 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1035 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1036 (uint32_t)(addrp[i] & 0xffffffff),
1037 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1038 (uint32_t)(addrp[i] >> 32));
1040 offset = id * sizeof (efx_qword_t);
1041 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1043 id = (id + 1) & (erp->er_mask);
1049 __in efx_rxq_t *erp,
1050 __in unsigned int added,
1051 __inout unsigned int *pushedp)
1053 efx_nic_t *enp = erp->er_enp;
1054 unsigned int pushed = *pushedp;
1059 /* All descriptors are pushed */
1062 /* Push the populated descriptors out */
1063 wptr = added & erp->er_mask;
1065 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1067 /* Only write the third DWORD */
1068 EFX_POPULATE_DWORD_1(dword,
1069 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1071 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1072 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1073 wptr, pushed & erp->er_mask);
1074 EFSYS_PIO_WRITE_BARRIER();
1075 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1076 erp->er_index, &dword, B_FALSE);
1079 static __checkReturn efx_rc_t
1081 __in efx_rxq_t *erp)
1083 efx_nic_t *enp = erp->er_enp;
1087 label = erp->er_index;
1089 /* Flush the queue */
1090 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1091 FRF_AZ_RX_FLUSH_DESCQ, label);
1092 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1099 __in efx_rxq_t *erp)
1101 efx_nic_t *enp = erp->er_enp;
1104 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1106 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1107 erp->er_index, &oword, B_TRUE);
1109 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1110 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1111 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1113 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1114 erp->er_index, &oword, B_TRUE);
1117 static __checkReturn efx_rc_t
1119 __in efx_nic_t *enp,
1120 __in unsigned int index,
1121 __in unsigned int label,
1122 __in efx_rxq_type_t type,
1123 __in efsys_mem_t *esmp,
1126 __in efx_evq_t *eep,
1127 __in efx_rxq_t *erp)
1129 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1135 _NOTE(ARGUNUSED(esmp))
1137 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1138 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1139 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1140 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1142 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1143 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1145 if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) {
1149 if (index >= encp->enc_rxq_limit) {
1153 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1155 if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS))
1157 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1163 case EFX_RXQ_TYPE_DEFAULT:
1167 #if EFSYS_OPT_RX_SCATTER
1168 case EFX_RXQ_TYPE_SCATTER:
1169 if (enp->en_family < EFX_FAMILY_SIENA) {
1175 #endif /* EFSYS_OPT_RX_SCATTER */
1182 /* Set up the new descriptor queue */
1183 EFX_POPULATE_OWORD_7(oword,
1184 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1185 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1186 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1187 FRF_AZ_RX_DESCQ_LABEL, label,
1188 FRF_AZ_RX_DESCQ_SIZE, size,
1189 FRF_AZ_RX_DESCQ_TYPE, 0,
1190 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1192 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1193 erp->er_index, &oword, B_TRUE);
1204 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1211 __in efx_rxq_t *erp)
1213 efx_nic_t *enp = erp->er_enp;
1216 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1217 --enp->en_rx_qcount;
1219 /* Purge descriptor queue */
1220 EFX_ZERO_OWORD(oword);
1222 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1223 erp->er_index, &oword, B_TRUE);
1225 /* Free the RXQ object */
1226 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1231 __in efx_nic_t *enp)
1233 _NOTE(ARGUNUSED(enp))
1236 #endif /* EFSYS_OPT_SIENA */