2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
40 static __checkReturn efx_rc_t
48 #if EFSYS_OPT_RX_SCATTER
49 static __checkReturn efx_rc_t
50 siena_rx_scatter_enable(
52 __in unsigned int buf_size);
53 #endif /* EFSYS_OPT_RX_SCATTER */
55 #if EFSYS_OPT_RX_SCALE
56 static __checkReturn efx_rc_t
57 siena_rx_scale_mode_set(
59 __in efx_rx_hash_alg_t alg,
60 __in efx_rx_hash_type_t type,
61 __in boolean_t insert);
63 static __checkReturn efx_rc_t
64 siena_rx_scale_key_set(
66 __in_ecount(n) uint8_t *key,
69 static __checkReturn efx_rc_t
70 siena_rx_scale_tbl_set(
72 __in_ecount(n) unsigned int *table,
75 static __checkReturn uint32_t
78 __in efx_rx_hash_alg_t func,
79 __in uint8_t *buffer);
81 #endif /* EFSYS_OPT_RX_SCALE */
83 static __checkReturn efx_rc_t
84 siena_rx_prefix_pktlen(
87 __out uint16_t *lengthp);
92 __in_ecount(n) efsys_dma_addr_t *addrp,
95 __in unsigned int completed,
96 __in unsigned int added);
101 __in unsigned int added,
102 __inout unsigned int *pushedp);
104 static __checkReturn efx_rc_t
106 __in efx_rxq_t *erp);
110 __in efx_rxq_t *erp);
112 static __checkReturn efx_rc_t
115 __in unsigned int index,
116 __in unsigned int label,
117 __in efx_rxq_type_t type,
118 __in efsys_mem_t *esmp,
122 __in efx_rxq_t *erp);
126 __in efx_rxq_t *erp);
128 #endif /* EFSYS_OPT_SIENA */
132 static const efx_rx_ops_t __efx_rx_siena_ops = {
133 siena_rx_init, /* erxo_init */
134 siena_rx_fini, /* erxo_fini */
135 #if EFSYS_OPT_RX_SCATTER
136 siena_rx_scatter_enable, /* erxo_scatter_enable */
138 #if EFSYS_OPT_RX_SCALE
139 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
140 siena_rx_scale_key_set, /* erxo_scale_key_set */
141 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
142 siena_rx_prefix_hash, /* erxo_prefix_hash */
144 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
145 siena_rx_qpost, /* erxo_qpost */
146 siena_rx_qpush, /* erxo_qpush */
147 siena_rx_qflush, /* erxo_qflush */
148 siena_rx_qenable, /* erxo_qenable */
149 siena_rx_qcreate, /* erxo_qcreate */
150 siena_rx_qdestroy, /* erxo_qdestroy */
152 #endif /* EFSYS_OPT_SIENA */
154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
156 ef10_rx_init, /* erxo_init */
157 ef10_rx_fini, /* erxo_fini */
158 #if EFSYS_OPT_RX_SCATTER
159 ef10_rx_scatter_enable, /* erxo_scatter_enable */
161 #if EFSYS_OPT_RX_SCALE
162 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
163 ef10_rx_scale_key_set, /* erxo_scale_key_set */
164 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
165 ef10_rx_prefix_hash, /* erxo_prefix_hash */
167 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
168 ef10_rx_qpost, /* erxo_qpost */
169 ef10_rx_qpush, /* erxo_qpush */
170 ef10_rx_qflush, /* erxo_qflush */
171 ef10_rx_qenable, /* erxo_qenable */
172 ef10_rx_qcreate, /* erxo_qcreate */
173 ef10_rx_qdestroy, /* erxo_qdestroy */
175 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
178 __checkReturn efx_rc_t
180 __inout efx_nic_t *enp)
182 const efx_rx_ops_t *erxop;
185 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
186 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
188 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
193 if (enp->en_mod_flags & EFX_MOD_RX) {
198 switch (enp->en_family) {
200 case EFX_FAMILY_SIENA:
201 erxop = &__efx_rx_siena_ops;
203 #endif /* EFSYS_OPT_SIENA */
205 #if EFSYS_OPT_HUNTINGTON
206 case EFX_FAMILY_HUNTINGTON:
207 erxop = &__efx_rx_ef10_ops;
209 #endif /* EFSYS_OPT_HUNTINGTON */
211 #if EFSYS_OPT_MEDFORD
212 case EFX_FAMILY_MEDFORD:
213 erxop = &__efx_rx_ef10_ops;
215 #endif /* EFSYS_OPT_MEDFORD */
223 if ((rc = erxop->erxo_init(enp)) != 0)
226 enp->en_erxop = erxop;
227 enp->en_mod_flags |= EFX_MOD_RX;
237 EFSYS_PROBE1(fail1, efx_rc_t, rc);
239 enp->en_erxop = NULL;
240 enp->en_mod_flags &= ~EFX_MOD_RX;
248 const efx_rx_ops_t *erxop = enp->en_erxop;
250 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
251 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
252 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
253 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
255 erxop->erxo_fini(enp);
257 enp->en_erxop = NULL;
258 enp->en_mod_flags &= ~EFX_MOD_RX;
261 #if EFSYS_OPT_RX_SCATTER
262 __checkReturn efx_rc_t
263 efx_rx_scatter_enable(
265 __in unsigned int buf_size)
267 const efx_rx_ops_t *erxop = enp->en_erxop;
270 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
271 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
273 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
279 EFSYS_PROBE1(fail1, efx_rc_t, rc);
282 #endif /* EFSYS_OPT_RX_SCATTER */
284 #if EFSYS_OPT_RX_SCALE
285 __checkReturn efx_rc_t
286 efx_rx_hash_support_get(
288 __out efx_rx_hash_support_t *supportp)
292 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
293 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
295 if (supportp == NULL) {
300 /* Report if resources are available to insert RX hash value */
301 *supportp = enp->en_hash_support;
306 EFSYS_PROBE1(fail1, efx_rc_t, rc);
311 __checkReturn efx_rc_t
312 efx_rx_scale_support_get(
314 __out efx_rx_scale_support_t *supportp)
318 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
319 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
321 if (supportp == NULL) {
326 /* Report if resources are available to support RSS */
327 *supportp = enp->en_rss_support;
332 EFSYS_PROBE1(fail1, efx_rc_t, rc);
337 __checkReturn efx_rc_t
338 efx_rx_scale_mode_set(
340 __in efx_rx_hash_alg_t alg,
341 __in efx_rx_hash_type_t type,
342 __in boolean_t insert)
344 const efx_rx_ops_t *erxop = enp->en_erxop;
347 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
348 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
350 if (erxop->erxo_scale_mode_set != NULL) {
351 if ((rc = erxop->erxo_scale_mode_set(enp, alg,
359 EFSYS_PROBE1(fail1, efx_rc_t, rc);
362 #endif /* EFSYS_OPT_RX_SCALE */
364 #if EFSYS_OPT_RX_SCALE
365 __checkReturn efx_rc_t
366 efx_rx_scale_key_set(
368 __in_ecount(n) uint8_t *key,
371 const efx_rx_ops_t *erxop = enp->en_erxop;
374 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
375 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
377 if ((rc = erxop->erxo_scale_key_set(enp, key, n)) != 0)
383 EFSYS_PROBE1(fail1, efx_rc_t, rc);
387 #endif /* EFSYS_OPT_RX_SCALE */
389 #if EFSYS_OPT_RX_SCALE
390 __checkReturn efx_rc_t
391 efx_rx_scale_tbl_set(
393 __in_ecount(n) unsigned int *table,
396 const efx_rx_ops_t *erxop = enp->en_erxop;
399 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
400 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
402 if ((rc = erxop->erxo_scale_tbl_set(enp, table, n)) != 0)
408 EFSYS_PROBE1(fail1, efx_rc_t, rc);
412 #endif /* EFSYS_OPT_RX_SCALE */
417 __in_ecount(n) efsys_dma_addr_t *addrp,
420 __in unsigned int completed,
421 __in unsigned int added)
423 efx_nic_t *enp = erp->er_enp;
424 const efx_rx_ops_t *erxop = enp->en_erxop;
426 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
428 erxop->erxo_qpost(erp, addrp, size, n, completed, added);
434 __in unsigned int added,
435 __inout unsigned int *pushedp)
437 efx_nic_t *enp = erp->er_enp;
438 const efx_rx_ops_t *erxop = enp->en_erxop;
440 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
442 erxop->erxo_qpush(erp, added, pushedp);
445 __checkReturn efx_rc_t
449 efx_nic_t *enp = erp->er_enp;
450 const efx_rx_ops_t *erxop = enp->en_erxop;
453 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
455 if ((rc = erxop->erxo_qflush(erp)) != 0)
461 EFSYS_PROBE1(fail1, efx_rc_t, rc);
470 efx_nic_t *enp = erp->er_enp;
471 const efx_rx_ops_t *erxop = enp->en_erxop;
473 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
475 erxop->erxo_qenable(erp);
478 __checkReturn efx_rc_t
481 __in unsigned int index,
482 __in unsigned int label,
483 __in efx_rxq_type_t type,
484 __in efsys_mem_t *esmp,
488 __deref_out efx_rxq_t **erpp)
490 const efx_rx_ops_t *erxop = enp->en_erxop;
494 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
495 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
497 /* Allocate an RXQ object */
498 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
505 erp->er_magic = EFX_RXQ_MAGIC;
507 erp->er_index = index;
508 erp->er_mask = n - 1;
511 if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id,
523 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
525 EFSYS_PROBE1(fail1, efx_rc_t, rc);
534 efx_nic_t *enp = erp->er_enp;
535 const efx_rx_ops_t *erxop = enp->en_erxop;
537 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
539 erxop->erxo_qdestroy(erp);
542 __checkReturn efx_rc_t
543 efx_psuedo_hdr_pkt_length_get(
545 __in uint8_t *buffer,
546 __out uint16_t *lengthp)
548 const efx_rx_ops_t *erxop = enp->en_erxop;
550 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
553 #if EFSYS_OPT_RX_SCALE
554 __checkReturn uint32_t
555 efx_psuedo_hdr_hash_get(
557 __in efx_rx_hash_alg_t func,
558 __in uint8_t *buffer)
560 const efx_rx_ops_t *erxop = enp->en_erxop;
562 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
563 return (erxop->erxo_prefix_hash(enp, func, buffer));
565 #endif /* EFSYS_OPT_RX_SCALE */
569 static __checkReturn efx_rc_t
576 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
578 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
579 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
580 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
581 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
582 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
583 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
584 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
586 /* Zero the RSS table */
587 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
589 EFX_ZERO_OWORD(oword);
590 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
591 index, &oword, B_TRUE);
594 #if EFSYS_OPT_RX_SCALE
595 /* The RSS key and indirection table are writable. */
596 enp->en_rss_support = EFX_RX_SCALE_EXCLUSIVE;
598 /* Hardware can insert RX hash with/without RSS */
599 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
600 #endif /* EFSYS_OPT_RX_SCALE */
605 #if EFSYS_OPT_RX_SCATTER
606 static __checkReturn efx_rc_t
607 siena_rx_scatter_enable(
609 __in unsigned int buf_size)
615 nbuf32 = buf_size / 32;
617 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
618 ((buf_size % 32) != 0)) {
623 if (enp->en_rx_qcount > 0) {
628 /* Set scatter buffer size */
629 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
630 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
631 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
633 /* Enable scatter for packets not matching a filter */
634 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
635 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
636 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
643 EFSYS_PROBE1(fail1, efx_rc_t, rc);
647 #endif /* EFSYS_OPT_RX_SCATTER */
650 #define EFX_RX_LFSR_HASH(_enp, _insert) \
654 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
655 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
656 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
657 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
658 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
659 (_insert) ? 1 : 0); \
660 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
662 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
663 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
665 EFX_SET_OWORD_FIELD(oword, \
666 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
667 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
671 _NOTE(CONSTANTCONDITION) \
674 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
678 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
679 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
680 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
682 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
684 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
685 (_insert) ? 1 : 0); \
686 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
688 _NOTE(CONSTANTCONDITION) \
691 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
695 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
696 EFX_SET_OWORD_FIELD(oword, \
697 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
698 EFX_SET_OWORD_FIELD(oword, \
699 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
700 EFX_SET_OWORD_FIELD(oword, \
701 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
702 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
706 _NOTE(CONSTANTCONDITION) \
710 #if EFSYS_OPT_RX_SCALE
712 static __checkReturn efx_rc_t
713 siena_rx_scale_mode_set(
715 __in efx_rx_hash_alg_t alg,
716 __in efx_rx_hash_type_t type,
717 __in boolean_t insert)
722 case EFX_RX_HASHALG_LFSR:
723 EFX_RX_LFSR_HASH(enp, insert);
726 case EFX_RX_HASHALG_TOEPLITZ:
727 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
728 type & (1 << EFX_RX_HASH_IPV4),
729 type & (1 << EFX_RX_HASH_TCPIPV4));
731 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
732 type & (1 << EFX_RX_HASH_IPV6),
733 type & (1 << EFX_RX_HASH_TCPIPV6),
750 EFSYS_PROBE1(fail1, efx_rc_t, rc);
752 EFX_RX_LFSR_HASH(enp, B_FALSE);
758 #if EFSYS_OPT_RX_SCALE
759 static __checkReturn efx_rc_t
760 siena_rx_scale_key_set(
762 __in_ecount(n) uint8_t *key,
772 /* Write Toeplitz IPv4 hash key */
773 EFX_ZERO_OWORD(oword);
774 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
775 offset > 0 && byte < n;
777 oword.eo_u8[offset - 1] = key[byte++];
779 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
783 /* Verify Toeplitz IPv4 hash key */
784 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
785 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
786 offset > 0 && byte < n;
788 if (oword.eo_u8[offset - 1] != key[byte++]) {
794 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
799 /* Write Toeplitz IPv6 hash key 3 */
800 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
801 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
802 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
803 offset > 0 && byte < n;
805 oword.eo_u8[offset - 1] = key[byte++];
807 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
809 /* Write Toeplitz IPv6 hash key 2 */
810 EFX_ZERO_OWORD(oword);
811 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
812 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
813 offset > 0 && byte < n;
815 oword.eo_u8[offset - 1] = key[byte++];
817 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
819 /* Write Toeplitz IPv6 hash key 1 */
820 EFX_ZERO_OWORD(oword);
821 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
822 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
823 offset > 0 && byte < n;
825 oword.eo_u8[offset - 1] = key[byte++];
827 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
831 /* Verify Toeplitz IPv6 hash key 3 */
832 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
833 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
834 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
835 offset > 0 && byte < n;
837 if (oword.eo_u8[offset - 1] != key[byte++]) {
843 /* Verify Toeplitz IPv6 hash key 2 */
844 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
845 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
846 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
847 offset > 0 && byte < n;
849 if (oword.eo_u8[offset - 1] != key[byte++]) {
855 /* Verify Toeplitz IPv6 hash key 1 */
856 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
857 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
858 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
859 offset > 0 && byte < n;
861 if (oword.eo_u8[offset - 1] != key[byte++]) {
877 EFSYS_PROBE1(fail1, efx_rc_t, rc);
883 #if EFSYS_OPT_RX_SCALE
884 static __checkReturn efx_rc_t
885 siena_rx_scale_tbl_set(
887 __in_ecount(n) unsigned int *table,
894 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
895 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
897 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
902 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
905 /* Calculate the entry to place in the table */
906 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
908 EFSYS_PROBE2(table, int, index, uint32_t, byte);
910 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
912 /* Write the table */
913 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
914 index, &oword, B_TRUE);
917 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
920 /* Determine if we're starting a new batch */
921 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
924 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
925 index, &oword, B_TRUE);
927 /* Verify the entry */
928 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
939 EFSYS_PROBE1(fail1, efx_rc_t, rc);
946 * Falcon/Siena psuedo-header
947 * --------------------------
949 * Receive packets are prefixed by an optional 16 byte pseudo-header.
950 * The psuedo-header is a byte array of one of the forms:
952 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
953 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
954 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
957 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
958 * LL.LL LFSR hash (16-bit big-endian)
961 #if EFSYS_OPT_RX_SCALE
962 static __checkReturn uint32_t
963 siena_rx_prefix_hash(
965 __in efx_rx_hash_alg_t func,
966 __in uint8_t *buffer)
968 _NOTE(ARGUNUSED(enp))
971 case EFX_RX_HASHALG_TOEPLITZ:
972 return ((buffer[12] << 24) |
977 case EFX_RX_HASHALG_LFSR:
978 return ((buffer[14] << 8) | buffer[15]);
985 #endif /* EFSYS_OPT_RX_SCALE */
987 static __checkReturn efx_rc_t
988 siena_rx_prefix_pktlen(
990 __in uint8_t *buffer,
991 __out uint16_t *lengthp)
993 _NOTE(ARGUNUSED(enp, buffer, lengthp))
995 /* Not supported by Falcon/Siena hardware */
1003 __in efx_rxq_t *erp,
1004 __in_ecount(n) efsys_dma_addr_t *addrp,
1006 __in unsigned int n,
1007 __in unsigned int completed,
1008 __in unsigned int added)
1012 unsigned int offset;
1015 /* The client driver must not overfill the queue */
1016 EFSYS_ASSERT3U(added - completed + n, <=,
1017 EFX_RXQ_LIMIT(erp->er_mask + 1));
1019 id = added & (erp->er_mask);
1020 for (i = 0; i < n; i++) {
1021 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1022 unsigned int, id, efsys_dma_addr_t, addrp[i],
1025 EFX_POPULATE_QWORD_3(qword,
1026 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1027 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1028 (uint32_t)(addrp[i] & 0xffffffff),
1029 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1030 (uint32_t)(addrp[i] >> 32));
1032 offset = id * sizeof (efx_qword_t);
1033 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1035 id = (id + 1) & (erp->er_mask);
1041 __in efx_rxq_t *erp,
1042 __in unsigned int added,
1043 __inout unsigned int *pushedp)
1045 efx_nic_t *enp = erp->er_enp;
1046 unsigned int pushed = *pushedp;
1051 /* All descriptors are pushed */
1054 /* Push the populated descriptors out */
1055 wptr = added & erp->er_mask;
1057 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1059 /* Only write the third DWORD */
1060 EFX_POPULATE_DWORD_1(dword,
1061 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1063 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1064 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1065 wptr, pushed & erp->er_mask);
1066 EFSYS_PIO_WRITE_BARRIER();
1067 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1068 erp->er_index, &dword, B_FALSE);
1071 static __checkReturn efx_rc_t
1073 __in efx_rxq_t *erp)
1075 efx_nic_t *enp = erp->er_enp;
1079 label = erp->er_index;
1081 /* Flush the queue */
1082 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1083 FRF_AZ_RX_FLUSH_DESCQ, label);
1084 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1091 __in efx_rxq_t *erp)
1093 efx_nic_t *enp = erp->er_enp;
1096 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1098 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1099 erp->er_index, &oword, B_TRUE);
1101 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1102 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1103 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1105 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1106 erp->er_index, &oword, B_TRUE);
1109 static __checkReturn efx_rc_t
1111 __in efx_nic_t *enp,
1112 __in unsigned int index,
1113 __in unsigned int label,
1114 __in efx_rxq_type_t type,
1115 __in efsys_mem_t *esmp,
1118 __in efx_evq_t *eep,
1119 __in efx_rxq_t *erp)
1121 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1127 _NOTE(ARGUNUSED(esmp))
1129 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1130 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1131 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1132 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1134 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1135 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1137 if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) {
1141 if (index >= encp->enc_rxq_limit) {
1145 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1147 if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS))
1149 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1155 case EFX_RXQ_TYPE_DEFAULT:
1159 #if EFSYS_OPT_RX_SCATTER
1160 case EFX_RXQ_TYPE_SCATTER:
1161 if (enp->en_family < EFX_FAMILY_SIENA) {
1167 #endif /* EFSYS_OPT_RX_SCATTER */
1174 /* Set up the new descriptor queue */
1175 EFX_POPULATE_OWORD_7(oword,
1176 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1177 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1178 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1179 FRF_AZ_RX_DESCQ_LABEL, label,
1180 FRF_AZ_RX_DESCQ_SIZE, size,
1181 FRF_AZ_RX_DESCQ_TYPE, 0,
1182 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1184 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1185 erp->er_index, &oword, B_TRUE);
1196 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1203 __in efx_rxq_t *erp)
1205 efx_nic_t *enp = erp->er_enp;
1208 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1209 --enp->en_rx_qcount;
1211 /* Purge descriptor queue */
1212 EFX_ZERO_OWORD(oword);
1214 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1215 erp->er_index, &oword, B_TRUE);
1217 /* Free the RXQ object */
1218 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1223 __in efx_nic_t *enp)
1225 _NOTE(ARGUNUSED(enp))
1228 #endif /* EFSYS_OPT_SIENA */