sys/dev/sfxge/common/efx_rx.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *    this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright notice,
  13  *    this list of conditions and the following disclaimer in the documentation
  14  *    and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  18  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  19  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  23  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  25  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * The views and conclusions contained in the software and documentation are
  29  * those of the authors and should not be interpreted as representing official
  30  * policies, either expressed or implied, of the FreeBSD Project.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include "efx.h"
  37 #include "efx_impl.h"
  38
  39
  40 #if EFSYS_OPT_SIENA
  41
  42 static  __checkReturn   efx_rc_t
  43 siena_rx_init(
  44         __in            efx_nic_t *enp);
  45
  46 static                  void
  47 siena_rx_fini(
  48         __in            efx_nic_t *enp);
  49
  50 #if EFSYS_OPT_RX_SCATTER
  51 static  __checkReturn   efx_rc_t
  52 siena_rx_scatter_enable(
  53         __in            efx_nic_t *enp,
  54         __in            unsigned int buf_size);
  55 #endif /* EFSYS_OPT_RX_SCATTER */
  56
  57 #if EFSYS_OPT_RX_SCALE
  58 static  __checkReturn   efx_rc_t
  59 siena_rx_scale_mode_set(
  60         __in            efx_nic_t *enp,
  61         __in            uint32_t rss_context,
  62         __in            efx_rx_hash_alg_t alg,
  63         __in            efx_rx_hash_type_t type,
  64         __in            boolean_t insert);
  65
  66 static  __checkReturn   efx_rc_t
  67 siena_rx_scale_key_set(
  68         __in            efx_nic_t *enp,
  69         __in            uint32_t rss_context,
  70         __in_ecount(n)  uint8_t *key,
  71         __in            size_t n);
  72
  73 static  __checkReturn   efx_rc_t
  74 siena_rx_scale_tbl_set(
  75         __in            efx_nic_t *enp,
  76         __in            uint32_t rss_context,
  77         __in_ecount(n)  unsigned int *table,
  78         __in            size_t n);
  79
  80 static  __checkReturn   uint32_t
  81 siena_rx_prefix_hash(
  82         __in            efx_nic_t *enp,
  83         __in            efx_rx_hash_alg_t func,
  84         __in            uint8_t *buffer);
  85
  86 #endif /* EFSYS_OPT_RX_SCALE */
  87
  88 static  __checkReturn   efx_rc_t
  89 siena_rx_prefix_pktlen(
  90         __in            efx_nic_t *enp,
  91         __in            uint8_t *buffer,
  92         __out           uint16_t *lengthp);
  93
  94 static                          void
  95 siena_rx_qpost(
  96         __in                    efx_rxq_t *erp,
  97         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
  98         __in                    size_t size,
  99         __in                    unsigned int ndescs,
 100         __in                    unsigned int completed,
 101         __in                    unsigned int added);
 102
 103 static                  void
 104 siena_rx_qpush(
 105         __in            efx_rxq_t *erp,
 106         __in            unsigned int added,
 107         __inout         unsigned int *pushedp);
 108
 109 #if EFSYS_OPT_RX_PACKED_STREAM
 110 static          void
 111 siena_rx_qpush_ps_credits(
 112         __in            efx_rxq_t *erp);
 113
 114 static  __checkReturn   uint8_t *
 115 siena_rx_qps_packet_info(
 116         __in            efx_rxq_t *erp,
 117         __in            uint8_t *buffer,
 118         __in            uint32_t buffer_length,
 119         __in            uint32_t current_offset,
 120         __out           uint16_t *lengthp,
 121         __out           uint32_t *next_offsetp,
 122         __out           uint32_t *timestamp);
 123 #endif
 124
 125 static  __checkReturn   efx_rc_t
 126 siena_rx_qflush(
 127         __in            efx_rxq_t *erp);
 128
 129 static                  void
 130 siena_rx_qenable(
 131         __in            efx_rxq_t *erp);
 132
 133 static  __checkReturn   efx_rc_t
 134 siena_rx_qcreate(
 135         __in            efx_nic_t *enp,
 136         __in            unsigned int index,
 137         __in            unsigned int label,
 138         __in            efx_rxq_type_t type,
 139         __in            uint32_t type_data,
 140         __in            efsys_mem_t *esmp,
 141         __in            size_t ndescs,
 142         __in            uint32_t id,
 143         __in            unsigned int flags,
 144         __in            efx_evq_t *eep,
 145         __in            efx_rxq_t *erp);
 146
 147 static                  void
 148 siena_rx_qdestroy(
 149         __in            efx_rxq_t *erp);
 150
 151 #endif /* EFSYS_OPT_SIENA */
 152
 153
 154 #if EFSYS_OPT_SIENA
 155 static const efx_rx_ops_t __efx_rx_siena_ops = {
 156         siena_rx_init,                          /* erxo_init */
 157         siena_rx_fini,                          /* erxo_fini */
 158 #if EFSYS_OPT_RX_SCATTER
 159         siena_rx_scatter_enable,                /* erxo_scatter_enable */
 160 #endif
 161 #if EFSYS_OPT_RX_SCALE
 162         NULL,                                   /* erxo_scale_context_alloc */
 163         NULL,                                   /* erxo_scale_context_free */
 164         siena_rx_scale_mode_set,                /* erxo_scale_mode_set */
 165         siena_rx_scale_key_set,                 /* erxo_scale_key_set */
 166         siena_rx_scale_tbl_set,                 /* erxo_scale_tbl_set */
 167         siena_rx_prefix_hash,                   /* erxo_prefix_hash */
 168 #endif
 169         siena_rx_prefix_pktlen,                 /* erxo_prefix_pktlen */
 170         siena_rx_qpost,                         /* erxo_qpost */
 171         siena_rx_qpush,                         /* erxo_qpush */
 172 #if EFSYS_OPT_RX_PACKED_STREAM
 173         siena_rx_qpush_ps_credits,              /* erxo_qpush_ps_credits */
 174         siena_rx_qps_packet_info,               /* erxo_qps_packet_info */
 175 #endif
 176         siena_rx_qflush,                        /* erxo_qflush */
 177         siena_rx_qenable,                       /* erxo_qenable */
 178         siena_rx_qcreate,                       /* erxo_qcreate */
 179         siena_rx_qdestroy,                      /* erxo_qdestroy */
 180 };
 181 #endif  /* EFSYS_OPT_SIENA */
 182
 183 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 184 static const efx_rx_ops_t __efx_rx_ef10_ops = {
 185         ef10_rx_init,                           /* erxo_init */
 186         ef10_rx_fini,                           /* erxo_fini */
 187 #if EFSYS_OPT_RX_SCATTER
 188         ef10_rx_scatter_enable,                 /* erxo_scatter_enable */
 189 #endif
 190 #if EFSYS_OPT_RX_SCALE
 191         ef10_rx_scale_context_alloc,            /* erxo_scale_context_alloc */
 192         ef10_rx_scale_context_free,             /* erxo_scale_context_free */
 193         ef10_rx_scale_mode_set,                 /* erxo_scale_mode_set */
 194         ef10_rx_scale_key_set,                  /* erxo_scale_key_set */
 195         ef10_rx_scale_tbl_set,                  /* erxo_scale_tbl_set */
 196         ef10_rx_prefix_hash,                    /* erxo_prefix_hash */
 197 #endif
 198         ef10_rx_prefix_pktlen,                  /* erxo_prefix_pktlen */
 199         ef10_rx_qpost,                          /* erxo_qpost */
 200         ef10_rx_qpush,                          /* erxo_qpush */
 201 #if EFSYS_OPT_RX_PACKED_STREAM
 202         ef10_rx_qpush_ps_credits,               /* erxo_qpush_ps_credits */
 203         ef10_rx_qps_packet_info,                /* erxo_qps_packet_info */
 204 #endif
 205         ef10_rx_qflush,                         /* erxo_qflush */
 206         ef10_rx_qenable,                        /* erxo_qenable */
 207         ef10_rx_qcreate,                        /* erxo_qcreate */
 208         ef10_rx_qdestroy,                       /* erxo_qdestroy */
 209 };
 210 #endif  /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 211
 212
 213         __checkReturn   efx_rc_t
 214 efx_rx_init(
 215         __inout         efx_nic_t *enp)
 216 {
 217         const efx_rx_ops_t *erxop;
 218         efx_rc_t rc;
 219
 220         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 221         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 222
 223         if (!(enp->en_mod_flags & EFX_MOD_EV)) {
 224                 rc = EINVAL;
 225                 goto fail1;
 226         }
 227
 228         if (enp->en_mod_flags & EFX_MOD_RX) {
 229                 rc = EINVAL;
 230                 goto fail2;
 231         }
 232
 233         switch (enp->en_family) {
 234 #if EFSYS_OPT_SIENA
 235         case EFX_FAMILY_SIENA:
 236                 erxop = &__efx_rx_siena_ops;
 237                 break;
 238 #endif /* EFSYS_OPT_SIENA */
 239
 240 #if EFSYS_OPT_HUNTINGTON
 241         case EFX_FAMILY_HUNTINGTON:
 242                 erxop = &__efx_rx_ef10_ops;
 243                 break;
 244 #endif /* EFSYS_OPT_HUNTINGTON */
 245
 246 #if EFSYS_OPT_MEDFORD
 247         case EFX_FAMILY_MEDFORD:
 248                 erxop = &__efx_rx_ef10_ops;
 249                 break;
 250 #endif /* EFSYS_OPT_MEDFORD */
 251
 252 #if EFSYS_OPT_MEDFORD2
 253         case EFX_FAMILY_MEDFORD2:
 254                 erxop = &__efx_rx_ef10_ops;
 255                 break;
 256 #endif /* EFSYS_OPT_MEDFORD2 */
 257
 258         default:
 259                 EFSYS_ASSERT(0);
 260                 rc = ENOTSUP;
 261                 goto fail3;
 262         }
 263
 264         if ((rc = erxop->erxo_init(enp)) != 0)
 265                 goto fail4;
 266
 267         enp->en_erxop = erxop;
 268         enp->en_mod_flags |= EFX_MOD_RX;
 269         return (0);
 270
 271 fail4:
 272         EFSYS_PROBE(fail4);
 273 fail3:
 274         EFSYS_PROBE(fail3);
 275 fail2:
 276         EFSYS_PROBE(fail2);
 277 fail1:
 278         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 279
 280         enp->en_erxop = NULL;
 281         enp->en_mod_flags &= ~EFX_MOD_RX;
 282         return (rc);
 283 }
 284
 285                         void
 286 efx_rx_fini(
 287         __in            efx_nic_t *enp)
 288 {
 289         const efx_rx_ops_t *erxop = enp->en_erxop;
 290
 291         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 292         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 293         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 294         EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
 295
 296         erxop->erxo_fini(enp);
 297
 298         enp->en_erxop = NULL;
 299         enp->en_mod_flags &= ~EFX_MOD_RX;
 300 }
 301
 302 #if EFSYS_OPT_RX_SCATTER
 303         __checkReturn   efx_rc_t
 304 efx_rx_scatter_enable(
 305         __in            efx_nic_t *enp,
 306         __in            unsigned int buf_size)
 307 {
 308         const efx_rx_ops_t *erxop = enp->en_erxop;
 309         efx_rc_t rc;
 310
 311         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 312         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 313
 314         if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
 315                 goto fail1;
 316
 317         return (0);
 318
 319 fail1:
 320         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 321         return (rc);
 322 }
 323 #endif  /* EFSYS_OPT_RX_SCATTER */
 324
 325 #if EFSYS_OPT_RX_SCALE
 326         __checkReturn                           efx_rc_t
 327 efx_rx_scale_hash_flags_get(
 328         __in                                    efx_nic_t *enp,
 329         __in                                    efx_rx_hash_alg_t hash_alg,
 330         __inout_ecount(EFX_RX_HASH_NFLAGS)      unsigned int *flagsp,
 331         __out                                   unsigned int *nflagsp)
 332 {
 333         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 334         boolean_t additional_modes;
 335         unsigned int *entryp = flagsp;
 336         efx_rc_t rc;
 337
 338         if (flagsp == NULL || nflagsp == NULL) {
 339                 rc = EINVAL;
 340                 goto fail1;
 341         }
 342
 343         additional_modes = encp->enc_rx_scale_additional_modes_supported;
 344
 345 #define LIST_FLAGS(_entryp, _class, _l4_hashing, _additional_modes)     \
 346         do {                                                            \
 347                 if (_l4_hashing) {                                      \
 348                         *(_entryp++) = EFX_RX_HASH(_class, 4TUPLE);     \
 349                                                                         \
 350                         if (_additional_modes) {                        \
 351                                 *(_entryp++) =                          \
 352                                     EFX_RX_HASH(_class, 2TUPLE_DST);    \
 353                                 *(_entryp++) =                          \
 354                                     EFX_RX_HASH(_class, 2TUPLE_SRC);    \
 355                         }                                               \
 356                 }                                                       \
 357                                                                         \
 358                 *(_entryp++) = EFX_RX_HASH(_class, 2TUPLE);             \
 359                                                                         \
 360                 if (_additional_modes) {                                \
 361                         *(_entryp++) = EFX_RX_HASH(_class, 1TUPLE_DST); \
 362                         *(_entryp++) = EFX_RX_HASH(_class, 1TUPLE_SRC); \
 363                 }                                                       \
 364                                                                         \
 365                 *(_entryp++) = EFX_RX_HASH(_class, DISABLE);            \
 366                                                                         \
 367                 _NOTE(CONSTANTCONDITION)                                \
 368         } while (B_FALSE)
 369
 370         switch (hash_alg) {
 371         case EFX_RX_HASHALG_TOEPLITZ:
 372                 LIST_FLAGS(entryp, IPV4_TCP, B_TRUE, additional_modes);
 373                 LIST_FLAGS(entryp, IPV6_TCP, B_TRUE, additional_modes);
 374
 375                 if (additional_modes) {
 376                         LIST_FLAGS(entryp, IPV4_UDP, B_TRUE, additional_modes);
 377                         LIST_FLAGS(entryp, IPV6_UDP, B_TRUE, additional_modes);
 378                 }
 379
 380                 LIST_FLAGS(entryp, IPV4, B_FALSE, additional_modes);
 381                 LIST_FLAGS(entryp, IPV6, B_FALSE, additional_modes);
 382                 break;
 383
 384         default:
 385                 rc = EINVAL;
 386                 goto fail2;
 387         }
 388
 389 #undef LIST_FLAGS
 390
 391         *nflagsp = (unsigned int)(entryp - flagsp);
 392         EFSYS_ASSERT3U(*nflagsp, <=, EFX_RX_HASH_NFLAGS);
 393
 394         return (0);
 395
 396 fail2:
 397         EFSYS_PROBE(fail2);
 398
 399 fail1:
 400         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 401
 402         return (rc);
 403 }
 404
 405         __checkReturn   efx_rc_t
 406 efx_rx_hash_default_support_get(
 407         __in            efx_nic_t *enp,
 408         __out           efx_rx_hash_support_t *supportp)
 409 {
 410         efx_rc_t rc;
 411
 412         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 413         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 414
 415         if (supportp == NULL) {
 416                 rc = EINVAL;
 417                 goto fail1;
 418         }
 419
 420         /*
 421          * Report the hashing support the client gets by default if it
 422          * does not allocate an RSS context itself.
 423          */
 424         *supportp = enp->en_hash_support;
 425
 426         return (0);
 427
 428 fail1:
 429         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 430
 431         return (rc);
 432 }
 433
 434         __checkReturn   efx_rc_t
 435 efx_rx_scale_default_support_get(
 436         __in            efx_nic_t *enp,
 437         __out           efx_rx_scale_context_type_t *typep)
 438 {
 439         efx_rc_t rc;
 440
 441         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 442         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 443
 444         if (typep == NULL) {
 445                 rc = EINVAL;
 446                 goto fail1;
 447         }
 448
 449         /*
 450          * Report the RSS support the client gets by default if it
 451          * does not allocate an RSS context itself.
 452          */
 453         *typep = enp->en_rss_context_type;
 454
 455         return (0);
 456
 457 fail1:
 458         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 459
 460         return (rc);
 461 }
 462 #endif  /* EFSYS_OPT_RX_SCALE */
 463
 464 #if EFSYS_OPT_RX_SCALE
 465         __checkReturn   efx_rc_t
 466 efx_rx_scale_context_alloc(
 467         __in            efx_nic_t *enp,
 468         __in            efx_rx_scale_context_type_t type,
 469         __in            uint32_t num_queues,
 470         __out           uint32_t *rss_contextp)
 471 {
 472         const efx_rx_ops_t *erxop = enp->en_erxop;
 473         efx_rc_t rc;
 474
 475         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 476         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 477
 478         if (erxop->erxo_scale_context_alloc == NULL) {
 479                 rc = ENOTSUP;
 480                 goto fail1;
 481         }
 482         if ((rc = erxop->erxo_scale_context_alloc(enp, type,
 483                             num_queues, rss_contextp)) != 0) {
 484                 goto fail2;
 485         }
 486
 487         return (0);
 488
 489 fail2:
 490         EFSYS_PROBE(fail2);
 491 fail1:
 492         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 493         return (rc);
 494 }
 495 #endif  /* EFSYS_OPT_RX_SCALE */
 496
 497 #if EFSYS_OPT_RX_SCALE
 498         __checkReturn   efx_rc_t
 499 efx_rx_scale_context_free(
 500         __in            efx_nic_t *enp,
 501         __in            uint32_t rss_context)
 502 {
 503         const efx_rx_ops_t *erxop = enp->en_erxop;
 504         efx_rc_t rc;
 505
 506         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 507         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 508
 509         if (erxop->erxo_scale_context_free == NULL) {
 510                 rc = ENOTSUP;
 511                 goto fail1;
 512         }
 513         if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
 514                 goto fail2;
 515
 516         return (0);
 517
 518 fail2:
 519         EFSYS_PROBE(fail2);
 520 fail1:
 521         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 522         return (rc);
 523 }
 524 #endif  /* EFSYS_OPT_RX_SCALE */
 525
 526 #if EFSYS_OPT_RX_SCALE
 527         __checkReturn   efx_rc_t
 528 efx_rx_scale_mode_set(
 529         __in            efx_nic_t *enp,
 530         __in            uint32_t rss_context,
 531         __in            efx_rx_hash_alg_t alg,
 532         __in            efx_rx_hash_type_t type,
 533         __in            boolean_t insert)
 534 {
 535         const efx_rx_ops_t *erxop = enp->en_erxop;
 536         unsigned int type_flags[EFX_RX_HASH_NFLAGS];
 537         unsigned int type_nflags;
 538         efx_rx_hash_type_t type_check;
 539         unsigned int i;
 540         efx_rc_t rc;
 541
 542         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 543         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 544
 545         /*
 546          * Legacy flags and modern bits cannot be
 547          * used at the same time in the hash type.
 548          */
 549         if ((type & EFX_RX_HASH_LEGACY_MASK) &&
 550             (type & ~EFX_RX_HASH_LEGACY_MASK)) {
 551                 rc = EINVAL;
 552                 goto fail1;
 553         }
 554
 555         /*
 556          * Translate legacy flags to the new representation
 557          * so that chip-specific handlers will consider the
 558          * new flags only.
 559          */
 560         if (type & EFX_RX_HASH_IPV4) {
 561                 type |= EFX_RX_HASH(IPV4, 2TUPLE);
 562                 type |= EFX_RX_HASH(IPV4_TCP, 2TUPLE);
 563                 type |= EFX_RX_HASH(IPV4_UDP, 2TUPLE);
 564         }
 565
 566         if (type & EFX_RX_HASH_TCPIPV4)
 567                 type |= EFX_RX_HASH(IPV4_TCP, 4TUPLE);
 568
 569         if (type & EFX_RX_HASH_IPV6) {
 570                 type |= EFX_RX_HASH(IPV6, 2TUPLE);
 571                 type |= EFX_RX_HASH(IPV6_TCP, 2TUPLE);
 572                 type |= EFX_RX_HASH(IPV6_UDP, 2TUPLE);
 573         }
 574
 575         if (type & EFX_RX_HASH_TCPIPV6)
 576                 type |= EFX_RX_HASH(IPV6_TCP, 4TUPLE);
 577
 578         type &= ~EFX_RX_HASH_LEGACY_MASK;
 579         type_check = type;
 580
 581         /*
 582          * Get the list of supported hash flags and sanitise the input.
 583          */
 584         rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags, &type_nflags);
 585         if (rc != 0)
 586                 goto fail2;
 587
 588         for (i = 0; i < type_nflags; ++i) {
 589                 if ((type_check & type_flags[i]) == type_flags[i])
 590                         type_check &= ~(type_flags[i]);
 591         }
 592
 593         if (type_check != 0) {
 594                 rc = EINVAL;
 595                 goto fail3;
 596         }
 597
 598         if (erxop->erxo_scale_mode_set != NULL) {
 599                 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
 600                             type, insert)) != 0)
 601                         goto fail4;
 602         }
 603
 604         return (0);
 605
 606 fail4:
 607         EFSYS_PROBE(fail4);
 608 fail3:
 609         EFSYS_PROBE(fail3);
 610 fail2:
 611         EFSYS_PROBE(fail2);
 612 fail1:
 613         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 614         return (rc);
 615 }
 616 #endif  /* EFSYS_OPT_RX_SCALE */
 617
 618 #if EFSYS_OPT_RX_SCALE
 619         __checkReturn   efx_rc_t
 620 efx_rx_scale_key_set(
 621         __in            efx_nic_t *enp,
 622         __in            uint32_t rss_context,
 623         __in_ecount(n)  uint8_t *key,
 624         __in            size_t n)
 625 {
 626         const efx_rx_ops_t *erxop = enp->en_erxop;
 627         efx_rc_t rc;
 628
 629         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 630         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 631
 632         if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
 633                 goto fail1;
 634
 635         return (0);
 636
 637 fail1:
 638         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 639
 640         return (rc);
 641 }
 642 #endif  /* EFSYS_OPT_RX_SCALE */
 643
 644 #if EFSYS_OPT_RX_SCALE
 645         __checkReturn   efx_rc_t
 646 efx_rx_scale_tbl_set(
 647         __in            efx_nic_t *enp,
 648         __in            uint32_t rss_context,
 649         __in_ecount(n)  unsigned int *table,
 650         __in            size_t n)
 651 {
 652         const efx_rx_ops_t *erxop = enp->en_erxop;
 653         efx_rc_t rc;
 654
 655         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 656         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 657
 658         if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
 659                 goto fail1;
 660
 661         return (0);
 662
 663 fail1:
 664         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 665
 666         return (rc);
 667 }
 668 #endif  /* EFSYS_OPT_RX_SCALE */
 669
 670                                 void
 671 efx_rx_qpost(
 672         __in                    efx_rxq_t *erp,
 673         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
 674         __in                    size_t size,
 675         __in                    unsigned int ndescs,
 676         __in                    unsigned int completed,
 677         __in                    unsigned int added)
 678 {
 679         efx_nic_t *enp = erp->er_enp;
 680         const efx_rx_ops_t *erxop = enp->en_erxop;
 681
 682         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 683
 684         erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
 685 }
 686
 687 #if EFSYS_OPT_RX_PACKED_STREAM
 688
 689                         void
 690 efx_rx_qpush_ps_credits(
 691         __in            efx_rxq_t *erp)
 692 {
 693         efx_nic_t *enp = erp->er_enp;
 694         const efx_rx_ops_t *erxop = enp->en_erxop;
 695
 696         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 697
 698         erxop->erxo_qpush_ps_credits(erp);
 699 }
 700
 701         __checkReturn   uint8_t *
 702 efx_rx_qps_packet_info(
 703         __in            efx_rxq_t *erp,
 704         __in            uint8_t *buffer,
 705         __in            uint32_t buffer_length,
 706         __in            uint32_t current_offset,
 707         __out           uint16_t *lengthp,
 708         __out           uint32_t *next_offsetp,
 709         __out           uint32_t *timestamp)
 710 {
 711         efx_nic_t *enp = erp->er_enp;
 712         const efx_rx_ops_t *erxop = enp->en_erxop;
 713
 714         return (erxop->erxo_qps_packet_info(erp, buffer,
 715                 buffer_length, current_offset, lengthp,
 716                 next_offsetp, timestamp));
 717 }
 718
 719 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
 720
 721                         void
 722 efx_rx_qpush(
 723         __in            efx_rxq_t *erp,
 724         __in            unsigned int added,
 725         __inout         unsigned int *pushedp)
 726 {
 727         efx_nic_t *enp = erp->er_enp;
 728         const efx_rx_ops_t *erxop = enp->en_erxop;
 729
 730         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 731
 732         erxop->erxo_qpush(erp, added, pushedp);
 733 }
 734
 735         __checkReturn   efx_rc_t
 736 efx_rx_qflush(
 737         __in            efx_rxq_t *erp)
 738 {
 739         efx_nic_t *enp = erp->er_enp;
 740         const efx_rx_ops_t *erxop = enp->en_erxop;
 741         efx_rc_t rc;
 742
 743         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 744
 745         if ((rc = erxop->erxo_qflush(erp)) != 0)
 746                 goto fail1;
 747
 748         return (0);
 749
 750 fail1:
 751         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 752
 753         return (rc);
 754 }
 755
 756                         void
 757 efx_rx_qenable(
 758         __in            efx_rxq_t *erp)
 759 {
 760         efx_nic_t *enp = erp->er_enp;
 761         const efx_rx_ops_t *erxop = enp->en_erxop;
 762
 763         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 764
 765         erxop->erxo_qenable(erp);
 766 }
 767
 768 static  __checkReturn   efx_rc_t
 769 efx_rx_qcreate_internal(
 770         __in            efx_nic_t *enp,
 771         __in            unsigned int index,
 772         __in            unsigned int label,
 773         __in            efx_rxq_type_t type,
 774         __in            uint32_t type_data,
 775         __in            efsys_mem_t *esmp,
 776         __in            size_t ndescs,
 777         __in            uint32_t id,
 778         __in            unsigned int flags,
 779         __in            efx_evq_t *eep,
 780         __deref_out     efx_rxq_t **erpp)
 781 {
 782         const efx_rx_ops_t *erxop = enp->en_erxop;
 783         efx_rxq_t *erp;
 784         efx_rc_t rc;
 785
 786         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 787         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 788
 789         /* Allocate an RXQ object */
 790         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
 791
 792         if (erp == NULL) {
 793                 rc = ENOMEM;
 794                 goto fail1;
 795         }
 796
 797         erp->er_magic = EFX_RXQ_MAGIC;
 798         erp->er_enp = enp;
 799         erp->er_index = index;
 800         erp->er_mask = ndescs - 1;
 801         erp->er_esmp = esmp;
 802
 803         if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
 804             ndescs, id, flags, eep, erp)) != 0)
 805                 goto fail2;
 806
 807         enp->en_rx_qcount++;
 808         *erpp = erp;
 809
 810         return (0);
 811
 812 fail2:
 813         EFSYS_PROBE(fail2);
 814
 815         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
 816 fail1:
 817         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 818
 819         return (rc);
 820 }
 821
 822         __checkReturn   efx_rc_t
 823 efx_rx_qcreate(
 824         __in            efx_nic_t *enp,
 825         __in            unsigned int index,
 826         __in            unsigned int label,
 827         __in            efx_rxq_type_t type,
 828         __in            efsys_mem_t *esmp,
 829         __in            size_t ndescs,
 830         __in            uint32_t id,
 831         __in            unsigned int flags,
 832         __in            efx_evq_t *eep,
 833         __deref_out     efx_rxq_t **erpp)
 834 {
 835         return efx_rx_qcreate_internal(enp, index, label, type, 0, esmp, ndescs,
 836             id, flags, eep, erpp);
 837 }
 838
 839 #if EFSYS_OPT_RX_PACKED_STREAM
 840
 841         __checkReturn   efx_rc_t
 842 efx_rx_qcreate_packed_stream(
 843         __in            efx_nic_t *enp,
 844         __in            unsigned int index,
 845         __in            unsigned int label,
 846         __in            uint32_t ps_buf_size,
 847         __in            efsys_mem_t *esmp,
 848         __in            size_t ndescs,
 849         __in            efx_evq_t *eep,
 850         __deref_out     efx_rxq_t **erpp)
 851 {
 852         return efx_rx_qcreate_internal(enp, index, label,
 853             EFX_RXQ_TYPE_PACKED_STREAM, ps_buf_size, esmp, ndescs,
 854             0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
 855 }
 856
 857 #endif
 858
 859                         void
 860 efx_rx_qdestroy(
 861         __in            efx_rxq_t *erp)
 862 {
 863         efx_nic_t *enp = erp->er_enp;
 864         const efx_rx_ops_t *erxop = enp->en_erxop;
 865
 866         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 867
 868         erxop->erxo_qdestroy(erp);
 869 }
 870
 871         __checkReturn   efx_rc_t
 872 efx_pseudo_hdr_pkt_length_get(
 873         __in            efx_rxq_t *erp,
 874         __in            uint8_t *buffer,
 875         __out           uint16_t *lengthp)
 876 {
 877         efx_nic_t *enp = erp->er_enp;
 878         const efx_rx_ops_t *erxop = enp->en_erxop;
 879
 880         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 881
 882         return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
 883 }
 884
 885 #if EFSYS_OPT_RX_SCALE
 886         __checkReturn   uint32_t
 887 efx_pseudo_hdr_hash_get(
 888         __in            efx_rxq_t *erp,
 889         __in            efx_rx_hash_alg_t func,
 890         __in            uint8_t *buffer)
 891 {
 892         efx_nic_t *enp = erp->er_enp;
 893         const efx_rx_ops_t *erxop = enp->en_erxop;
 894
 895         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 896
 897         EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
 898         return (erxop->erxo_prefix_hash(enp, func, buffer));
 899 }
 900 #endif  /* EFSYS_OPT_RX_SCALE */
 901
 902 #if EFSYS_OPT_SIENA
 903
 904 static  __checkReturn   efx_rc_t
 905 siena_rx_init(
 906         __in            efx_nic_t *enp)
 907 {
 908         efx_oword_t oword;
 909         unsigned int index;
 910
 911         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
 912
 913         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
 914         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
 915         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
 916         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
 917         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
 918         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
 919         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
 920
 921         /* Zero the RSS table */
 922         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
 923             index++) {
 924                 EFX_ZERO_OWORD(oword);
 925                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
 926                                     index, &oword, B_TRUE);
 927         }
 928
 929 #if EFSYS_OPT_RX_SCALE
 930         /* The RSS key and indirection table are writable. */
 931         enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
 932
 933         /* Hardware can insert RX hash with/without RSS */
 934         enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
 935 #endif  /* EFSYS_OPT_RX_SCALE */
 936
 937         return (0);
 938 }
 939
 940 #if EFSYS_OPT_RX_SCATTER
 941 static  __checkReturn   efx_rc_t
 942 siena_rx_scatter_enable(
 943         __in            efx_nic_t *enp,
 944         __in            unsigned int buf_size)
 945 {
 946         unsigned int nbuf32;
 947         efx_oword_t oword;
 948         efx_rc_t rc;
 949
 950         nbuf32 = buf_size / 32;
 951         IF ((NBUF32 == 0) ||
 952             (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
 953             ((buf_size % 32) != 0)) {
 954                 rc = EINVAL;
 955                 goto fail1;
 956         }
 957
 958         if (enp->en_rx_qcount > 0) {
 959                 rc = EBUSY;
 960                 goto fail2;
 961         }
 962
 963         /* Set scatter buffer size */
 964         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
 965         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
 966         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
 967
 968         /* Enable scatter for packets not matching a filter */
 969         EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
 970         EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
 971         EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
 972
 973         return (0);
 974
 975 fail2:
 976         EFSYS_PROBE(fail2);
 977 fail1:
 978         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 979
 980         return (rc);
 981 }
 982 #endif  /* EFSYS_OPT_RX_SCATTER */
 983
 984
 985 #define EFX_RX_LFSR_HASH(_enp, _insert)                                 \
 986         do {                                                            \
 987                 efx_oword_t oword;                                      \
 988                                                                         \
 989                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
 990                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);      \
 991                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);       \
 992                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);       \
 993                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
 994                     (_insert) ? 1 : 0);                                 \
 995                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
 996                                                                         \
 997                 if ((_enp)->en_family == EFX_FAMILY_SIENA) {            \
 998                         EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3,   \
 999                             &oword);                                    \
1000                         EFX_SET_OWORD_FIELD(oword,                      \
1001                             FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0);        \
1002                         EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3,  \
1003                             &oword);                                    \
1004                 }                                                       \
1005                                                                         \
1006                 _NOTE(CONSTANTCONDITION)                                \
1007         } while (B_FALSE)
1008
1009 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp)             \
1010         do {                                                            \
1011                 efx_oword_t oword;                                      \
1012                                                                         \
1013                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
1014                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1);      \
1015                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH,           \
1016                     (_ip) ? 1 : 0);                                     \
1017                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP,           \
1018                     (_tcp) ? 0 : 1);                                    \
1019                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
1020                     (_insert) ? 1 : 0);                                 \
1021                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
1022                                                                         \
1023                 _NOTE(CONSTANTCONDITION)                                \
1024         } while (B_FALSE)
1025
1026 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc)                 \
1027         do {                                                            \
1028                 efx_oword_t oword;                                      \
1029                                                                         \
1030                 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword);  \
1031                 EFX_SET_OWORD_FIELD(oword,                              \
1032                     FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1);                \
1033                 EFX_SET_OWORD_FIELD(oword,                              \
1034                     FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1035                 EFX_SET_OWORD_FIELD(oword,                              \
1036                     FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1);   \
1037                 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1038                                                                         \
1039                 (_rc) = 0;                                              \
1040                                                                         \
1041                 _NOTE(CONSTANTCONDITION)                                \
1042         } while (B_FALSE)
1043
1044
1045 #if EFSYS_OPT_RX_SCALE
1046
1047 static  __checkReturn   efx_rc_t
1048 siena_rx_scale_mode_set(
1049         __in            efx_nic_t *enp,
1050         __in            uint32_t rss_context,
1051         __in            efx_rx_hash_alg_t alg,
1052         __in            efx_rx_hash_type_t type,
1053         __in            boolean_t insert)
1054 {
1055         efx_rx_hash_type_t type_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE);
1056         efx_rx_hash_type_t type_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
1057         efx_rx_hash_type_t type_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE);
1058         efx_rx_hash_type_t type_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
1059         efx_rc_t rc;
1060
1061         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1062                 rc = EINVAL;
1063                 goto fail1;
1064         }
1065
1066         switch (alg) {
1067         case EFX_RX_HASHALG_LFSR:
1068                 EFX_RX_LFSR_HASH(enp, insert);
1069                 break;
1070
1071         case EFX_RX_HASHALG_TOEPLITZ:
1072                 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1073                     (type & type_ipv4) == type_ipv4,
1074                     (type & type_ipv4_tcp) == type_ipv4_tcp);
1075
1076                 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1077                     (type & type_ipv6) == type_ipv6,
1078                     (type & type_ipv6_tcp) == type_ipv6_tcp,
1079                     rc);
1080                 if (rc != 0)
1081                         goto fail2;
1082
1083                 break;
1084
1085         default:
1086                 rc = EINVAL;
1087                 goto fail3;
1088         }
1089
1090         return (0);
1091
1092 fail3:
1093         EFSYS_PROBE(fail3);
1094 fail2:
1095         EFSYS_PROBE(fail2);
1096 fail1:
1097         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1098
1099         EFX_RX_LFSR_HASH(enp, B_FALSE);
1100
1101         return (rc);
1102 }
1103 #endif
1104
1105 #if EFSYS_OPT_RX_SCALE
1106 static  __checkReturn   efx_rc_t
1107 siena_rx_scale_key_set(
1108         __in            efx_nic_t *enp,
1109         __in            uint32_t rss_context,
1110         __in_ecount(n)  uint8_t *key,
1111         __in            size_t n)
1112 {
1113         efx_oword_t oword;
1114         unsigned int byte;
1115         unsigned int offset;
1116         efx_rc_t rc;
1117
1118         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1119                 rc = EINVAL;
1120                 goto fail1;
1121         }
1122
1123         byte = 0;
1124
1125         /* Write Toeplitz IPv4 hash key */
1126         EFX_ZERO_OWORD(oword);
1127         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1128             offset > 0 && byte < n;
1129             --offset)
1130                 oword.eo_u8[offset - 1] = key[byte++];
1131
1132         EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1133
1134         byte = 0;
1135
1136         /* Verify Toeplitz IPv4 hash key */
1137         EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1138         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1139             offset > 0 && byte < n;
1140             --offset) {
1141                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1142                         rc = EFAULT;
1143                         goto fail2;
1144                 }
1145         }
1146
1147         if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1148                 goto done;
1149
1150         byte = 0;
1151
1152         /* Write Toeplitz IPv6 hash key 3 */
1153         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1154         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1155             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1156             offset > 0 && byte < n;
1157             --offset)
1158                 oword.eo_u8[offset - 1] = key[byte++];
1159
1160         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1161
1162         /* Write Toeplitz IPv6 hash key 2 */
1163         EFX_ZERO_OWORD(oword);
1164         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1165             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1166             offset > 0 && byte < n;
1167             --offset)
1168                 oword.eo_u8[offset - 1] = key[byte++];
1169
1170         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1171
1172         /* Write Toeplitz IPv6 hash key 1 */
1173         EFX_ZERO_OWORD(oword);
1174         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1175             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1176             offset > 0 && byte < n;
1177             --offset)
1178                 oword.eo_u8[offset - 1] = key[byte++];
1179
1180         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1181
1182         byte = 0;
1183
1184         /* Verify Toeplitz IPv6 hash key 3 */
1185         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1186         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1187             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1188             offset > 0 && byte < n;
1189             --offset) {
1190                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1191                         rc = EFAULT;
1192                         goto fail3;
1193                 }
1194         }
1195
1196         /* Verify Toeplitz IPv6 hash key 2 */
1197         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1198         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1199             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1200             offset > 0 && byte < n;
1201             --offset) {
1202                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1203                         rc = EFAULT;
1204                         goto fail4;
1205                 }
1206         }
1207
1208         /* Verify Toeplitz IPv6 hash key 1 */
1209         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1210         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1211             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1212             offset > 0 && byte < n;
1213             --offset) {
1214                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1215                         rc = EFAULT;
1216                         goto fail5;
1217                 }
1218         }
1219
1220 done:
1221         return (0);
1222
1223 fail5:
1224         EFSYS_PROBE(fail5);
1225 fail4:
1226         EFSYS_PROBE(fail4);
1227 fail3:
1228         EFSYS_PROBE(fail3);
1229 fail2:
1230         EFSYS_PROBE(fail2);
1231 fail1:
1232         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1233
1234         return (rc);
1235 }
1236 #endif
1237
1238 #if EFSYS_OPT_RX_SCALE
1239 static  __checkReturn   efx_rc_t
1240 siena_rx_scale_tbl_set(
1241         __in            efx_nic_t *enp,
1242         __in            uint32_t rss_context,
1243         __in_ecount(n)  unsigned int *table,
1244         __in            size_t n)
1245 {
1246         efx_oword_t oword;
1247         int index;
1248         efx_rc_t rc;
1249
1250         EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1251         EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1252
1253         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1254                 rc = EINVAL;
1255                 goto fail1;
1256         }
1257
1258         if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1259                 rc = EINVAL;
1260                 goto fail2;
1261         }
1262
1263         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1264                 uint32_t byte;
1265
1266                 /* Calculate the entry to place in the table */
1267                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1268
1269                 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1270
1271                 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1272
1273                 /* Write the table */
1274                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1275                                     index, &oword, B_TRUE);
1276         }
1277
1278         for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1279                 uint32_t byte;
1280
1281                 /* Determine if we're starting a new batch */
1282                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1283
1284                 /* Read the table */
1285                 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1286                                     index, &oword, B_TRUE);
1287
1288                 /* Verify the entry */
1289                 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1290                         rc = EFAULT;
1291                         goto fail3;
1292                 }
1293         }
1294
1295         return (0);
1296
1297 fail3:
1298         EFSYS_PROBE(fail3);
1299 fail2:
1300         EFSYS_PROBE(fail2);
1301 fail1:
1302         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1303
1304         return (rc);
1305 }
1306 #endif
1307
1308 /*
1309  * Falcon/Siena pseudo-header
1310  * --------------------------
1311  *
1312  * Receive packets are prefixed by an optional 16 byte pseudo-header.
1313  * The pseudo-header is a byte array of one of the forms:
1314  *
1315  *  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
1316  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1317  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1318  *
1319  * where:
1320  *   TT.TT.TT.TT   Toeplitz hash (32-bit big-endian)
1321  *   LL.LL         LFSR hash     (16-bit big-endian)
1322  */
1323
1324 #if EFSYS_OPT_RX_SCALE
1325 static  __checkReturn   uint32_t
1326 siena_rx_prefix_hash(
1327         __in            efx_nic_t *enp,
1328         __in            efx_rx_hash_alg_t func,
1329         __in            uint8_t *buffer)
1330 {
1331         _NOTE(ARGUNUSED(enp))
1332
1333         switch (func) {
1334         case EFX_RX_HASHALG_TOEPLITZ:
1335                 return ((buffer[12] << 24) |
1336                     (buffer[13] << 16) |
1337                     (buffer[14] <<  8) |
1338                     buffer[15]);
1339
1340         case EFX_RX_HASHALG_LFSR:
1341                 return ((buffer[14] << 8) | buffer[15]);
1342
1343         default:
1344                 EFSYS_ASSERT(0);
1345                 return (0);
1346         }
1347 }
1348 #endif /* EFSYS_OPT_RX_SCALE */
1349
1350 static  __checkReturn   efx_rc_t
1351 siena_rx_prefix_pktlen(
1352         __in            efx_nic_t *enp,
1353         __in            uint8_t *buffer,
1354         __out           uint16_t *lengthp)
1355 {
1356         _NOTE(ARGUNUSED(enp, buffer, lengthp))
1357
1358         /* Not supported by Falcon/Siena hardware */
1359         EFSYS_ASSERT(0);
1360         return (ENOTSUP);
1361 }
1362
1363
1364 static                          void
1365 siena_rx_qpost(
1366         __in                    efx_rxq_t *erp,
1367         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
1368         __in                    size_t size,
1369         __in                    unsigned int ndescs,
1370         __in                    unsigned int completed,
1371         __in                    unsigned int added)
1372 {
1373         efx_qword_t qword;
1374         unsigned int i;
1375         unsigned int offset;
1376         unsigned int id;
1377
1378         /* The client driver must not overfill the queue */
1379         EFSYS_ASSERT3U(added - completed + ndescs, <=,
1380             EFX_RXQ_LIMIT(erp->er_mask + 1));
1381
1382         id = added & (erp->er_mask);
1383         for (i = 0; i < ndescs; i++) {
1384                 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1385                     unsigned int, id, efsys_dma_addr_t, addrp[i],
1386                     size_t, size);
1387
1388                 EFX_POPULATE_QWORD_3(qword,
1389                     FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1390                     FSF_AZ_RX_KER_BUF_ADDR_DW0,
1391                     (uint32_t)(addrp[i] & 0xffffffff),
1392                     FSF_AZ_RX_KER_BUF_ADDR_DW1,
1393                     (uint32_t)(addrp[i] >> 32));
1394
1395                 offset = id * sizeof (efx_qword_t);
1396                 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1397
1398                 id = (id + 1) & (erp->er_mask);
1399         }
1400 }
1401
1402 static                  void
1403 siena_rx_qpush(
1404         __in    efx_rxq_t *erp,
1405         __in    unsigned int added,
1406         __inout unsigned int *pushedp)
1407 {
1408         efx_nic_t *enp = erp->er_enp;
1409         unsigned int pushed = *pushedp;
1410         uint32_t wptr;
1411         efx_oword_t oword;
1412         efx_dword_t dword;
1413
1414         /* All descriptors are pushed */
1415         *pushedp = added;
1416
1417         /* Push the populated descriptors out */
1418         wptr = added & erp->er_mask;
1419
1420         EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1421
1422         /* Only write the third DWORD */
1423         EFX_POPULATE_DWORD_1(dword,
1424             EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1425
1426         /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1427         EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1428             wptr, pushed & erp->er_mask);
1429         EFSYS_PIO_WRITE_BARRIER();
1430         EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1431                             erp->er_index, &dword, B_FALSE);
1432 }
1433
1434 #if EFSYS_OPT_RX_PACKED_STREAM
1435 static          void
1436 siena_rx_qpush_ps_credits(
1437         __in            efx_rxq_t *erp)
1438 {
1439         /* Not supported by Siena hardware */
1440         EFSYS_ASSERT(0);
1441 }
1442
1443 static          uint8_t *
1444 siena_rx_qps_packet_info(
1445         __in            efx_rxq_t *erp,
1446         __in            uint8_t *buffer,
1447         __in            uint32_t buffer_length,
1448         __in            uint32_t current_offset,
1449         __out           uint16_t *lengthp,
1450         __out           uint32_t *next_offsetp,
1451         __out           uint32_t *timestamp)
1452 {
1453         /* Not supported by Siena hardware */
1454         EFSYS_ASSERT(0);
1455
1456         return (NULL);
1457 }
1458 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1459
1460 static  __checkReturn   efx_rc_t
1461 siena_rx_qflush(
1462         __in    efx_rxq_t *erp)
1463 {
1464         efx_nic_t *enp = erp->er_enp;
1465         efx_oword_t oword;
1466         uint32_t label;
1467
1468         label = erp->er_index;
1469
1470         /* Flush the queue */
1471         EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1472             FRF_AZ_RX_FLUSH_DESCQ, label);
1473         EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1474
1475         return (0);
1476 }
1477
1478 static          void
1479 siena_rx_qenable(
1480         __in    efx_rxq_t *erp)
1481 {
1482         efx_nic_t *enp = erp->er_enp;
1483         efx_oword_t oword;
1484
1485         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1486
1487         EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1488                             erp->er_index, &oword, B_TRUE);
1489
1490         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1491         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1492         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1493
1494         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1495                             erp->er_index, &oword, B_TRUE);
1496 }
1497
1498 static  __checkReturn   efx_rc_t
1499 siena_rx_qcreate(
1500         __in            efx_nic_t *enp,
1501         __in            unsigned int index,
1502         __in            unsigned int label,
1503         __in            efx_rxq_type_t type,
1504         __in            uint32_t type_data,
1505         __in            efsys_mem_t *esmp,
1506         __in            size_t ndescs,
1507         __in            uint32_t id,
1508         __in            unsigned int flags,
1509         __in            efx_evq_t *eep,
1510         __in            efx_rxq_t *erp)
1511 {
1512         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1513         efx_oword_t oword;
1514         uint32_t size;
1515         boolean_t jumbo = B_FALSE;
1516         efx_rc_t rc;
1517
1518         _NOTE(ARGUNUSED(esmp))
1519         _NOTE(ARGUNUSED(type_data))
1520
1521         EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1522             (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1523         EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1524         EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1525
1526         EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1527         EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1528
1529         if (!ISP2(ndescs) ||
1530             (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1531                 rc = EINVAL;
1532                 goto fail1;
1533         }
1534         if (index >= encp->enc_rxq_limit) {
1535                 rc = EINVAL;
1536                 goto fail2;
1537         }
1538         for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1539             size++)
1540                 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1541                         break;
1542         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1543                 rc = EINVAL;
1544                 goto fail3;
1545         }
1546
1547         switch (type) {
1548         case EFX_RXQ_TYPE_DEFAULT:
1549                 break;
1550
1551         default:
1552                 rc = EINVAL;
1553                 goto fail4;
1554         }
1555
1556         if (flags & EFX_RXQ_FLAG_SCATTER) {
1557 #if EFSYS_OPT_RX_SCATTER
1558                 jumbo = B_TRUE;
1559 #else
1560                 rc = EINVAL;
1561                 goto fail5;
1562 #endif  /* EFSYS_OPT_RX_SCATTER */
1563         }
1564
1565         /* Set up the new descriptor queue */
1566         EFX_POPULATE_OWORD_7(oword,
1567             FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1568             FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1569             FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1570             FRF_AZ_RX_DESCQ_LABEL, label,
1571             FRF_AZ_RX_DESCQ_SIZE, size,
1572             FRF_AZ_RX_DESCQ_TYPE, 0,
1573             FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1574
1575         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1576                             erp->er_index, &oword, B_TRUE);
1577
1578         return (0);
1579
1580 #if !EFSYS_OPT_RX_SCATTER
1581 fail5:
1582         EFSYS_PROBE(fail5);
1583 #endif
1584 fail4:
1585         EFSYS_PROBE(fail4);
1586 fail3:
1587         EFSYS_PROBE(fail3);
1588 fail2:
1589         EFSYS_PROBE(fail2);
1590 fail1:
1591         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1592
1593         return (rc);
1594 }
1595
1596 static          void
1597 siena_rx_qdestroy(
1598         __in    efx_rxq_t *erp)
1599 {
1600         efx_nic_t *enp = erp->er_enp;
1601         efx_oword_t oword;
1602
1603         EFSYS_ASSERT(enp->en_rx_qcount != 0);
1604         --enp->en_rx_qcount;
1605
1606         /* Purge descriptor queue */
1607         EFX_ZERO_OWORD(oword);
1608
1609         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1610                             erp->er_index, &oword, B_TRUE);
1611
1612         /* Free the RXQ object */
1613         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1614 }
1615
1616 static          void
1617 siena_rx_fini(
1618         __in    efx_nic_t *enp)
1619 {
1620         _NOTE(ARGUNUSED(enp))
1621 }
1622
1623 #endif /* EFSYS_OPT_SIENA */