2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
33 #ifndef _SYS_HUNT_IMPL_H
34 #define _SYS_HUNT_IMPL_H
38 #include "efx_regs_ef10.h"
46 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
47 * possibly be increased, or the write size reported by newer firmware used
50 #define EF10_NVRAM_CHUNK 0x80
52 /* Alignment requirement for value written to RX WPTR:
53 * the WPTR must be aligned to an 8 descriptor boundary
55 #define EF10_RX_WPTR_ALIGN 8
58 * Max byte offset into the packet the TCP header must start for the hardware
59 * to be able to parse the packet correctly.
60 * FIXME: Move to ef10_impl.h when it is included in all driver builds.
62 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
64 /* Invalid RSS context handle */
65 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
70 __checkReturn efx_rc_t
78 __checkReturn efx_rc_t
81 __in unsigned int index,
82 __in efsys_mem_t *esmp,
91 __checkReturn efx_rc_t
94 __in unsigned int count);
101 __checkReturn efx_rc_t
104 __in unsigned int us);
108 ef10_ev_qstats_update(
110 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
111 #endif /* EFSYS_OPT_QSTATS */
114 ef10_ev_rxlabel_init(
117 __in unsigned int label);
120 ef10_ev_rxlabel_fini(
122 __in unsigned int label);
126 __checkReturn efx_rc_t
129 __in efx_intr_type_t type,
130 __in efsys_mem_t *esmp);
134 __in efx_nic_t *enp);
138 __in efx_nic_t *enp);
141 ef10_intr_disable_unlocked(
142 __in efx_nic_t *enp);
144 __checkReturn efx_rc_t
147 __in unsigned int level);
150 ef10_intr_status_line(
152 __out boolean_t *fatalp,
153 __out uint32_t *qmaskp);
156 ef10_intr_status_message(
158 __in unsigned int message,
159 __out boolean_t *fatalp);
163 __in efx_nic_t *enp);
166 __in efx_nic_t *enp);
170 extern __checkReturn efx_rc_t
172 __in efx_nic_t *enp);
174 extern __checkReturn efx_rc_t
176 __in efx_nic_t *enp);
178 extern __checkReturn efx_rc_t
179 ef10_nic_set_drv_limits(
180 __inout efx_nic_t *enp,
181 __in efx_drv_limits_t *edlp);
183 extern __checkReturn efx_rc_t
184 ef10_nic_get_vi_pool(
186 __out uint32_t *vi_countp);
188 extern __checkReturn efx_rc_t
189 ef10_nic_get_bar_region(
191 __in efx_nic_region_t region,
192 __out uint32_t *offsetp,
193 __out size_t *sizep);
195 extern __checkReturn efx_rc_t
197 __in efx_nic_t *enp);
199 extern __checkReturn efx_rc_t
201 __in efx_nic_t *enp);
205 extern __checkReturn efx_rc_t
206 ef10_nic_register_test(
207 __in efx_nic_t *enp);
209 #endif /* EFSYS_OPT_DIAG */
213 __in efx_nic_t *enp);
217 __in efx_nic_t *enp);
222 extern __checkReturn efx_rc_t
225 __out efx_link_mode_t *link_modep);
227 extern __checkReturn efx_rc_t
230 __out boolean_t *mac_upp);
232 extern __checkReturn efx_rc_t
234 __in efx_nic_t *enp);
236 extern __checkReturn efx_rc_t
237 hunt_mac_reconfigure(
238 __in efx_nic_t *enp);
240 extern __checkReturn efx_rc_t
241 hunt_mac_multicast_list_set(
242 __in efx_nic_t *enp);
244 extern __checkReturn efx_rc_t
245 hunt_mac_filter_default_rxq_set(
248 __in boolean_t using_rss);
251 hunt_mac_filter_default_rxq_clear(
252 __in efx_nic_t *enp);
254 #if EFSYS_OPT_LOOPBACK
256 extern __checkReturn efx_rc_t
257 hunt_mac_loopback_set(
259 __in efx_link_mode_t link_mode,
260 __in efx_loopback_type_t loopback_type);
262 #endif /* EFSYS_OPT_LOOPBACK */
264 #if EFSYS_OPT_MAC_STATS
266 extern __checkReturn efx_rc_t
267 hunt_mac_stats_update(
269 __in efsys_mem_t *esmp,
270 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
271 __inout_opt uint32_t *generationp);
273 #endif /* EFSYS_OPT_MAC_STATS */
280 extern __checkReturn efx_rc_t
283 __in const efx_mcdi_transport_t *mtp);
287 __in efx_nic_t *enp);
290 ef10_mcdi_send_request(
295 __in size_t sdu_len);
297 extern __checkReturn boolean_t
298 ef10_mcdi_poll_response(
299 __in efx_nic_t *enp);
302 ef10_mcdi_read_response(
304 __out_bcount(length) void *bufferp,
309 ef10_mcdi_request_copyout(
311 __in efx_mcdi_req_t *emrp);
314 ef10_mcdi_poll_reboot(
315 __in efx_nic_t *enp);
317 extern __checkReturn efx_rc_t
318 ef10_mcdi_feature_supported(
320 __in efx_mcdi_feature_id_t id,
321 __out boolean_t *supportedp);
323 #endif /* EFSYS_OPT_MCDI */
327 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
329 extern __checkReturn efx_rc_t
330 ef10_nvram_buf_read_tlv(
332 __in_bcount(max_seg_size) caddr_t seg_data,
333 __in size_t max_seg_size,
335 __deref_out_bcount_opt(*sizep) caddr_t *datap,
336 __out size_t *sizep);
338 extern __checkReturn efx_rc_t
339 ef10_nvram_buf_write_tlv(
340 __inout_bcount(partn_size) caddr_t partn_data,
341 __in size_t partn_size,
343 __in_bcount(tag_size) caddr_t tag_data,
344 __in size_t tag_size,
345 __out size_t *total_lengthp);
347 extern __checkReturn efx_rc_t
348 ef10_nvram_partn_read_tlv(
352 __deref_out_bcount_opt(*sizep) caddr_t *datap,
353 __out size_t *sizep);
355 extern __checkReturn efx_rc_t
356 ef10_nvram_partn_write_tlv(
360 __in_bcount(size) caddr_t data,
363 extern __checkReturn efx_rc_t
364 ef10_nvram_partn_write_segment_tlv(
368 __in_bcount(size) caddr_t data,
370 __in boolean_t all_segments);
372 extern __checkReturn efx_rc_t
373 ef10_nvram_partn_lock(
375 __in uint32_t partn);
377 extern __checkReturn efx_rc_t
378 ef10_nvram_partn_read(
381 __in unsigned int offset,
382 __out_bcount(size) caddr_t data,
385 extern __checkReturn efx_rc_t
386 ef10_nvram_partn_erase(
389 __in unsigned int offset,
392 extern __checkReturn efx_rc_t
393 ef10_nvram_partn_write(
396 __in unsigned int offset,
397 __out_bcount(size) caddr_t data,
401 ef10_nvram_partn_unlock(
403 __in uint32_t partn);
405 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
411 extern __checkReturn efx_rc_t
413 __in efx_nic_t *enp);
415 #endif /* EFSYS_OPT_DIAG */
417 extern __checkReturn efx_rc_t
418 ef10_nvram_get_version(
420 __in efx_nvram_type_t type,
421 __out uint32_t *subtypep,
422 __out_ecount(4) uint16_t version[4]);
424 extern __checkReturn efx_rc_t
427 __in efx_nvram_type_t type,
428 __out size_t *pref_chunkp);
430 extern __checkReturn efx_rc_t
431 ef10_nvram_read_chunk(
433 __in efx_nvram_type_t type,
434 __in unsigned int offset,
435 __out_bcount(size) caddr_t data,
438 extern __checkReturn efx_rc_t
441 __in efx_nvram_type_t type);
443 extern __checkReturn efx_rc_t
444 ef10_nvram_write_chunk(
446 __in efx_nvram_type_t type,
447 __in unsigned int offset,
448 __in_bcount(size) caddr_t data,
452 ef10_nvram_rw_finish(
454 __in efx_nvram_type_t type);
456 extern __checkReturn efx_rc_t
457 ef10_nvram_partn_set_version(
460 __in_ecount(4) uint16_t version[4]);
462 extern __checkReturn efx_rc_t
463 ef10_nvram_set_version(
465 __in efx_nvram_type_t type,
466 __in_ecount(4) uint16_t version[4]);
468 extern __checkReturn efx_rc_t
469 ef10_nvram_type_to_partn(
471 __in efx_nvram_type_t type,
472 __out uint32_t *partnp);
474 extern __checkReturn efx_rc_t
475 ef10_nvram_partn_size(
478 __out size_t *sizep);
480 #endif /* EFSYS_OPT_NVRAM */
485 typedef struct hunt_link_state_s {
486 uint32_t hls_adv_cap_mask;
487 uint32_t hls_lp_cap_mask;
488 unsigned int hls_fcntl;
489 efx_link_mode_t hls_link_mode;
490 #if EFSYS_OPT_LOOPBACK
491 efx_loopback_type_t hls_loopback;
493 boolean_t hls_mac_up;
499 __in efx_qword_t *eqp,
500 __out efx_link_mode_t *link_modep);
502 extern __checkReturn efx_rc_t
505 __out hunt_link_state_t *hlsp);
507 extern __checkReturn efx_rc_t
512 extern __checkReturn efx_rc_t
513 hunt_phy_reconfigure(
514 __in efx_nic_t *enp);
516 extern __checkReturn efx_rc_t
518 __in efx_nic_t *enp);
520 extern __checkReturn efx_rc_t
523 __out uint32_t *ouip);
525 #if EFSYS_OPT_PHY_STATS
527 extern __checkReturn efx_rc_t
528 hunt_phy_stats_update(
530 __in efsys_mem_t *esmp,
531 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
533 #endif /* EFSYS_OPT_PHY_STATS */
535 #if EFSYS_OPT_PHY_PROPS
542 __in unsigned int id);
544 #endif /* EFSYS_OPT_NAMES */
546 extern __checkReturn efx_rc_t
549 __in unsigned int id,
551 __out uint32_t *valp);
553 extern __checkReturn efx_rc_t
556 __in unsigned int id,
559 #endif /* EFSYS_OPT_PHY_PROPS */
563 extern __checkReturn efx_rc_t
564 hunt_bist_enable_offline(
565 __in efx_nic_t *enp);
567 extern __checkReturn efx_rc_t
570 __in efx_bist_type_t type);
572 extern __checkReturn efx_rc_t
575 __in efx_bist_type_t type,
576 __out efx_bist_result_t *resultp,
577 __out_opt __drv_when(count > 0, __notnull)
578 uint32_t *value_maskp,
579 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
580 unsigned long *valuesp,
586 __in efx_bist_type_t type);
588 #endif /* EFSYS_OPT_BIST */
595 extern __checkReturn efx_rc_t
598 __in efx_sram_pattern_fn_t func);
600 #endif /* EFSYS_OPT_DIAG */
605 extern __checkReturn efx_rc_t
607 __in efx_nic_t *enp);
611 __in efx_nic_t *enp);
613 extern __checkReturn efx_rc_t
616 __in unsigned int index,
617 __in unsigned int label,
618 __in efsys_mem_t *esmp,
624 __out unsigned int *addedp);
628 __in efx_txq_t *etp);
630 extern __checkReturn efx_rc_t
633 __in_ecount(n) efx_buffer_t *eb,
635 __in unsigned int completed,
636 __inout unsigned int *addedp);
641 __in unsigned int added,
642 __in unsigned int pushed);
644 extern __checkReturn efx_rc_t
647 __in unsigned int ns);
649 extern __checkReturn efx_rc_t
651 __in efx_txq_t *etp);
655 __in efx_txq_t *etp);
657 extern __checkReturn efx_rc_t
659 __in efx_txq_t *etp);
662 ef10_tx_qpio_disable(
663 __in efx_txq_t *etp);
665 extern __checkReturn efx_rc_t
668 __in_ecount(buf_length) uint8_t *buffer,
669 __in size_t buf_length,
670 __in size_t pio_buf_offset);
672 extern __checkReturn efx_rc_t
675 __in size_t pkt_length,
676 __in unsigned int completed,
677 __inout unsigned int *addedp);
679 extern __checkReturn efx_rc_t
682 __in_ecount(n) efx_desc_t *ed,
684 __in unsigned int completed,
685 __inout unsigned int *addedp);
688 ef10_tx_qdesc_dma_create(
690 __in efsys_dma_addr_t addr,
693 __out efx_desc_t *edp);
696 hunt_tx_qdesc_tso_create(
698 __in uint16_t ipv4_id,
699 __in uint32_t tcp_seq,
700 __in uint8_t tcp_flags,
701 __out efx_desc_t *edp);
704 ef10_tx_qdesc_tso2_create(
706 __in uint16_t ipv4_id,
707 __in uint32_t tcp_seq,
708 __in uint16_t tcp_mss,
709 __out_ecount(count) efx_desc_t *edp,
713 ef10_tx_qdesc_vlantci_create(
715 __in uint16_t vlan_tci,
716 __out efx_desc_t *edp);
722 ef10_tx_qstats_update(
724 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
726 #endif /* EFSYS_OPT_QSTATS */
730 /* Missing register definitions */
731 #ifndef ER_DZ_TX_PIOBUF_OFST
732 #define ER_DZ_TX_PIOBUF_OFST 0x00001000
734 #ifndef ER_DZ_TX_PIOBUF_STEP
735 #define ER_DZ_TX_PIOBUF_STEP 8192
737 #ifndef ER_DZ_TX_PIOBUF_ROWS
738 #define ER_DZ_TX_PIOBUF_ROWS 2048
741 #ifndef ER_DZ_TX_PIOBUF_SIZE
742 #define ER_DZ_TX_PIOBUF_SIZE 2048
745 #define HUNT_PIOBUF_NBUFS (16)
746 #define HUNT_PIOBUF_SIZE (ER_DZ_TX_PIOBUF_SIZE)
748 #define HUNT_MIN_PIO_ALLOC_SIZE (HUNT_PIOBUF_SIZE / 32)
750 #define HUNT_LEGACY_PF_PRIVILEGE_MASK \
751 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
752 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
753 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
754 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
755 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
756 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
757 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
758 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
759 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
760 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
761 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
763 #define HUNT_LEGACY_VF_PRIVILEGE_MASK 0
765 typedef uint32_t efx_piobuf_handle_t;
767 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
769 extern __checkReturn efx_rc_t
771 __inout efx_nic_t *enp,
772 __out uint32_t *bufnump,
773 __out efx_piobuf_handle_t *handlep,
774 __out uint32_t *blknump,
775 __out uint32_t *offsetp,
776 __out size_t *sizep);
778 extern __checkReturn efx_rc_t
780 __inout efx_nic_t *enp,
781 __in uint32_t bufnum,
782 __in uint32_t blknum);
784 extern __checkReturn efx_rc_t
786 __inout efx_nic_t *enp,
787 __in uint32_t vi_index,
788 __in efx_piobuf_handle_t handle);
790 extern __checkReturn efx_rc_t
792 __inout efx_nic_t *enp,
793 __in uint32_t vi_index);
800 extern __checkReturn efx_rc_t
802 __in efx_nic_t *enp);
804 extern __checkReturn efx_rc_t
807 __out size_t *sizep);
809 extern __checkReturn efx_rc_t
812 __out_bcount(size) caddr_t data,
815 extern __checkReturn efx_rc_t
818 __in_bcount(size) caddr_t data,
821 extern __checkReturn efx_rc_t
824 __in_bcount(size) caddr_t data,
827 extern __checkReturn efx_rc_t
830 __in_bcount(size) caddr_t data,
832 __inout efx_vpd_value_t *evvp);
834 extern __checkReturn efx_rc_t
837 __in_bcount(size) caddr_t data,
839 __in efx_vpd_value_t *evvp);
841 extern __checkReturn efx_rc_t
844 __in_bcount(size) caddr_t data,
846 __out efx_vpd_value_t *evvp,
847 __inout unsigned int *contp);
849 extern __checkReturn efx_rc_t
852 __in_bcount(size) caddr_t data,
857 __in efx_nic_t *enp);
859 #endif /* EFSYS_OPT_VPD */
864 extern __checkReturn efx_rc_t
866 __in efx_nic_t *enp);
868 #if EFSYS_OPT_RX_SCATTER
869 extern __checkReturn efx_rc_t
870 ef10_rx_scatter_enable(
872 __in unsigned int buf_size);
873 #endif /* EFSYS_OPT_RX_SCATTER */
876 #if EFSYS_OPT_RX_SCALE
878 extern __checkReturn efx_rc_t
879 ef10_rx_scale_mode_set(
881 __in efx_rx_hash_alg_t alg,
882 __in efx_rx_hash_type_t type,
883 __in boolean_t insert);
885 extern __checkReturn efx_rc_t
886 ef10_rx_scale_key_set(
888 __in_ecount(n) uint8_t *key,
891 extern __checkReturn efx_rc_t
892 ef10_rx_scale_tbl_set(
894 __in_ecount(n) unsigned int *table,
897 extern __checkReturn uint32_t
900 __in efx_rx_hash_alg_t func,
901 __in uint8_t *buffer);
903 #endif /* EFSYS_OPT_RX_SCALE */
905 extern __checkReturn efx_rc_t
906 ef10_rx_prefix_pktlen(
908 __in uint8_t *buffer,
909 __out uint16_t *lengthp);
914 __in_ecount(n) efsys_dma_addr_t *addrp,
917 __in unsigned int completed,
918 __in unsigned int added);
923 __in unsigned int added,
924 __inout unsigned int *pushedp);
926 extern __checkReturn efx_rc_t
928 __in efx_rxq_t *erp);
932 __in efx_rxq_t *erp);
934 extern __checkReturn efx_rc_t
937 __in unsigned int index,
938 __in unsigned int label,
939 __in efx_rxq_type_t type,
940 __in efsys_mem_t *esmp,
944 __in efx_rxq_t *erp);
948 __in efx_rxq_t *erp);
952 __in efx_nic_t *enp);
956 typedef struct ef10_filter_handle_s {
959 } ef10_filter_handle_t;
961 typedef struct ef10_filter_entry_s {
962 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
963 ef10_filter_handle_t efe_handle;
964 } ef10_filter_entry_t;
967 * BUSY flag indicates that an update is in progress.
968 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
970 #define EFX_EF10_FILTER_FLAG_BUSY 1U
971 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
972 #define EFX_EF10_FILTER_FLAGS 3U
975 * Size of the hash table used by the driver. Doesn't need to be the
976 * same size as the hardware's table.
978 #define EFX_EF10_FILTER_TBL_ROWS 8192
980 /* Allow for the broadcast address to be added to the multicast list */
981 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
983 typedef struct ef10_filter_table_s {
984 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
985 efx_rxq_t * eft_default_rxq;
986 boolean_t eft_using_rss;
987 uint32_t eft_unicst_filter_index;
988 boolean_t eft_unicst_filter_set;
989 uint32_t eft_mulcst_filter_indexes[
990 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
991 uint32_t eft_mulcst_filter_count;
992 } ef10_filter_table_t;
994 __checkReturn efx_rc_t
996 __in efx_nic_t *enp);
1000 __in efx_nic_t *enp);
1002 __checkReturn efx_rc_t
1003 ef10_filter_restore(
1004 __in efx_nic_t *enp);
1006 __checkReturn efx_rc_t
1008 __in efx_nic_t *enp,
1009 __inout efx_filter_spec_t *spec,
1010 __in boolean_t may_replace);
1012 __checkReturn efx_rc_t
1014 __in efx_nic_t *enp,
1015 __inout efx_filter_spec_t *spec);
1017 extern __checkReturn efx_rc_t
1018 ef10_filter_supported_filters(
1019 __in efx_nic_t *enp,
1020 __out uint32_t *list,
1021 __out size_t *length);
1023 extern __checkReturn efx_rc_t
1024 ef10_filter_reconfigure(
1025 __in efx_nic_t *enp,
1026 __in_ecount(6) uint8_t const *mac_addr,
1027 __in boolean_t all_unicst,
1028 __in boolean_t mulcst,
1029 __in boolean_t all_mulcst,
1030 __in boolean_t brdcst,
1031 __in_ecount(6*count) uint8_t const *addrs,
1035 ef10_filter_get_default_rxq(
1036 __in efx_nic_t *enp,
1037 __out efx_rxq_t **erpp,
1038 __out boolean_t *using_rss);
1041 ef10_filter_default_rxq_set(
1042 __in efx_nic_t *enp,
1043 __in efx_rxq_t *erp,
1044 __in boolean_t using_rss);
1047 ef10_filter_default_rxq_clear(
1048 __in efx_nic_t *enp);
1051 #endif /* EFSYS_OPT_FILTER */
1053 extern __checkReturn efx_rc_t
1054 efx_mcdi_get_function_info(
1055 __in efx_nic_t *enp,
1056 __out uint32_t *pfp,
1057 __out_opt uint32_t *vfp);
1059 extern __checkReturn efx_rc_t
1060 efx_mcdi_privilege_mask(
1061 __in efx_nic_t *enp,
1064 __out uint32_t *maskp);
1070 #endif /* _SYS_HUNT_IMPL_H */