2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
39 #if EFSYS_OPT_HUNTINGTON
41 #include "ef10_tlv_layout.h"
43 static __checkReturn efx_rc_t
44 efx_mcdi_get_port_assignment(
46 __out uint32_t *portp)
49 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
50 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
53 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
54 enp->en_family == EFX_FAMILY_MEDFORD);
56 (void) memset(payload, 0, sizeof (payload));
57 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
58 req.emr_in_buf = payload;
59 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
60 req.emr_out_buf = payload;
61 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
63 efx_mcdi_execute(enp, &req);
65 if (req.emr_rc != 0) {
70 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
75 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
82 EFSYS_PROBE1(fail1, efx_rc_t, rc);
87 static __checkReturn efx_rc_t
88 efx_mcdi_get_port_modes(
90 __out uint32_t *modesp)
93 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
94 MC_CMD_GET_PORT_MODES_OUT_LEN)];
97 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
98 enp->en_family == EFX_FAMILY_MEDFORD);
100 (void) memset(payload, 0, sizeof (payload));
101 req.emr_cmd = MC_CMD_GET_PORT_MODES;
102 req.emr_in_buf = payload;
103 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
104 req.emr_out_buf = payload;
105 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
107 efx_mcdi_execute(enp, &req);
109 if (req.emr_rc != 0) {
114 /* Accept pre-Medford size (8 bytes - no CurrentMode field) */
115 if (req.emr_out_length_used <
116 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
121 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
128 EFSYS_PROBE1(fail1, efx_rc_t, rc);
134 static __checkReturn efx_rc_t
135 efx_mcdi_vadaptor_alloc(
137 __in uint32_t port_id)
140 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
141 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
144 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
146 (void) memset(payload, 0, sizeof (payload));
147 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
148 req.emr_in_buf = payload;
149 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
150 req.emr_out_buf = payload;
151 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
153 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
154 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
155 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
156 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
158 efx_mcdi_execute(enp, &req);
160 if (req.emr_rc != 0) {
168 EFSYS_PROBE1(fail1, efx_rc_t, rc);
173 static __checkReturn efx_rc_t
174 efx_mcdi_vadaptor_free(
176 __in uint32_t port_id)
179 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
180 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
183 (void) memset(payload, 0, sizeof (payload));
184 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
185 req.emr_in_buf = payload;
186 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
187 req.emr_out_buf = payload;
188 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
190 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
192 efx_mcdi_execute(enp, &req);
194 if (req.emr_rc != 0) {
202 EFSYS_PROBE1(fail1, efx_rc_t, rc);
207 static __checkReturn efx_rc_t
208 efx_mcdi_get_mac_address_pf(
210 __out_ecount_opt(6) uint8_t mac_addrp[6])
213 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
214 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
217 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
218 enp->en_family == EFX_FAMILY_MEDFORD);
220 (void) memset(payload, 0, sizeof (payload));
221 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
222 req.emr_in_buf = payload;
223 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
224 req.emr_out_buf = payload;
225 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
227 efx_mcdi_execute(enp, &req);
229 if (req.emr_rc != 0) {
234 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
239 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
244 if (mac_addrp != NULL) {
247 addrp = MCDI_OUT2(req, uint8_t,
248 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
250 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
260 EFSYS_PROBE1(fail1, efx_rc_t, rc);
265 static __checkReturn efx_rc_t
266 efx_mcdi_get_mac_address_vf(
268 __out_ecount_opt(6) uint8_t mac_addrp[6])
271 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
272 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
275 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
276 enp->en_family == EFX_FAMILY_MEDFORD);
278 (void) memset(payload, 0, sizeof (payload));
279 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
280 req.emr_in_buf = payload;
281 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
282 req.emr_out_buf = payload;
283 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
285 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
286 EVB_PORT_ID_ASSIGNED);
288 efx_mcdi_execute(enp, &req);
290 if (req.emr_rc != 0) {
295 if (req.emr_out_length_used <
296 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
301 if (MCDI_OUT_DWORD(req,
302 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
307 if (mac_addrp != NULL) {
310 addrp = MCDI_OUT2(req, uint8_t,
311 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
313 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
323 EFSYS_PROBE1(fail1, efx_rc_t, rc);
328 static __checkReturn efx_rc_t
331 __out uint32_t *sys_freqp)
334 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
335 MC_CMD_GET_CLOCK_OUT_LEN)];
338 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
339 enp->en_family == EFX_FAMILY_MEDFORD);
341 (void) memset(payload, 0, sizeof (payload));
342 req.emr_cmd = MC_CMD_GET_CLOCK;
343 req.emr_in_buf = payload;
344 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
345 req.emr_out_buf = payload;
346 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
348 efx_mcdi_execute(enp, &req);
350 if (req.emr_rc != 0) {
355 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
360 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
361 if (*sys_freqp == 0) {
373 EFSYS_PROBE1(fail1, efx_rc_t, rc);
378 static __checkReturn efx_rc_t
379 efx_mcdi_get_vector_cfg(
381 __out_opt uint32_t *vec_basep,
382 __out_opt uint32_t *pf_nvecp,
383 __out_opt uint32_t *vf_nvecp)
386 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
387 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
390 (void) memset(payload, 0, sizeof (payload));
391 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
392 req.emr_in_buf = payload;
393 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
394 req.emr_out_buf = payload;
395 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
397 efx_mcdi_execute(enp, &req);
399 if (req.emr_rc != 0) {
404 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
409 if (vec_basep != NULL)
410 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
411 if (pf_nvecp != NULL)
412 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
413 if (vf_nvecp != NULL)
414 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
421 EFSYS_PROBE1(fail1, efx_rc_t, rc);
426 static __checkReturn efx_rc_t
427 efx_mcdi_get_capabilities(
429 __out efx_dword_t *flagsp)
432 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
433 MC_CMD_GET_CAPABILITIES_OUT_LEN)];
436 (void) memset(payload, 0, sizeof (payload));
437 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
438 req.emr_in_buf = payload;
439 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
440 req.emr_out_buf = payload;
441 req.emr_out_length = MC_CMD_GET_CAPABILITIES_OUT_LEN;
443 efx_mcdi_execute(enp, &req);
445 if (req.emr_rc != 0) {
450 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
455 *flagsp = *MCDI_OUT2(req, efx_dword_t, GET_CAPABILITIES_OUT_FLAGS1);
462 EFSYS_PROBE1(fail1, efx_rc_t, rc);
468 static __checkReturn efx_rc_t
471 __in uint32_t min_vi_count,
472 __in uint32_t max_vi_count,
473 __out uint32_t *vi_basep,
474 __out uint32_t *vi_countp,
475 __out uint32_t *vi_shiftp)
478 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
479 MC_CMD_ALLOC_VIS_OUT_LEN)];
482 if (vi_countp == NULL) {
487 (void) memset(payload, 0, sizeof (payload));
488 req.emr_cmd = MC_CMD_ALLOC_VIS;
489 req.emr_in_buf = payload;
490 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
491 req.emr_out_buf = payload;
492 req.emr_out_length = MC_CMD_ALLOC_VIS_OUT_LEN;
494 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
495 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
497 efx_mcdi_execute(enp, &req);
499 if (req.emr_rc != 0) {
504 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
509 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
510 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
512 /* Report VI_SHIFT if available (always zero for Huntington) */
513 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
516 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
525 EFSYS_PROBE1(fail1, efx_rc_t, rc);
531 static __checkReturn efx_rc_t
538 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
539 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
541 req.emr_cmd = MC_CMD_FREE_VIS;
542 req.emr_in_buf = NULL;
543 req.emr_in_length = 0;
544 req.emr_out_buf = NULL;
545 req.emr_out_length = 0;
547 efx_mcdi_execute_quiet(enp, &req);
549 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
550 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
558 EFSYS_PROBE1(fail1, efx_rc_t, rc);
564 static __checkReturn efx_rc_t
565 efx_mcdi_alloc_piobuf(
567 __out efx_piobuf_handle_t *handlep)
570 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
571 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
574 if (handlep == NULL) {
579 (void) memset(payload, 0, sizeof (payload));
580 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
581 req.emr_in_buf = payload;
582 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
583 req.emr_out_buf = payload;
584 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
586 efx_mcdi_execute_quiet(enp, &req);
588 if (req.emr_rc != 0) {
593 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
598 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
607 EFSYS_PROBE1(fail1, efx_rc_t, rc);
612 static __checkReturn efx_rc_t
613 efx_mcdi_free_piobuf(
615 __in efx_piobuf_handle_t handle)
618 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
619 MC_CMD_FREE_PIOBUF_OUT_LEN)];
622 (void) memset(payload, 0, sizeof (payload));
623 req.emr_cmd = MC_CMD_FREE_PIOBUF;
624 req.emr_in_buf = payload;
625 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
626 req.emr_out_buf = payload;
627 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
629 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
631 efx_mcdi_execute_quiet(enp, &req);
633 if (req.emr_rc != 0) {
641 EFSYS_PROBE1(fail1, efx_rc_t, rc);
646 static __checkReturn efx_rc_t
647 efx_mcdi_link_piobuf(
649 __in uint32_t vi_index,
650 __in efx_piobuf_handle_t handle)
653 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
654 MC_CMD_LINK_PIOBUF_OUT_LEN)];
657 (void) memset(payload, 0, sizeof (payload));
658 req.emr_cmd = MC_CMD_LINK_PIOBUF;
659 req.emr_in_buf = payload;
660 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
661 req.emr_out_buf = payload;
662 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
664 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
665 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
667 efx_mcdi_execute(enp, &req);
669 if (req.emr_rc != 0) {
677 EFSYS_PROBE1(fail1, efx_rc_t, rc);
682 static __checkReturn efx_rc_t
683 efx_mcdi_unlink_piobuf(
685 __in uint32_t vi_index)
688 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
689 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
692 (void) memset(payload, 0, sizeof (payload));
693 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
694 req.emr_in_buf = payload;
695 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
696 req.emr_out_buf = payload;
697 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
699 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
701 efx_mcdi_execute(enp, &req);
703 if (req.emr_rc != 0) {
711 EFSYS_PROBE1(fail1, efx_rc_t, rc);
717 ef10_nic_alloc_piobufs(
719 __in uint32_t max_piobuf_count)
721 efx_piobuf_handle_t *handlep;
725 EFSYS_ASSERT3U(max_piobuf_count, <=,
726 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
728 enp->en_arch.ef10.ena_piobuf_count = 0;
730 for (i = 0; i < max_piobuf_count; i++) {
731 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
733 if ((rc = efx_mcdi_alloc_piobuf(enp, handlep)) != 0)
736 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
737 enp->en_arch.ef10.ena_piobuf_count++;
743 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
744 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
746 efx_mcdi_free_piobuf(enp, *handlep);
747 *handlep = EFX_PIOBUF_HANDLE_INVALID;
749 enp->en_arch.ef10.ena_piobuf_count = 0;
754 ef10_nic_free_piobufs(
757 efx_piobuf_handle_t *handlep;
760 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
761 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
763 efx_mcdi_free_piobuf(enp, *handlep);
764 *handlep = EFX_PIOBUF_HANDLE_INVALID;
766 enp->en_arch.ef10.ena_piobuf_count = 0;
769 /* Sub-allocate a block from a piobuf */
770 __checkReturn efx_rc_t
772 __inout efx_nic_t *enp,
773 __out uint32_t *bufnump,
774 __out efx_piobuf_handle_t *handlep,
775 __out uint32_t *blknump,
776 __out uint32_t *offsetp,
779 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
780 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
781 uint32_t blk_per_buf;
785 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
786 enp->en_family == EFX_FAMILY_MEDFORD);
787 EFSYS_ASSERT(bufnump);
788 EFSYS_ASSERT(handlep);
789 EFSYS_ASSERT(blknump);
790 EFSYS_ASSERT(offsetp);
793 if ((edcp->edc_pio_alloc_size == 0) ||
794 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
798 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
800 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
801 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
806 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
807 for (blk = 0; blk < blk_per_buf; blk++) {
808 if ((*map & (1u << blk)) == 0) {
818 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
821 *sizep = edcp->edc_pio_alloc_size;
822 *offsetp = blk * (*sizep);
829 EFSYS_PROBE1(fail1, efx_rc_t, rc);
834 /* Free a piobuf sub-allocated block */
835 __checkReturn efx_rc_t
837 __inout efx_nic_t *enp,
838 __in uint32_t bufnum,
839 __in uint32_t blknum)
844 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
845 (blknum >= (8 * sizeof (*map)))) {
850 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
851 if ((*map & (1u << blknum)) == 0) {
855 *map &= ~(1u << blknum);
862 EFSYS_PROBE1(fail1, efx_rc_t, rc);
867 __checkReturn efx_rc_t
869 __inout efx_nic_t *enp,
870 __in uint32_t vi_index,
871 __in efx_piobuf_handle_t handle)
873 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
876 __checkReturn efx_rc_t
878 __inout efx_nic_t *enp,
879 __in uint32_t vi_index)
881 return (efx_mcdi_unlink_piobuf(enp, vi_index));
884 static __checkReturn efx_rc_t
885 ef10_get_datapath_caps(
888 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
889 efx_dword_t datapath_capabilities;
892 if ((rc = efx_mcdi_get_capabilities(enp, &datapath_capabilities)) != 0)
896 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
897 * We only support the 14 byte prefix here.
899 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
900 GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14) != 1) {
904 encp->enc_rx_prefix_size = 14;
906 /* Check if the firmware supports TSO */
907 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
908 GET_CAPABILITIES_OUT_TX_TSO) == 1)
909 encp->enc_fw_assisted_tso_enabled = B_TRUE;
911 encp->enc_fw_assisted_tso_enabled = B_FALSE;
913 /* Check if the firmware has vadapter/vport/vswitch support */
914 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
915 GET_CAPABILITIES_OUT_EVB) == 1)
916 encp->enc_datapath_cap_evb = B_TRUE;
918 encp->enc_datapath_cap_evb = B_FALSE;
920 /* Check if the firmware supports VLAN insertion */
921 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
922 GET_CAPABILITIES_OUT_TX_VLAN_INSERTION) == 1)
923 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
925 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
927 /* Check if the firmware supports RX event batching */
928 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
929 GET_CAPABILITIES_OUT_RX_BATCHING) == 1) {
930 encp->enc_rx_batching_enabled = B_TRUE;
931 encp->enc_rx_batch_max = 16;
933 encp->enc_rx_batching_enabled = B_FALSE;
936 /* Check if the firmware supports disabling scatter on RXQs */
937 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
938 GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER) == 1) {
939 encp->enc_rx_disable_scatter_supported = B_TRUE;
941 encp->enc_rx_disable_scatter_supported = B_FALSE;
944 /* Check if the firmware supports set mac with running filters */
945 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
946 GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED)
948 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
950 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
958 EFSYS_PROBE1(fail1, efx_rc_t, rc);
964 * The external port mapping is a one-based numbering of the external
965 * connectors on the board. It does not distinguish off-board separated
966 * outputs such as multi-headed cables.
967 * The number of ports that map to each external port connector
968 * on the board is determined by the chip family and the port modes to
969 * which the NIC can be configured. The mapping table lists modes with
970 * port numbering requirements in increasing order.
976 } __ef10_external_port_mappings[] = {
977 /* Supported modes requiring 1 output per port */
979 EFX_FAMILY_HUNTINGTON,
980 (1 << TLV_PORT_MODE_10G) |
981 (1 << TLV_PORT_MODE_10G_10G) |
982 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
985 /* Supported modes requiring 2 outputs per port */
987 EFX_FAMILY_HUNTINGTON,
988 (1 << TLV_PORT_MODE_40G) |
989 (1 << TLV_PORT_MODE_40G_40G) |
990 (1 << TLV_PORT_MODE_40G_10G_10G) |
991 (1 << TLV_PORT_MODE_10G_10G_40G),
995 * NOTE: Medford modes will require 4 outputs per port:
996 * TLV_PORT_MODE_10G_10G_10G_10G_Q
997 * TLV_PORT_MODE_10G_10G_10G_10G_Q2
998 * The Q2 mode routes outputs to external port 2. Support for this
999 * will require a new field specifying the number to add after
1000 * scaling by stride. This is fixed at 1 currently.
1004 static __checkReturn efx_rc_t
1005 ef10_external_port_mapping(
1006 __in efx_nic_t *enp,
1008 __out uint8_t *external_portp)
1012 uint32_t port_modes;
1014 uint32_t stride = 1; /* default 1-1 mapping */
1016 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes)) != 0) {
1017 /* No port mode information available - use default mapping */
1022 * Infer the internal port -> external port mapping from
1023 * the possible port modes for this NIC.
1025 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1026 if (__ef10_external_port_mappings[i].family !=
1029 matches = (__ef10_external_port_mappings[i].modes_mask &
1032 stride = __ef10_external_port_mappings[i].stride;
1033 port_modes &= ~matches;
1037 if (port_modes != 0) {
1038 /* Some advertised modes are not supported */
1045 * Scale as required by last matched mode and then convert to
1046 * one-based numbering
1048 *external_portp = (uint8_t)(port / stride) + 1;
1052 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1057 static __checkReturn efx_rc_t
1059 __in efx_nic_t *enp)
1061 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1062 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1063 uint8_t mac_addr[6];
1064 uint32_t board_type = 0;
1065 hunt_link_state_t hls;
1066 efx_port_t *epp = &(enp->en_port);
1073 uint32_t base, nvec;
1076 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1080 * NOTE: The MCDI protocol numbers ports from zero.
1081 * The common code MCDI interface numbers ports from one.
1083 emip->emi_port = port + 1;
1085 if ((rc = ef10_external_port_mapping(enp, port,
1086 &encp->enc_external_port)) != 0)
1090 * Get PCIe function number from firmware (used for
1091 * per-function privilege and dynamic config info).
1092 * - PCIe PF: pf = PF number, vf = 0xffff.
1093 * - PCIe VF: pf = parent PF, vf = VF number.
1095 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1101 /* MAC address for this function */
1102 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1103 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1104 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1106 * If the static config does not include a global MAC
1107 * address pool then the board may return a locally
1108 * administered MAC address (this should only happen on
1109 * incorrectly programmed boards).
1114 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1119 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1121 /* Board configuration */
1122 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1124 /* Unprivileged functions may not be able to read board cfg */
1131 encp->enc_board_type = board_type;
1132 encp->enc_clk_mult = 1; /* not used for Huntington */
1134 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1135 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1138 /* Obtain the default PHY advertised capabilities */
1139 if ((rc = hunt_phy_get_link(enp, &hls)) != 0)
1141 epp->ep_default_adv_cap_mask = hls.hls_adv_cap_mask;
1142 epp->ep_adv_cap_mask = hls.hls_adv_cap_mask;
1145 * Enable firmware workarounds for hardware errata.
1146 * Expected responses are:
1148 * Success: workaround enabled or disabled as requested.
1149 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
1150 * Firmware does not support the MC_CMD_WORKAROUND request.
1151 * (assume that the workaround is not supported).
1152 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
1153 * Firmware does not support the requested workaround.
1154 * - MC_CMD_ERR_EPERM (reported as EACCES):
1155 * Unprivileged function cannot enable/disable workarounds.
1157 * See efx_mcdi_request_errcode() for MCDI error translations.
1161 * If the bug35388 workaround is enabled, then use an indirect access
1162 * method to avoid unsafe EVQ writes.
1164 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
1166 if ((rc == 0) || (rc == EACCES))
1167 encp->enc_bug35388_workaround = B_TRUE;
1168 else if ((rc == ENOTSUP) || (rc == ENOENT))
1169 encp->enc_bug35388_workaround = B_FALSE;
1174 * If the bug41750 workaround is enabled, then do not test interrupts,
1175 * as the test will fail (seen with Greenport controllers).
1177 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
1180 encp->enc_bug41750_workaround = B_TRUE;
1181 } else if (rc == EACCES) {
1182 /* Assume a controller with 40G ports needs the workaround. */
1183 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
1184 encp->enc_bug41750_workaround = B_TRUE;
1186 encp->enc_bug41750_workaround = B_FALSE;
1187 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1188 encp->enc_bug41750_workaround = B_FALSE;
1192 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
1193 /* Interrupt testing does not work for VFs. See bug50084. */
1194 encp->enc_bug41750_workaround = B_TRUE;
1198 * If the bug26807 workaround is enabled, then firmware has enabled
1199 * support for chained multicast filters. Firmware will reset (FLR)
1200 * functions which have filters in the hardware filter table when the
1201 * workaround is enabled/disabled.
1203 * We must recheck if the workaround is enabled after inserting the
1204 * first hardware filter, in case it has been changed since this check.
1206 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
1209 encp->enc_bug26807_workaround = B_TRUE;
1210 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
1212 * Other functions had installed filters before the
1213 * workaround was enabled, and they have been reset
1216 EFSYS_PROBE(bug26807_workaround_flr_done);
1217 /* FIXME: bump MC warm boot count ? */
1219 } else if (rc == EACCES) {
1221 * Unprivileged functions cannot enable the workaround in older
1224 encp->enc_bug26807_workaround = B_FALSE;
1225 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1226 encp->enc_bug26807_workaround = B_FALSE;
1231 /* Get sysclk frequency (in MHz). */
1232 if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
1236 * The timer quantum is 1536 sysclk cycles, documented for the
1237 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
1239 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
1240 if (encp->enc_bug35388_workaround) {
1241 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
1242 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
1244 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
1245 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
1248 /* Check capabilities of running datapath firmware */
1249 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1252 /* Alignment for receive packet DMA buffers */
1253 encp->enc_rx_buf_align_start = 1;
1254 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
1256 /* Alignment for WPTR updates */
1257 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1260 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1261 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1262 * resources (allocated to this PCIe function), which is zero until
1263 * after we have allocated VIs.
1265 encp->enc_evq_limit = 1024;
1266 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1267 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1269 encp->enc_buftbl_limit = 0xFFFFFFFF;
1271 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
1272 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
1273 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
1276 * Get the current privilege mask. Note that this may be modified
1277 * dynamically, so this value is informational only. DO NOT use
1278 * the privilege mask to check for sufficient privileges, as that
1279 * can result in time-of-check/time-of-use bugs.
1281 if ((rc = efx_mcdi_privilege_mask(enp, pf, vf, &mask)) != 0) {
1285 /* Fallback for old firmware without privilege mask support */
1286 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1287 /* Assume PF has admin privilege */
1288 mask = HUNT_LEGACY_PF_PRIVILEGE_MASK;
1290 /* VF is always unprivileged by default */
1291 mask = HUNT_LEGACY_VF_PRIVILEGE_MASK;
1295 encp->enc_privilege_mask = mask;
1297 /* Get interrupt vector limits */
1298 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1299 if (EFX_PCI_FUNCTION_IS_PF(encp))
1302 /* Ignore error (cannot query vector limits from a VF). */
1306 encp->enc_intr_vec_base = base;
1307 encp->enc_intr_limit = nvec;
1310 * Maximum number of bytes into the frame the TCP header can start for
1311 * firmware assisted TSO to work.
1313 encp->enc_tx_tso_tcp_header_offset_limit = 208;
1318 EFSYS_PROBE(fail14);
1320 EFSYS_PROBE(fail13);
1322 EFSYS_PROBE(fail12);
1324 EFSYS_PROBE(fail11);
1326 EFSYS_PROBE(fail10);
1344 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1350 __checkReturn efx_rc_t
1352 __in efx_nic_t *enp)
1354 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1355 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1358 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1359 enp->en_family == EFX_FAMILY_MEDFORD);
1361 /* Read and clear any assertion state */
1362 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1365 /* Exit the assertion handler */
1366 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1370 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1373 if ((rc = hunt_board_cfg(enp)) != 0)
1378 * Set default driver config limits (based on board config).
1380 * FIXME: For now allocate a fixed number of VIs which is likely to be
1381 * sufficient and small enough to allow multiple functions on the same
1384 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1385 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1387 /* The client driver must configure and enable PIO buffer support */
1388 edcp->edc_max_piobuf_count = 0;
1389 edcp->edc_pio_alloc_size = 0;
1391 #if EFSYS_OPT_MAC_STATS
1392 /* Wipe the MAC statistics */
1393 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1397 #if EFSYS_OPT_LOOPBACK
1398 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1402 #if EFSYS_OPT_MON_STATS
1403 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1404 /* Unprivileged functions do not have access to sensors */
1410 encp->enc_features = enp->en_features;
1414 #if EFSYS_OPT_MON_STATS
1418 #if EFSYS_OPT_LOOPBACK
1422 #if EFSYS_OPT_MAC_STATS
1433 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1438 __checkReturn efx_rc_t
1439 ef10_nic_set_drv_limits(
1440 __inout efx_nic_t *enp,
1441 __in efx_drv_limits_t *edlp)
1443 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1444 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1445 uint32_t min_evq_count, max_evq_count;
1446 uint32_t min_rxq_count, max_rxq_count;
1447 uint32_t min_txq_count, max_txq_count;
1455 /* Get minimum required and maximum usable VI limits */
1456 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1457 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1458 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1460 edcp->edc_min_vi_count =
1461 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1463 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1464 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1465 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1467 edcp->edc_max_vi_count =
1468 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1471 * Check limits for sub-allocated piobuf blocks.
1472 * PIO is optional, so don't fail if the limits are incorrect.
1474 if ((encp->enc_piobuf_size == 0) ||
1475 (encp->enc_piobuf_limit == 0) ||
1476 (edlp->edl_min_pio_alloc_size == 0) ||
1477 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1479 edcp->edc_max_piobuf_count = 0;
1480 edcp->edc_pio_alloc_size = 0;
1482 uint32_t blk_size, blk_count, blks_per_piobuf;
1485 MAX(edlp->edl_min_pio_alloc_size,
1486 encp->enc_piobuf_min_alloc_size);
1488 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1489 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1491 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1493 /* A zero max pio alloc count means unlimited */
1494 if ((edlp->edl_max_pio_alloc_count > 0) &&
1495 (edlp->edl_max_pio_alloc_count < blk_count)) {
1496 blk_count = edlp->edl_max_pio_alloc_count;
1499 edcp->edc_pio_alloc_size = blk_size;
1500 edcp->edc_max_piobuf_count =
1501 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1507 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1513 __checkReturn efx_rc_t
1515 __in efx_nic_t *enp)
1518 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1519 MC_CMD_ENTITY_RESET_OUT_LEN)];
1522 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1523 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1525 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1528 (void) memset(payload, 0, sizeof (payload));
1529 req.emr_cmd = MC_CMD_ENTITY_RESET;
1530 req.emr_in_buf = payload;
1531 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1532 req.emr_out_buf = payload;
1533 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1535 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1536 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1538 efx_mcdi_execute(enp, &req);
1540 if (req.emr_rc != 0) {
1545 /* Clear RX/TX DMA queue errors */
1546 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1555 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1560 __checkReturn efx_rc_t
1562 __in efx_nic_t *enp)
1564 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1565 uint32_t min_vi_count, max_vi_count;
1566 uint32_t vi_count, vi_base, vi_shift;
1572 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1573 enp->en_family == EFX_FAMILY_MEDFORD);
1575 /* Enable reporting of some events (e.g. link change) */
1576 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1579 /* Allocate (optional) on-chip PIO buffers */
1580 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1583 * For best performance, PIO writes should use a write-combined
1584 * (WC) memory mapping. Using a separate WC mapping for the PIO
1585 * aperture of each VI would be a burden to drivers (and not
1586 * possible if the host page size is >4Kbyte).
1588 * To avoid this we use a single uncached (UC) mapping for VI
1589 * register access, and a single WC mapping for extra VIs used
1592 * Each piobuf must be linked to a VI in the WC mapping, and to
1593 * each VI that is using a sub-allocated block from the piobuf.
1595 min_vi_count = edcp->edc_min_vi_count;
1597 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1599 /* Ensure that the previously attached driver's VIs are freed */
1600 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1604 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1605 * fails then retrying the request for fewer VI resources may succeed.
1608 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1609 &vi_base, &vi_count, &vi_shift)) != 0)
1612 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1614 if (vi_count < min_vi_count) {
1619 enp->en_arch.ef10.ena_vi_base = vi_base;
1620 enp->en_arch.ef10.ena_vi_count = vi_count;
1621 enp->en_arch.ef10.ena_vi_shift = vi_shift;
1623 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1624 /* Not enough extra VIs to map piobufs */
1625 ef10_nic_free_piobufs(enp);
1628 enp->en_arch.ef10.ena_pio_write_vi_base =
1629 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1631 /* Save UC memory mapping details */
1632 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1633 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1634 enp->en_arch.ef10.ena_uc_mem_map_size =
1635 (ER_DZ_TX_PIOBUF_STEP *
1636 enp->en_arch.ef10.ena_pio_write_vi_base);
1638 enp->en_arch.ef10.ena_uc_mem_map_size =
1639 (ER_DZ_TX_PIOBUF_STEP *
1640 enp->en_arch.ef10.ena_vi_count);
1643 /* Save WC memory mapping details */
1644 enp->en_arch.ef10.ena_wc_mem_map_offset =
1645 enp->en_arch.ef10.ena_uc_mem_map_offset +
1646 enp->en_arch.ef10.ena_uc_mem_map_size;
1648 enp->en_arch.ef10.ena_wc_mem_map_size =
1649 (ER_DZ_TX_PIOBUF_STEP *
1650 enp->en_arch.ef10.ena_piobuf_count);
1652 /* Link piobufs to extra VIs in WC mapping */
1653 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1654 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1655 rc = efx_mcdi_link_piobuf(enp,
1656 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1657 enp->en_arch.ef10.ena_piobuf_handle[i]);
1664 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1666 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1667 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1668 * retry the request several times after waiting a while. The wait time
1669 * between retries starts small (10ms) and exponentially increases.
1670 * Total wait time is a little over two seconds. Retry logic in the
1671 * client driver may mean this whole loop is repeated if it continues to
1676 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1677 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1680 * Do not retry alloc for PF, or for other errors on
1686 /* VF startup before PF is ready. Retry allocation. */
1688 /* Too many attempts */
1692 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1693 EFSYS_SLEEP(delay_us);
1695 if (delay_us < 500000)
1699 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1700 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1715 ef10_nic_free_piobufs(enp);
1718 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1723 __checkReturn efx_rc_t
1724 ef10_nic_get_vi_pool(
1725 __in efx_nic_t *enp,
1726 __out uint32_t *vi_countp)
1728 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1729 enp->en_family == EFX_FAMILY_MEDFORD);
1732 * Report VIs that the client driver can use.
1733 * Do not include VIs used for PIO buffer writes.
1735 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1740 __checkReturn efx_rc_t
1741 ef10_nic_get_bar_region(
1742 __in efx_nic_t *enp,
1743 __in efx_nic_region_t region,
1744 __out uint32_t *offsetp,
1745 __out size_t *sizep)
1749 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1750 enp->en_family == EFX_FAMILY_MEDFORD);
1753 * TODO: Specify host memory mapping alignment and granularity
1754 * in efx_drv_limits_t so that they can be taken into account
1755 * when allocating extra VIs for PIO writes.
1759 /* UC mapped memory BAR region for VI registers */
1760 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1761 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1764 case EFX_REGION_PIO_WRITE_VI:
1765 /* WC mapped memory BAR region for piobuf writes */
1766 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1767 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1778 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1785 __in efx_nic_t *enp)
1790 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1791 enp->en_vport_id = 0;
1793 /* Unlink piobufs from extra VIs in WC mapping */
1794 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1795 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1796 rc = efx_mcdi_unlink_piobuf(enp,
1797 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1803 ef10_nic_free_piobufs(enp);
1805 (void) efx_mcdi_free_vis(enp);
1806 enp->en_arch.ef10.ena_vi_count = 0;
1811 __in efx_nic_t *enp)
1813 #if EFSYS_OPT_MON_STATS
1814 mcdi_mon_cfg_free(enp);
1815 #endif /* EFSYS_OPT_MON_STATS */
1816 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1821 __checkReturn efx_rc_t
1822 ef10_nic_register_test(
1823 __in efx_nic_t *enp)
1828 _NOTE(ARGUNUSED(enp))
1838 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1843 #endif /* EFSYS_OPT_DIAG */
1847 #endif /* EFSYS_OPT_HUNTINGTON */