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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_MCDI
40 #if EFSYS_OPT_HUNTINGTON
42 #include "ef10_tlv_layout.h"
44 static __checkReturn efx_rc_t
45 hunt_nic_get_required_pcie_bandwidth(
47 __out uint32_t *bandwidth_mbpsp)
50 uint32_t max_port_mode;
55 * On Huntington, the firmware may not give us the current port mode, so
56 * we need to go by the set of available port modes and assume the most
57 * capable mode is in use.
60 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
61 /* No port mode info available */
66 if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
68 * This needs the full PCIe bandwidth (and could use
69 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
71 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
72 EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
75 if (port_modes & (1 << TLV_PORT_MODE_40G)) {
76 max_port_mode = TLV_PORT_MODE_40G;
77 } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
78 max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
80 /* Assume two 10G ports */
81 max_port_mode = TLV_PORT_MODE_10G_10G;
84 if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
90 *bandwidth_mbpsp = bandwidth;
97 EFSYS_PROBE1(fail1, efx_rc_t, rc);
102 __checkReturn efx_rc_t
106 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
107 efx_port_t *epp = &(enp->en_port);
109 uint32_t sysclk, dpcpu_clk;
114 * Enable firmware workarounds for hardware errata.
115 * Expected responses are:
117 * Success: workaround enabled or disabled as requested.
118 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
119 * Firmware does not support the MC_CMD_WORKAROUND request.
120 * (assume that the workaround is not supported).
121 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
122 * Firmware does not support the requested workaround.
123 * - MC_CMD_ERR_EPERM (reported as EACCES):
124 * Unprivileged function cannot enable/disable workarounds.
126 * See efx_mcdi_request_errcode() for MCDI error translations.
130 * If the bug35388 workaround is enabled, then use an indirect access
131 * method to avoid unsafe EVQ writes.
133 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
135 if ((rc == 0) || (rc == EACCES))
136 encp->enc_bug35388_workaround = B_TRUE;
137 else if ((rc == ENOTSUP) || (rc == ENOENT))
138 encp->enc_bug35388_workaround = B_FALSE;
143 * If the bug41750 workaround is enabled, then do not test interrupts,
144 * as the test will fail (seen with Greenport controllers).
146 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
149 encp->enc_bug41750_workaround = B_TRUE;
150 } else if (rc == EACCES) {
151 /* Assume a controller with 40G ports needs the workaround. */
152 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
153 encp->enc_bug41750_workaround = B_TRUE;
155 encp->enc_bug41750_workaround = B_FALSE;
156 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
157 encp->enc_bug41750_workaround = B_FALSE;
161 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
162 /* Interrupt testing does not work for VFs. See bug50084. */
163 encp->enc_bug41750_workaround = B_TRUE;
167 * If the bug26807 workaround is enabled, then firmware has enabled
168 * support for chained multicast filters. Firmware will reset (FLR)
169 * functions which have filters in the hardware filter table when the
170 * workaround is enabled/disabled.
172 * We must recheck if the workaround is enabled after inserting the
173 * first hardware filter, in case it has been changed since this check.
175 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
178 encp->enc_bug26807_workaround = B_TRUE;
179 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
181 * Other functions had installed filters before the
182 * workaround was enabled, and they have been reset
185 EFSYS_PROBE(bug26807_workaround_flr_done);
186 /* FIXME: bump MC warm boot count ? */
188 } else if (rc == EACCES) {
190 * Unprivileged functions cannot enable the workaround in older
193 encp->enc_bug26807_workaround = B_FALSE;
194 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
195 encp->enc_bug26807_workaround = B_FALSE;
200 /* Get clock frequencies (in MHz). */
201 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
205 * The Huntington timer quantum is 1536 sysclk cycles, documented for
206 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
208 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
209 if (encp->enc_bug35388_workaround) {
210 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
211 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
213 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
214 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
217 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
219 /* Alignment for receive packet DMA buffers */
220 encp->enc_rx_buf_align_start = 1;
221 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
224 * The workaround for bug35388 uses the top bit of transmit queue
225 * descriptor writes, preventing the use of 4096 descriptor TXQs.
227 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
229 EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
230 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
231 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
232 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
234 if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
236 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
238 /* All Huntington devices have a PCIe Gen3, 8 lane connector */
239 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
252 EFSYS_PROBE1(fail1, efx_rc_t, rc);
258 #endif /* EFSYS_OPT_HUNTINGTON */