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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_MCDI
40 #if EFSYS_OPT_HUNTINGTON
42 #include "ef10_tlv_layout.h"
44 static __checkReturn efx_rc_t
45 hunt_nic_get_required_pcie_bandwidth(
47 __out uint32_t *bandwidth_mbpsp)
50 uint32_t max_port_mode;
55 * On Huntington, the firmware may not give us the current port mode, so
56 * we need to go by the set of available port modes and assume the most
57 * capable mode is in use.
60 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
61 /* No port mode info available */
66 if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
68 * This needs the full PCIe bandwidth (and could use
69 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
71 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
72 EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
75 if (port_modes & (1 << TLV_PORT_MODE_40G)) {
76 max_port_mode = TLV_PORT_MODE_40G;
77 } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
78 max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
80 /* Assume two 10G ports */
81 max_port_mode = TLV_PORT_MODE_10G_10G;
84 if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
90 *bandwidth_mbpsp = bandwidth;
97 EFSYS_PROBE1(fail1, efx_rc_t, rc);
102 __checkReturn efx_rc_t
106 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
107 uint32_t board_type = 0;
108 ef10_link_state_t els;
109 efx_port_t *epp = &(enp->en_port);
112 uint32_t sysclk, dpcpu_clk;
117 /* Huntington has a fixed 8Kbyte VI window size */
118 EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP == 8192);
119 EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP == 8192);
120 EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP == 8192);
121 EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP == 8192);
122 EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP == 8192);
124 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
125 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
127 /* Board configuration */
128 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
130 /* Unprivileged functions may not be able to read board cfg */
137 encp->enc_board_type = board_type;
138 encp->enc_clk_mult = 1; /* not used for Huntington */
140 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
141 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
144 /* Obtain the default PHY advertised capabilities */
145 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
147 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
148 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
151 * Enable firmware workarounds for hardware errata.
152 * Expected responses are:
154 * Success: workaround enabled or disabled as requested.
155 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
156 * Firmware does not support the MC_CMD_WORKAROUND request.
157 * (assume that the workaround is not supported).
158 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
159 * Firmware does not support the requested workaround.
160 * - MC_CMD_ERR_EPERM (reported as EACCES):
161 * Unprivileged function cannot enable/disable workarounds.
163 * See efx_mcdi_request_errcode() for MCDI error translations.
167 * If the bug35388 workaround is enabled, then use an indirect access
168 * method to avoid unsafe EVQ writes.
170 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
172 if ((rc == 0) || (rc == EACCES))
173 encp->enc_bug35388_workaround = B_TRUE;
174 else if ((rc == ENOTSUP) || (rc == ENOENT))
175 encp->enc_bug35388_workaround = B_FALSE;
180 * If the bug41750 workaround is enabled, then do not test interrupts,
181 * as the test will fail (seen with Greenport controllers).
183 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
186 encp->enc_bug41750_workaround = B_TRUE;
187 } else if (rc == EACCES) {
188 /* Assume a controller with 40G ports needs the workaround. */
189 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
190 encp->enc_bug41750_workaround = B_TRUE;
192 encp->enc_bug41750_workaround = B_FALSE;
193 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
194 encp->enc_bug41750_workaround = B_FALSE;
198 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
199 /* Interrupt testing does not work for VFs. See bug50084. */
200 encp->enc_bug41750_workaround = B_TRUE;
204 * If the bug26807 workaround is enabled, then firmware has enabled
205 * support for chained multicast filters. Firmware will reset (FLR)
206 * functions which have filters in the hardware filter table when the
207 * workaround is enabled/disabled.
209 * We must recheck if the workaround is enabled after inserting the
210 * first hardware filter, in case it has been changed since this check.
212 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
215 encp->enc_bug26807_workaround = B_TRUE;
216 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
218 * Other functions had installed filters before the
219 * workaround was enabled, and they have been reset
222 EFSYS_PROBE(bug26807_workaround_flr_done);
223 /* FIXME: bump MC warm boot count ? */
225 } else if (rc == EACCES) {
227 * Unprivileged functions cannot enable the workaround in older
230 encp->enc_bug26807_workaround = B_FALSE;
231 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
232 encp->enc_bug26807_workaround = B_FALSE;
237 /* Get clock frequencies (in MHz). */
238 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
242 * The Huntington timer quantum is 1536 sysclk cycles, documented for
243 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
245 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
246 if (encp->enc_bug35388_workaround) {
247 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
248 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
250 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
251 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
254 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
256 /* Check capabilities of running datapath firmware */
257 if ((rc = ef10_get_datapath_caps(enp)) != 0)
260 /* Alignment for receive packet DMA buffers */
261 encp->enc_rx_buf_align_start = 1;
262 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
264 /* Alignment for WPTR updates */
265 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
268 * Maximum number of exclusive RSS contexts which can be allocated. The
269 * hardware supports 64, but 6 are reserved for shared contexts. They
270 * are a global resource so not all may be available.
272 encp->enc_rx_scale_max_exclusive_contexts = 58;
274 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
275 /* No boundary crossing limits */
276 encp->enc_tx_dma_desc_boundary = 0;
279 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
280 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
281 * resources (allocated to this PCIe function), which is zero until
282 * after we have allocated VIs.
284 encp->enc_evq_limit = 1024;
285 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
286 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
289 * The workaround for bug35388 uses the top bit of transmit queue
290 * descriptor writes, preventing the use of 4096 descriptor TXQs.
292 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
294 encp->enc_buftbl_limit = 0xFFFFFFFF;
296 EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
297 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
298 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
299 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
302 * Get the current privilege mask. Note that this may be modified
303 * dynamically, so this value is informational only. DO NOT use
304 * the privilege mask to check for sufficient privileges, as that
305 * can result in time-of-check/time-of-use bugs.
307 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
309 encp->enc_privilege_mask = mask;
311 /* Get interrupt vector limits */
312 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
313 if (EFX_PCI_FUNCTION_IS_PF(encp))
316 /* Ignore error (cannot query vector limits from a VF). */
320 encp->enc_intr_vec_base = base;
321 encp->enc_intr_limit = nvec;
324 * Maximum number of bytes into the frame the TCP header can start for
325 * firmware assisted TSO to work.
327 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
329 if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
331 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
333 /* All Huntington devices have a PCIe Gen3, 8 lane connector */
334 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
359 EFSYS_PROBE1(fail1, efx_rc_t, rc);
365 #endif /* EFSYS_OPT_HUNTINGTON */