2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015-2018 Solarflare Communications Inc.
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33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
40 #if EFSYS_OPT_MEDFORD2
42 static __checkReturn efx_rc_t
43 medford2_nic_get_required_pcie_bandwidth(
45 __out uint32_t *bandwidth_mbpsp)
50 /* FIXME: support new Medford2 dynamic port modes */
52 if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
56 *bandwidth_mbpsp = bandwidth;
61 EFSYS_PROBE1(fail1, efx_rc_t, rc);
66 __checkReturn efx_rc_t
70 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
71 uint32_t sysclk, dpcpu_clk;
77 * Enable firmware workarounds for hardware errata.
78 * Expected responses are:
80 * Success: workaround enabled or disabled as requested.
81 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
82 * Firmware does not support the MC_CMD_WORKAROUND request.
83 * (assume that the workaround is not supported).
84 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
85 * Firmware does not support the requested workaround.
86 * - MC_CMD_ERR_EPERM (reported as EACCES):
87 * Unprivileged function cannot enable/disable workarounds.
89 * See efx_mcdi_request_errcode() for MCDI error translations.
93 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
95 * Interrupt testing does not work for VFs on Medford2.
96 * See bug50084 and bug71432 comment 21.
98 encp->enc_bug41750_workaround = B_TRUE;
101 /* Chained multicast is always enabled on Medford2 */
102 encp->enc_bug26807_workaround = B_TRUE;
105 * If the bug61265 workaround is enabled, then interrupt holdoff timers
106 * cannot be controlled by timer table writes, so MCDI must be used
107 * (timer table writes can still be used for wakeup timers).
109 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
111 if ((rc == 0) || (rc == EACCES))
112 encp->enc_bug61265_workaround = B_TRUE;
113 else if ((rc == ENOTSUP) || (rc == ENOENT))
114 encp->enc_bug61265_workaround = B_FALSE;
118 /* Checksums for TSO sends should always be correct on Medford2. */
119 encp->enc_bug61297_workaround = B_FALSE;
121 /* Get clock frequencies (in MHz). */
122 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
126 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
127 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
129 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
130 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
131 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
133 /* Alignment for receive packet DMA buffers */
134 encp->enc_rx_buf_align_start = 1;
136 /* Get the RX DMA end padding alignment configuration */
137 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
141 /* Assume largest tail padding size supported by hardware */
144 encp->enc_rx_buf_align_end = end_padding;
147 * The maximum supported transmit queue size is 2048. TXQs with 4096
148 * descriptors are not supported as the top bit is used for vfifo
151 encp->enc_txq_max_ndescs = 2048;
153 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
154 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
155 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
156 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
159 * Medford2 stores a single global copy of VPD, not per-PF as on
162 encp->enc_vpd_is_global = B_TRUE;
164 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
167 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
168 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
179 EFSYS_PROBE1(fail1, efx_rc_t, rc);
184 #endif /* EFSYS_OPT_MEDFORD2 */