2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015-2018 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * The views and conclusions contained in the software and documentation are
29 * those of the authors and should not be interpreted as representing official
30 * policies, either expressed or implied, of the FreeBSD Project.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
39 #if EFSYS_OPT_MEDFORD2
41 static __checkReturn efx_rc_t
42 medford2_nic_get_required_pcie_bandwidth(
44 __out uint32_t *bandwidth_mbpsp)
49 /* FIXME: support new Medford2 dynamic port modes */
51 if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
55 *bandwidth_mbpsp = bandwidth;
60 EFSYS_PROBE1(fail1, efx_rc_t, rc);
65 __checkReturn efx_rc_t
69 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
70 uint32_t sysclk, dpcpu_clk;
76 * Enable firmware workarounds for hardware errata.
77 * Expected responses are:
79 * Success: workaround enabled or disabled as requested.
80 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
81 * Firmware does not support the MC_CMD_WORKAROUND request.
82 * (assume that the workaround is not supported).
83 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
84 * Firmware does not support the requested workaround.
85 * - MC_CMD_ERR_EPERM (reported as EACCES):
86 * Unprivileged function cannot enable/disable workarounds.
88 * See efx_mcdi_request_errcode() for MCDI error translations.
91 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
93 * Interrupt testing does not work for VFs on Medford2.
94 * See bug50084 and bug71432 comment 21.
96 encp->enc_bug41750_workaround = B_TRUE;
99 /* Chained multicast is always enabled on Medford2 */
100 encp->enc_bug26807_workaround = B_TRUE;
103 * If the bug61265 workaround is enabled, then interrupt holdoff timers
104 * cannot be controlled by timer table writes, so MCDI must be used
105 * (timer table writes can still be used for wakeup timers).
107 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
109 if ((rc == 0) || (rc == EACCES))
110 encp->enc_bug61265_workaround = B_TRUE;
111 else if ((rc == ENOTSUP) || (rc == ENOENT))
112 encp->enc_bug61265_workaround = B_FALSE;
116 /* Checksums for TSO sends should always be correct on Medford2. */
117 encp->enc_bug61297_workaround = B_FALSE;
119 /* Get clock frequencies (in MHz). */
120 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
124 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
125 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
127 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
128 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
129 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
131 /* Alignment for receive packet DMA buffers */
132 encp->enc_rx_buf_align_start = 1;
134 /* Get the RX DMA end padding alignment configuration */
135 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
139 /* Assume largest tail padding size supported by hardware */
142 encp->enc_rx_buf_align_end = end_padding;
145 * The maximum supported transmit queue size is 2048. TXQs with 4096
146 * descriptors are not supported as the top bit is used for vfifo
149 encp->enc_txq_max_ndescs = 2048;
151 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
152 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
153 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
154 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
157 * Medford2 stores a single global copy of VPD, not per-PF as on
160 encp->enc_vpd_is_global = B_TRUE;
162 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
165 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
166 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
177 EFSYS_PROBE1(fail1, efx_rc_t, rc);
182 #endif /* EFSYS_OPT_MEDFORD2 */