2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
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11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
40 static __checkReturn efx_rc_t
41 efx_mcdi_get_rxdp_config(
43 __out uint32_t *end_paddingp)
46 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
47 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
51 memset(payload, 0, sizeof (payload));
52 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
53 req.emr_in_buf = payload;
54 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
55 req.emr_out_buf = payload;
56 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
58 efx_mcdi_execute(enp, &req);
59 if (req.emr_rc != 0) {
64 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
65 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
66 /* RX DMA end padding is disabled */
69 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
70 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
71 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
74 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
77 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
86 *end_paddingp = end_padding;
93 EFSYS_PROBE1(fail1, efx_rc_t, rc);
98 static __checkReturn efx_rc_t
99 medford_nic_get_required_pcie_bandwidth(
101 __out uint32_t *bandwidth_mbpsp)
104 uint32_t current_mode;
108 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
109 ¤t_mode)) != 0) {
110 /* No port mode info available. */
115 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
120 *bandwidth_mbpsp = bandwidth;
125 EFSYS_PROBE1(fail1, efx_rc_t, rc);
130 __checkReturn efx_rc_t
134 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
135 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
136 uint8_t mac_addr[6] = { 0 };
137 uint32_t board_type = 0;
138 ef10_link_state_t els;
139 efx_port_t *epp = &(enp->en_port);
144 uint32_t sysclk, dpcpu_clk;
146 uint32_t end_padding;
151 * FIXME: Likely to be incomplete and incorrect.
152 * Parts of this should be shared with Huntington.
155 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
159 * NOTE: The MCDI protocol numbers ports from zero.
160 * The common code MCDI interface numbers ports from one.
162 emip->emi_port = port + 1;
164 if ((rc = ef10_external_port_mapping(enp, port,
165 &encp->enc_external_port)) != 0)
169 * Get PCIe function number from firmware (used for
170 * per-function privilege and dynamic config info).
171 * - PCIe PF: pf = PF number, vf = 0xffff.
172 * - PCIe VF: pf = parent PF, vf = VF number.
174 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
180 /* MAC address for this function */
181 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
182 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
183 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
185 * Disable static config checking for Medford NICs, ONLY
186 * for manufacturing test and setup at the factory, to
187 * allow the static config to be installed.
189 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
190 if ((rc == 0) && (mac_addr[0] & 0x02)) {
192 * If the static config does not include a global MAC
193 * address pool then the board may return a locally
194 * administered MAC address (this should only happen on
195 * incorrectly programmed boards).
199 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
201 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
206 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
208 /* Board configuration */
209 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
211 /* Unprivileged functions may not be able to read board cfg */
218 encp->enc_board_type = board_type;
219 encp->enc_clk_mult = 1; /* not used for Medford */
221 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
222 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
225 /* Obtain the default PHY advertised capabilities */
226 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
228 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
229 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
232 * Enable firmware workarounds for hardware errata.
233 * Expected responses are:
235 * Success: workaround enabled or disabled as requested.
236 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
237 * Firmware does not support the MC_CMD_WORKAROUND request.
238 * (assume that the workaround is not supported).
239 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
240 * Firmware does not support the requested workaround.
241 * - MC_CMD_ERR_EPERM (reported as EACCES):
242 * Unprivileged function cannot enable/disable workarounds.
244 * See efx_mcdi_request_errcode() for MCDI error translations.
248 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
250 * Interrupt testing does not work for VFs. See bug50084.
251 * FIXME: Does this still apply to Medford?
253 encp->enc_bug41750_workaround = B_TRUE;
256 /* Chained multicast is always enabled on Medford */
257 encp->enc_bug26807_workaround = B_TRUE;
260 * If the bug61265 workaround is enabled, then interrupt holdoff timers
261 * cannot be controlled by timer table writes, so MCDI must be used
262 * (timer table writes can still be used for wakeup timers).
264 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
266 if ((rc == 0) || (rc == EACCES))
267 encp->enc_bug61265_workaround = B_TRUE;
268 else if ((rc == ENOTSUP) || (rc == ENOENT))
269 encp->enc_bug61265_workaround = B_FALSE;
273 /* Get clock frequencies (in MHz). */
274 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
278 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
279 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
281 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
282 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
283 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
285 /* Check capabilities of running datapath firmware */
286 if ((rc = ef10_get_datapath_caps(enp)) != 0)
289 /* Alignment for receive packet DMA buffers */
290 encp->enc_rx_buf_align_start = 1;
292 /* Get the RX DMA end padding alignment configuration */
293 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
297 /* Assume largest tail padding size supported by hardware */
300 encp->enc_rx_buf_align_end = end_padding;
302 /* Alignment for WPTR updates */
303 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
306 * Maximum number of exclusive RSS contexts which can be allocated. The
307 * hardware supports 64, but 6 are reserved for shared contexts. They
308 * are a global resource so not all may be available.
310 encp->enc_rx_scale_max_exclusive_contexts = 58;
312 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
313 /* No boundary crossing limits */
314 encp->enc_tx_dma_desc_boundary = 0;
317 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
318 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
319 * resources (allocated to this PCIe function), which is zero until
320 * after we have allocated VIs.
322 encp->enc_evq_limit = 1024;
323 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
324 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
327 * The maximum supported transmit queue size is 2048. TXQs with 4096
328 * descriptors are not supported as the top bit is used for vfifo
331 encp->enc_txq_max_ndescs = 2048;
333 encp->enc_buftbl_limit = 0xFFFFFFFF;
335 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
336 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
337 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
340 * Get the current privilege mask. Note that this may be modified
341 * dynamically, so this value is informational only. DO NOT use
342 * the privilege mask to check for sufficient privileges, as that
343 * can result in time-of-check/time-of-use bugs.
345 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
347 encp->enc_privilege_mask = mask;
349 /* Get interrupt vector limits */
350 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
351 if (EFX_PCI_FUNCTION_IS_PF(encp))
354 /* Ignore error (cannot query vector limits from a VF). */
358 encp->enc_intr_vec_base = base;
359 encp->enc_intr_limit = nvec;
362 * Maximum number of bytes into the frame the TCP header can start for
363 * firmware assisted TSO to work.
365 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
368 * Medford stores a single global copy of VPD, not per-PF as on
371 encp->enc_vpd_is_global = B_TRUE;
373 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
376 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
377 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
408 EFSYS_PROBE1(fail1, efx_rc_t, rc);
413 #endif /* EFSYS_OPT_MEDFORD */