2 * Copyright (c) 2015 Solarflare Communications Inc.
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6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
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11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
40 #include "ef10_tlv_layout.h"
42 __checkReturn efx_rc_t
46 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
47 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
48 uint8_t mac_addr[6] = { 0 };
49 uint32_t board_type = 0;
50 ef10_link_state_t els;
51 efx_port_t *epp = &(enp->en_port);
62 * FIXME: Likely to be incomplete and incorrect.
63 * Parts of this should be shared with Huntington.
66 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
70 * NOTE: The MCDI protocol numbers ports from zero.
71 * The common code MCDI interface numbers ports from one.
73 emip->emi_port = port + 1;
75 if ((rc = ef10_external_port_mapping(enp, port,
76 &encp->enc_external_port)) != 0)
80 * Get PCIe function number from firmware (used for
81 * per-function privilege and dynamic config info).
82 * - PCIe PF: pf = PF number, vf = 0xffff.
83 * - PCIe VF: pf = parent PF, vf = VF number.
85 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
91 /* MAC address for this function */
92 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
93 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
94 if ((rc == 0) && (mac_addr[0] & 0x02)) {
96 * If the static config does not include a global MAC
97 * address pool then the board may return a locally
98 * administered MAC address (this should only happen on
99 * incorrectly programmed boards).
104 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
109 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
111 /* Board configuration */
112 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
114 /* Unprivileged functions may not be able to read board cfg */
121 encp->enc_board_type = board_type;
122 encp->enc_clk_mult = 1; /* not used for Medford */
124 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
125 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
128 /* Obtain the default PHY advertised capabilities */
129 if ((rc = hunt_phy_get_link(enp, &els)) != 0)
131 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
132 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
134 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
136 * Interrupt testing does not work for VFs. See bug50084.
137 * FIXME: Does this still apply to Medford?
139 encp->enc_bug41750_workaround = B_TRUE;
142 /* Chained multicast is always enabled on Medford */
143 encp->enc_bug26807_workaround = B_TRUE;
145 /* Get sysclk frequency (in MHz). */
146 if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
150 * The timer quantum is 1536 sysclk cycles, documented for the
151 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
153 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
154 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
155 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
157 /* Check capabilities of running datapath firmware */
158 if ((rc = ef10_get_datapath_caps(enp)) != 0)
161 /* Alignment for receive packet DMA buffers */
162 encp->enc_rx_buf_align_start = 1;
164 /* FIXME: RX DMA end padding is configurable on Medford */
165 encp->enc_rx_buf_align_end = 64;
167 /* Alignment for WPTR updates */
168 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
171 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
172 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
173 * resources (allocated to this PCIe function), which is zero until
174 * after we have allocated VIs.
176 encp->enc_evq_limit = 1024;
177 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
178 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
180 encp->enc_buftbl_limit = 0xFFFFFFFF;
182 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
183 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
184 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
187 * Get the current privilege mask. Note that this may be modified
188 * dynamically, so this value is informational only. DO NOT use
189 * the privilege mask to check for sufficient privileges, as that
190 * can result in time-of-check/time-of-use bugs.
192 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
194 encp->enc_privilege_mask = mask;
196 /* Get interrupt vector limits */
197 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
198 if (EFX_PCI_FUNCTION_IS_PF(encp))
201 /* Ignore error (cannot query vector limits from a VF). */
205 encp->enc_intr_vec_base = base;
206 encp->enc_intr_limit = nvec;
209 * Maximum number of bytes into the frame the TCP header can start for
210 * firmware assisted TSO to work.
212 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
215 * Medford stores a single global copy of VPD, not per-PF as on
218 encp->enc_vpd_is_global = B_TRUE;
243 EFSYS_PROBE1(fail1, efx_rc_t, rc);
248 #endif /* EFSYS_OPT_MEDFORD */