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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
39 static __checkReturn efx_rc_t
40 medford_nic_get_required_pcie_bandwidth(
42 __out uint32_t *bandwidth_mbpsp)
47 if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
51 *bandwidth_mbpsp = bandwidth;
56 EFSYS_PROBE1(fail1, efx_rc_t, rc);
61 __checkReturn efx_rc_t
65 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
66 uint32_t sysclk, dpcpu_clk;
72 * Enable firmware workarounds for hardware errata.
73 * Expected responses are:
75 * Success: workaround enabled or disabled as requested.
76 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
77 * Firmware does not support the MC_CMD_WORKAROUND request.
78 * (assume that the workaround is not supported).
79 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
80 * Firmware does not support the requested workaround.
81 * - MC_CMD_ERR_EPERM (reported as EACCES):
82 * Unprivileged function cannot enable/disable workarounds.
84 * See efx_mcdi_request_errcode() for MCDI error translations.
87 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
89 * Interrupt testing does not work for VFs. See bug50084 and
90 * bug71432 comment 21.
92 encp->enc_bug41750_workaround = B_TRUE;
95 /* Chained multicast is always enabled on Medford */
96 encp->enc_bug26807_workaround = B_TRUE;
99 * If the bug61265 workaround is enabled, then interrupt holdoff timers
100 * cannot be controlled by timer table writes, so MCDI must be used
101 * (timer table writes can still be used for wakeup timers).
103 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
105 if ((rc == 0) || (rc == EACCES))
106 encp->enc_bug61265_workaround = B_TRUE;
107 else if ((rc == ENOTSUP) || (rc == ENOENT))
108 encp->enc_bug61265_workaround = B_FALSE;
112 /* Checksums for TSO sends can be incorrect on Medford. */
113 encp->enc_bug61297_workaround = B_TRUE;
115 /* Get clock frequencies (in MHz). */
116 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
120 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
121 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
123 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
124 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
125 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
127 /* Alignment for receive packet DMA buffers */
128 encp->enc_rx_buf_align_start = 1;
130 /* Get the RX DMA end padding alignment configuration */
131 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
135 /* Assume largest tail padding size supported by hardware */
138 encp->enc_rx_buf_align_end = end_padding;
141 * The maximum supported transmit queue size is 2048. TXQs with 4096
142 * descriptors are not supported as the top bit is used for vfifo
145 encp->enc_txq_max_ndescs = 2048;
147 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
148 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
149 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
150 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
153 * Medford stores a single global copy of VPD, not per-PF as on
156 encp->enc_vpd_is_global = B_TRUE;
158 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
161 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
162 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
173 EFSYS_PROBE1(fail1, efx_rc_t, rc);
178 #endif /* EFSYS_OPT_MEDFORD */