2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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8 * modification, are permitted provided that the following conditions are met:
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35 #ifndef _SYS_SIENA_FLASH_H
36 #define _SYS_SIENA_FLASH_H
40 /* Fixed locations near the start of flash (which may be in the internal PHY
41 * firmware header) point to the boot header.
43 * - parsed by MC boot ROM and firmware
44 * - reserved (but not parsed) by PHY firmware
48 #define SIENA_MC_BOOT_PHY_FW_HDR_LEN (0x20)
50 #define SIENA_MC_BOOT_PTR_LOCATION (0x18) /* First thing we try to boot */
51 #define SIENA_MC_BOOT_ALT_PTR_LOCATION (0x1c) /* Alternative if that fails */
53 #define SIENA_MC_BOOT_HDR_LEN (0x200)
55 #define SIENA_MC_BOOT_MAGIC (0x51E4A001)
56 #define SIENA_MC_BOOT_VERSION (1)
59 /*Structures supporting an arbitrary number of binary blobs in the flash image
60 intended to house code and tables for the satellite cpus*/
61 /*thanks to random.org for:*/
62 #define BLOBS_HEADER_MAGIC (0xBDA3BBD4)
63 #define BLOB_HEADER_MAGIC (0xA1478A91)
65 typedef struct blobs_hdr_s { /* GENERATED BY scripts/genfwdef */
67 efx_dword_t no_of_blobs;
70 typedef struct blob_hdr_s { /* GENERATED BY scripts/genfwdef */
73 efx_dword_t build_variant;
79 #define BLOB_CPU_TYPE_TXDI_TEXT (0)
80 #define BLOB_CPU_TYPE_RXDI_TEXT (1)
81 #define BLOB_CPU_TYPE_TXDP_TEXT (2)
82 #define BLOB_CPU_TYPE_RXDP_TEXT (3)
83 #define BLOB_CPU_TYPE_RXHRSL_HR_LUT (4)
84 #define BLOB_CPU_TYPE_RXHRSL_HR_LUT_CFG (5)
85 #define BLOB_CPU_TYPE_TXHRSL_HR_LUT (6)
86 #define BLOB_CPU_TYPE_TXHRSL_HR_LUT_CFG (7)
87 #define BLOB_CPU_TYPE_RXHRSL_HR_PGM (8)
88 #define BLOB_CPU_TYPE_RXHRSL_SL_PGM (9)
89 #define BLOB_CPU_TYPE_TXHRSL_HR_PGM (10)
90 #define BLOB_CPU_TYPE_TXHRSL_SL_PGM (11)
91 #define BLOB_CPU_TYPE_RXDI_VTBL0 (12)
92 #define BLOB_CPU_TYPE_TXDI_VTBL0 (13)
93 #define BLOB_CPU_TYPE_RXDI_VTBL1 (14)
94 #define BLOB_CPU_TYPE_TXDI_VTBL1 (15)
95 #define BLOB_CPU_TYPE_DUMPSPEC (32)
96 #define BLOB_CPU_TYPE_MC_XIP (33)
98 #define BLOB_CPU_TYPE_INVALID (31)
101 * The upper four bits of the CPU type field specify the compression
102 * algorithm used for this blob.
104 #define BLOB_COMPRESSION_MASK (0xf0000000)
105 #define BLOB_CPU_TYPE_MASK (0x0fffffff)
107 #define BLOB_COMPRESSION_NONE (0x00000000) /* Stored as is */
108 #define BLOB_COMPRESSION_LZ (0x10000000) /* see lib/lzdecoder.c */
110 typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */
111 efx_dword_t magic; /* = SIENA_MC_BOOT_MAGIC */
112 efx_word_t hdr_version; /* this structure definition is version 1 */
113 efx_byte_t board_type;
114 efx_byte_t firmware_version_a;
115 efx_byte_t firmware_version_b;
116 efx_byte_t firmware_version_c;
117 efx_word_t checksum; /* of whole header area + firmware image */
118 efx_word_t firmware_version_d;
119 efx_byte_t mcfw_subtype;
120 efx_byte_t generation; /* Valid for medford, SBZ for earlier chips */
121 efx_dword_t firmware_text_offset; /* offset to firmware .text */
122 efx_dword_t firmware_text_size; /* length of firmware .text, in bytes */
123 efx_dword_t firmware_data_offset; /* offset to firmware .data */
124 efx_dword_t firmware_data_size; /* length of firmware .data, in bytes */
125 efx_byte_t spi_rate; /* SPI rate for reading image, 0 is BootROM default */
126 efx_byte_t spi_phase_adj; /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */
127 efx_word_t xpm_sector; /* The sector that contains the key, or 0xffff if unsigned (medford) SBZ (earlier) */
128 efx_dword_t reserved_c[7]; /* (set to 0) */
129 } siena_mc_boot_hdr_t;
131 #define SIENA_MC_BOOT_HDR_PADDING \
132 (SIENA_MC_BOOT_HDR_LEN - sizeof(siena_mc_boot_hdr_t))
134 #define SIENA_MC_STATIC_CONFIG_MAGIC (0xBDCF5555)
135 #define SIENA_MC_STATIC_CONFIG_VERSION (0)
137 typedef struct siena_mc_static_config_hdr_s { /* GENERATED BY scripts/genfwdef */
138 efx_dword_t magic; /* = SIENA_MC_STATIC_CONFIG_MAGIC */
139 efx_word_t length; /* of header area (i.e. not including VPD) */
141 efx_byte_t csum; /* over header area (i.e. not including VPD) */
142 efx_dword_t static_vpd_offset;
143 efx_dword_t static_vpd_length;
144 efx_dword_t capabilities;
145 efx_byte_t mac_addr_base[6];
146 efx_byte_t green_mode_cal; /* Green mode calibration result */
147 efx_byte_t green_mode_valid; /* Whether cal holds a valid value */
148 efx_word_t mac_addr_count;
149 efx_word_t mac_addr_stride;
150 efx_word_t calibrated_vref; /* Vref as measured during production */
151 efx_word_t adc_vref; /* Vref as read by ADC */
152 efx_dword_t reserved2[1]; /* (write as zero) */
153 efx_dword_t num_dbi_items;
156 efx_word_t byte_enables;
159 } siena_mc_static_config_hdr_t;
161 #define SIENA_MC_DYNAMIC_CONFIG_MAGIC (0xBDCFDDDD)
162 #define SIENA_MC_DYNAMIC_CONFIG_VERSION (0)
164 typedef struct siena_mc_fw_version_s { /* GENERATED BY scripts/genfwdef */
165 efx_dword_t fw_subtype;
166 efx_word_t version_w;
167 efx_word_t version_x;
168 efx_word_t version_y;
169 efx_word_t version_z;
170 } siena_mc_fw_version_t;
172 typedef struct siena_mc_dynamic_config_hdr_s { /* GENERATED BY scripts/genfwdef */
173 efx_dword_t magic; /* = SIENA_MC_DYNAMIC_CONFIG_MAGIC */
174 efx_word_t length; /* of header area (i.e. not including VPD) */
176 efx_byte_t csum; /* over header area (i.e. not including VPD) */
177 efx_dword_t dynamic_vpd_offset;
178 efx_dword_t dynamic_vpd_length;
179 efx_dword_t num_fw_version_items;
180 siena_mc_fw_version_t fw_version[];
181 } siena_mc_dynamic_config_hdr_t;
183 #define SIENA_MC_EXPROM_SINGLE_MAGIC (0xAA55) /* little-endian uint16_t */
185 #define SIENA_MC_EXPROM_COMBO_MAGIC (0xB0070102) /* little-endian uint32_t */
186 #define SIENA_MC_EXPROM_COMBO_V2_MAGIC (0xB0070103) /* little-endian uint32_t */
188 typedef struct siena_mc_combo_rom_hdr_s { /* GENERATED BY scripts/genfwdef */
189 efx_dword_t magic; /* = SIENA_MC_EXPROM_COMBO_MAGIC or SIENA_MC_EXPROM_COMBO_V2_MAGIC */
192 efx_dword_t len1; /* length of first image */
193 efx_dword_t len2; /* length of second image */
194 efx_dword_t off1; /* offset of first byte to edit to combine images */
195 efx_dword_t off2; /* offset of second byte to edit to combine images */
196 efx_word_t infoblk0_off;/* infoblk offset */
197 efx_word_t infoblk1_off;/* infoblk offset */
198 efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */
199 efx_byte_t reserved[7];/* (set to 0) */
202 efx_dword_t len1; /* length of first image */
203 efx_dword_t len2; /* length of second image */
204 efx_dword_t off1; /* offset of first byte to edit to combine images */
205 efx_dword_t off2; /* offset of second byte to edit to combine images */
206 efx_word_t infoblk_off;/* infoblk start offset */
207 efx_word_t infoblk_count;/* infoblk count */
208 efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */
209 efx_byte_t reserved[7];/* (set to 0) */
212 } siena_mc_combo_rom_hdr_t;
216 #endif /* _SYS_SIENA_FLASH_H */