2 * Copyright (c) 2009-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
39 __checkReturn efx_rc_t
42 __out efx_link_mode_t *link_modep)
44 efx_port_t *epp = &(enp->en_port);
45 siena_link_state_t sls;
48 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
51 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
52 epp->ep_fcntl = sls.sls_fcntl;
54 *link_modep = sls.sls_link_mode;
59 EFSYS_PROBE1(fail1, efx_rc_t, rc);
61 *link_modep = EFX_LINK_UNKNOWN;
66 __checkReturn efx_rc_t
69 __out boolean_t *mac_upp)
71 siena_link_state_t sls;
75 * Because Siena doesn't *require* polling, we can't rely on
76 * siena_mac_poll() being executed to populate epp->ep_mac_up.
78 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
81 *mac_upp = sls.sls_mac_up;
86 EFSYS_PROBE1(fail1, efx_rc_t, rc);
91 __checkReturn efx_rc_t
92 siena_mac_reconfigure(
95 efx_port_t *epp = &(enp->en_port);
96 efx_oword_t multicast_hash[2];
98 uint8_t payload[MAX(MAX(MC_CMD_SET_MAC_IN_LEN,
99 MC_CMD_SET_MAC_OUT_LEN),
100 MAX(MC_CMD_SET_MCAST_HASH_IN_LEN,
101 MC_CMD_SET_MCAST_HASH_OUT_LEN))];
105 (void) memset(payload, 0, sizeof (payload));
106 req.emr_cmd = MC_CMD_SET_MAC;
107 req.emr_in_buf = payload;
108 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN;
109 req.emr_out_buf = payload;
110 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
112 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu);
113 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0);
114 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR),
116 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT,
117 SET_MAC_IN_REJECT_UNCST, !epp->ep_all_unicst,
118 SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst);
120 if (epp->ep_fcntl_autoneg)
121 /* efx_fcntl_set() has already set the phy capabilities */
122 fcntl = MC_CMD_FCNTL_AUTO;
123 else if (epp->ep_fcntl & EFX_FCNTL_RESPOND)
124 fcntl = (epp->ep_fcntl & EFX_FCNTL_GENERATE)
126 : MC_CMD_FCNTL_RESPOND;
128 fcntl = MC_CMD_FCNTL_OFF;
130 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, fcntl);
132 efx_mcdi_execute(enp, &req);
134 if (req.emr_rc != 0) {
139 /* Push multicast hash */
141 if (epp->ep_all_mulcst) {
142 /* A hash matching all multicast is all 1s */
143 EFX_SET_OWORD(multicast_hash[0]);
144 EFX_SET_OWORD(multicast_hash[1]);
145 } else if (epp->ep_mulcst) {
146 /* Use the hash set by the multicast list */
147 multicast_hash[0] = epp->ep_multicst_hash[0];
148 multicast_hash[1] = epp->ep_multicst_hash[1];
150 /* A hash matching no traffic is simply 0 */
151 EFX_ZERO_OWORD(multicast_hash[0]);
152 EFX_ZERO_OWORD(multicast_hash[1]);
156 * Broadcast packets go through the multicast hash filter.
157 * The IEEE 802.3 CRC32 of the broadcast address is 0xbe2612ff
158 * so we always add bit 0xff to the mask (bit 0x7f in the
161 if (epp->ep_brdcst) {
163 * NOTE: due to constant folding, some of this evaluates
164 * to null expressions, giving E_EXPR_NULL_EFFECT during
165 * lint on Illumos. No good way to fix this without
166 * explicit coding the individual word/bit setting.
167 * So just suppress lint for this one line.
170 EFX_SET_OWORD_BIT(multicast_hash[1], 0x7f);
173 (void) memset(payload, 0, sizeof (payload));
174 req.emr_cmd = MC_CMD_SET_MCAST_HASH;
175 req.emr_in_buf = payload;
176 req.emr_in_length = MC_CMD_SET_MCAST_HASH_IN_LEN;
177 req.emr_out_buf = payload;
178 req.emr_out_length = MC_CMD_SET_MCAST_HASH_OUT_LEN;
180 memcpy(MCDI_IN2(req, uint8_t, SET_MCAST_HASH_IN_HASH0),
181 multicast_hash, sizeof (multicast_hash));
183 efx_mcdi_execute(enp, &req);
185 if (req.emr_rc != 0) {
195 EFSYS_PROBE1(fail1, efx_rc_t, rc);
200 #if EFSYS_OPT_LOOPBACK
202 __checkReturn efx_rc_t
203 siena_mac_loopback_set(
205 __in efx_link_mode_t link_mode,
206 __in efx_loopback_type_t loopback_type)
208 efx_port_t *epp = &(enp->en_port);
209 const efx_phy_ops_t *epop = epp->ep_epop;
210 efx_loopback_type_t old_loopback_type;
211 efx_link_mode_t old_loopback_link_mode;
214 /* The PHY object handles this on Siena */
215 old_loopback_type = epp->ep_loopback_type;
216 old_loopback_link_mode = epp->ep_loopback_link_mode;
217 epp->ep_loopback_type = loopback_type;
218 epp->ep_loopback_link_mode = link_mode;
220 if ((rc = epop->epo_reconfigure(enp)) != 0)
226 EFSYS_PROBE1(fail1, efx_rc_t, rc);
228 epp->ep_loopback_type = old_loopback_type;
229 epp->ep_loopback_link_mode = old_loopback_link_mode;
234 #endif /* EFSYS_OPT_LOOPBACK */
236 #if EFSYS_OPT_MAC_STATS
238 __checkReturn efx_rc_t
239 siena_mac_stats_get_mask(
241 __inout_bcount(mask_size) uint32_t *maskp,
242 __in size_t mask_size)
244 const struct efx_mac_stats_range siena_stats[] = {
245 { EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS },
246 /* EFX_MAC_RX_ERRORS is not supported */
247 { EFX_MAC_RX_FCS_ERRORS, EFX_MAC_TX_EX_DEF_PKTS },
251 _NOTE(ARGUNUSED(enp))
253 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
254 siena_stats, EFX_ARRAY_SIZE(siena_stats))) != 0)
260 EFSYS_PROBE1(fail1, efx_rc_t, rc);
265 #define SIENA_MAC_STAT_READ(_esmp, _field, _eqp) \
266 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
268 __checkReturn efx_rc_t
269 siena_mac_stats_update(
271 __in efsys_mem_t *esmp,
272 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
273 __inout_opt uint32_t *generationp)
276 efx_qword_t generation_start;
277 efx_qword_t generation_end;
279 _NOTE(ARGUNUSED(enp))
281 /* Read END first so we don't race with the MC */
282 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE);
283 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_END,
285 EFSYS_MEM_READ_BARRIER();
288 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value);
289 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
290 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value);
291 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
293 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value);
294 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value);
296 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value);
297 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value);
299 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value);
300 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value);
302 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value);
303 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value);
305 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value);
306 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value);
308 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value);
309 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
310 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value);
311 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
313 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value);
314 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value);
316 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value);
317 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value);
319 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value);
320 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value);
322 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value);
323 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value);
325 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value);
326 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value);
328 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value);
329 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
330 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value);
331 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
333 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value);
334 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value);
336 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value);
337 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value);
339 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS,
341 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value);
343 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS,
345 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value);
347 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value);
348 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value);
350 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value);
351 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value);
353 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS,
355 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value);
358 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value);
359 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value);
361 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value);
362 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value);
364 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value);
365 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value);
367 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value);
368 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value);
370 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value);
371 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value);
373 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value);
374 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value);
376 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value);
377 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
378 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value);
379 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
381 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value);
382 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value);
384 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value);
385 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value);
387 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value);
388 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value);
390 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value);
391 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value);
393 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value);
394 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value);
396 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value);
397 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
398 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value);
399 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
401 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value);
402 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value);
404 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value);
405 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value);
407 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value);
408 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value);
410 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value);
411 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value);
413 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value);
414 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value);
416 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value);
417 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value);
419 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value);
420 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value);
422 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value);
423 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]),
424 &(value.eq_dword[0]));
425 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]),
426 &(value.eq_dword[1]));
428 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value);
429 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]),
430 &(value.eq_dword[0]));
431 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]),
432 &(value.eq_dword[1]));
434 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value);
435 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]),
436 &(value.eq_dword[0]));
437 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]),
438 &(value.eq_dword[1]));
440 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value);
441 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]),
442 &(value.eq_dword[0]));
443 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]),
444 &(value.eq_dword[1]));
446 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value);
447 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value);
449 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value);
450 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value);
452 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE);
453 EFSYS_MEM_READ_BARRIER();
454 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START,
457 /* Check that we didn't read the stats in the middle of a DMA */
458 /* Not a good enough check ? */
459 if (memcmp(&generation_start, &generation_end,
460 sizeof (generation_start)))
464 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);
469 #endif /* EFSYS_OPT_MAC_STATS */
471 __checkReturn efx_rc_t
479 #endif /* EFSYS_OPT_SIENA */