2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * The views and conclusions contained in the software and documentation are
29 * those of the authors and should not be interpreted as representing official
30 * policies, either expressed or implied, of the FreeBSD Project.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
43 __in uint32_t mcdi_cap,
44 __out uint32_t *maskp)
49 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN))
50 mask |= (1 << EFX_PHY_CAP_10HDX);
51 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN))
52 mask |= (1 << EFX_PHY_CAP_10FDX);
53 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN))
54 mask |= (1 << EFX_PHY_CAP_100HDX);
55 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN))
56 mask |= (1 << EFX_PHY_CAP_100FDX);
57 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN))
58 mask |= (1 << EFX_PHY_CAP_1000HDX);
59 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN))
60 mask |= (1 << EFX_PHY_CAP_1000FDX);
61 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN))
62 mask |= (1 << EFX_PHY_CAP_10000FDX);
63 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN))
64 mask |= (1 << EFX_PHY_CAP_PAUSE);
65 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN))
66 mask |= (1 << EFX_PHY_CAP_ASYM);
67 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
68 mask |= (1 << EFX_PHY_CAP_AN);
74 siena_phy_decode_link_mode(
76 __in uint32_t link_flags,
77 __in unsigned int speed,
78 __in unsigned int fcntl,
79 __out efx_link_mode_t *link_modep,
80 __out unsigned int *fcntlp)
82 boolean_t fd = !!(link_flags &
83 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
84 boolean_t up = !!(link_flags &
85 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
90 *link_modep = EFX_LINK_DOWN;
91 else if (speed == 10000 && fd)
92 *link_modep = EFX_LINK_10000FDX;
93 else if (speed == 1000)
94 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX;
95 else if (speed == 100)
96 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX;
98 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX;
100 *link_modep = EFX_LINK_UNKNOWN;
102 if (fcntl == MC_CMD_FCNTL_OFF)
104 else if (fcntl == MC_CMD_FCNTL_RESPOND)
105 *fcntlp = EFX_FCNTL_RESPOND;
106 else if (fcntl == MC_CMD_FCNTL_BIDIR)
107 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
109 EFSYS_PROBE1(mc_pcol_error, int, fcntl);
117 __in efx_qword_t *eqp,
118 __out efx_link_mode_t *link_modep)
120 efx_port_t *epp = &(enp->en_port);
121 unsigned int link_flags;
124 efx_link_mode_t link_mode;
125 uint32_t lp_cap_mask;
128 * Convert the LINKCHANGE speed enumeration into mbit/s, in the
129 * same way as GET_LINK encodes the speed
131 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) {
132 case MCDI_EVENT_LINKCHANGE_SPEED_100M:
135 case MCDI_EVENT_LINKCHANGE_SPEED_1G:
138 case MCDI_EVENT_LINKCHANGE_SPEED_10G:
146 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS);
147 siena_phy_decode_link_mode(enp, link_flags, speed,
148 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL),
150 siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP),
154 * It's safe to update ep_lp_cap_mask without the driver's port lock
155 * because presumably any concurrently running efx_port_poll() is
156 * only going to arrive at the same value.
158 * ep_fcntl has two meanings. It's either the link common fcntl
159 * (if the PHY supports AN), or it's the forced link state. If
160 * the former, it's safe to update the value for the same reason as
161 * for ep_lp_cap_mask. If the latter, then just ignore the value,
162 * because we can race with efx_mac_fcntl_set().
164 epp->ep_lp_cap_mask = lp_cap_mask;
165 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))
166 epp->ep_fcntl = fcntl;
168 *link_modep = link_mode;
171 __checkReturn efx_rc_t
174 __in boolean_t power)
181 /* Check if the PHY is a zombie */
182 if ((rc = siena_phy_verify(enp)) != 0)
185 enp->en_reset_flags |= EFX_RESET_PHY;
190 EFSYS_PROBE1(fail1, efx_rc_t, rc);
195 __checkReturn efx_rc_t
198 __out siena_link_state_t *slsp)
201 uint8_t payload[MAX(MC_CMD_GET_LINK_IN_LEN,
202 MC_CMD_GET_LINK_OUT_LEN)];
205 (void) memset(payload, 0, sizeof (payload));
206 req.emr_cmd = MC_CMD_GET_LINK;
207 req.emr_in_buf = payload;
208 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN;
209 req.emr_out_buf = payload;
210 req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN;
212 efx_mcdi_execute(enp, &req);
214 if (req.emr_rc != 0) {
219 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) {
224 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP),
225 &slsp->sls_adv_cap_mask);
226 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP),
227 &slsp->sls_lp_cap_mask);
229 siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
230 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED),
231 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL),
232 &slsp->sls_link_mode, &slsp->sls_fcntl);
234 #if EFSYS_OPT_LOOPBACK
235 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */
236 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
237 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
238 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
239 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
240 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
241 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
242 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
243 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
244 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
245 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI);
246 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR);
247 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR);
248 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR);
249 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR);
250 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY);
251 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS);
252 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS);
253 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD);
255 slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE);
256 #endif /* EFSYS_OPT_LOOPBACK */
258 slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0;
265 EFSYS_PROBE1(fail1, efx_rc_t, rc);
270 __checkReturn efx_rc_t
271 siena_phy_reconfigure(
274 efx_port_t *epp = &(enp->en_port);
276 uint8_t payload[MAX(MAX(MC_CMD_SET_ID_LED_IN_LEN,
277 MC_CMD_SET_ID_LED_OUT_LEN),
278 MAX(MC_CMD_SET_LINK_IN_LEN,
279 MC_CMD_SET_LINK_OUT_LEN))];
281 unsigned int led_mode;
285 (void) memset(payload, 0, sizeof (payload));
286 req.emr_cmd = MC_CMD_SET_LINK;
287 req.emr_in_buf = payload;
288 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN;
289 req.emr_out_buf = payload;
290 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN;
292 cap_mask = epp->ep_adv_cap_mask;
293 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP,
294 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1,
295 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1,
296 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1,
297 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1,
298 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1,
299 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1,
300 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1,
301 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1,
302 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1,
303 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1);
305 #if EFSYS_OPT_LOOPBACK
306 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE,
307 epp->ep_loopback_type);
308 switch (epp->ep_loopback_link_mode) {
309 case EFX_LINK_100FDX:
312 case EFX_LINK_1000FDX:
315 case EFX_LINK_10000FDX:
322 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE);
324 #endif /* EFSYS_OPT_LOOPBACK */
325 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed);
327 #if EFSYS_OPT_PHY_FLAGS
328 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags);
330 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0);
331 #endif /* EFSYS_OPT_PHY_FLAGS */
333 efx_mcdi_execute(enp, &req);
335 if (req.emr_rc != 0) {
340 /* And set the blink mode */
341 (void) memset(payload, 0, sizeof (payload));
342 req.emr_cmd = MC_CMD_SET_ID_LED;
343 req.emr_in_buf = payload;
344 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN;
345 req.emr_out_buf = payload;
346 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN;
348 #if EFSYS_OPT_PHY_LED_CONTROL
349 switch (epp->ep_phy_led_mode) {
350 case EFX_PHY_LED_DEFAULT:
351 led_mode = MC_CMD_LED_DEFAULT;
353 case EFX_PHY_LED_OFF:
354 led_mode = MC_CMD_LED_OFF;
357 led_mode = MC_CMD_LED_ON;
361 led_mode = MC_CMD_LED_DEFAULT;
364 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode);
366 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT);
367 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
369 efx_mcdi_execute(enp, &req);
371 if (req.emr_rc != 0) {
381 EFSYS_PROBE1(fail1, efx_rc_t, rc);
386 __checkReturn efx_rc_t
391 uint8_t payload[MAX(MC_CMD_GET_PHY_STATE_IN_LEN,
392 MC_CMD_GET_PHY_STATE_OUT_LEN)];
396 (void) memset(payload, 0, sizeof (payload));
397 req.emr_cmd = MC_CMD_GET_PHY_STATE;
398 req.emr_in_buf = payload;
399 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN;
400 req.emr_out_buf = payload;
401 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN;
403 efx_mcdi_execute(enp, &req);
405 if (req.emr_rc != 0) {
410 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) {
415 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE);
416 if (state != MC_CMD_PHY_STATE_OK) {
417 if (state != MC_CMD_PHY_STATE_ZOMBIE)
418 EFSYS_PROBE1(mc_pcol_error, int, state);
430 EFSYS_PROBE1(fail1, efx_rc_t, rc);
435 __checkReturn efx_rc_t
438 __out uint32_t *ouip)
440 _NOTE(ARGUNUSED(enp, ouip))
445 #if EFSYS_OPT_PHY_STATS
447 #define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
448 _mc_record, _efx_record) \
449 if ((_vmask) & (1ULL << (_mc_record))) { \
450 (_smask) |= (1ULL << (_efx_record)); \
451 if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \
453 EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\
454 (_stat)[_efx_record] = \
455 EFX_DWORD_FIELD(dword, EFX_DWORD_0); \
459 #define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \
460 SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
461 MC_CMD_ ## _record, \
462 EFX_PHY_STAT_ ## _record)
465 siena_phy_decode_stats(
468 __in_opt efsys_mem_t *esmp,
469 __out_opt uint64_t *smaskp,
470 __inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat)
474 _NOTE(ARGUNUSED(enp))
476 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI);
477 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP);
478 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT);
479 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT);
481 if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) {
482 smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) |
483 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) |
484 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) |
485 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D));
486 if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
489 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL,
491 sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
492 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1;
493 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1;
494 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1;
495 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1;
499 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A,
501 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B,
503 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C,
505 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D,
508 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP);
509 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT);
510 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT);
511 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER);
512 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS);
514 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP,
515 EFX_PHY_STAT_PHY_XS_LINK_UP);
516 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT,
517 EFX_PHY_STAT_PHY_XS_RX_FAULT);
518 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT,
519 EFX_PHY_STAT_PHY_XS_TX_FAULT);
520 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN,
521 EFX_PHY_STAT_PHY_XS_ALIGN);
523 if (vmask & (1 << MC_CMD_PHYXS_SYNC)) {
524 smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) |
525 (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) |
526 (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) |
527 (1 << EFX_PHY_STAT_PHY_XS_SYNC_D));
528 if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
531 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword);
532 sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
533 stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1;
534 stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1;
535 stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1;
536 stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1;
540 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP);
541 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE);
543 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP,
544 EFX_PHY_STAT_CL22EXT_LINK_UP);
550 __checkReturn efx_rc_t
551 siena_phy_stats_update(
553 __in efsys_mem_t *esmp,
554 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
556 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
557 uint32_t vmask = encp->enc_mcdi_phy_stat_mask;
560 uint8_t payload[MAX(MC_CMD_PHY_STATS_IN_LEN,
561 MC_CMD_PHY_STATS_OUT_DMA_LEN)];
564 (void) memset(payload, 0, sizeof (payload));
565 req.emr_cmd = MC_CMD_PHY_STATS;
566 req.emr_in_buf = payload;
567 req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN;
568 req.emr_out_buf = payload;
569 req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN;
571 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO,
572 EFSYS_MEM_ADDR(esmp) & 0xffffffff);
573 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI,
574 EFSYS_MEM_ADDR(esmp) >> 32);
576 efx_mcdi_execute(enp, &req);
578 if (req.emr_rc != 0) {
582 EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN);
584 siena_phy_decode_stats(enp, vmask, esmp, &smask, stat);
585 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask);
590 EFSYS_PROBE1(fail1, efx_rc_t, rc);
595 #endif /* EFSYS_OPT_PHY_STATS */
599 __checkReturn efx_rc_t
600 siena_phy_bist_start(
602 __in efx_bist_type_t type)
606 if ((rc = efx_mcdi_bist_start(enp, type)) != 0)
612 EFSYS_PROBE1(fail1, efx_rc_t, rc);
617 static __checkReturn unsigned long
618 siena_phy_sft9001_bist_status(
622 case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY:
623 return (EFX_PHY_CABLE_STATUS_BUSY);
624 case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT:
625 return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT);
626 case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT:
627 return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT);
628 case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN:
629 return (EFX_PHY_CABLE_STATUS_OPEN);
630 case MC_CMD_POLL_BIST_SFT9001_PAIR_OK:
631 return (EFX_PHY_CABLE_STATUS_OK);
633 return (EFX_PHY_CABLE_STATUS_INVALID);
637 __checkReturn efx_rc_t
640 __in efx_bist_type_t type,
641 __out efx_bist_result_t *resultp,
642 __out_opt __drv_when(count > 0, __notnull)
643 uint32_t *value_maskp,
644 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
645 unsigned long *valuesp,
648 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
649 uint8_t payload[MAX(MC_CMD_POLL_BIST_IN_LEN,
650 MCDI_CTL_SDU_LEN_MAX)];
651 uint32_t value_mask = 0;
656 (void) memset(payload, 0, sizeof (payload));
657 req.emr_cmd = MC_CMD_POLL_BIST;
658 req.emr_in_buf = payload;
659 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN;
660 req.emr_out_buf = payload;
661 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX;
663 efx_mcdi_execute(enp, &req);
665 if (req.emr_rc != 0) {
670 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) {
676 (void) memset(valuesp, '\0', count * sizeof (unsigned long));
678 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT);
680 /* Extract PHY specific results */
681 if (result == MC_CMD_POLL_BIST_PASSED &&
682 encp->enc_phy_type == EFX_PHY_SFT9001B &&
683 req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN &&
684 (type == EFX_BIST_TYPE_PHY_CABLE_SHORT ||
685 type == EFX_BIST_TYPE_PHY_CABLE_LONG)) {
688 if (count > EFX_BIST_PHY_CABLE_LENGTH_A) {
690 valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] =
692 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A);
693 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A);
696 if (count > EFX_BIST_PHY_CABLE_LENGTH_B) {
698 valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] =
700 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B);
701 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B);
704 if (count > EFX_BIST_PHY_CABLE_LENGTH_C) {
706 valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] =
708 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C);
709 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C);
712 if (count > EFX_BIST_PHY_CABLE_LENGTH_D) {
714 valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] =
716 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D);
717 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D);
720 if (count > EFX_BIST_PHY_CABLE_STATUS_A) {
721 if (valuesp != NULL) {
722 word = MCDI_OUT_WORD(req,
723 POLL_BIST_OUT_SFT9001_CABLE_STATUS_A);
724 valuesp[EFX_BIST_PHY_CABLE_STATUS_A] =
725 siena_phy_sft9001_bist_status(word);
727 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A);
730 if (count > EFX_BIST_PHY_CABLE_STATUS_B) {
731 if (valuesp != NULL) {
732 word = MCDI_OUT_WORD(req,
733 POLL_BIST_OUT_SFT9001_CABLE_STATUS_B);
734 valuesp[EFX_BIST_PHY_CABLE_STATUS_B] =
735 siena_phy_sft9001_bist_status(word);
737 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B);
740 if (count > EFX_BIST_PHY_CABLE_STATUS_C) {
741 if (valuesp != NULL) {
742 word = MCDI_OUT_WORD(req,
743 POLL_BIST_OUT_SFT9001_CABLE_STATUS_C);
744 valuesp[EFX_BIST_PHY_CABLE_STATUS_C] =
745 siena_phy_sft9001_bist_status(word);
747 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C);
750 if (count > EFX_BIST_PHY_CABLE_STATUS_D) {
751 if (valuesp != NULL) {
752 word = MCDI_OUT_WORD(req,
753 POLL_BIST_OUT_SFT9001_CABLE_STATUS_D);
754 valuesp[EFX_BIST_PHY_CABLE_STATUS_D] =
755 siena_phy_sft9001_bist_status(word);
757 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D);
760 } else if (result == MC_CMD_POLL_BIST_FAILED &&
761 encp->enc_phy_type == EFX_PHY_QLX111V &&
762 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN &&
763 count > EFX_BIST_FAULT_CODE) {
765 valuesp[EFX_BIST_FAULT_CODE] =
766 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST);
767 value_mask |= 1 << EFX_BIST_FAULT_CODE;
770 if (value_maskp != NULL)
771 *value_maskp = value_mask;
773 EFSYS_ASSERT(resultp != NULL);
774 if (result == MC_CMD_POLL_BIST_RUNNING)
775 *resultp = EFX_BIST_RESULT_RUNNING;
776 else if (result == MC_CMD_POLL_BIST_PASSED)
777 *resultp = EFX_BIST_RESULT_PASSED;
779 *resultp = EFX_BIST_RESULT_FAILED;
786 EFSYS_PROBE1(fail1, efx_rc_t, rc);
794 __in efx_bist_type_t type)
796 /* There is no way to stop BIST on Siena */
797 _NOTE(ARGUNUSED(enp, type))
800 #endif /* EFSYS_OPT_BIST */
802 #endif /* EFSYS_OPT_SIENA */