2 * Copyright (c) 2009-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
43 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
45 uint32_t rx_base, tx_base;
47 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
48 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
50 rx_base = encp->enc_buftbl_limit;
51 tx_base = rx_base + (encp->enc_rxq_limit *
52 EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
54 /* Initialize the transmit descriptor cache */
55 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base);
56 EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
58 EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, EFX_TXQ_DC_SIZE);
59 EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword);
61 /* Initialize the receive descriptor cache */
62 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base);
63 EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
65 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, EFX_RXQ_DC_SIZE);
66 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword);
68 /* Set receive descriptor pre-fetch low water mark */
69 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56);
70 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword);
72 /* Set the event queue to use for SRAM updates */
73 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0);
74 EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);
79 __checkReturn efx_rc_t
82 __in efx_sram_pattern_fn_t func)
92 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
94 /* Reconfigure into HALF buffer table mode */
95 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 0);
96 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
99 * Move the descriptor caches up to the top of SRAM, and test
100 * all of SRAM below them. We only miss out one row here.
102 rows = SIENA_SRAM_ROWS - 1;
103 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rows);
104 EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
106 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, rows + 1);
107 EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
110 * Write the pattern through BUF_HALF_TBL. Write
111 * in 64 entry batches, waiting 1us in between each batch
112 * to guarantee not to overflow the SRAM fifo
114 for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
115 func(wptr, B_FALSE, &qword);
116 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
118 if ((wptr - rptr) < 64 && wptr < rows - 1)
123 for (; rptr <= wptr; ++rptr) {
124 func(rptr, B_FALSE, &qword);
125 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
128 if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
135 /* And do the same negated */
136 for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
137 func(wptr, B_TRUE, &qword);
138 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
140 if ((wptr - rptr) < 64 && wptr < rows - 1)
145 for (; rptr <= wptr; ++rptr) {
146 func(rptr, B_TRUE, &qword);
147 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
150 if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
157 /* Restore back to FULL buffer table mode */
158 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
159 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
162 * We don't need to reconfigure SRAM again because the API
163 * requires efx_nic_fini() to be called after an sram test.
170 EFSYS_PROBE1(fail1, efx_rc_t, rc);
172 /* Restore back to FULL buffer table mode */
173 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
174 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
179 #endif /* EFSYS_OPT_DIAG */
181 #endif /* EFSYS_OPT_SIENA */