2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
45 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
47 uint32_t rx_base, tx_base;
49 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
50 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
52 rx_base = encp->enc_buftbl_limit;
53 tx_base = rx_base + (encp->enc_rxq_limit *
54 EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
56 /* Initialize the transmit descriptor cache */
57 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base);
58 EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
60 EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, EFX_TXQ_DC_SIZE);
61 EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword);
63 /* Initialize the receive descriptor cache */
64 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base);
65 EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
67 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, EFX_RXQ_DC_SIZE);
68 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword);
70 /* Set receive descriptor pre-fetch low water mark */
71 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56);
72 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword);
74 /* Set the event queue to use for SRAM updates */
75 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0);
76 EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);
81 __checkReturn efx_rc_t
84 __in efx_sram_pattern_fn_t func)
94 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
96 /* Reconfigure into HALF buffer table mode */
97 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 0);
98 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
101 * Move the descriptor caches up to the top of SRAM, and test
102 * all of SRAM below them. We only miss out one row here.
104 rows = SIENA_SRAM_ROWS - 1;
105 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rows);
106 EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
108 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, rows + 1);
109 EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
112 * Write the pattern through BUF_HALF_TBL. Write
113 * in 64 entry batches, waiting 1us in between each batch
114 * to guarantee not to overflow the SRAM fifo
116 for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
117 func(wptr, B_FALSE, &qword);
118 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
120 if ((wptr - rptr) < 64 && wptr < rows - 1)
125 for (; rptr <= wptr; ++rptr) {
126 func(rptr, B_FALSE, &qword);
127 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
130 if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
137 /* And do the same negated */
138 for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
139 func(wptr, B_TRUE, &qword);
140 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
142 if ((wptr - rptr) < 64 && wptr < rows - 1)
147 for (; rptr <= wptr; ++rptr) {
148 func(rptr, B_TRUE, &qword);
149 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
152 if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
159 /* Restore back to FULL buffer table mode */
160 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
161 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
164 * We don't need to reconfigure SRAM again because the API
165 * requires efx_nic_fini() to be called after an sram test.
172 EFSYS_PROBE1(fail1, efx_rc_t, rc);
174 /* Restore back to FULL buffer table mode */
175 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
176 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
181 #endif /* EFSYS_OPT_DIAG */
183 #endif /* EFSYS_OPT_SIENA */