2 * Copyright (c) 2008-2010 Nikolay Denev <ndenev@gmail.com>
3 * Copyright (c) 2007-2008 Alexander Pohoyda <alexander.pohoyda@gmx.net>
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS''
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
25 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AUTHORS OR
26 * THE VOICES IN THEIR HEADS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
33 * OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * SiS 190/191 PCI Ethernet NIC driver.
42 * Adapted to SiS 190 NIC by Alexander Pohoyda based on the original
43 * SiS 900 driver by Bill Paul, using SiS 190/191 Solaris driver by
44 * Masayuki Murayama and SiS 190/191 GNU/Linux driver by K.M. Liu
45 * <kmliu@sis.com>. Thanks to Pyun YongHyeon <pyunyh@gmail.com> for
46 * review and very useful comments.
48 * Adapted to SiS 191 NIC by Nikolay Denev with further ideas from the
49 * Linux and Solaris drivers.
52 #include <sys/param.h>
53 #include <sys/systm.h>
55 #include <sys/endian.h>
56 #include <sys/kernel.h>
58 #include <sys/malloc.h>
60 #include <sys/module.h>
61 #include <sys/mutex.h>
63 #include <sys/socket.h>
64 #include <sys/sockio.h>
68 #include <net/if_var.h>
69 #include <net/if_arp.h>
70 #include <net/ethernet.h>
71 #include <net/if_dl.h>
72 #include <net/if_media.h>
73 #include <net/if_types.h>
74 #include <net/if_vlan_var.h>
76 #include <netinet/in.h>
77 #include <netinet/in_systm.h>
78 #include <netinet/ip.h>
79 #include <netinet/tcp.h>
81 #include <machine/bus.h>
82 #include <machine/in_cksum.h>
84 #include <dev/mii/mii.h>
85 #include <dev/mii/miivar.h>
87 #include <dev/pci/pcireg.h>
88 #include <dev/pci/pcivar.h>
90 #include <dev/sge/if_sgereg.h>
92 MODULE_DEPEND(sge, pci, 1, 1, 1);
93 MODULE_DEPEND(sge, ether, 1, 1, 1);
94 MODULE_DEPEND(sge, miibus, 1, 1, 1);
96 /* "device miibus0" required. See GENERIC if you get errors here. */
97 #include "miibus_if.h"
100 * Various supported device vendors/types and their names.
102 static struct sge_type sge_devs[] = {
103 { SIS_VENDORID, SIS_DEVICEID_190, "SiS190 Fast Ethernet" },
104 { SIS_VENDORID, SIS_DEVICEID_191, "SiS191 Fast/Gigabit Ethernet" },
108 static int sge_probe(device_t);
109 static int sge_attach(device_t);
110 static int sge_detach(device_t);
111 static int sge_shutdown(device_t);
112 static int sge_suspend(device_t);
113 static int sge_resume(device_t);
115 static int sge_miibus_readreg(device_t, int, int);
116 static int sge_miibus_writereg(device_t, int, int, int);
117 static void sge_miibus_statchg(device_t);
119 static int sge_newbuf(struct sge_softc *, int);
120 static int sge_encap(struct sge_softc *, struct mbuf **);
122 sge_discard_rxbuf(struct sge_softc *, int);
123 static void sge_rxeof(struct sge_softc *);
124 static void sge_txeof(struct sge_softc *);
125 static void sge_intr(void *);
126 static void sge_tick(void *);
127 static void sge_start(struct ifnet *);
128 static void sge_start_locked(struct ifnet *);
129 static int sge_ioctl(struct ifnet *, u_long, caddr_t);
130 static void sge_init(void *);
131 static void sge_init_locked(struct sge_softc *);
132 static void sge_stop(struct sge_softc *);
133 static void sge_watchdog(struct sge_softc *);
134 static int sge_ifmedia_upd(struct ifnet *);
135 static void sge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
137 static int sge_get_mac_addr_apc(struct sge_softc *, uint8_t *);
138 static int sge_get_mac_addr_eeprom(struct sge_softc *, uint8_t *);
139 static uint16_t sge_read_eeprom(struct sge_softc *, int);
141 static void sge_rxfilter(struct sge_softc *);
142 static void sge_setvlan(struct sge_softc *);
143 static void sge_reset(struct sge_softc *);
144 static int sge_list_rx_init(struct sge_softc *);
145 static int sge_list_rx_free(struct sge_softc *);
146 static int sge_list_tx_init(struct sge_softc *);
147 static int sge_list_tx_free(struct sge_softc *);
149 static int sge_dma_alloc(struct sge_softc *);
150 static void sge_dma_free(struct sge_softc *);
151 static void sge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
153 static device_method_t sge_methods[] = {
154 /* Device interface */
155 DEVMETHOD(device_probe, sge_probe),
156 DEVMETHOD(device_attach, sge_attach),
157 DEVMETHOD(device_detach, sge_detach),
158 DEVMETHOD(device_suspend, sge_suspend),
159 DEVMETHOD(device_resume, sge_resume),
160 DEVMETHOD(device_shutdown, sge_shutdown),
163 DEVMETHOD(miibus_readreg, sge_miibus_readreg),
164 DEVMETHOD(miibus_writereg, sge_miibus_writereg),
165 DEVMETHOD(miibus_statchg, sge_miibus_statchg),
170 static driver_t sge_driver = {
171 "sge", sge_methods, sizeof(struct sge_softc)
174 static devclass_t sge_devclass;
176 DRIVER_MODULE(sge, pci, sge_driver, sge_devclass, 0, 0);
177 DRIVER_MODULE(miibus, sge, miibus_driver, miibus_devclass, 0, 0);
180 * Register space access macros.
182 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sge_res, reg, val)
183 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->sge_res, reg, val)
184 #define CSR_WRITE_1(cs, reg, val) bus_write_1(sc->sge_res, reg, val)
186 #define CSR_READ_4(sc, reg) bus_read_4(sc->sge_res, reg)
187 #define CSR_READ_2(sc, reg) bus_read_2(sc->sge_res, reg)
188 #define CSR_READ_1(sc, reg) bus_read_1(sc->sge_res, reg)
190 /* Define to show Tx/Rx error status. */
191 #undef SGE_SHOW_ERRORS
193 #define SGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
196 sge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
202 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
208 * Read a sequence of words from the EEPROM.
211 sge_read_eeprom(struct sge_softc *sc, int offset)
216 KASSERT(offset <= EI_OFFSET, ("EEPROM offset too big"));
217 CSR_WRITE_4(sc, ROMInterface,
218 EI_REQ | EI_OP_RD | (offset << EI_OFFSET_SHIFT));
220 for (i = 0; i < SGE_TIMEOUT; i++) {
221 val = CSR_READ_4(sc, ROMInterface);
222 if ((val & EI_REQ) == 0)
226 if (i == SGE_TIMEOUT) {
227 device_printf(sc->sge_dev,
228 "EEPROM read timeout : 0x%08x\n", val);
232 return ((val & EI_DATA) >> EI_DATA_SHIFT);
236 sge_get_mac_addr_eeprom(struct sge_softc *sc, uint8_t *dest)
241 val = sge_read_eeprom(sc, EEPROMSignature);
242 if (val == 0xffff || val == 0) {
243 device_printf(sc->sge_dev,
244 "invalid EEPROM signature : 0x%04x\n", val);
248 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
249 val = sge_read_eeprom(sc, EEPROMMACAddr + i / 2);
250 dest[i + 0] = (uint8_t)val;
251 dest[i + 1] = (uint8_t)(val >> 8);
254 if ((sge_read_eeprom(sc, EEPROMInfo) & 0x80) != 0)
255 sc->sge_flags |= SGE_FLAG_RGMII;
260 * For SiS96x, APC CMOS RAM is used to store ethernet address.
261 * APC CMOS RAM is accessed through ISA bridge.
264 sge_get_mac_addr_apc(struct sge_softc *sc, uint8_t *dest)
266 #if defined(__amd64__) || defined(__i386__)
268 device_t bus, dev = NULL;
273 } *tp, apc_tbls[] = {
274 { SIS_VENDORID, 0x0965 },
275 { SIS_VENDORID, 0x0966 },
276 { SIS_VENDORID, 0x0968 }
279 int busnum, cnt, i, j, numkids;
281 cnt = sizeof(apc_tbls) / sizeof(apc_tbls[0]);
282 pci = devclass_find("pci");
283 for (busnum = 0; busnum < devclass_get_maxunit(pci); busnum++) {
284 bus = devclass_get_device(pci, busnum);
287 if (device_get_children(bus, &kids, &numkids) != 0)
289 for (i = 0; i < numkids; i++) {
291 if (pci_get_class(dev) == PCIC_BRIDGE &&
292 pci_get_subclass(dev) == PCIS_BRIDGE_ISA) {
294 for (j = 0; j < cnt; j++) {
295 if (pci_get_vendor(dev) == tp->vid &&
296 pci_get_device(dev) == tp->did) {
306 device_printf(sc->sge_dev, "couldn't find PCI-ISA bridge\n");
309 /* Enable port 0x78 and 0x79 to access APC registers. */
310 reg = pci_read_config(dev, 0x48, 1);
311 pci_write_config(dev, 0x48, reg & ~0x02, 1);
313 pci_read_config(dev, 0x48, 1);
314 /* Read stored ethernet address. */
315 for (i = 0; i < ETHER_ADDR_LEN; i++) {
316 outb(0x78, 0x09 + i);
320 if ((inb(0x79) & 0x80) != 0)
321 sc->sge_flags |= SGE_FLAG_RGMII;
322 /* Restore access to APC registers. */
323 pci_write_config(dev, 0x48, reg, 1);
332 sge_miibus_readreg(device_t dev, int phy, int reg)
334 struct sge_softc *sc;
338 sc = device_get_softc(dev);
339 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
340 (reg << GMI_REG_SHIFT) | GMI_OP_RD | GMI_REQ);
342 for (i = 0; i < SGE_TIMEOUT; i++) {
343 val = CSR_READ_4(sc, GMIIControl);
344 if ((val & GMI_REQ) == 0)
348 if (i == SGE_TIMEOUT) {
349 device_printf(sc->sge_dev, "PHY read timeout : %d\n", reg);
352 return ((val & GMI_DATA) >> GMI_DATA_SHIFT);
356 sge_miibus_writereg(device_t dev, int phy, int reg, int data)
358 struct sge_softc *sc;
362 sc = device_get_softc(dev);
363 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
364 (reg << GMI_REG_SHIFT) | (data << GMI_DATA_SHIFT) |
365 GMI_OP_WR | GMI_REQ);
367 for (i = 0; i < SGE_TIMEOUT; i++) {
368 val = CSR_READ_4(sc, GMIIControl);
369 if ((val & GMI_REQ) == 0)
373 if (i == SGE_TIMEOUT)
374 device_printf(sc->sge_dev, "PHY write timeout : %d\n", reg);
379 sge_miibus_statchg(device_t dev)
381 struct sge_softc *sc;
382 struct mii_data *mii;
386 sc = device_get_softc(dev);
387 mii = device_get_softc(sc->sge_miibus);
389 if (mii == NULL || ifp == NULL ||
390 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
393 sc->sge_flags &= ~SGE_FLAG_LINK;
394 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
395 (IFM_ACTIVE | IFM_AVALID)) {
396 switch (IFM_SUBTYPE(mii->mii_media_active)) {
398 sc->sge_flags |= SGE_FLAG_LINK;
402 sc->sge_flags |= SGE_FLAG_LINK;
403 speed = SC_SPEED_100;
406 if ((sc->sge_flags & SGE_FLAG_FASTETHER) == 0) {
407 sc->sge_flags |= SGE_FLAG_LINK;
408 speed = SC_SPEED_1000;
415 if ((sc->sge_flags & SGE_FLAG_LINK) == 0)
417 /* Reprogram MAC to resolved speed/duplex/flow-control parameters. */
418 ctl = CSR_READ_4(sc, StationControl);
419 ctl &= ~(0x0f000000 | SC_FDX | SC_SPEED_MASK);
420 if (speed == SC_SPEED_1000) {
422 sc->sge_flags |= SGE_FLAG_SPEED_1000;
425 sc->sge_flags &= ~SGE_FLAG_SPEED_1000;
428 if ((sc->sge_flags & SGE_FLAG_GMII) != 0)
432 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
434 sc->sge_flags |= SGE_FLAG_FDX;
436 sc->sge_flags &= ~SGE_FLAG_FDX;
437 CSR_WRITE_4(sc, StationControl, ctl);
438 if ((sc->sge_flags & SGE_FLAG_RGMII) != 0) {
439 CSR_WRITE_4(sc, RGMIIDelay, 0x0441);
440 CSR_WRITE_4(sc, RGMIIDelay, 0x0440);
445 sge_rxfilter(struct sge_softc *sc)
448 struct ifmultiaddr *ifma;
449 uint32_t crc, hashes[2];
455 rxfilt = CSR_READ_2(sc, RxMacControl);
456 rxfilt &= ~(AcceptBroadcast | AcceptAllPhys | AcceptMulticast);
457 rxfilt |= AcceptMyPhys;
458 if ((ifp->if_flags & IFF_BROADCAST) != 0)
459 rxfilt |= AcceptBroadcast;
460 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
461 if ((ifp->if_flags & IFF_PROMISC) != 0)
462 rxfilt |= AcceptAllPhys;
463 rxfilt |= AcceptMulticast;
464 hashes[0] = 0xFFFFFFFF;
465 hashes[1] = 0xFFFFFFFF;
467 rxfilt |= AcceptMulticast;
468 hashes[0] = hashes[1] = 0;
469 /* Now program new ones. */
471 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
472 if (ifma->ifma_addr->sa_family != AF_LINK)
474 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
475 ifma->ifma_addr), ETHER_ADDR_LEN);
476 hashes[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
478 if_maddr_runlock(ifp);
480 CSR_WRITE_2(sc, RxMacControl, rxfilt);
481 CSR_WRITE_4(sc, RxHashTable, hashes[0]);
482 CSR_WRITE_4(sc, RxHashTable2, hashes[1]);
486 sge_setvlan(struct sge_softc *sc)
494 if ((ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) == 0)
496 rxfilt = CSR_READ_2(sc, RxMacControl);
497 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
498 rxfilt |= RXMAC_STRIP_VLAN;
500 rxfilt &= ~RXMAC_STRIP_VLAN;
501 CSR_WRITE_2(sc, RxMacControl, rxfilt);
505 sge_reset(struct sge_softc *sc)
508 CSR_WRITE_4(sc, IntrMask, 0);
509 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
512 CSR_WRITE_4(sc, IntrControl, 0x8000);
513 CSR_READ_4(sc, IntrControl);
515 CSR_WRITE_4(sc, IntrControl, 0);
517 CSR_WRITE_4(sc, TX_CTL, 0x1a00);
518 CSR_WRITE_4(sc, RX_CTL, 0x1a00);
520 CSR_WRITE_4(sc, IntrMask, 0);
521 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
523 CSR_WRITE_4(sc, GMIIControl, 0);
527 * Probe for an SiS chip. Check the PCI vendor and device
528 * IDs against our list and return a device name if we find a match.
531 sge_probe(device_t dev)
536 while (t->sge_name != NULL) {
537 if ((pci_get_vendor(dev) == t->sge_vid) &&
538 (pci_get_device(dev) == t->sge_did)) {
539 device_set_desc(dev, t->sge_name);
540 return (BUS_PROBE_DEFAULT);
549 * Attach the interface. Allocate softc structures, do ifmedia
550 * setup and ethernet/BPF attach.
553 sge_attach(device_t dev)
555 struct sge_softc *sc;
557 uint8_t eaddr[ETHER_ADDR_LEN];
560 sc = device_get_softc(dev);
563 mtx_init(&sc->sge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
565 callout_init_mtx(&sc->sge_stat_ch, &sc->sge_mtx, 0);
568 * Map control/status registers.
570 pci_enable_busmaster(dev);
572 /* Allocate resources. */
573 sc->sge_res_id = PCIR_BAR(0);
574 sc->sge_res_type = SYS_RES_MEMORY;
575 sc->sge_res = bus_alloc_resource_any(dev, sc->sge_res_type,
576 &sc->sge_res_id, RF_ACTIVE);
577 if (sc->sge_res == NULL) {
578 device_printf(dev, "couldn't allocate resource\n");
584 sc->sge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
585 RF_SHAREABLE | RF_ACTIVE);
586 if (sc->sge_irq == NULL) {
587 device_printf(dev, "couldn't allocate IRQ resources\n");
591 sc->sge_rev = pci_get_revid(dev);
592 if (pci_get_device(dev) == SIS_DEVICEID_190)
593 sc->sge_flags |= SGE_FLAG_FASTETHER | SGE_FLAG_SIS190;
594 /* Reset the adapter. */
597 /* Get MAC address from the EEPROM. */
598 if ((pci_read_config(dev, 0x73, 1) & 0x01) != 0)
599 sge_get_mac_addr_apc(sc, eaddr);
601 sge_get_mac_addr_eeprom(sc, eaddr);
603 if ((error = sge_dma_alloc(sc)) != 0)
606 ifp = sc->sge_ifp = if_alloc(IFT_ETHER);
608 device_printf(dev, "cannot allocate ifnet structure.\n");
613 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
614 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
615 ifp->if_ioctl = sge_ioctl;
616 ifp->if_start = sge_start;
617 ifp->if_init = sge_init;
618 ifp->if_snd.ifq_drv_maxlen = SGE_TX_RING_CNT - 1;
619 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
620 IFQ_SET_READY(&ifp->if_snd);
621 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM | IFCAP_TSO4;
622 ifp->if_hwassist = SGE_CSUM_FEATURES | CSUM_TSO;
623 ifp->if_capenable = ifp->if_capabilities;
627 error = mii_attach(dev, &sc->sge_miibus, ifp, sge_ifmedia_upd,
628 sge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
630 device_printf(dev, "attaching PHYs failed\n");
635 * Call MI attach routine.
637 ether_ifattach(ifp, eaddr);
640 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM |
641 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
642 ifp->if_capenable = ifp->if_capabilities;
643 /* Tell the upper layer(s) we support long frames. */
644 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
646 /* Hook interrupt last to avoid having to lock softc */
647 error = bus_setup_intr(dev, sc->sge_irq, INTR_TYPE_NET | INTR_MPSAFE,
648 NULL, sge_intr, sc, &sc->sge_intrhand);
650 device_printf(dev, "couldn't set up irq\n");
663 * Shutdown hardware and free up resources. This can be called any
664 * time after the mutex has been initialized. It is called in both
665 * the error case in attach and the normal detach case so it needs
666 * to be careful about only freeing resources that have actually been
670 sge_detach(device_t dev)
672 struct sge_softc *sc;
675 sc = device_get_softc(dev);
677 /* These should only be active if attach succeeded. */
678 if (device_is_attached(dev)) {
683 callout_drain(&sc->sge_stat_ch);
686 device_delete_child(dev, sc->sge_miibus);
687 bus_generic_detach(dev);
689 if (sc->sge_intrhand)
690 bus_teardown_intr(dev, sc->sge_irq, sc->sge_intrhand);
692 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sge_irq);
694 bus_release_resource(dev, sc->sge_res_type, sc->sge_res_id,
699 mtx_destroy(&sc->sge_mtx);
705 * Stop all chip I/O so that the kernel's probe routines don't
706 * get confused by errant DMAs when rebooting.
709 sge_shutdown(device_t dev)
711 struct sge_softc *sc;
713 sc = device_get_softc(dev);
721 sge_suspend(device_t dev)
723 struct sge_softc *sc;
726 sc = device_get_softc(dev);
729 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
736 sge_resume(device_t dev)
738 struct sge_softc *sc;
741 sc = device_get_softc(dev);
744 if ((ifp->if_flags & IFF_UP) != 0)
751 sge_dma_alloc(struct sge_softc *sc)
753 struct sge_chain_data *cd;
754 struct sge_list_data *ld;
755 struct sge_rxdesc *rxd;
756 struct sge_txdesc *txd;
761 error = bus_dma_tag_create(bus_get_dma_tag(sc->sge_dev),
762 1, 0, /* alignment, boundary */
763 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
764 BUS_SPACE_MAXADDR, /* highaddr */
765 NULL, NULL, /* filter, filterarg */
766 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
768 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
774 device_printf(sc->sge_dev,
775 "could not create parent DMA tag.\n");
779 /* RX descriptor ring */
780 error = bus_dma_tag_create(cd->sge_tag,
781 SGE_DESC_ALIGN, 0, /* alignment, boundary */
782 BUS_SPACE_MAXADDR, /* lowaddr */
783 BUS_SPACE_MAXADDR, /* highaddr */
784 NULL, NULL, /* filter, filterarg */
785 SGE_RX_RING_SZ, 1, /* maxsize,nsegments */
786 SGE_RX_RING_SZ, /* maxsegsize */
792 device_printf(sc->sge_dev,
793 "could not create Rx ring DMA tag.\n");
796 /* Allocate DMA'able memory and load DMA map for RX ring. */
797 error = bus_dmamem_alloc(cd->sge_rx_tag, (void **)&ld->sge_rx_ring,
798 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
801 device_printf(sc->sge_dev,
802 "could not allocate DMA'able memory for Rx ring.\n");
805 error = bus_dmamap_load(cd->sge_rx_tag, cd->sge_rx_dmamap,
806 ld->sge_rx_ring, SGE_RX_RING_SZ, sge_dma_map_addr,
807 &ld->sge_rx_paddr, BUS_DMA_NOWAIT);
809 device_printf(sc->sge_dev,
810 "could not load DMA'able memory for Rx ring.\n");
813 /* TX descriptor ring */
814 error = bus_dma_tag_create(cd->sge_tag,
815 SGE_DESC_ALIGN, 0, /* alignment, boundary */
816 BUS_SPACE_MAXADDR, /* lowaddr */
817 BUS_SPACE_MAXADDR, /* highaddr */
818 NULL, NULL, /* filter, filterarg */
819 SGE_TX_RING_SZ, 1, /* maxsize,nsegments */
820 SGE_TX_RING_SZ, /* maxsegsize */
826 device_printf(sc->sge_dev,
827 "could not create Rx ring DMA tag.\n");
830 /* Allocate DMA'able memory and load DMA map for TX ring. */
831 error = bus_dmamem_alloc(cd->sge_tx_tag, (void **)&ld->sge_tx_ring,
832 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
835 device_printf(sc->sge_dev,
836 "could not allocate DMA'able memory for Tx ring.\n");
839 error = bus_dmamap_load(cd->sge_tx_tag, cd->sge_tx_dmamap,
840 ld->sge_tx_ring, SGE_TX_RING_SZ, sge_dma_map_addr,
841 &ld->sge_tx_paddr, BUS_DMA_NOWAIT);
843 device_printf(sc->sge_dev,
844 "could not load DMA'able memory for Rx ring.\n");
848 /* Create DMA tag for Tx buffers. */
849 error = bus_dma_tag_create(cd->sge_tag, 1, 0, BUS_SPACE_MAXADDR,
850 BUS_SPACE_MAXADDR, NULL, NULL, SGE_TSO_MAXSIZE, SGE_MAXTXSEGS,
851 SGE_TSO_MAXSEGSIZE, 0, NULL, NULL, &cd->sge_txmbuf_tag);
853 device_printf(sc->sge_dev,
854 "could not create Tx mbuf DMA tag.\n");
858 /* Create DMA tag for Rx buffers. */
859 error = bus_dma_tag_create(cd->sge_tag, SGE_RX_BUF_ALIGN, 0,
860 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
861 MCLBYTES, 0, NULL, NULL, &cd->sge_rxmbuf_tag);
863 device_printf(sc->sge_dev,
864 "could not create Rx mbuf DMA tag.\n");
868 /* Create DMA maps for Tx buffers. */
869 for (i = 0; i < SGE_TX_RING_CNT; i++) {
870 txd = &cd->sge_txdesc[i];
872 txd->tx_dmamap = NULL;
874 error = bus_dmamap_create(cd->sge_txmbuf_tag, 0,
877 device_printf(sc->sge_dev,
878 "could not create Tx DMA map.\n");
882 /* Create spare DMA map for Rx buffer. */
883 error = bus_dmamap_create(cd->sge_rxmbuf_tag, 0, &cd->sge_rx_spare_map);
885 device_printf(sc->sge_dev,
886 "could not create spare Rx DMA map.\n");
889 /* Create DMA maps for Rx buffers. */
890 for (i = 0; i < SGE_RX_RING_CNT; i++) {
891 rxd = &cd->sge_rxdesc[i];
893 rxd->rx_dmamap = NULL;
894 error = bus_dmamap_create(cd->sge_rxmbuf_tag, 0,
897 device_printf(sc->sge_dev,
898 "could not create Rx DMA map.\n");
907 sge_dma_free(struct sge_softc *sc)
909 struct sge_chain_data *cd;
910 struct sge_list_data *ld;
911 struct sge_rxdesc *rxd;
912 struct sge_txdesc *txd;
918 if (cd->sge_rx_tag != NULL) {
919 if (cd->sge_rx_dmamap != NULL)
920 bus_dmamap_unload(cd->sge_rx_tag, cd->sge_rx_dmamap);
921 if (cd->sge_rx_dmamap != NULL && ld->sge_rx_ring != NULL)
922 bus_dmamem_free(cd->sge_rx_tag, ld->sge_rx_ring,
924 ld->sge_rx_ring = NULL;
925 cd->sge_rx_dmamap = NULL;
926 bus_dma_tag_destroy(cd->sge_rx_tag);
927 cd->sge_rx_tag = NULL;
930 if (cd->sge_tx_tag != NULL) {
931 if (cd->sge_tx_dmamap != NULL)
932 bus_dmamap_unload(cd->sge_tx_tag, cd->sge_tx_dmamap);
933 if (cd->sge_tx_dmamap != NULL && ld->sge_tx_ring != NULL)
934 bus_dmamem_free(cd->sge_tx_tag, ld->sge_tx_ring,
936 ld->sge_tx_ring = NULL;
937 cd->sge_tx_dmamap = NULL;
938 bus_dma_tag_destroy(cd->sge_tx_tag);
939 cd->sge_tx_tag = NULL;
942 if (cd->sge_rxmbuf_tag != NULL) {
943 for (i = 0; i < SGE_RX_RING_CNT; i++) {
944 rxd = &cd->sge_rxdesc[i];
945 if (rxd->rx_dmamap != NULL) {
946 bus_dmamap_destroy(cd->sge_rxmbuf_tag,
948 rxd->rx_dmamap = NULL;
951 if (cd->sge_rx_spare_map != NULL) {
952 bus_dmamap_destroy(cd->sge_rxmbuf_tag,
953 cd->sge_rx_spare_map);
954 cd->sge_rx_spare_map = NULL;
956 bus_dma_tag_destroy(cd->sge_rxmbuf_tag);
957 cd->sge_rxmbuf_tag = NULL;
960 if (cd->sge_txmbuf_tag != NULL) {
961 for (i = 0; i < SGE_TX_RING_CNT; i++) {
962 txd = &cd->sge_txdesc[i];
963 if (txd->tx_dmamap != NULL) {
964 bus_dmamap_destroy(cd->sge_txmbuf_tag,
966 txd->tx_dmamap = NULL;
969 bus_dma_tag_destroy(cd->sge_txmbuf_tag);
970 cd->sge_txmbuf_tag = NULL;
972 if (cd->sge_tag != NULL)
973 bus_dma_tag_destroy(cd->sge_tag);
978 * Initialize the TX descriptors.
981 sge_list_tx_init(struct sge_softc *sc)
983 struct sge_list_data *ld;
984 struct sge_chain_data *cd;
989 bzero(ld->sge_tx_ring, SGE_TX_RING_SZ);
990 ld->sge_tx_ring[SGE_TX_RING_CNT - 1].sge_flags = htole32(RING_END);
991 bus_dmamap_sync(cd->sge_tx_tag, cd->sge_tx_dmamap,
992 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1000 sge_list_tx_free(struct sge_softc *sc)
1002 struct sge_chain_data *cd;
1003 struct sge_txdesc *txd;
1006 SGE_LOCK_ASSERT(sc);
1007 cd = &sc->sge_cdata;
1008 for (i = 0; i < SGE_TX_RING_CNT; i++) {
1009 txd = &cd->sge_txdesc[i];
1010 if (txd->tx_m != NULL) {
1011 bus_dmamap_sync(cd->sge_txmbuf_tag, txd->tx_dmamap,
1012 BUS_DMASYNC_POSTWRITE);
1013 bus_dmamap_unload(cd->sge_txmbuf_tag, txd->tx_dmamap);
1024 * Initialize the RX descriptors and allocate mbufs for them. Note that
1025 * we arrange the descriptors in a closed ring, so that the last descriptor
1026 * has RING_END flag set.
1029 sge_list_rx_init(struct sge_softc *sc)
1031 struct sge_chain_data *cd;
1034 SGE_LOCK_ASSERT(sc);
1035 cd = &sc->sge_cdata;
1036 cd->sge_rx_cons = 0;
1037 bzero(sc->sge_ldata.sge_rx_ring, SGE_RX_RING_SZ);
1038 for (i = 0; i < SGE_RX_RING_CNT; i++) {
1039 if (sge_newbuf(sc, i) != 0)
1042 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1043 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1048 sge_list_rx_free(struct sge_softc *sc)
1050 struct sge_chain_data *cd;
1051 struct sge_rxdesc *rxd;
1054 SGE_LOCK_ASSERT(sc);
1055 cd = &sc->sge_cdata;
1056 for (i = 0; i < SGE_RX_RING_CNT; i++) {
1057 rxd = &cd->sge_rxdesc[i];
1058 if (rxd->rx_m != NULL) {
1059 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1060 BUS_DMASYNC_POSTREAD);
1061 bus_dmamap_unload(cd->sge_rxmbuf_tag,
1071 * Initialize an RX descriptor and attach an MBUF cluster.
1074 sge_newbuf(struct sge_softc *sc, int prod)
1077 struct sge_desc *desc;
1078 struct sge_chain_data *cd;
1079 struct sge_rxdesc *rxd;
1080 bus_dma_segment_t segs[1];
1084 SGE_LOCK_ASSERT(sc);
1086 cd = &sc->sge_cdata;
1087 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1090 m->m_len = m->m_pkthdr.len = MCLBYTES;
1091 m_adj(m, SGE_RX_BUF_ALIGN);
1092 error = bus_dmamap_load_mbuf_sg(cd->sge_rxmbuf_tag,
1093 cd->sge_rx_spare_map, m, segs, &nsegs, 0);
1098 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1099 rxd = &cd->sge_rxdesc[prod];
1100 if (rxd->rx_m != NULL) {
1101 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1102 BUS_DMASYNC_POSTREAD);
1103 bus_dmamap_unload(cd->sge_rxmbuf_tag, rxd->rx_dmamap);
1105 map = rxd->rx_dmamap;
1106 rxd->rx_dmamap = cd->sge_rx_spare_map;
1107 cd->sge_rx_spare_map = map;
1108 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1109 BUS_DMASYNC_PREREAD);
1112 desc = &sc->sge_ldata.sge_rx_ring[prod];
1113 desc->sge_sts_size = 0;
1114 desc->sge_ptr = htole32(SGE_ADDR_LO(segs[0].ds_addr));
1115 desc->sge_flags = htole32(segs[0].ds_len);
1116 if (prod == SGE_RX_RING_CNT - 1)
1117 desc->sge_flags |= htole32(RING_END);
1118 desc->sge_cmdsts = htole32(RDC_OWN | RDC_INTR);
1122 static __inline void
1123 sge_discard_rxbuf(struct sge_softc *sc, int index)
1125 struct sge_desc *desc;
1127 desc = &sc->sge_ldata.sge_rx_ring[index];
1128 desc->sge_sts_size = 0;
1129 desc->sge_flags = htole32(MCLBYTES - SGE_RX_BUF_ALIGN);
1130 if (index == SGE_RX_RING_CNT - 1)
1131 desc->sge_flags |= htole32(RING_END);
1132 desc->sge_cmdsts = htole32(RDC_OWN | RDC_INTR);
1136 * A frame has been uploaded: pass the resulting mbuf chain up to
1137 * the higher level protocols.
1140 sge_rxeof(struct sge_softc *sc)
1144 struct sge_chain_data *cd;
1145 struct sge_desc *cur_rx;
1146 uint32_t rxinfo, rxstat;
1149 SGE_LOCK_ASSERT(sc);
1152 cd = &sc->sge_cdata;
1154 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1155 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1156 cons = cd->sge_rx_cons;
1157 for (prog = 0; prog < SGE_RX_RING_CNT; prog++,
1158 SGE_INC(cons, SGE_RX_RING_CNT)) {
1159 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1161 cur_rx = &sc->sge_ldata.sge_rx_ring[cons];
1162 rxinfo = le32toh(cur_rx->sge_cmdsts);
1163 if ((rxinfo & RDC_OWN) != 0)
1165 rxstat = le32toh(cur_rx->sge_sts_size);
1166 if ((rxstat & RDS_CRCOK) == 0 || SGE_RX_ERROR(rxstat) != 0 ||
1167 SGE_RX_NSEGS(rxstat) != 1) {
1168 /* XXX We don't support multi-segment frames yet. */
1169 #ifdef SGE_SHOW_ERRORS
1170 device_printf(sc->sge_dev, "Rx error : 0x%b\n", rxstat,
1173 sge_discard_rxbuf(sc, cons);
1177 m = cd->sge_rxdesc[cons].rx_m;
1178 if (sge_newbuf(sc, cons) != 0) {
1179 sge_discard_rxbuf(sc, cons);
1183 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1184 if ((rxinfo & RDC_IP_CSUM) != 0 &&
1185 (rxinfo & RDC_IP_CSUM_OK) != 0)
1186 m->m_pkthdr.csum_flags |=
1187 CSUM_IP_CHECKED | CSUM_IP_VALID;
1188 if (((rxinfo & RDC_TCP_CSUM) != 0 &&
1189 (rxinfo & RDC_TCP_CSUM_OK) != 0) ||
1190 ((rxinfo & RDC_UDP_CSUM) != 0 &&
1191 (rxinfo & RDC_UDP_CSUM_OK) != 0)) {
1192 m->m_pkthdr.csum_flags |=
1193 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1194 m->m_pkthdr.csum_data = 0xffff;
1197 /* Check for VLAN tagged frame. */
1198 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1199 (rxstat & RDS_VLAN) != 0) {
1200 m->m_pkthdr.ether_vtag = rxinfo & RDC_VLAN_MASK;
1201 m->m_flags |= M_VLANTAG;
1204 * Account for 10bytes auto padding which is used
1205 * to align IP header on 32bit boundary. Also note,
1206 * CRC bytes is automatically removed by the
1209 m->m_data += SGE_RX_PAD_BYTES;
1210 m->m_pkthdr.len = m->m_len = SGE_RX_BYTES(rxstat) -
1212 m->m_pkthdr.rcvif = ifp;
1215 (*ifp->if_input)(ifp, m);
1220 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1221 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1222 cd->sge_rx_cons = cons;
1227 * A frame was downloaded to the chip. It's safe for us to clean up
1231 sge_txeof(struct sge_softc *sc)
1234 struct sge_list_data *ld;
1235 struct sge_chain_data *cd;
1236 struct sge_txdesc *txd;
1238 int cons, nsegs, prod;
1240 SGE_LOCK_ASSERT(sc);
1243 ld = &sc->sge_ldata;
1244 cd = &sc->sge_cdata;
1246 if (cd->sge_tx_cnt == 0)
1248 bus_dmamap_sync(cd->sge_tx_tag, cd->sge_tx_dmamap,
1249 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1250 cons = cd->sge_tx_cons;
1251 prod = cd->sge_tx_prod;
1252 for (; cons != prod;) {
1253 txstat = le32toh(ld->sge_tx_ring[cons].sge_cmdsts);
1254 if ((txstat & TDC_OWN) != 0)
1257 * Only the first descriptor of multi-descriptor transmission
1258 * is updated by controller. Driver should skip entire
1259 * chained buffers for the transmitted frame. In other words
1260 * TDC_OWN bit is valid only at the first descriptor of a
1261 * multi-descriptor transmission.
1263 if (SGE_TX_ERROR(txstat) != 0) {
1264 #ifdef SGE_SHOW_ERRORS
1265 device_printf(sc->sge_dev, "Tx error : 0x%b\n",
1266 txstat, TX_ERR_BITS);
1271 ifp->if_collisions += (txstat & 0xFFFF) - 1;
1275 txd = &cd->sge_txdesc[cons];
1276 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
1277 ld->sge_tx_ring[cons].sge_cmdsts = 0;
1278 SGE_INC(cons, SGE_TX_RING_CNT);
1280 /* Reclaim transmitted mbuf. */
1281 KASSERT(txd->tx_m != NULL,
1282 ("%s: freeing NULL mbuf\n", __func__));
1283 bus_dmamap_sync(cd->sge_txmbuf_tag, txd->tx_dmamap,
1284 BUS_DMASYNC_POSTWRITE);
1285 bus_dmamap_unload(cd->sge_txmbuf_tag, txd->tx_dmamap);
1288 cd->sge_tx_cnt -= txd->tx_ndesc;
1289 KASSERT(cd->sge_tx_cnt >= 0,
1290 ("%s: Active Tx desc counter was garbled\n", __func__));
1292 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1294 cd->sge_tx_cons = cons;
1295 if (cd->sge_tx_cnt == 0)
1302 struct sge_softc *sc;
1303 struct mii_data *mii;
1307 SGE_LOCK_ASSERT(sc);
1310 mii = device_get_softc(sc->sge_miibus);
1312 if ((sc->sge_flags & SGE_FLAG_LINK) == 0) {
1313 sge_miibus_statchg(sc->sge_dev);
1314 if ((sc->sge_flags & SGE_FLAG_LINK) != 0 &&
1315 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1316 sge_start_locked(ifp);
1319 * Reclaim transmitted frames here as we do not request
1320 * Tx completion interrupt for every queued frames to
1321 * reduce excessive interrupts.
1325 callout_reset(&sc->sge_stat_ch, hz, sge_tick, sc);
1331 struct sge_softc *sc;
1339 status = CSR_READ_4(sc, IntrStatus);
1340 if (status == 0xFFFFFFFF || (status & SGE_INTRS) == 0) {
1345 /* Acknowledge interrupts. */
1346 CSR_WRITE_4(sc, IntrStatus, status);
1347 /* Disable further interrupts. */
1348 CSR_WRITE_4(sc, IntrMask, 0);
1350 * It seems the controller supports some kind of interrupt
1351 * moderation mechanism but we still don't know how to
1352 * enable that. To reduce number of generated interrupts
1353 * under load we check pending interrupts in a loop. This
1354 * will increase number of register access and is not correct
1355 * way to handle interrupt moderation but there seems to be
1356 * no other way at this time.
1359 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1361 if ((status & (INTR_RX_DONE | INTR_RX_IDLE)) != 0) {
1363 /* Wakeup Rx MAC. */
1364 if ((status & INTR_RX_IDLE) != 0)
1365 CSR_WRITE_4(sc, RX_CTL,
1366 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB);
1368 if ((status & (INTR_TX_DONE | INTR_TX_IDLE)) != 0)
1370 status = CSR_READ_4(sc, IntrStatus);
1371 if ((status & SGE_INTRS) == 0)
1373 /* Acknowledge interrupts. */
1374 CSR_WRITE_4(sc, IntrStatus, status);
1376 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1377 /* Re-enable interrupts */
1378 CSR_WRITE_4(sc, IntrMask, SGE_INTRS);
1379 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1380 sge_start_locked(ifp);
1386 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1387 * pointers to the fragment pointers.
1390 sge_encap(struct sge_softc *sc, struct mbuf **m_head)
1393 struct sge_desc *desc;
1394 struct sge_txdesc *txd;
1395 bus_dma_segment_t txsegs[SGE_MAXTXSEGS];
1396 uint32_t cflags, mss;
1397 int error, i, nsegs, prod, si;
1399 SGE_LOCK_ASSERT(sc);
1401 si = prod = sc->sge_cdata.sge_tx_prod;
1402 txd = &sc->sge_cdata.sge_txdesc[prod];
1403 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1404 struct ether_header *eh;
1407 uint32_t ip_off, poff;
1409 if (M_WRITABLE(*m_head) == 0) {
1410 /* Get a writable copy. */
1411 m = m_dup(*m_head, M_NOWAIT);
1419 ip_off = sizeof(struct ether_header);
1420 m = m_pullup(*m_head, ip_off);
1425 eh = mtod(m, struct ether_header *);
1426 /* Check the existence of VLAN tag. */
1427 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1428 ip_off = sizeof(struct ether_vlan_header);
1429 m = m_pullup(m, ip_off);
1435 m = m_pullup(m, ip_off + sizeof(struct ip));
1440 ip = (struct ip *)(mtod(m, char *) + ip_off);
1441 poff = ip_off + (ip->ip_hl << 2);
1442 m = m_pullup(m, poff + sizeof(struct tcphdr));
1447 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1448 m = m_pullup(m, poff + (tcp->th_off << 2));
1454 * Reset IP checksum and recompute TCP pseudo
1455 * checksum that NDIS specification requires.
1457 ip = (struct ip *)(mtod(m, char *) + ip_off);
1459 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1460 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1461 htons(IPPROTO_TCP));
1465 error = bus_dmamap_load_mbuf_sg(sc->sge_cdata.sge_txmbuf_tag,
1466 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1467 if (error == EFBIG) {
1468 m = m_collapse(*m_head, M_NOWAIT, SGE_MAXTXSEGS);
1475 error = bus_dmamap_load_mbuf_sg(sc->sge_cdata.sge_txmbuf_tag,
1476 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1482 } else if (error != 0)
1485 KASSERT(nsegs != 0, ("zero segment returned"));
1486 /* Check descriptor overrun. */
1487 if (sc->sge_cdata.sge_tx_cnt + nsegs >= SGE_TX_RING_CNT) {
1488 bus_dmamap_unload(sc->sge_cdata.sge_txmbuf_tag, txd->tx_dmamap);
1491 bus_dmamap_sync(sc->sge_cdata.sge_txmbuf_tag, txd->tx_dmamap,
1492 BUS_DMASYNC_PREWRITE);
1497 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1499 mss = (uint32_t)m->m_pkthdr.tso_segsz;
1502 if (m->m_pkthdr.csum_flags & CSUM_IP)
1503 cflags |= TDC_IP_CSUM;
1504 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1505 cflags |= TDC_TCP_CSUM;
1506 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1507 cflags |= TDC_UDP_CSUM;
1509 for (i = 0; i < nsegs; i++) {
1510 desc = &sc->sge_ldata.sge_tx_ring[prod];
1512 desc->sge_sts_size = htole32(m->m_pkthdr.len | mss);
1513 desc->sge_cmdsts = 0;
1515 desc->sge_sts_size = 0;
1516 desc->sge_cmdsts = htole32(TDC_OWN);
1518 desc->sge_ptr = htole32(SGE_ADDR_LO(txsegs[i].ds_addr));
1519 desc->sge_flags = htole32(txsegs[i].ds_len);
1520 if (prod == SGE_TX_RING_CNT - 1)
1521 desc->sge_flags |= htole32(RING_END);
1522 sc->sge_cdata.sge_tx_cnt++;
1523 SGE_INC(prod, SGE_TX_RING_CNT);
1525 /* Update producer index. */
1526 sc->sge_cdata.sge_tx_prod = prod;
1528 desc = &sc->sge_ldata.sge_tx_ring[si];
1529 /* Configure VLAN. */
1530 if((m->m_flags & M_VLANTAG) != 0) {
1531 cflags |= m->m_pkthdr.ether_vtag;
1532 desc->sge_sts_size |= htole32(TDS_INS_VLAN);
1534 desc->sge_cmdsts |= htole32(TDC_DEF | TDC_CRC | TDC_PAD | cflags);
1536 if ((sc->sge_flags & SGE_FLAG_SPEED_1000) != 0)
1537 desc->sge_cmdsts |= htole32(TDC_BST);
1539 if ((sc->sge_flags & SGE_FLAG_FDX) == 0) {
1540 desc->sge_cmdsts |= htole32(TDC_COL | TDC_CRS | TDC_BKF);
1541 if ((sc->sge_flags & SGE_FLAG_SPEED_1000) != 0)
1542 desc->sge_cmdsts |= htole32(TDC_EXT | TDC_BST);
1545 /* Request interrupt and give ownership to controller. */
1546 desc->sge_cmdsts |= htole32(TDC_OWN | TDC_INTR);
1548 txd->tx_ndesc = nsegs;
1553 sge_start(struct ifnet *ifp)
1555 struct sge_softc *sc;
1559 sge_start_locked(ifp);
1564 sge_start_locked(struct ifnet *ifp)
1566 struct sge_softc *sc;
1567 struct mbuf *m_head;
1571 SGE_LOCK_ASSERT(sc);
1573 if ((sc->sge_flags & SGE_FLAG_LINK) == 0 ||
1574 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1578 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1579 if (sc->sge_cdata.sge_tx_cnt > (SGE_TX_RING_CNT -
1581 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1584 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1587 if (sge_encap(sc, &m_head)) {
1590 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1591 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1596 * If there's a BPF listener, bounce a copy of this frame
1599 BPF_MTAP(ifp, m_head);
1603 bus_dmamap_sync(sc->sge_cdata.sge_tx_tag,
1604 sc->sge_cdata.sge_tx_dmamap,
1605 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1606 CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB | TX_CTL_POLL);
1614 struct sge_softc *sc;
1618 sge_init_locked(sc);
1623 sge_init_locked(struct sge_softc *sc)
1626 struct mii_data *mii;
1630 SGE_LOCK_ASSERT(sc);
1632 mii = device_get_softc(sc->sge_miibus);
1633 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1636 * Cancel pending I/O and free all RX/TX buffers.
1641 /* Init circular RX list. */
1642 if (sge_list_rx_init(sc) == ENOBUFS) {
1643 device_printf(sc->sge_dev, "no memory for Rx buffers\n");
1647 /* Init TX descriptors. */
1648 sge_list_tx_init(sc);
1650 * Load the address of the RX and TX lists.
1652 CSR_WRITE_4(sc, TX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_tx_paddr));
1653 CSR_WRITE_4(sc, RX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_rx_paddr));
1655 CSR_WRITE_4(sc, TxMacControl, 0x60);
1656 CSR_WRITE_4(sc, RxWakeOnLan, 0);
1657 CSR_WRITE_4(sc, RxWakeOnLanData, 0);
1658 /* Allow receiving VLAN frames. */
1659 CSR_WRITE_2(sc, RxMPSControl, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN +
1662 for (i = 0; i < ETHER_ADDR_LEN; i++)
1663 CSR_WRITE_1(sc, RxMacAddr + i, IF_LLADDR(ifp)[i]);
1664 /* Configure RX MAC. */
1665 rxfilt = RXMAC_STRIP_FCS | RXMAC_PAD_ENB | RXMAC_CSUM_ENB;
1666 CSR_WRITE_2(sc, RxMacControl, rxfilt);
1670 /* Initialize default speed/duplex information. */
1671 if ((sc->sge_flags & SGE_FLAG_FASTETHER) == 0)
1672 sc->sge_flags |= SGE_FLAG_SPEED_1000;
1673 sc->sge_flags |= SGE_FLAG_FDX;
1674 if ((sc->sge_flags & SGE_FLAG_RGMII) != 0)
1675 CSR_WRITE_4(sc, StationControl, 0x04008001);
1677 CSR_WRITE_4(sc, StationControl, 0x04000001);
1679 * XXX Try to mitigate interrupts.
1681 CSR_WRITE_4(sc, IntrControl, 0x08880000);
1683 if (sc->sge_intrcontrol != 0)
1684 CSR_WRITE_4(sc, IntrControl, sc->sge_intrcontrol);
1685 if (sc->sge_intrtimer != 0)
1686 CSR_WRITE_4(sc, IntrTimer, sc->sge_intrtimer);
1690 * Clear and enable interrupts.
1692 CSR_WRITE_4(sc, IntrStatus, 0xFFFFFFFF);
1693 CSR_WRITE_4(sc, IntrMask, SGE_INTRS);
1695 /* Enable receiver and transmitter. */
1696 CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB);
1697 CSR_WRITE_4(sc, RX_CTL, 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB);
1699 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1700 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1702 sc->sge_flags &= ~SGE_FLAG_LINK;
1704 callout_reset(&sc->sge_stat_ch, hz, sge_tick, sc);
1708 * Set media options.
1711 sge_ifmedia_upd(struct ifnet *ifp)
1713 struct sge_softc *sc;
1714 struct mii_data *mii;
1715 struct mii_softc *miisc;
1720 mii = device_get_softc(sc->sge_miibus);
1721 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1723 error = mii_mediachg(mii);
1730 * Report current media status.
1733 sge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1735 struct sge_softc *sc;
1736 struct mii_data *mii;
1740 mii = device_get_softc(sc->sge_miibus);
1741 if ((ifp->if_flags & IFF_UP) == 0) {
1746 ifmr->ifm_active = mii->mii_media_active;
1747 ifmr->ifm_status = mii->mii_media_status;
1752 sge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1754 struct sge_softc *sc;
1756 struct mii_data *mii;
1757 int error = 0, mask, reinit;
1760 ifr = (struct ifreq *)data;
1765 if ((ifp->if_flags & IFF_UP) != 0) {
1766 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1767 ((ifp->if_flags ^ sc->sge_if_flags) &
1768 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1771 sge_init_locked(sc);
1772 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1774 sc->sge_if_flags = ifp->if_flags;
1780 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1781 if ((mask & IFCAP_TXCSUM) != 0 &&
1782 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1783 ifp->if_capenable ^= IFCAP_TXCSUM;
1784 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1785 ifp->if_hwassist |= SGE_CSUM_FEATURES;
1787 ifp->if_hwassist &= ~SGE_CSUM_FEATURES;
1789 if ((mask & IFCAP_RXCSUM) != 0 &&
1790 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
1791 ifp->if_capenable ^= IFCAP_RXCSUM;
1792 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1793 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1794 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1795 if ((mask & IFCAP_TSO4) != 0 &&
1796 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
1797 ifp->if_capenable ^= IFCAP_TSO4;
1798 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
1799 ifp->if_hwassist |= CSUM_TSO;
1801 ifp->if_hwassist &= ~CSUM_TSO;
1803 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1804 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1805 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1806 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1807 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1809 * Due to unknown reason, toggling VLAN hardware
1810 * tagging require interface reinitialization.
1812 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1813 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
1814 ifp->if_capenable &=
1815 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
1818 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1819 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1820 sge_init_locked(sc);
1823 VLAN_CAPABILITIES(ifp);
1828 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1834 mii = device_get_softc(sc->sge_miibus);
1835 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1838 error = ether_ioctl(ifp, command, data);
1846 sge_watchdog(struct sge_softc *sc)
1850 SGE_LOCK_ASSERT(sc);
1851 if (sc->sge_timer == 0 || --sc->sge_timer > 0)
1855 if ((sc->sge_flags & SGE_FLAG_LINK) == 0) {
1856 if (1 || bootverbose)
1857 device_printf(sc->sge_dev,
1858 "watchdog timeout (lost link)\n");
1860 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1861 sge_init_locked(sc);
1864 device_printf(sc->sge_dev, "watchdog timeout\n");
1867 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1868 sge_init_locked(sc);
1869 if (!IFQ_DRV_IS_EMPTY(&sc->sge_ifp->if_snd))
1870 sge_start_locked(ifp);
1874 * Stop the adapter and free any mbufs allocated to the
1878 sge_stop(struct sge_softc *sc)
1884 SGE_LOCK_ASSERT(sc);
1887 callout_stop(&sc->sge_stat_ch);
1888 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1890 CSR_WRITE_4(sc, IntrMask, 0);
1891 CSR_READ_4(sc, IntrMask);
1892 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
1893 /* Stop TX/RX MAC. */
1894 CSR_WRITE_4(sc, TX_CTL, 0x1a00);
1895 CSR_WRITE_4(sc, RX_CTL, 0x1a00);
1896 /* XXX Can we assume active DMA cycles gone? */
1898 CSR_WRITE_4(sc, IntrMask, 0);
1899 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
1901 sc->sge_flags &= ~SGE_FLAG_LINK;
1902 sge_list_rx_free(sc);
1903 sge_list_tx_free(sc);