sys/dev/siba/siba_core.c

   1 /*-
   2  * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  *
  16  * NO WARRANTY
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27  * THE POSSIBILITY OF SUCH DAMAGES.
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 /*
  34  * the Sonics Silicon Backplane driver.
  35  */
  36
  37 #include <sys/param.h>
  38 #include <sys/systm.h>
  39 #include <sys/malloc.h>
  40 #include <sys/module.h>
  41 #include <sys/kernel.h>
  42 #include <sys/endian.h>
  43 #include <sys/errno.h>
  44 #include <sys/lock.h>
  45 #include <sys/mutex.h>
  46 #include <machine/bus.h>
  47 #include <machine/resource.h>
  48 #include <sys/bus.h>
  49 #include <sys/rman.h>
  50 #include <sys/socket.h>
  51
  52 #include <net/if.h>
  53 #include <net/if_media.h>
  54 #include <net/if_arp.h>
  55
  56 #include <dev/pci/pcivar.h>
  57 #include <dev/pci/pcireg.h>
  58
  59 #include <dev/siba/siba_ids.h>
  60 #include <dev/siba/sibareg.h>
  61 #include <dev/siba/sibavar.h>
  62
  63 #ifdef SIBA_DEBUG
  64 enum {
  65         SIBA_DEBUG_SCAN         = 0x00000001,   /* scan */
  66         SIBA_DEBUG_PMU          = 0x00000002,   /* PMU */
  67         SIBA_DEBUG_PLL          = 0x00000004,   /* PLL */
  68         SIBA_DEBUG_SWITCHCORE   = 0x00000008,   /* switching core */
  69         SIBA_DEBUG_SPROM        = 0x00000010,   /* SPROM */
  70         SIBA_DEBUG_CORE         = 0x00000020,   /* handling cores */
  71         SIBA_DEBUG_ANY          = 0xffffffff
  72 };
  73 #define DPRINTF(siba, m, fmt, ...) do {                 \
  74         if (siba->siba_debug & (m))                     \
  75                 printf(fmt, __VA_ARGS__);               \
  76 } while (0)
  77 #else
  78 #define DPRINTF(siba, m, fmt, ...) do { (void) siba; } while (0)
  79 #endif
  80 #define N(a)                    (sizeof(a) / sizeof(a[0]))
  81
  82 static void     siba_pci_gpio(struct siba_softc *, uint32_t, int);
  83 static void     siba_scan(struct siba_softc *);
  84 static int      siba_switchcore(struct siba_softc *, uint8_t);
  85 static int      siba_pci_switchcore_sub(struct siba_softc *, uint8_t);
  86 static uint32_t siba_scan_read_4(struct siba_softc *, uint8_t, uint16_t);
  87 static uint16_t siba_dev2chipid(struct siba_softc *);
  88 static uint16_t siba_pci_read_2(struct siba_dev_softc *, uint16_t);
  89 static uint32_t siba_pci_read_4(struct siba_dev_softc *, uint16_t);
  90 static void     siba_pci_write_2(struct siba_dev_softc *, uint16_t, uint16_t);
  91 static void     siba_pci_write_4(struct siba_dev_softc *, uint16_t, uint32_t);
  92 static void     siba_cc_clock(struct siba_cc *,
  93                     enum siba_clock);
  94 static void     siba_cc_pmu_init(struct siba_cc *);
  95 static void     siba_cc_power_init(struct siba_cc *);
  96 static void     siba_cc_powerup_delay(struct siba_cc *);
  97 static int      siba_cc_clockfreq(struct siba_cc *, int);
  98 static void     siba_cc_pmu1_pll0_init(struct siba_cc *, uint32_t);
  99 static void     siba_cc_pmu0_pll0_init(struct siba_cc *, uint32_t);
 100 static enum siba_clksrc siba_cc_clksrc(struct siba_cc *);
 101 static const struct siba_cc_pmu1_plltab *siba_cc_pmu1_plltab_find(uint32_t);
 102 static uint32_t siba_cc_pll_read(struct siba_cc *, uint32_t);
 103 static void     siba_cc_pll_write(struct siba_cc *, uint32_t,
 104                     uint32_t);
 105 static const struct siba_cc_pmu0_plltab *
 106                 siba_cc_pmu0_plltab_findentry(uint32_t);
 107 static int      siba_pci_sprom(struct siba_softc *, struct siba_sprom *);
 108 static int      siba_sprom_read(struct siba_softc *, uint16_t *, uint16_t);
 109 static int      sprom_check_crc(const uint16_t *, size_t);
 110 static uint8_t  siba_crc8(uint8_t, uint8_t);
 111 static void     siba_sprom_r123(struct siba_sprom *, const uint16_t *);
 112 static void     siba_sprom_r45(struct siba_sprom *, const uint16_t *);
 113 static void     siba_sprom_r8(struct siba_sprom *, const uint16_t *);
 114 static int8_t   siba_sprom_r123_antgain(uint8_t, const uint16_t *, uint16_t,
 115                     uint16_t);
 116 static uint32_t siba_tmslow_reject_bitmask(struct siba_dev_softc *);
 117 static uint32_t siba_pcicore_read_4(struct siba_pci *, uint16_t);
 118 static void     siba_pcicore_write_4(struct siba_pci *, uint16_t, uint32_t);
 119 static uint32_t siba_pcie_read(struct siba_pci *, uint32_t);
 120 static void     siba_pcie_write(struct siba_pci *, uint32_t, uint32_t);
 121 static void     siba_pcie_mdio_write(struct siba_pci *, uint8_t, uint8_t,
 122                     uint16_t);
 123 static void     siba_pci_read_multi_1(struct siba_dev_softc *, void *, size_t,
 124                     uint16_t);
 125 static void     siba_pci_read_multi_2(struct siba_dev_softc *, void *, size_t,
 126                     uint16_t);
 127 static void     siba_pci_read_multi_4(struct siba_dev_softc *, void *, size_t,
 128                     uint16_t);
 129 static void     siba_pci_write_multi_1(struct siba_dev_softc *, const void *,
 130                     size_t, uint16_t);
 131 static void     siba_pci_write_multi_2(struct siba_dev_softc *, const void *,
 132                     size_t, uint16_t);
 133 static void     siba_pci_write_multi_4(struct siba_dev_softc *, const void *,
 134                     size_t, uint16_t);
 135 static const char *siba_core_name(uint16_t);
 136 static void     siba_pcicore_init(struct siba_pci *);
 137 static uint32_t siba_read_4_sub(struct siba_dev_softc *, uint16_t);
 138 static void     siba_write_4_sub(struct siba_dev_softc *, uint16_t, uint32_t);
 139 static void     siba_powerup_sub(struct siba_softc *, int);
 140 static int      siba_powerdown_sub(struct siba_softc *);
 141 static int      siba_dev_isup_sub(struct siba_dev_softc *);
 142 static void     siba_dev_up_sub(struct siba_dev_softc *, uint32_t);
 143 static void     siba_dev_down_sub(struct siba_dev_softc *, uint32_t);
 144 int             siba_core_attach(struct siba_softc *);
 145 int             siba_core_detach(struct siba_softc *);
 146 int             siba_core_suspend(struct siba_softc *);
 147 int             siba_core_resume(struct siba_softc *);
 148 uint8_t         siba_getncores(device_t, uint16_t);
 149
 150 static const struct siba_bus_ops siba_pci_ops = {
 151         .read_2         = siba_pci_read_2,
 152         .read_4         = siba_pci_read_4,
 153         .write_2        = siba_pci_write_2,
 154         .write_4        = siba_pci_write_4,
 155         .read_multi_1   = siba_pci_read_multi_1,
 156         .read_multi_2   = siba_pci_read_multi_2,
 157         .read_multi_4   = siba_pci_read_multi_4,
 158         .write_multi_1  = siba_pci_write_multi_1,
 159         .write_multi_2  = siba_pci_write_multi_2,
 160         .write_multi_4  = siba_pci_write_multi_4,
 161 };
 162
 163 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4325_updown[] =
 164     SIBA_CC_PMU_4325_RES_UPDOWN;
 165 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4325_depend[] =
 166     SIBA_CC_PMU_4325_RES_DEPEND;
 167 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4328_updown[] =
 168     SIBA_CC_PMU_4328_RES_UPDOWN;
 169 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4328_depend[] =
 170     SIBA_CC_PMU_4328_RES_DEPEND;
 171 static const struct siba_cc_pmu0_plltab siba_cc_pmu0_plltab[] =
 172     SIBA_CC_PMU0_PLLTAB_ENTRY;
 173 static const struct siba_cc_pmu1_plltab siba_cc_pmu1_plltab[] =
 174     SIBA_CC_PMU1_PLLTAB_ENTRY;
 175
 176 int
 177 siba_core_attach(struct siba_softc *siba)
 178 {
 179         struct siba_cc *scc;
 180         int error;
 181
 182         KASSERT(siba->siba_type == SIBA_TYPE_PCI,
 183             ("unsupported BUS type (%#x)", siba->siba_type));
 184
 185         siba->siba_ops = &siba_pci_ops;
 186
 187         siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1);
 188         siba_scan(siba);
 189
 190         /* XXX init PCI or PCMCIA host devices */
 191
 192         siba_powerup_sub(siba, 0);
 193
 194         /* init ChipCommon */
 195         scc = &siba->siba_cc;
 196         if (scc->scc_dev != NULL) {
 197                 siba_cc_pmu_init(scc);
 198                 siba_cc_power_init(scc);
 199                 siba_cc_clock(scc, SIBA_CLOCK_FAST);
 200                 siba_cc_powerup_delay(scc);
 201         }
 202
 203         error = siba_pci_sprom(siba, &siba->siba_sprom);
 204         if (error) {
 205                 siba_powerdown_sub(siba);
 206                 return (error);
 207         }
 208
 209         siba_pcicore_init(&siba->siba_pci);
 210         siba_powerdown_sub(siba);
 211
 212         return (bus_generic_attach(siba->siba_dev));
 213 }
 214
 215 int
 216 siba_core_detach(struct siba_softc *siba)
 217 {
 218         /* detach & delete all children */
 219         device_delete_children(siba->siba_dev);
 220         return (0);
 221 }
 222
 223 static void
 224 siba_pci_gpio(struct siba_softc *siba, uint32_t what, int on)
 225 {
 226         uint32_t in, out;
 227         uint16_t status;
 228
 229         if (siba->siba_type != SIBA_TYPE_PCI)
 230                 return;
 231
 232         out = pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4);
 233         if (on == 0) {
 234                 if (what & SIBA_GPIO_PLL)
 235                         out |= SIBA_GPIO_PLL;
 236                 if (what & SIBA_GPIO_CRYSTAL)
 237                         out &= ~SIBA_GPIO_CRYSTAL;
 238                 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
 239                 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT_EN,
 240                     pci_read_config(siba->siba_dev,
 241                         SIBA_GPIO_OUT_EN, 4) | what, 4);
 242                 return;
 243         }
 244
 245         in = pci_read_config(siba->siba_dev, SIBA_GPIO_IN, 4);
 246         if ((in & SIBA_GPIO_CRYSTAL) != SIBA_GPIO_CRYSTAL) {
 247                 if (what & SIBA_GPIO_CRYSTAL) {
 248                         out |= SIBA_GPIO_CRYSTAL;
 249                         if (what & SIBA_GPIO_PLL)
 250                                 out |= SIBA_GPIO_PLL;
 251                         pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
 252                         pci_write_config(siba->siba_dev,
 253                             SIBA_GPIO_OUT_EN, pci_read_config(siba->siba_dev,
 254                                 SIBA_GPIO_OUT_EN, 4) | what, 4);
 255                         DELAY(1000);
 256                 }
 257                 if (what & SIBA_GPIO_PLL) {
 258                         out &= ~SIBA_GPIO_PLL;
 259                         pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
 260                         DELAY(5000);
 261                 }
 262         }
 263
 264         status = pci_read_config(siba->siba_dev, PCIR_STATUS, 2);
 265         status &= ~PCIM_STATUS_STABORT;
 266         pci_write_config(siba->siba_dev, PCIR_STATUS, status, 2);
 267 }
 268
 269 static void
 270 siba_scan(struct siba_softc *siba)
 271 {
 272         struct siba_dev_softc *sd;
 273         uint32_t idhi, tmp;
 274         device_t child;
 275         int base, dev_i = 0, error, i, is_pcie, n_80211 = 0, n_cc = 0,
 276             n_pci = 0;
 277
 278         KASSERT(siba->siba_type == SIBA_TYPE_PCI,
 279             ("unsupported BUS type (%#x)", siba->siba_type));
 280
 281         siba->siba_ndevs = 0;
 282         error = siba_switchcore(siba, 0); /* need the first core */
 283         if (error)
 284                 return;
 285
 286         idhi = siba_scan_read_4(siba, 0, SIBA_IDHIGH);
 287         if (SIBA_IDHIGH_CORECODE(idhi) == SIBA_DEVID_CHIPCOMMON) {
 288                 tmp = siba_scan_read_4(siba, 0, SIBA_CC_CHIPID);
 289                 siba->siba_chipid = SIBA_CC_ID(tmp);
 290                 siba->siba_chiprev = SIBA_CC_REV(tmp);
 291                 siba->siba_chippkg = SIBA_CC_PKG(tmp);
 292                 if (SIBA_IDHIGH_REV(idhi) >= 4)
 293                         siba->siba_ndevs = SIBA_CC_NCORES(tmp);
 294                 siba->siba_cc.scc_caps = siba_scan_read_4(siba, 0,
 295                     SIBA_CC_CAPS);
 296         } else {
 297                 if (siba->siba_type == SIBA_TYPE_PCI) {
 298                         siba->siba_chipid = siba_dev2chipid(siba);
 299                         siba->siba_chiprev = pci_read_config(siba->siba_dev,
 300                             PCIR_REVID, 2);
 301                         siba->siba_chippkg = 0;
 302                 } else {
 303                         siba->siba_chipid = 0x4710;
 304                         siba->siba_chiprev = 0;
 305                         siba->siba_chippkg = 0;
 306                 }
 307         }
 308         if (siba->siba_ndevs == 0)
 309                 siba->siba_ndevs = siba_getncores(siba->siba_dev,
 310                     siba->siba_chipid);
 311         if (siba->siba_ndevs > SIBA_MAX_CORES) {
 312                 device_printf(siba->siba_dev,
 313                     "too many siba cores (max %d %d)\n",
 314                     SIBA_MAX_CORES, siba->siba_ndevs);
 315                 return;
 316         }
 317
 318         /* looking basic information about each cores/devices */
 319         for (i = 0; i < siba->siba_ndevs; i++) {
 320                 error = siba_switchcore(siba, i);
 321                 if (error)
 322                         return;
 323                 sd = &(siba->siba_devs[dev_i]);
 324                 idhi = siba_scan_read_4(siba, i, SIBA_IDHIGH);
 325                 sd->sd_bus = siba;
 326                 sd->sd_id.sd_device = SIBA_IDHIGH_CORECODE(idhi);
 327                 sd->sd_id.sd_rev = SIBA_IDHIGH_REV(idhi);
 328                 sd->sd_id.sd_vendor = SIBA_IDHIGH_VENDOR(idhi);
 329                 sd->sd_ops = siba->siba_ops;
 330                 sd->sd_coreidx = i;
 331
 332                 DPRINTF(siba, SIBA_DEBUG_SCAN,
 333                     "core %d (%s) found (cc %#xrev %#x vendor %#x)\n",
 334                     i, siba_core_name(sd->sd_id.sd_device),
 335                     sd->sd_id.sd_device, sd->sd_id.sd_rev, sd->sd_id.vendor);
 336
 337                 switch (sd->sd_id.sd_device) {
 338                 case SIBA_DEVID_CHIPCOMMON:
 339                         n_cc++;
 340                         if (n_cc > 1) {
 341                                 device_printf(siba->siba_dev,
 342                                     "warn: multiple ChipCommon\n");
 343                                 break;
 344                         }
 345                         siba->siba_cc.scc_dev = sd;
 346                         break;
 347                 case SIBA_DEVID_80211:
 348                         n_80211++;
 349                         if (n_80211 > 1) {
 350                                 device_printf(siba->siba_dev,
 351                                     "warn: multiple 802.11 core\n");
 352                                 continue;
 353                         }
 354                         break;
 355                 case SIBA_DEVID_PCI:
 356                 case SIBA_DEVID_PCIE:
 357                         n_pci++;
 358                         error = pci_find_cap(siba->siba_dev, PCIY_EXPRESS,
 359                             &base);
 360                         is_pcie = (error == 0) ? 1 : 0;
 361
 362                         if (n_pci > 1) {
 363                                 device_printf(siba->siba_dev,
 364                                     "warn: multiple PCI(E) cores\n");
 365                                 break;
 366                         }
 367                         if (sd->sd_id.sd_device == SIBA_DEVID_PCI &&
 368                             is_pcie == 1)
 369                                 continue;
 370                         if (sd->sd_id.sd_device == SIBA_DEVID_PCIE &&
 371                             is_pcie == 0)
 372                                 continue;
 373                         siba->siba_pci.spc_dev = sd;
 374                         break;
 375                 case SIBA_DEVID_MODEM:
 376                 case SIBA_DEVID_PCMCIA:
 377                         break;
 378                 default:
 379                         device_printf(siba->siba_dev,
 380                             "unsupported coreid (%s)\n",
 381                             siba_core_name(sd->sd_id.sd_device));
 382                         break;
 383                 }
 384                 dev_i++;
 385
 386                 child = device_add_child(siba->siba_dev, NULL, -1);
 387                 if (child == NULL) {
 388                         device_printf(siba->siba_dev, "child attach failed\n");
 389                         continue;
 390                 }
 391
 392                 device_set_ivars(child, sd);
 393         }
 394         siba->siba_ndevs = dev_i;
 395 }
 396
 397 static int
 398 siba_switchcore(struct siba_softc *siba, uint8_t idx)
 399 {
 400
 401         switch (siba->siba_type) {
 402         case SIBA_TYPE_PCI:
 403                 return (siba_pci_switchcore_sub(siba, idx));
 404         default:
 405                 KASSERT(0 == 1,
 406                     ("%s: unsupported bustype %#x", __func__,
 407                     siba->siba_type));
 408         }
 409         return (0);
 410 }
 411
 412 static int
 413 siba_pci_switchcore_sub(struct siba_softc *siba, uint8_t idx)
 414 {
 415 #define RETRY_MAX       50
 416         int i;
 417         uint32_t dir;
 418
 419         dir = SIBA_REGWIN(idx);
 420
 421         for (i = 0; i < RETRY_MAX; i++) {
 422                 pci_write_config(siba->siba_dev, SIBA_BAR0, dir, 4);
 423                 if (pci_read_config(siba->siba_dev, SIBA_BAR0, 4) == dir)
 424                         return (0);
 425                 DELAY(10);
 426         }
 427         return (ENODEV);
 428 #undef RETRY_MAX
 429 }
 430
 431 static int
 432 siba_pci_switchcore(struct siba_softc *siba, struct siba_dev_softc *sd)
 433 {
 434         int error;
 435
 436         DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "Switching to %s core, index %d\n",
 437             siba_core_name(sd->sd_id.sd_device), sd->sd_coreidx);
 438
 439         error = siba_pci_switchcore_sub(siba, sd->sd_coreidx);
 440         if (error == 0)
 441                 siba->siba_curdev = sd;
 442
 443         return (error);
 444 }
 445
 446 static uint32_t
 447 siba_scan_read_4(struct siba_softc *siba, uint8_t coreidx,
 448     uint16_t offset)
 449 {
 450
 451         (void)coreidx;
 452         KASSERT(siba->siba_type == SIBA_TYPE_PCI,
 453             ("unsupported BUS type (%#x)", siba->siba_type));
 454
 455         return (SIBA_READ_4(siba, offset));
 456 }
 457
 458 static uint16_t
 459 siba_dev2chipid(struct siba_softc *siba)
 460 {
 461         uint16_t chipid = 0;
 462
 463         switch (siba->siba_pci_did) {
 464         case 0x4301:
 465                 chipid = 0x4301;
 466                 break;
 467         case 0x4305:
 468         case 0x4306:
 469         case 0x4307:
 470                 chipid = 0x4307;
 471                 break;
 472         case 0x4403:
 473                 chipid = 0x4402;
 474                 break;
 475         case 0x4610:
 476         case 0x4611:
 477         case 0x4612:
 478         case 0x4613:
 479         case 0x4614:
 480         case 0x4615:
 481                 chipid = 0x4610;
 482                 break;
 483         case 0x4710:
 484         case 0x4711:
 485         case 0x4712:
 486         case 0x4713:
 487         case 0x4714:
 488         case 0x4715:
 489                 chipid = 0x4710;
 490                 break;
 491         case 0x4320:
 492         case 0x4321:
 493         case 0x4322:
 494         case 0x4323:
 495         case 0x4324:
 496         case 0x4325:
 497                 chipid = 0x4309;
 498                 break;
 499         case PCI_DEVICE_ID_BCM4401:
 500         case PCI_DEVICE_ID_BCM4401B0:
 501         case PCI_DEVICE_ID_BCM4401B1:
 502                 chipid = 0x4401;
 503                 break;
 504         default:
 505                 device_printf(siba->siba_dev, "unknown PCI did (%d)\n",
 506                     siba->siba_pci_did);
 507         }
 508
 509         return (chipid);
 510 }
 511
 512 /*
 513  * Earlier ChipCommon revisions have hardcoded number of cores
 514  * present dependent on the ChipCommon ID.
 515  */
 516 uint8_t
 517 siba_getncores(device_t dev, uint16_t chipid)
 518 {
 519         switch (chipid) {
 520         case 0x4401:
 521         case 0x4402:
 522                 return (3);
 523         case 0x4301:
 524         case 0x4307:
 525                 return (5);
 526         case 0x4306:
 527                 return (6);
 528         case SIBA_CCID_SENTRY5:
 529                 return (7);
 530         case 0x4310:
 531                 return (8);
 532         case SIBA_CCID_BCM4710:
 533         case 0x4610:
 534         case SIBA_CCID_BCM4704:
 535                 return (9);
 536         default:
 537                 device_printf(dev, "unknown the chipset ID %#x\n", chipid);
 538         }
 539
 540         return (1);
 541 }
 542
 543 static const char *
 544 siba_core_name(uint16_t coreid)
 545 {
 546
 547         switch (coreid) {
 548         case SIBA_DEVID_CHIPCOMMON:
 549                 return ("ChipCommon");
 550         case SIBA_DEVID_ILINE20:
 551                 return ("ILine 20");
 552         case SIBA_DEVID_SDRAM:
 553                 return ("SDRAM");
 554         case SIBA_DEVID_PCI:
 555                 return ("PCI");
 556         case SIBA_DEVID_MIPS:
 557                 return ("MIPS");
 558         case SIBA_DEVID_ETHERNET:
 559                 return ("Fast Ethernet");
 560         case SIBA_DEVID_MODEM:
 561                 return ("Modem");
 562         case SIBA_DEVID_USB11_HOSTDEV:
 563                 return ("USB 1.1 Hostdev");
 564         case SIBA_DEVID_ADSL:
 565                 return ("ADSL");
 566         case SIBA_DEVID_ILINE100:
 567                 return ("ILine 100");
 568         case SIBA_DEVID_IPSEC:
 569                 return ("IPSEC");
 570         case SIBA_DEVID_PCMCIA:
 571                 return ("PCMCIA");
 572         case SIBA_DEVID_INTERNAL_MEM:
 573                 return ("Internal Memory");
 574         case SIBA_DEVID_SDRAMDDR:
 575                 return ("MEMC SDRAM");
 576         case SIBA_DEVID_EXTIF:
 577                 return ("EXTIF");
 578         case SIBA_DEVID_80211:
 579                 return ("IEEE 802.11");
 580         case SIBA_DEVID_MIPS_3302:
 581                 return ("MIPS 3302");
 582         case SIBA_DEVID_USB11_HOST:
 583                 return ("USB 1.1 Host");
 584         case SIBA_DEVID_USB11_DEV:
 585                 return ("USB 1.1 Device");
 586         case SIBA_DEVID_USB20_HOST:
 587                 return ("USB 2.0 Host");
 588         case SIBA_DEVID_USB20_DEV:
 589                 return ("USB 2.0 Device");
 590         case SIBA_DEVID_SDIO_HOST:
 591                 return ("SDIO Host");
 592         case SIBA_DEVID_ROBOSWITCH:
 593                 return ("Roboswitch");
 594         case SIBA_DEVID_PARA_ATA:
 595                 return ("PATA");
 596         case SIBA_DEVID_SATA_XORDMA:
 597                 return ("SATA XOR-DMA");
 598         case SIBA_DEVID_ETHERNET_GBIT:
 599                 return ("GBit Ethernet");
 600         case SIBA_DEVID_PCIE:
 601                 return ("PCI-Express");
 602         case SIBA_DEVID_MIMO_PHY:
 603                 return ("MIMO PHY");
 604         case SIBA_DEVID_SRAM_CTRLR:
 605                 return ("SRAM Controller");
 606         case SIBA_DEVID_MINI_MACPHY:
 607                 return ("Mini MACPHY");
 608         case SIBA_DEVID_ARM_1176:
 609                 return ("ARM 1176");
 610         case SIBA_DEVID_ARM_7TDMI:
 611                 return ("ARM 7TDMI");
 612         }
 613         return ("unknown");
 614 }
 615
 616 static uint16_t
 617 siba_pci_read_2(struct siba_dev_softc *sd, uint16_t offset)
 618 {
 619         struct siba_softc *siba = sd->sd_bus;
 620
 621         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 622                 return (0xffff);
 623
 624         return (SIBA_READ_2(siba, offset));
 625 }
 626
 627 static uint32_t
 628 siba_pci_read_4(struct siba_dev_softc *sd, uint16_t offset)
 629 {
 630         struct siba_softc *siba = sd->sd_bus;
 631
 632         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 633                 return (0xffff);
 634
 635         return (SIBA_READ_4(siba, offset));
 636 }
 637
 638 static void
 639 siba_pci_write_2(struct siba_dev_softc *sd, uint16_t offset, uint16_t value)
 640 {
 641         struct siba_softc *siba = sd->sd_bus;
 642
 643         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 644                 return;
 645
 646         SIBA_WRITE_2(siba, offset, value);
 647 }
 648
 649 static void
 650 siba_pci_write_4(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
 651 {
 652         struct siba_softc *siba = sd->sd_bus;
 653
 654         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 655                 return;
 656
 657         SIBA_WRITE_4(siba, offset, value);
 658 }
 659
 660 static void
 661 siba_pci_read_multi_1(struct siba_dev_softc *sd, void *buffer, size_t count,
 662     uint16_t offset)
 663 {
 664         struct siba_softc *siba = sd->sd_bus;
 665
 666         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
 667                 memset(buffer, 0xff, count);
 668                 return;
 669         }
 670
 671         SIBA_READ_MULTI_1(siba, offset, buffer, count);
 672 }
 673
 674 static void
 675 siba_pci_read_multi_2(struct siba_dev_softc *sd, void *buffer, size_t count,
 676     uint16_t offset)
 677 {
 678         struct siba_softc *siba = sd->sd_bus;
 679
 680         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
 681                 memset(buffer, 0xff, count);
 682                 return;
 683         }
 684
 685         KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__));
 686         SIBA_READ_MULTI_2(siba, offset, buffer, count >> 1);
 687 }
 688
 689 static void
 690 siba_pci_read_multi_4(struct siba_dev_softc *sd, void *buffer, size_t count,
 691     uint16_t offset)
 692 {
 693         struct siba_softc *siba = sd->sd_bus;
 694
 695         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
 696                 memset(buffer, 0xff, count);
 697                 return;
 698         }
 699
 700         KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__));
 701         SIBA_READ_MULTI_4(siba, offset, buffer, count >> 2);
 702 }
 703
 704 static void
 705 siba_pci_write_multi_1(struct siba_dev_softc *sd, const void *buffer,
 706     size_t count, uint16_t offset)
 707 {
 708         struct siba_softc *siba = sd->sd_bus;
 709
 710         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 711                 return;
 712
 713         SIBA_WRITE_MULTI_1(siba, offset, buffer, count);
 714 }
 715
 716 static void
 717 siba_pci_write_multi_2(struct siba_dev_softc *sd, const void *buffer,
 718     size_t count, uint16_t offset)
 719 {
 720         struct siba_softc *siba = sd->sd_bus;
 721
 722         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 723                 return;
 724
 725         KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__));
 726         SIBA_WRITE_MULTI_2(siba, offset, buffer, count >> 1);
 727 }
 728
 729 static void
 730 siba_pci_write_multi_4(struct siba_dev_softc *sd, const void *buffer,
 731     size_t count, uint16_t offset)
 732 {
 733         struct siba_softc *siba = sd->sd_bus;
 734
 735         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 736                 return;
 737
 738         KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__));
 739         SIBA_WRITE_MULTI_4(siba, offset, buffer, count >> 2);
 740 }
 741
 742 void
 743 siba_powerup(device_t dev, int dynamic)
 744 {
 745         struct siba_dev_softc *sd = device_get_ivars(dev);
 746         struct siba_softc *siba = sd->sd_bus;
 747
 748         siba_powerup_sub(siba, dynamic);
 749 }
 750
 751 static void
 752 siba_powerup_sub(struct siba_softc *siba, int dynamic)
 753 {
 754
 755         siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1);
 756         siba_cc_clock(&siba->siba_cc,
 757             (dynamic != 0) ? SIBA_CLOCK_DYNAMIC : SIBA_CLOCK_FAST);
 758 }
 759
 760 static void
 761 siba_cc_clock(struct siba_cc *scc, enum siba_clock clock)
 762 {
 763         struct siba_dev_softc *sd = scc->scc_dev;
 764         struct siba_softc *siba;
 765         uint32_t tmp;
 766
 767         if (sd == NULL)
 768                 return;
 769         siba = sd->sd_bus;
 770         /*
 771          * chipcommon < r6 (no dynamic clock control)
 772          * chipcommon >= r10 (unknown)
 773          */
 774         if (sd->sd_id.sd_rev < 6 || sd->sd_id.sd_rev >= 10 ||
 775             (scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
 776                 return;
 777
 778         switch (clock) {
 779         case SIBA_CLOCK_DYNAMIC:
 780                 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) &
 781                     ~(SIBA_CC_CLKSLOW_ENXTAL | SIBA_CC_CLKSLOW_FSLOW |
 782                     SIBA_CC_CLKSLOW_IPLL);
 783                 if ((tmp & SIBA_CC_CLKSLOW_SRC) != SIBA_CC_CLKSLOW_SRC_CRYSTAL)
 784                         tmp |= SIBA_CC_CLKSLOW_ENXTAL;
 785                 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp);
 786                 if (tmp & SIBA_CC_CLKSLOW_ENXTAL)
 787                         siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 0);
 788                 break;
 789         case SIBA_CLOCK_SLOW:
 790                 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
 791                     SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
 792                     SIBA_CC_CLKSLOW_FSLOW);
 793                 break;
 794         case SIBA_CLOCK_FAST:
 795                 /* crystal on */
 796                 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 1);
 797                 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
 798                     (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
 799                         SIBA_CC_CLKSLOW_IPLL) & ~SIBA_CC_CLKSLOW_FSLOW);
 800                 break;
 801         default:
 802                 KASSERT(0 == 1,
 803                     ("%s: unsupported clock %#x", __func__, clock));
 804         }
 805 }
 806
 807 uint16_t
 808 siba_read_2(device_t dev, uint16_t offset)
 809 {
 810         struct siba_dev_softc *sd = device_get_ivars(dev);
 811
 812         return (sd->sd_ops->read_2(sd, offset));
 813 }
 814
 815 uint32_t
 816 siba_read_4(device_t dev, uint16_t offset)
 817 {
 818         struct siba_dev_softc *sd = device_get_ivars(dev);
 819
 820         return (siba_read_4_sub(sd, offset));
 821 }
 822
 823 static uint32_t
 824 siba_read_4_sub(struct siba_dev_softc *sd, uint16_t offset)
 825 {
 826
 827         return (sd->sd_ops->read_4(sd, offset));
 828 }
 829
 830 void
 831 siba_write_2(device_t dev, uint16_t offset, uint16_t value)
 832 {
 833         struct siba_dev_softc *sd = device_get_ivars(dev);
 834
 835         sd->sd_ops->write_2(sd, offset, value);
 836 }
 837
 838 void
 839 siba_write_4(device_t dev, uint16_t offset, uint32_t value)
 840 {
 841         struct siba_dev_softc *sd = device_get_ivars(dev);
 842
 843         return (siba_write_4_sub(sd, offset, value));
 844 }
 845
 846 static void
 847 siba_write_4_sub(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
 848 {
 849
 850         sd->sd_ops->write_4(sd, offset, value);
 851 }
 852
 853 void
 854 siba_read_multi_1(device_t dev, void *buffer, size_t count,
 855     uint16_t offset)
 856 {
 857         struct siba_dev_softc *sd = device_get_ivars(dev);
 858
 859         sd->sd_ops->read_multi_1(sd, buffer, count, offset);
 860 }
 861
 862 void
 863 siba_read_multi_2(device_t dev, void *buffer, size_t count,
 864     uint16_t offset)
 865 {
 866         struct siba_dev_softc *sd = device_get_ivars(dev);
 867
 868         sd->sd_ops->read_multi_2(sd, buffer, count, offset);
 869 }
 870
 871 void
 872 siba_read_multi_4(device_t dev, void *buffer, size_t count,
 873     uint16_t offset)
 874 {
 875         struct siba_dev_softc *sd = device_get_ivars(dev);
 876
 877         sd->sd_ops->read_multi_4(sd, buffer, count, offset);
 878 }
 879
 880 void
 881 siba_write_multi_1(device_t dev, const void *buffer, size_t count,
 882     uint16_t offset)
 883 {
 884         struct siba_dev_softc *sd = device_get_ivars(dev);
 885
 886         sd->sd_ops->write_multi_1(sd, buffer, count, offset);
 887 }
 888
 889 void
 890 siba_write_multi_2(device_t dev, const void *buffer, size_t count,
 891     uint16_t offset)
 892 {
 893         struct siba_dev_softc *sd = device_get_ivars(dev);
 894
 895         sd->sd_ops->write_multi_2(sd, buffer, count, offset);
 896 }
 897
 898 void
 899 siba_write_multi_4(device_t dev, const void *buffer, size_t count,
 900     uint16_t offset)
 901 {
 902         struct siba_dev_softc *sd = device_get_ivars(dev);
 903
 904         sd->sd_ops->write_multi_4(sd, buffer, count, offset);
 905 }
 906
 907 static void
 908 siba_cc_pmu_init(struct siba_cc *scc)
 909 {
 910         const struct siba_cc_pmu_res_updown *updown = NULL;
 911         const struct siba_cc_pmu_res_depend *depend = NULL;
 912         struct siba_dev_softc *sd = scc->scc_dev;
 913         struct siba_softc *siba = sd->sd_bus;
 914         uint32_t min = 0, max = 0, pmucap;
 915         unsigned int i, updown_size, depend_size;
 916
 917         if ((scc->scc_caps & SIBA_CC_CAPS_PMU) == 0)
 918                 return;
 919
 920         pmucap = SIBA_CC_READ32(scc, SIBA_CC_PMUCAPS);
 921         scc->scc_pmu.rev = (pmucap & SIBA_CC_PMUCAPS_REV);
 922
 923         DPRINTF(siba, SIBA_DEBUG_PMU, "PMU(r%u) found (caps %#x)\n",
 924             scc->scc_pmu.rev, pmucap);
 925
 926         if (scc->scc_pmu.rev >= 1) {
 927                 if (siba->siba_chiprev < 2 && siba->siba_chipid == 0x4325)
 928                         SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL,
 929                             ~SIBA_CC_PMUCTL_NOILP);
 930                 else
 931                         SIBA_CC_SET32(scc, SIBA_CC_PMUCTL,
 932                             SIBA_CC_PMUCTL_NOILP);
 933         }
 934
 935         /* initialize PLL & PMU resources */
 936         switch (siba->siba_chipid) {
 937         case 0x4312:
 938                 siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
 939                 /* use the default: min = 0xcbb max = 0x7ffff */
 940                 break;
 941         case 0x4325:
 942                 siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
 943
 944                 updown = siba_cc_pmu_4325_updown;
 945                 updown_size = N(siba_cc_pmu_4325_updown);
 946                 depend = siba_cc_pmu_4325_depend;
 947                 depend_size = N(siba_cc_pmu_4325_depend);
 948
 949                 min = (1 << SIBA_CC_PMU_4325_BURST) |
 950                     (1 << SIBA_CC_PMU_4325_LN);
 951                 if (SIBA_CC_READ32(scc, SIBA_CC_CHIPSTAT) &
 952                     SIBA_CC_CHST_4325_PMUTOP_2B)
 953                         min |= (1 << SIBA_CC_PMU_4325_CLBURST);
 954                 max = 0xfffff;
 955                 break;
 956         case 0x4328:
 957                 siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
 958
 959                 updown = siba_cc_pmu_4328_updown;
 960                 updown_size = N(siba_cc_pmu_4328_updown);
 961                 depend = siba_cc_pmu_4328_depend;
 962                 depend_size = N(siba_cc_pmu_4328_depend);
 963
 964                 min = (1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) |
 965                           (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM) |
 966                           (1 << SIBA_CC_PMU_4328_CRYSTAL_EN);
 967
 968                 max = 0xfffff;
 969                 break;
 970         case 0x5354:
 971                 siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
 972
 973                 max = 0xfffff;
 974                 break;
 975         default:
 976                 device_printf(siba->siba_dev,
 977                     "unknown chipid %#x for PLL & PMU init\n",
 978                     siba->siba_chipid);
 979         }
 980
 981         if (updown) {
 982                 for (i = 0; i < updown_size; i++) {
 983                         SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
 984                             updown[i].res);
 985                         SIBA_CC_WRITE32(scc, SIBA_CC_PMU_UPDNTM,
 986                             updown[i].updown);
 987                 }
 988         }
 989         if (depend) {
 990                 for (i = 0; i < depend_size; i++) {
 991                         SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
 992                             depend[i].res);
 993                         switch (depend[i].task) {
 994                         case SIBA_CC_PMU_DEP_SET:
 995                                 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_DEPMSK,
 996                                     depend[i].depend);
 997                                 break;
 998                         case SIBA_CC_PMU_DEP_ADD:
 999                                 SIBA_CC_SET32(scc, SIBA_CC_PMU_DEPMSK,
1000                                     depend[i].depend);
1001                                 break;
1002                         case SIBA_CC_PMU_DEP_REMOVE:
1003                                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_DEPMSK,
1004                                     ~(depend[i].depend));
1005                                 break;
1006                         default:
1007                                 KASSERT(0 == 1,
1008                                     ("%s:%d: assertion failed",
1009                                         __func__, __LINE__));
1010                         }
1011                 }
1012         }
1013
1014         if (min)
1015                 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MINRES, min);
1016         if (max)
1017                 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MAXRES, max);
1018 }
1019
1020 static void
1021 siba_cc_power_init(struct siba_cc *scc)
1022 {
1023         struct siba_softc *siba = scc->scc_dev->sd_bus;
1024         int maxfreq;
1025
1026         if (siba->siba_chipid == 0x4321) {
1027                 if (siba->siba_chiprev == 0)
1028                         SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0x3a4);
1029                 else if (siba->siba_chiprev == 1)
1030                         SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0xa4);
1031         }
1032
1033         if ((scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
1034                 return;
1035
1036         if (scc->scc_dev->sd_id.sd_rev >= 10)
1037                 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSYSCTL,
1038                     (SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) &
1039                     0xffff) | 0x40000);
1040         else {
1041                 maxfreq = siba_cc_clockfreq(scc, 1);
1042                 SIBA_CC_WRITE32(scc, SIBA_CC_PLLONDELAY,
1043                     (maxfreq * 150 + 999999) / 1000000);
1044                 SIBA_CC_WRITE32(scc, SIBA_CC_FREFSELDELAY,
1045                     (maxfreq * 15 + 999999) / 1000000);
1046         }
1047 }
1048
1049 static void
1050 siba_cc_powerup_delay(struct siba_cc *scc)
1051 {
1052         struct siba_softc *siba = scc->scc_dev->sd_bus;
1053         int min;
1054
1055         if (siba->siba_type != SIBA_TYPE_PCI ||
1056             !(scc->scc_caps & SIBA_CC_CAPS_PWCTL))
1057                 return;
1058
1059         min = siba_cc_clockfreq(scc, 0);
1060         scc->scc_powerup_delay =
1061             (((SIBA_CC_READ32(scc, SIBA_CC_PLLONDELAY) + 2) * 1000000) +
1062             (min - 1)) / min;
1063 }
1064
1065 static int
1066 siba_cc_clockfreq(struct siba_cc *scc, int max)
1067 {
1068         enum siba_clksrc src;
1069         int div = 1, limit = 0;
1070
1071         src = siba_cc_clksrc(scc);
1072         if (scc->scc_dev->sd_id.sd_rev < 6) {
1073                 div = (src == SIBA_CC_CLKSRC_PCI) ? 64 :
1074                     (src == SIBA_CC_CLKSRC_CRYSTAL) ? 32 : 1;
1075                 KASSERT(div != 1,
1076                     ("%s: unknown clock %d", __func__, src));
1077         } else if (scc->scc_dev->sd_id.sd_rev < 10) {
1078                 switch (src) {
1079                 case SIBA_CC_CLKSRC_CRYSTAL:
1080                 case SIBA_CC_CLKSRC_PCI:
1081                         div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) >> 16) +
1082                             1) * 4;
1083                         break;
1084                 case SIBA_CC_CLKSRC_LOWPW:
1085                         break;
1086                 }
1087         } else
1088                 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) >> 16) + 1) * 4;
1089
1090         switch (src) {
1091         case SIBA_CC_CLKSRC_CRYSTAL:
1092                 limit = (max) ? 20200000 : 19800000;
1093                 break;
1094         case SIBA_CC_CLKSRC_LOWPW:
1095                 limit = (max) ? 43000 : 25000;
1096                 break;
1097         case SIBA_CC_CLKSRC_PCI:
1098                 limit = (max) ? 34000000 : 25000000;
1099                 break;
1100         }
1101
1102         return (limit / div);
1103 }
1104
1105 static void
1106 siba_cc_pmu1_pll0_init(struct siba_cc *scc, uint32_t freq)
1107 {
1108         struct siba_dev_softc *sd = scc->scc_dev;
1109         struct siba_softc *siba = sd->sd_bus;
1110         const struct siba_cc_pmu1_plltab *e = NULL;
1111         uint32_t bufsth = 0, pll, pmu;
1112         unsigned int i;
1113
1114         KASSERT(freq == 0, ("%s:%d: assertion vail", __func__, __LINE__));
1115         if (siba->siba_chipid == 0x4312) {
1116                 scc->scc_pmu.freq = 20000;
1117                 return;
1118         }
1119
1120         e = siba_cc_pmu1_plltab_find(SIBA_CC_PMU1_DEFAULT_FREQ);
1121         KASSERT(e != NULL, ("%s:%d: assertion vail", __func__, __LINE__));
1122         scc->scc_pmu.freq = e->freq;
1123
1124         pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1125         if (SIBA_CC_PMUCTL_XF_VAL(pmu) == e->xf)
1126                 return;
1127
1128         DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n",
1129             (e->freq / 1000), (e->freq % 1000));
1130
1131         /* turn PLL off */
1132         switch (siba->siba_chipid) {
1133         case 0x4325:
1134                 bufsth = 0x222222;
1135                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1136                     ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) |
1137                       (1 << SIBA_CC_PMU_4325_HT)));
1138                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1139                     ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) |
1140                       (1 << SIBA_CC_PMU_4325_HT)));
1141                 break;
1142         default:
1143                 KASSERT(0 == 1,
1144                     ("%s:%d: assertion failed", __func__, __LINE__));
1145         }
1146         for (i = 0; i < 1500; i++) {
1147                 if (!(SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) &
1148                       SIBA_CC_CLKCTLSTATUS_HT))
1149                         break;
1150                 DELAY(10);
1151         }
1152         if (SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & SIBA_CC_CLKCTLSTATUS_HT)
1153                 device_printf(siba->siba_dev, "failed to turn PLL off!\n");
1154
1155         pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0);
1156         pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV);
1157         pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV;
1158         pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV;
1159         siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll);
1160
1161         pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2);
1162         pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE);
1163         pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT;
1164         pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE;
1165         siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, pll);
1166
1167         pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL3);
1168         pll &= ~SIBA_CC_PMU1_PLL3_NDIVFRAC;
1169         pll |= ((uint32_t)e->ndiv_frac << 0) & SIBA_CC_PMU1_PLL3_NDIVFRAC;
1170         siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, pll);
1171
1172         if (bufsth) {
1173                 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL5);
1174                 pll &= ~SIBA_CC_PMU1_PLL5_CLKDRV;
1175                 pll |= (bufsth << 8) & SIBA_CC_PMU1_PLL5_CLKDRV;
1176                 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, pll);
1177         }
1178
1179         pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1180         pmu &= ~(SIBA_CC_PMUCTL_ILP | SIBA_CC_PMUCTL_XF);
1181         pmu |= ((((uint32_t)e->freq + 127) / 128 - 1) << 16) &
1182             SIBA_CC_PMUCTL_ILP;
1183         pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
1184         SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
1185 }
1186
1187 static void
1188 siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq)
1189 {
1190         struct siba_dev_softc *sd = scc->scc_dev;
1191         struct siba_softc *siba = sd->sd_bus;
1192         const struct siba_cc_pmu0_plltab *e = NULL;
1193         uint32_t pmu, tmp, pll;
1194         unsigned int i;
1195
1196         if ((siba->siba_chipid == 0x5354) && !xtalfreq)
1197                 xtalfreq = 25000;
1198         if (xtalfreq)
1199                 e = siba_cc_pmu0_plltab_findentry(xtalfreq);
1200         if (!e)
1201                 e = siba_cc_pmu0_plltab_findentry(
1202                     SIBA_CC_PMU0_DEFAULT_XTALFREQ);
1203         KASSERT(e != NULL, ("%s:%d: fail", __func__, __LINE__));
1204         xtalfreq = e->freq;
1205         scc->scc_pmu.freq = e->freq;
1206
1207         pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1208         if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf)
1209                 return;
1210
1211         DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n",
1212             (xtalfreq / 1000), (xtalfreq % 1000));
1213
1214         KASSERT(siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354,
1215             ("%s:%d: fail", __func__, __LINE__));
1216
1217         switch (siba->siba_chipid) {
1218         case 0x4328:
1219                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1220                     ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU));
1221                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1222                     ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU));
1223                 break;
1224         case 0x5354:
1225                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1226                     ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU));
1227                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1228                     ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU));
1229                 break;
1230         }
1231         for (i = 1500; i; i--) {
1232                 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
1233                 if (!(tmp & SIBA_CC_CLKCTLSTATUS_HT))
1234                         break;
1235                 DELAY(10);
1236         }
1237         tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
1238         if (tmp & SIBA_CC_CLKCTLSTATUS_HT)
1239                 device_printf(siba->siba_dev, "failed to turn PLL off!\n");
1240
1241         /* set PDIV */
1242         pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL0);
1243         if (xtalfreq >= SIBA_CC_PMU0_PLL0_PDIV_FREQ)
1244                 pll |= SIBA_CC_PMU0_PLL0_PDIV_MSK;
1245         else
1246                 pll &= ~SIBA_CC_PMU0_PLL0_PDIV_MSK;
1247         siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL0, pll);
1248
1249         /* set WILD */
1250         pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL1);
1251         pll &= ~(SIBA_CC_PMU0_PLL1_STOPMOD | SIBA_CC_PMU0_PLL1_IMSK |
1252             SIBA_CC_PMU0_PLL1_FMSK);
1253         pll |= ((uint32_t)e->wb_int << 28) & SIBA_CC_PMU0_PLL1_IMSK;
1254         pll |= ((uint32_t)e->wb_frac << 8) & SIBA_CC_PMU0_PLL1_FMSK;
1255         if (e->wb_frac == 0)
1256                 pll |= SIBA_CC_PMU0_PLL1_STOPMOD;
1257         siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL1, pll);
1258
1259         /* set WILD */
1260         pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL2);
1261         pll &= ~SIBA_CC_PMU0_PLL2_IMSKHI;
1262         pll |= (((uint32_t)e->wb_int >> 4) << 0) & SIBA_CC_PMU0_PLL2_IMSKHI;
1263         siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL2, pll);
1264
1265         /* set freq and divisor. */
1266         pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1267         pmu &= ~SIBA_CC_PMUCTL_ILP;
1268         pmu |= (((xtalfreq + 127) / 128 - 1) << 16) & SIBA_CC_PMUCTL_ILP;
1269         pmu &= ~SIBA_CC_PMUCTL_XF;
1270         pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
1271         SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
1272 }
1273
1274 static enum siba_clksrc
1275 siba_cc_clksrc(struct siba_cc *scc)
1276 {
1277         struct siba_dev_softc *sd = scc->scc_dev;
1278         struct siba_softc *siba = sd->sd_bus;
1279
1280         if (sd->sd_id.sd_rev < 6) {
1281                 if (siba->siba_type == SIBA_TYPE_PCI) {
1282                         if (pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4) &
1283                             0x10)
1284                                 return (SIBA_CC_CLKSRC_PCI);
1285                         return (SIBA_CC_CLKSRC_CRYSTAL);
1286                 }
1287                 if (siba->siba_type == SIBA_TYPE_SSB ||
1288                     siba->siba_type == SIBA_TYPE_PCMCIA)
1289                         return (SIBA_CC_CLKSRC_CRYSTAL);
1290         }
1291         if (sd->sd_id.sd_rev < 10) {
1292                 switch (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 0x7) {
1293                 case 0:
1294                         return (SIBA_CC_CLKSRC_LOWPW);
1295                 case 1:
1296                         return (SIBA_CC_CLKSRC_CRYSTAL);
1297                 case 2:
1298                         return (SIBA_CC_CLKSRC_PCI);
1299                 default:
1300                         break;
1301                 }
1302         }
1303
1304         return (SIBA_CC_CLKSRC_CRYSTAL);
1305 }
1306
1307 static const struct siba_cc_pmu1_plltab *
1308 siba_cc_pmu1_plltab_find(uint32_t crystalfreq)
1309 {
1310         const struct siba_cc_pmu1_plltab *e;
1311         unsigned int i;
1312
1313         for (i = 0; i < N(siba_cc_pmu1_plltab); i++) {
1314                 e = &siba_cc_pmu1_plltab[i];
1315                 if (crystalfreq == e->freq)
1316                         return (e);
1317         }
1318
1319         return (NULL);
1320 }
1321
1322 static uint32_t
1323 siba_cc_pll_read(struct siba_cc *scc, uint32_t offset)
1324 {
1325
1326         SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
1327         return (SIBA_CC_READ32(scc, SIBA_CC_PLLCTL_DATA));
1328 }
1329
1330 static void
1331 siba_cc_pll_write(struct siba_cc *scc, uint32_t offset, uint32_t value)
1332 {
1333
1334         SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
1335         SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, value);
1336 }
1337
1338 static const struct siba_cc_pmu0_plltab *
1339 siba_cc_pmu0_plltab_findentry(uint32_t crystalfreq)
1340 {
1341         const struct siba_cc_pmu0_plltab *e;
1342         unsigned int i;
1343
1344         for (i = 0; i < N(siba_cc_pmu0_plltab); i++) {
1345                 e = &siba_cc_pmu0_plltab[i];
1346                 if (e->freq == crystalfreq)
1347                         return (e);
1348         }
1349
1350         return (NULL);
1351 }
1352
1353 static int
1354 siba_pci_sprom(struct siba_softc *siba, struct siba_sprom *sprom)
1355 {
1356         int error = ENOMEM;
1357         uint16_t *buf;
1358
1359         buf = malloc(SIBA_SPROMSIZE_R123 * sizeof(uint16_t),
1360             M_DEVBUF, M_NOWAIT | M_ZERO);
1361         if (buf == NULL)
1362                 return (ENOMEM);
1363         siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R123);
1364         error = sprom_check_crc(buf, siba->siba_spromsize);
1365         if (error) {
1366                 free(buf, M_DEVBUF);
1367                 buf = malloc(SIBA_SPROMSIZE_R4 * sizeof(uint16_t),
1368                     M_DEVBUF, M_NOWAIT | M_ZERO);
1369                 if (buf == NULL)
1370                         return (ENOMEM);
1371                 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R4);
1372                 error = sprom_check_crc(buf, siba->siba_spromsize);
1373                 if (error)
1374                         device_printf(siba->siba_dev, "warn: bad SPROM CRC\n");
1375         }
1376
1377         bzero(sprom, sizeof(*sprom));
1378
1379         sprom->rev = buf[siba->siba_spromsize - 1] & 0x00FF;
1380         DPRINTF(siba, SIBA_DEBUG_SPROM, "SPROM rev %d\n",
1381             sprom->rev);
1382         memset(sprom->mac_eth, 0xff, 6);
1383         memset(sprom->mac_80211a, 0xff, 6);
1384         if ((siba->siba_chipid & 0xff00) == 0x4400) {
1385                 sprom->rev = 1;
1386                 siba_sprom_r123(sprom, buf);
1387         } else if (siba->siba_chipid == 0x4321) {
1388                 sprom->rev = 4;
1389                 siba_sprom_r45(sprom, buf);
1390         } else {
1391                 switch (sprom->rev) {
1392                 case 1:
1393                 case 2:
1394                 case 3:
1395                         siba_sprom_r123(sprom, buf);
1396                         break;
1397                 case 4:
1398                 case 5:
1399                         siba_sprom_r45(sprom, buf);
1400                         break;
1401                 case 8:
1402                         siba_sprom_r8(sprom, buf);
1403                         break;
1404                 default:
1405                         device_printf(siba->siba_dev,
1406                             "unknown SPROM revision %d.\n", sprom->rev);
1407                         siba_sprom_r123(sprom, buf);
1408                 }
1409         }
1410
1411         if (sprom->bf_lo == 0xffff)
1412                 sprom->bf_lo = 0;
1413         if (sprom->bf_hi == 0xffff)
1414                 sprom->bf_hi = 0;
1415
1416         free(buf, M_DEVBUF);
1417         return (error);
1418 }
1419
1420 static int
1421 siba_sprom_read(struct siba_softc *siba, uint16_t *sprom, uint16_t len)
1422 {
1423         int i;
1424
1425         for (i = 0; i < len; i++)
1426                 sprom[i] = SIBA_READ_2(siba, SIBA_SPROM_BASE + (i * 2));
1427
1428         siba->siba_spromsize = len;
1429         return (0);
1430 }
1431
1432 static int
1433 sprom_check_crc(const uint16_t *sprom, size_t size)
1434 {
1435         int word;
1436         uint8_t crc0, crc1 = 0xff;
1437
1438         crc0 = (sprom[size - 1] & SIBA_SPROM_REV_CRC) >> 8;
1439         for (word = 0; word < size - 1; word++) {
1440                 crc1 = siba_crc8(crc1, sprom[word] & 0x00ff);
1441                 crc1 = siba_crc8(crc1, (sprom[word] & 0xff00) >> 8);
1442         }
1443         crc1 = siba_crc8(crc1, sprom[size - 1] & 0x00ff);
1444         crc1 ^= 0xff;
1445
1446         return ((crc0 != crc1) ? EPROTO : 0);
1447 }
1448
1449 static uint8_t
1450 siba_crc8(uint8_t crc, uint8_t data)
1451 {
1452         static const uint8_t ct[] = {
1453                 0x00, 0xf7, 0xb9, 0x4e, 0x25, 0xd2, 0x9c, 0x6b,
1454                 0x4a, 0xbd, 0xf3, 0x04, 0x6f, 0x98, 0xd6, 0x21,
1455                 0x94, 0x63, 0x2d, 0xda, 0xb1, 0x46, 0x08, 0xff,
1456                 0xde, 0x29, 0x67, 0x90, 0xfb, 0x0c, 0x42, 0xb5,
1457                 0x7f, 0x88, 0xc6, 0x31, 0x5a, 0xad, 0xe3, 0x14,
1458                 0x35, 0xc2, 0x8c, 0x7b, 0x10, 0xe7, 0xa9, 0x5e,
1459                 0xeb, 0x1c, 0x52, 0xa5, 0xce, 0x39, 0x77, 0x80,
1460                 0xa1, 0x56, 0x18, 0xef, 0x84, 0x73, 0x3d, 0xca,
1461                 0xfe, 0x09, 0x47, 0xb0, 0xdb, 0x2c, 0x62, 0x95,
1462                 0xb4, 0x43, 0x0d, 0xfa, 0x91, 0x66, 0x28, 0xdf,
1463                 0x6a, 0x9d, 0xd3, 0x24, 0x4f, 0xb8, 0xf6, 0x01,
1464                 0x20, 0xd7, 0x99, 0x6e, 0x05, 0xf2, 0xbc, 0x4b,
1465                 0x81, 0x76, 0x38, 0xcf, 0xa4, 0x53, 0x1d, 0xea,
1466                 0xcb, 0x3c, 0x72, 0x85, 0xee, 0x19, 0x57, 0xa0,
1467                 0x15, 0xe2, 0xac, 0x5b, 0x30, 0xc7, 0x89, 0x7e,
1468                 0x5f, 0xa8, 0xe6, 0x11, 0x7a, 0x8d, 0xc3, 0x34,
1469                 0xab, 0x5c, 0x12, 0xe5, 0x8e, 0x79, 0x37, 0xc0,
1470                 0xe1, 0x16, 0x58, 0xaf, 0xc4, 0x33, 0x7d, 0x8a,
1471                 0x3f, 0xc8, 0x86, 0x71, 0x1a, 0xed, 0xa3, 0x54,
1472                 0x75, 0x82, 0xcc, 0x3b, 0x50, 0xa7, 0xe9, 0x1e,
1473                 0xd4, 0x23, 0x6d, 0x9a, 0xf1, 0x06, 0x48, 0xbf,
1474                 0x9e, 0x69, 0x27, 0xd0, 0xbb, 0x4c, 0x02, 0xf5,
1475                 0x40, 0xb7, 0xf9, 0x0e, 0x65, 0x92, 0xdc, 0x2b,
1476                 0x0a, 0xfd, 0xb3, 0x44, 0x2f, 0xd8, 0x96, 0x61,
1477                 0x55, 0xa2, 0xec, 0x1b, 0x70, 0x87, 0xc9, 0x3e,
1478                 0x1f, 0xe8, 0xa6, 0x51, 0x3a, 0xcd, 0x83, 0x74,
1479                 0xc1, 0x36, 0x78, 0x8f, 0xe4, 0x13, 0x5d, 0xaa,
1480                 0x8b, 0x7c, 0x32, 0xc5, 0xae, 0x59, 0x17, 0xe0,
1481                 0x2a, 0xdd, 0x93, 0x64, 0x0f, 0xf8, 0xb6, 0x41,
1482                 0x60, 0x97, 0xd9, 0x2e, 0x45, 0xb2, 0xfc, 0x0b,
1483                 0xbe, 0x49, 0x07, 0xf0, 0x9b, 0x6c, 0x22, 0xd5,
1484                 0xf4, 0x03, 0x4d, 0xba, 0xd1, 0x26, 0x68, 0x9f,
1485         };
1486         return (ct[crc ^ data]);
1487 }
1488
1489 #define SIBA_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
1490 #define SIBA_OFFSET(offset)     \
1491         (((offset) - SIBA_SPROM_BASE) / sizeof(uint16_t))
1492 #define SIBA_SHIFTOUT_SUB(__x, __mask)                                  \
1493         (((__x) & (__mask)) / SIBA_LOWEST_SET_BIT(__mask))
1494 #define SIBA_SHIFTOUT(_var, _offset, _mask)                             \
1495         out->_var = SIBA_SHIFTOUT_SUB(in[SIBA_OFFSET(_offset)], (_mask))
1496 #define SIBA_SHIFTOUT_4(_var, _offset, _mask, _shift)                   \
1497         out->_var = ((((uint32_t)in[SIBA_OFFSET((_offset)+2)] << 16 |   \
1498             in[SIBA_OFFSET(_offset)]) & (_mask)) >> (_shift))
1499
1500 static void
1501 siba_sprom_r123(struct siba_sprom *out, const uint16_t *in)
1502 {
1503         int i;
1504         uint16_t v;
1505         int8_t gain;
1506         uint16_t loc[3];
1507
1508         if (out->rev == 3)
1509                 loc[0] = SIBA_SPROM3_MAC_80211BG;
1510         else {
1511                 loc[0] = SIBA_SPROM1_MAC_80211BG;
1512                 loc[1] = SIBA_SPROM1_MAC_ETH;
1513                 loc[2] = SIBA_SPROM1_MAC_80211A;
1514         }
1515         for (i = 0; i < 3; i++) {
1516                 v = in[SIBA_OFFSET(loc[0]) + i];
1517                 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1518         }
1519         if (out->rev < 3) {
1520                 for (i = 0; i < 3; i++) {
1521                         v = in[SIBA_OFFSET(loc[1]) + i];
1522                         *(((uint16_t *)out->mac_eth) + i) = htobe16(v);
1523                 }
1524                 for (i = 0; i < 3; i++) {
1525                         v = in[SIBA_OFFSET(loc[2]) + i];
1526                         *(((uint16_t *)out->mac_80211a) + i) = htobe16(v);
1527                 }
1528         }
1529         SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM1_ETHPHY,
1530             SIBA_SPROM1_ETHPHY_MII_ETH0);
1531         SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM1_ETHPHY,
1532             SIBA_SPROM1_ETHPHY_MII_ETH1);
1533         SIBA_SHIFTOUT(mdio_eth0, SIBA_SPROM1_ETHPHY,
1534             SIBA_SPROM1_ETHPHY_MDIO_ETH0);
1535         SIBA_SHIFTOUT(mdio_eth1, SIBA_SPROM1_ETHPHY,
1536             SIBA_SPROM1_ETHPHY_MDIO_ETH1);
1537         SIBA_SHIFTOUT(brev, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_BREV);
1538         SIBA_SHIFTOUT(ccode, SIBA_SPROM1_BOARDINFO,
1539             SIBA_SPROM1_BOARDINFO_CCODE);
1540         SIBA_SHIFTOUT(ant_a, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_ANTA);
1541         SIBA_SHIFTOUT(ant_bg, SIBA_SPROM1_BOARDINFO,
1542             SIBA_SPROM1_BOARDINFO_ANTBG);
1543         SIBA_SHIFTOUT(pa0b0, SIBA_SPROM1_PA0B0, 0xffff);
1544         SIBA_SHIFTOUT(pa0b1, SIBA_SPROM1_PA0B1, 0xffff);
1545         SIBA_SHIFTOUT(pa0b2, SIBA_SPROM1_PA0B2, 0xffff);
1546         SIBA_SHIFTOUT(pa1b0, SIBA_SPROM1_PA1B0, 0xffff);
1547         SIBA_SHIFTOUT(pa1b1, SIBA_SPROM1_PA1B1, 0xffff);
1548         SIBA_SHIFTOUT(pa1b2, SIBA_SPROM1_PA1B2, 0xffff);
1549         SIBA_SHIFTOUT(gpio0, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P0);
1550         SIBA_SHIFTOUT(gpio1, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P1);
1551         SIBA_SHIFTOUT(gpio2, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P2);
1552         SIBA_SHIFTOUT(gpio3, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P3);
1553
1554         SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_A);
1555         SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_BG);
1556         SIBA_SHIFTOUT(tssi_a, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_A);
1557         SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_BG);
1558         SIBA_SHIFTOUT(bf_lo, SIBA_SPROM1_BFLOW, 0xffff);
1559         if (out->rev >= 2)
1560                 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM2_BFHIGH, 0xffff);
1561
1562         /* antenna gain */
1563         gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_BG, 0);
1564         out->again.ghz24.a0 = out->again.ghz24.a1 = gain;
1565         out->again.ghz24.a2 = out->again.ghz24.a3 = gain;
1566         gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_A, 8);
1567         out->again.ghz5.a0 = out->again.ghz5.a1 = gain;
1568         out->again.ghz5.a2 = out->again.ghz5.a3 = gain;
1569 }
1570
1571 static void
1572 siba_sprom_r45(struct siba_sprom *out, const uint16_t *in)
1573 {
1574         int i;
1575         uint16_t v;
1576         uint16_t mac_80211bg_offset;
1577
1578         if (out->rev == 4)
1579                 mac_80211bg_offset = SIBA_SPROM4_MAC_80211BG;
1580         else
1581                 mac_80211bg_offset = SIBA_SPROM5_MAC_80211BG;
1582         for (i = 0; i < 3; i++) {
1583                 v = in[SIBA_OFFSET(mac_80211bg_offset) + i];
1584                 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1585         }
1586         SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET0A);
1587         SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET1A);
1588         if (out->rev == 4) {
1589                 SIBA_SHIFTOUT(ccode, SIBA_SPROM4_CCODE, 0xffff);
1590                 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM4_BFLOW, 0xffff);
1591                 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM4_BFHIGH, 0xffff);
1592         } else {
1593                 SIBA_SHIFTOUT(ccode, SIBA_SPROM5_CCODE, 0xffff);
1594                 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM5_BFLOW, 0xffff);
1595                 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM5_BFHIGH, 0xffff);
1596         }
1597         SIBA_SHIFTOUT(ant_a, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_A);
1598         SIBA_SHIFTOUT(ant_bg, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_BG);
1599         SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_MAXP_BG_MASK);
1600         SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_TSSI_BG);
1601         SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_MAXP_A_MASK);
1602         SIBA_SHIFTOUT(tssi_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_TSSI_A);
1603         if (out->rev == 4) {
1604                 SIBA_SHIFTOUT(gpio0, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P0);
1605                 SIBA_SHIFTOUT(gpio1, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P1);
1606                 SIBA_SHIFTOUT(gpio2, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P2);
1607                 SIBA_SHIFTOUT(gpio3, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P3);
1608         } else {
1609                 SIBA_SHIFTOUT(gpio0, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P0);
1610                 SIBA_SHIFTOUT(gpio1, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P1);
1611                 SIBA_SHIFTOUT(gpio2, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P2);
1612                 SIBA_SHIFTOUT(gpio3, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P3);
1613         }
1614
1615         /* antenna gain */
1616         SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN0);
1617         SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN1);
1618         SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN2);
1619         SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN3);
1620         bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5));
1621 }
1622
1623 static void
1624 siba_sprom_r8(struct siba_sprom *out, const uint16_t *in)
1625 {
1626         int i;
1627         uint16_t v;
1628
1629         for (i = 0; i < 3; i++) {
1630                 v = in[SIBA_OFFSET(SIBA_SPROM8_MAC_80211BG) + i];
1631                 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1632         }
1633         SIBA_SHIFTOUT(ccode, SIBA_SPROM8_CCODE, 0xffff);
1634         SIBA_SHIFTOUT(bf_lo, SIBA_SPROM8_BFLOW, 0xffff);
1635         SIBA_SHIFTOUT(bf_hi, SIBA_SPROM8_BFHIGH, 0xffff);
1636         SIBA_SHIFTOUT(bf2_lo, SIBA_SPROM8_BFL2LO, 0xffff);
1637         SIBA_SHIFTOUT(bf2_hi, SIBA_SPROM8_BFL2HI, 0xffff);
1638         SIBA_SHIFTOUT(ant_a, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_A);
1639         SIBA_SHIFTOUT(ant_bg, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_BG);
1640         SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_MAXP_BG_MASK);
1641         SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_TSSI_BG);
1642         SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_MAXP_A_MASK);
1643         SIBA_SHIFTOUT(tssi_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_TSSI_A);
1644         SIBA_SHIFTOUT(maxpwr_ah, SIBA_SPROM8_MAXP_AHL,
1645             SIBA_SPROM8_MAXP_AH_MASK);
1646         SIBA_SHIFTOUT(maxpwr_al, SIBA_SPROM8_MAXP_AHL,
1647             SIBA_SPROM8_MAXP_AL_MASK);
1648         SIBA_SHIFTOUT(gpio0, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P0);
1649         SIBA_SHIFTOUT(gpio1, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P1);
1650         SIBA_SHIFTOUT(gpio2, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P2);
1651         SIBA_SHIFTOUT(gpio3, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P3);
1652         SIBA_SHIFTOUT(tri2g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI2G);
1653         SIBA_SHIFTOUT(tri5g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI5G);
1654         SIBA_SHIFTOUT(tri5gl, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GL);
1655         SIBA_SHIFTOUT(tri5gh, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GH);
1656         SIBA_SHIFTOUT(rxpo2g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO2G);
1657         SIBA_SHIFTOUT(rxpo5g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO5G);
1658         SIBA_SHIFTOUT(rssismf2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMF2G);
1659         SIBA_SHIFTOUT(rssismc2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMC2G);
1660         SIBA_SHIFTOUT(rssisav2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISAV2G);
1661         SIBA_SHIFTOUT(bxa2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_BXA2G);
1662         SIBA_SHIFTOUT(rssismf5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMF5G);
1663         SIBA_SHIFTOUT(rssismc5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMC5G);
1664         SIBA_SHIFTOUT(rssisav5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISAV5G);
1665         SIBA_SHIFTOUT(bxa5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_BXA5G);
1666
1667         SIBA_SHIFTOUT(pa0b0, SIBA_SPROM8_PA0B0, 0xffff);
1668         SIBA_SHIFTOUT(pa0b1, SIBA_SPROM8_PA0B1, 0xffff);
1669         SIBA_SHIFTOUT(pa0b2, SIBA_SPROM8_PA0B2, 0xffff);
1670         SIBA_SHIFTOUT(pa1b0, SIBA_SPROM8_PA1B0, 0xffff);
1671         SIBA_SHIFTOUT(pa1b1, SIBA_SPROM8_PA1B1, 0xffff);
1672         SIBA_SHIFTOUT(pa1b2, SIBA_SPROM8_PA1B2, 0xffff);
1673         SIBA_SHIFTOUT(pa1lob0, SIBA_SPROM8_PA1LOB0, 0xffff);
1674         SIBA_SHIFTOUT(pa1lob1, SIBA_SPROM8_PA1LOB1, 0xffff);
1675         SIBA_SHIFTOUT(pa1lob2, SIBA_SPROM8_PA1LOB2, 0xffff);
1676         SIBA_SHIFTOUT(pa1hib0, SIBA_SPROM8_PA1HIB0, 0xffff);
1677         SIBA_SHIFTOUT(pa1hib1, SIBA_SPROM8_PA1HIB1, 0xffff);
1678         SIBA_SHIFTOUT(pa1hib2, SIBA_SPROM8_PA1HIB2, 0xffff);
1679         SIBA_SHIFTOUT(cck2gpo, SIBA_SPROM8_CCK2GPO, 0xffff);
1680
1681         SIBA_SHIFTOUT_4(ofdm2gpo, SIBA_SPROM8_OFDM2GPO, 0xffffffff, 0);
1682         SIBA_SHIFTOUT_4(ofdm5glpo, SIBA_SPROM8_OFDM5GLPO, 0xffffffff, 0);
1683         SIBA_SHIFTOUT_4(ofdm5gpo, SIBA_SPROM8_OFDM5GPO, 0xffffffff, 0);
1684         SIBA_SHIFTOUT_4(ofdm5ghpo, SIBA_SPROM8_OFDM5GHPO, 0xffffffff, 0);
1685
1686         /* antenna gain */
1687         SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN0);
1688         SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN1);
1689         SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN2);
1690         SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN3);
1691         bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5));
1692 }
1693
1694 static int8_t
1695 siba_sprom_r123_antgain(uint8_t sprom_revision, const uint16_t *in,
1696     uint16_t mask, uint16_t shift)
1697 {
1698         uint16_t v;
1699         uint8_t gain;
1700
1701         v = in[SIBA_OFFSET(SIBA_SPROM1_AGAIN)];
1702         gain = (v & mask) >> shift;
1703         gain = (gain == 0xff) ? 2 : (sprom_revision == 1) ? gain << 2 :
1704             ((gain & 0xc0) >> 6) | ((gain & 0x3f) << 2);
1705
1706         return ((int8_t)gain);
1707 }
1708
1709 #undef SIBA_LOWEST_SET_BIT
1710 #undef SIBA_OFFSET
1711 #undef SIBA_SHIFTOUT_SUB
1712 #undef SIBA_SHIFTOUT
1713
1714 int
1715 siba_powerdown(device_t dev)
1716 {
1717         struct siba_dev_softc *sd = device_get_ivars(dev);
1718         struct siba_softc *siba = sd->sd_bus;
1719
1720         return (siba_powerdown_sub(siba));
1721 }
1722
1723 static int
1724 siba_powerdown_sub(struct siba_softc *siba)
1725 {
1726         struct siba_cc *scc;
1727
1728         if (siba->siba_type == SIBA_TYPE_SSB)
1729                 return (0);
1730
1731         scc = &siba->siba_cc;
1732         if (!scc->scc_dev || scc->scc_dev->sd_id.sd_rev < 5)
1733                 return (0);
1734         siba_cc_clock(scc, SIBA_CLOCK_SLOW);
1735         siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0);
1736         return (0);
1737 }
1738
1739 static void
1740 siba_pcicore_init(struct siba_pci *spc)
1741 {
1742         struct siba_dev_softc *sd = spc->spc_dev;
1743
1744         if (sd == NULL)
1745                 return;
1746
1747         if (!siba_dev_isup_sub(sd))
1748                 siba_dev_up_sub(sd, 0);
1749
1750         KASSERT(spc->spc_hostmode == 0,
1751             ("%s:%d: hostmode", __func__, __LINE__));
1752         /* disable PCI interrupt */
1753         siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0);
1754 }
1755
1756 int
1757 siba_dev_isup(device_t dev)
1758 {
1759         struct siba_dev_softc *sd = device_get_ivars(dev);
1760
1761         return (siba_dev_isup_sub(sd));
1762 }
1763
1764 static int
1765 siba_dev_isup_sub(struct siba_dev_softc *sd)
1766 {
1767         uint32_t reject, val;
1768
1769         reject = siba_tmslow_reject_bitmask(sd);
1770         val = siba_read_4_sub(sd, SIBA_TGSLOW);
1771         val &= SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_RESET | reject;
1772
1773         return (val == SIBA_TGSLOW_CLOCK);
1774 }
1775
1776 void
1777 siba_dev_up(device_t dev, uint32_t flags)
1778 {
1779         struct siba_dev_softc *sd = device_get_ivars(dev);
1780
1781         siba_dev_up_sub(sd, flags);
1782 }
1783
1784 static void
1785 siba_dev_up_sub(struct siba_dev_softc *sd, uint32_t flags)
1786 {
1787         uint32_t val;
1788
1789         siba_dev_down_sub(sd, flags);
1790         siba_write_4_sub(sd, SIBA_TGSLOW,
1791             SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
1792         siba_read_4_sub(sd, SIBA_TGSLOW);
1793         DELAY(1);
1794
1795         if (siba_read_4_sub(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR)
1796                 siba_write_4_sub(sd, SIBA_TGSHIGH, 0);
1797
1798         val = siba_read_4_sub(sd, SIBA_IAS);
1799         if (val & (SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT)) {
1800                 val &= ~(SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT);
1801                 siba_write_4_sub(sd, SIBA_IAS, val);
1802         }
1803
1804         siba_write_4_sub(sd, SIBA_TGSLOW,
1805             SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
1806         siba_read_4_sub(sd, SIBA_TGSLOW);
1807         DELAY(1);
1808
1809         siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags);
1810         siba_read_4_sub(sd, SIBA_TGSLOW);
1811         DELAY(1);
1812 }
1813
1814 static uint32_t
1815 siba_tmslow_reject_bitmask(struct siba_dev_softc *sd)
1816 {
1817         uint32_t rev = siba_read_4_sub(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV;
1818
1819         switch (rev) {
1820         case SIBA_IDLOW_SSBREV_22:
1821                 return (SIBA_TGSLOW_REJECT_22);
1822         case SIBA_IDLOW_SSBREV_23:
1823                 return (SIBA_TGSLOW_REJECT_23);
1824         case SIBA_IDLOW_SSBREV_24:
1825         case SIBA_IDLOW_SSBREV_25:
1826         case SIBA_IDLOW_SSBREV_26:
1827         case SIBA_IDLOW_SSBREV_27:
1828                 return (SIBA_TGSLOW_REJECT_23);
1829         default:
1830                 KASSERT(0 == 1,
1831                     ("%s:%d: unknown backplane rev %#x\n",
1832                         __func__, __LINE__, rev));
1833         }
1834         return (SIBA_TGSLOW_REJECT_22 | SIBA_TGSLOW_REJECT_23);
1835 }
1836
1837 void
1838 siba_dev_down(device_t dev, uint32_t flags)
1839 {
1840         struct siba_dev_softc *sd = device_get_ivars(dev);
1841
1842         siba_dev_down_sub(sd, flags);
1843 }
1844
1845 static void
1846 siba_dev_down_sub(struct siba_dev_softc *sd, uint32_t flags)
1847 {
1848         struct siba_softc *siba = sd->sd_bus;
1849         uint32_t reject, val;
1850         int i;
1851
1852         if (siba_read_4_sub(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET)
1853                 return;
1854
1855         reject = siba_tmslow_reject_bitmask(sd);
1856         siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK);
1857
1858         for (i = 0; i < 1000; i++) {
1859                 val = siba_read_4_sub(sd, SIBA_TGSLOW);
1860                 if (val & reject)
1861                         break;
1862                 DELAY(10);
1863         }
1864         if ((val & reject) == 0) {
1865                 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n",
1866                     reject, SIBA_TGSLOW);
1867         }
1868         for (i = 0; i < 1000; i++) {
1869                 val = siba_read_4_sub(sd, SIBA_TGSHIGH);
1870                 if (!(val & SIBA_TGSHIGH_BUSY))
1871                         break;
1872                 DELAY(10);
1873         }
1874         if ((val & SIBA_TGSHIGH_BUSY) != 0) {
1875                 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n",
1876                     SIBA_TGSHIGH_BUSY, SIBA_TGSHIGH);
1877         }
1878
1879         siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK |
1880             reject | SIBA_TGSLOW_RESET | flags);
1881         siba_read_4_sub(sd, SIBA_TGSLOW);
1882         DELAY(1);
1883         siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags);
1884         siba_read_4_sub(sd, SIBA_TGSLOW);
1885         DELAY(1);
1886 }
1887
1888 static void
1889 siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd)
1890 {
1891         struct siba_dev_softc *psd = spc->spc_dev;
1892         struct siba_softc *siba = psd->sd_bus;
1893         uint32_t tmp;
1894
1895         if (psd->sd_id.sd_device == SIBA_DEVID_PCI) {
1896                 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2,
1897                     siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2) |
1898                     SIBA_PCICORE_SBTOPCI_PREF | SIBA_PCICORE_SBTOPCI_BURST);
1899
1900                 if (psd->sd_id.sd_rev < 5) {
1901                         tmp = siba_read_4_sub(psd, SIBA_IMCFGLO);
1902                         tmp &= ~SIBA_IMCFGLO_SERTO;
1903                         tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO;
1904                         tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */;
1905                         siba_write_4_sub(psd, SIBA_IMCFGLO, tmp);
1906
1907                         /* broadcast value */
1908                         sd = (siba->siba_cc.scc_dev != NULL) ?
1909                             siba->siba_cc.scc_dev : siba->siba_pci.spc_dev;
1910                         if (sd != NULL) {
1911                                 siba_write_4_sub(sd, SIBA_PCICORE_BCAST_ADDR,
1912                                     0xfd8);
1913                                 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_ADDR);
1914                                 siba_write_4_sub(sd,
1915                                     SIBA_PCICORE_BCAST_DATA, 0);
1916                                 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_DATA);
1917                         }
1918                 } else if (psd->sd_id.sd_rev >= 11) {
1919                         tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2);
1920                         tmp |= SIBA_PCICORE_SBTOPCI_MRM;
1921                         siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp);
1922                 }
1923         } else {
1924                 KASSERT(psd->sd_id.sd_device == SIBA_DEVID_PCIE, ("only PCIE"));
1925                 if ((psd->sd_id.sd_rev == 0) || (psd->sd_id.sd_rev == 1))
1926                         siba_pcie_write(spc, 0x4,
1927                             siba_pcie_read(spc, 0x4) | 0x8);
1928                 if (psd->sd_id.sd_rev == 0) {
1929                         siba_pcie_mdio_write(spc, 0x1f, 2, 0x8128); /* Timer */
1930                         siba_pcie_mdio_write(spc, 0x1f, 6, 0x0100); /* CDR */
1931                         siba_pcie_mdio_write(spc, 0x1f, 7, 0x1466); /* CDR BW */
1932                 } else if (psd->sd_id.sd_rev == 1)
1933                         siba_pcie_write(spc, 0x100,
1934                             siba_pcie_read(spc, 0x100) | 0x40);
1935         }
1936         spc->spc_inited = 1;
1937 }
1938
1939 void
1940 siba_pcicore_intr(device_t dev)
1941 {
1942         struct siba_dev_softc *sd = device_get_ivars(dev);
1943         struct siba_softc *siba = sd->sd_bus;
1944         struct siba_pci *spc = &siba->siba_pci;
1945         struct siba_dev_softc *psd = spc->spc_dev;
1946         uint32_t tmp;
1947
1948         if (siba->siba_type != SIBA_TYPE_PCI || !psd)
1949                 return;
1950
1951         KASSERT(siba == psd->sd_bus, ("different pointers"));
1952
1953         /* enable interrupts */
1954         if (siba->siba_dev != NULL &&
1955             (psd->sd_id.sd_rev >= 6 ||
1956              psd->sd_id.sd_device == SIBA_DEVID_PCIE)) {
1957                 tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4);
1958                 tmp |= (1 << sd->sd_coreidx) << 8;
1959                 pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4);
1960         } else {
1961                 tmp = siba_read_4_sub(sd, SIBA_TPS);
1962                 tmp &= SIBA_TPS_BPFLAG;
1963                 siba_write_4_sub(psd, SIBA_INTR_MASK,
1964                     siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp));
1965         }
1966
1967         /* setup PCIcore */
1968         if (spc->spc_inited == 0)
1969                 siba_pcicore_setup(spc, sd);
1970 }
1971
1972 static uint32_t
1973 siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset)
1974 {
1975
1976         return (siba_read_4_sub(spc->spc_dev, offset));
1977 }
1978
1979 static void
1980 siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value)
1981 {
1982
1983         siba_write_4_sub(spc->spc_dev, offset, value);
1984 }
1985
1986 static uint32_t
1987 siba_pcie_read(struct siba_pci *spc, uint32_t address)
1988 {
1989
1990         siba_pcicore_write_4(spc, 0x130, address);
1991         return (siba_pcicore_read_4(spc, 0x134));
1992 }
1993
1994 static void
1995 siba_pcie_write(struct siba_pci *spc, uint32_t address, uint32_t data)
1996 {
1997
1998         siba_pcicore_write_4(spc, 0x130, address);
1999         siba_pcicore_write_4(spc, 0x134, data);
2000 }
2001
2002 static void
2003 siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address,
2004     uint16_t data)
2005 {
2006         int i;
2007
2008         siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0x80 | 0x2);
2009         siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_DATA,
2010             (1 << 30) | (1 << 28) |
2011             ((uint32_t)device << 22) | ((uint32_t)address << 18) |
2012             (1 << 17) | data);
2013         DELAY(10);
2014         for (i = 0; i < 10; i++) {
2015                 if (siba_pcicore_read_4(spc, SIBA_PCICORE_MDIO_CTL) & 0x100)
2016                         break;
2017                 DELAY(1000);
2018         }
2019         siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0);
2020 }
2021
2022 uint32_t
2023 siba_dma_translation(device_t dev)
2024 {
2025 #ifdef INVARIANTS
2026         struct siba_dev_softc *sd = device_get_ivars(dev);
2027         struct siba_softc *siba = sd->sd_bus;
2028
2029         KASSERT(siba->siba_type == SIBA_TYPE_PCI,
2030             ("unsupported bustype %d\n", siba->siba_type));
2031 #endif
2032         return (SIBA_PCI_DMA);
2033 }
2034
2035 void
2036 siba_barrier(device_t dev, int flags)
2037 {
2038         struct siba_dev_softc *sd = device_get_ivars(dev);
2039         struct siba_softc *siba = sd->sd_bus;
2040
2041         SIBA_BARRIER(siba, flags);
2042 }
2043
2044 static void
2045 siba_cc_suspend(struct siba_cc *scc)
2046 {
2047
2048         siba_cc_clock(scc, SIBA_CLOCK_SLOW);
2049 }
2050
2051 static void
2052 siba_cc_resume(struct siba_cc *scc)
2053 {
2054
2055         siba_cc_power_init(scc);
2056         siba_cc_clock(scc, SIBA_CLOCK_FAST);
2057 }
2058
2059 int
2060 siba_core_suspend(struct siba_softc *siba)
2061 {
2062
2063         siba_cc_suspend(&siba->siba_cc);
2064         siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0);
2065         return (0);
2066 }
2067
2068 int
2069 siba_core_resume(struct siba_softc *siba)
2070 {
2071
2072         siba->siba_pci.spc_inited = 0;
2073         siba->siba_curdev = NULL;
2074
2075         siba_powerup_sub(siba, 0);
2076         /* XXX setup H/W for PCMCIA??? */
2077         siba_cc_resume(&siba->siba_cc);
2078         siba_powerdown_sub(siba);
2079
2080         return (0);
2081 }
2082
2083 static void
2084 siba_cc_regctl_setmask(struct siba_cc *cc, uint32_t offset, uint32_t mask,
2085     uint32_t set)
2086 {
2087
2088         SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR);
2089         SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_ADDR, offset);
2090         SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR);
2091         SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_DATA,
2092             (SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA) & mask) | set);
2093         SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA);
2094 }
2095
2096 void
2097 siba_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt)
2098 {
2099         struct siba_dev_softc *sd = device_get_ivars(dev);
2100         struct siba_softc *siba = sd->sd_bus;
2101         struct siba_cc *scc = &siba->siba_cc;
2102         uint32_t *p = NULL, info[5][3] = {
2103                 { 2, 25,  0xf },
2104                 { 3,  1,  0xf },
2105                 { 3,  9,  0xf },
2106                 { 3, 17, 0x3f },
2107                 { 0, 21, 0x3f }
2108         };
2109
2110         if (siba->siba_chipid == 0x4312) {
2111                 if (id != SIBA_LDO_PAREF)
2112                         return;
2113                 p = info[4];
2114                 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
2115                     (volt & p[2]) << p[1]);
2116                 return;
2117         }
2118         if (siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354) {
2119                 switch (id) {
2120                 case SIBA_LDO_PAREF:
2121                         p = info[3];
2122                         break;
2123                 case SIBA_LDO_VOLT1:
2124                         p = info[0];
2125                         break;
2126                 case SIBA_LDO_VOLT2:
2127                         p = info[1];
2128                         break;
2129                 case SIBA_LDO_VOLT3:
2130                         p = info[2];
2131                         break;
2132                 default:
2133                         KASSERT(0 == 1,
2134                             ("%s: unsupported voltage ID %#x", __func__, id));
2135                         return;
2136                 }
2137                 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
2138                     (volt & p[2]) << p[1]);
2139         }
2140 }
2141
2142 void
2143 siba_cc_pmu_set_ldoparef(device_t dev, uint8_t on)
2144 {
2145         struct siba_dev_softc *sd = device_get_ivars(dev);
2146         struct siba_softc *siba = sd->sd_bus;
2147         struct siba_cc *scc = &siba->siba_cc;
2148         int ldo;
2149
2150         ldo = ((siba->siba_chipid == 0x4312) ? SIBA_CC_PMU_4312_PA_REF :
2151             ((siba->siba_chipid == 0x4328) ? SIBA_CC_PMU_4328_PA_REF :
2152             ((siba->siba_chipid == 0x5354) ? SIBA_CC_PMU_5354_PA_REF : -1)));
2153         if (ldo == -1)
2154                 return;
2155
2156         if (on)
2157                 SIBA_CC_SET32(scc, SIBA_CC_PMU_MINRES, 1 << ldo);
2158         else
2159                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo));
2160         SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES);
2161 }
2162
2163 int
2164 siba_read_sprom(device_t dev, device_t child, int which, uintptr_t *result)
2165 {
2166         struct siba_dev_softc *sd = device_get_ivars(child);
2167         struct siba_softc *siba = sd->sd_bus;
2168
2169         switch (which) {
2170         case SIBA_SPROMVAR_REV:
2171                 *result = siba->siba_sprom.rev;
2172                 break;
2173         case SIBA_SPROMVAR_MAC_80211BG:
2174                 *((uint8_t **) result) = siba->siba_sprom.mac_80211bg;
2175                 break;
2176         case SIBA_SPROMVAR_MAC_ETH:
2177                 *((uint8_t **) result) = siba->siba_sprom.mac_eth;
2178                 break;
2179         case SIBA_SPROMVAR_MAC_80211A:
2180                 *((uint8_t **) result) = siba->siba_sprom.mac_80211a;
2181                 break;
2182         case SIBA_SPROMVAR_MII_ETH0:
2183                 *result = siba->siba_sprom.mii_eth0;
2184                 break;
2185         case SIBA_SPROMVAR_MII_ETH1:
2186                 *result = siba->siba_sprom.mii_eth1;
2187                 break;
2188         case SIBA_SPROMVAR_MDIO_ETH0:
2189                 *result = siba->siba_sprom.mdio_eth0;
2190                 break;
2191         case SIBA_SPROMVAR_MDIO_ETH1:
2192                 *result = siba->siba_sprom.mdio_eth1;
2193                 break;
2194         case SIBA_SPROMVAR_BREV:
2195                 *result = siba->siba_sprom.brev;
2196                 break;
2197         case SIBA_SPROMVAR_CCODE:
2198                 *result = siba->siba_sprom.ccode;
2199                 break;
2200         case SIBA_SPROMVAR_ANT_A:
2201                 *result = siba->siba_sprom.ant_a;
2202                 break;
2203         case SIBA_SPROMVAR_ANT_BG:
2204                 *result = siba->siba_sprom.ant_bg;
2205                 break;
2206         case SIBA_SPROMVAR_PA0B0:
2207                 *result = siba->siba_sprom.pa0b0;
2208                 break;
2209         case SIBA_SPROMVAR_PA0B1:
2210                 *result = siba->siba_sprom.pa0b1;
2211                 break;
2212         case SIBA_SPROMVAR_PA0B2:
2213                 *result = siba->siba_sprom.pa0b2;
2214                 break;
2215         case SIBA_SPROMVAR_PA1B0:
2216                 *result = siba->siba_sprom.pa1b0;
2217                 break;
2218         case SIBA_SPROMVAR_PA1B1:
2219                 *result = siba->siba_sprom.pa1b1;
2220                 break;
2221         case SIBA_SPROMVAR_PA1B2:
2222                 *result = siba->siba_sprom.pa1b2;
2223                 break;
2224         case SIBA_SPROMVAR_PA1LOB0:
2225                 *result = siba->siba_sprom.pa1lob0;
2226                 break;
2227         case SIBA_SPROMVAR_PA1LOB1:
2228                 *result = siba->siba_sprom.pa1lob1;
2229                 break;
2230         case SIBA_SPROMVAR_PA1LOB2:
2231                 *result = siba->siba_sprom.pa1lob2;
2232                 break;
2233         case SIBA_SPROMVAR_PA1HIB0:
2234                 *result = siba->siba_sprom.pa1hib0;
2235                 break;
2236         case SIBA_SPROMVAR_PA1HIB1:
2237                 *result = siba->siba_sprom.pa1hib1;
2238                 break;
2239         case SIBA_SPROMVAR_PA1HIB2:
2240                 *result = siba->siba_sprom.pa1hib2;
2241                 break;
2242         case SIBA_SPROMVAR_GPIO0:
2243                 *result = siba->siba_sprom.gpio0;
2244                 break;
2245         case SIBA_SPROMVAR_GPIO1:
2246                 *result = siba->siba_sprom.gpio1;
2247                 break;
2248         case SIBA_SPROMVAR_GPIO2:
2249                 *result = siba->siba_sprom.gpio2;
2250                 break;
2251         case SIBA_SPROMVAR_GPIO3:
2252                 *result = siba->siba_sprom.gpio3;
2253                 break;
2254         case SIBA_SPROMVAR_MAXPWR_AL:
2255                 *result = siba->siba_sprom.maxpwr_al;
2256                 break;
2257         case SIBA_SPROMVAR_MAXPWR_A:
2258                 *result = siba->siba_sprom.maxpwr_a;
2259                 break;
2260         case SIBA_SPROMVAR_MAXPWR_AH:
2261                 *result = siba->siba_sprom.maxpwr_ah;
2262                 break;
2263         case SIBA_SPROMVAR_MAXPWR_BG:
2264                 *result = siba->siba_sprom.maxpwr_bg;
2265                 break;
2266         case SIBA_SPROMVAR_RXPO2G:
2267                 *result = siba->siba_sprom.rxpo2g;
2268                 break;
2269         case SIBA_SPROMVAR_RXPO5G:
2270                 *result = siba->siba_sprom.rxpo5g;
2271                 break;
2272         case SIBA_SPROMVAR_TSSI_A:
2273                 *result = siba->siba_sprom.tssi_a;
2274                 break;
2275         case SIBA_SPROMVAR_TSSI_BG:
2276                 *result = siba->siba_sprom.tssi_bg;
2277                 break;
2278         case SIBA_SPROMVAR_TRI2G:
2279                 *result = siba->siba_sprom.tri2g;
2280                 break;
2281         case SIBA_SPROMVAR_TRI5GL:
2282                 *result = siba->siba_sprom.tri5gl;
2283                 break;
2284         case SIBA_SPROMVAR_TRI5G:
2285                 *result = siba->siba_sprom.tri5g;
2286                 break;
2287         case SIBA_SPROMVAR_TRI5GH:
2288                 *result = siba->siba_sprom.tri5gh;
2289                 break;
2290         case SIBA_SPROMVAR_RSSISAV2G:
2291                 *result = siba->siba_sprom.rssisav2g;
2292                 break;
2293         case SIBA_SPROMVAR_RSSISMC2G:
2294                 *result = siba->siba_sprom.rssismc2g;
2295                 break;
2296         case SIBA_SPROMVAR_RSSISMF2G:
2297                 *result = siba->siba_sprom.rssismf2g;
2298                 break;
2299         case SIBA_SPROMVAR_BXA2G:
2300                 *result = siba->siba_sprom.bxa2g;
2301                 break;
2302         case SIBA_SPROMVAR_RSSISAV5G:
2303                 *result = siba->siba_sprom.rssisav5g;
2304                 break;
2305         case SIBA_SPROMVAR_RSSISMC5G:
2306                 *result = siba->siba_sprom.rssismc5g;
2307                 break;
2308         case SIBA_SPROMVAR_RSSISMF5G:
2309                 *result = siba->siba_sprom.rssismf5g;
2310                 break;
2311         case SIBA_SPROMVAR_BXA5G:
2312                 *result = siba->siba_sprom.bxa5g;
2313                 break;
2314         case SIBA_SPROMVAR_CCK2GPO:
2315                 *result = siba->siba_sprom.cck2gpo;
2316                 break;
2317         case SIBA_SPROMVAR_OFDM2GPO:
2318                 *result = siba->siba_sprom.ofdm2gpo;
2319                 break;
2320         case SIBA_SPROMVAR_OFDM5GLPO:
2321                 *result = siba->siba_sprom.ofdm5glpo;
2322                 break;
2323         case SIBA_SPROMVAR_OFDM5GPO:
2324                 *result = siba->siba_sprom.ofdm5gpo;
2325                 break;
2326         case SIBA_SPROMVAR_OFDM5GHPO:
2327                 *result = siba->siba_sprom.ofdm5ghpo;
2328                 break;
2329         case SIBA_SPROMVAR_BF_LO:
2330                 *result = siba->siba_sprom.bf_lo;
2331                 break;
2332         case SIBA_SPROMVAR_BF_HI:
2333                 *result = siba->siba_sprom.bf_hi;
2334                 break;
2335         case SIBA_SPROMVAR_BF2_LO:
2336                 *result = siba->siba_sprom.bf2_lo;
2337                 break;
2338         case SIBA_SPROMVAR_BF2_HI:
2339                 *result = siba->siba_sprom.bf2_hi;
2340                 break;
2341         default:
2342                 return (ENOENT);
2343         }
2344         return (0);
2345 }
2346
2347 int
2348 siba_write_sprom(device_t dev, device_t child, int which, uintptr_t value)
2349 {
2350         struct siba_dev_softc *sd = device_get_ivars(child);
2351         struct siba_softc *siba = sd->sd_bus;
2352
2353         switch (which) {
2354         case SIBA_SPROMVAR_REV:
2355                 siba->siba_sprom.rev = value;
2356                 break;
2357         case SIBA_SPROMVAR_MII_ETH0:
2358                 siba->siba_sprom.mii_eth0 = value;
2359                 break;
2360         case SIBA_SPROMVAR_MII_ETH1:
2361                 siba->siba_sprom.mii_eth1 = value;
2362                 break;
2363         case SIBA_SPROMVAR_MDIO_ETH0:
2364                 siba->siba_sprom.mdio_eth0 = value;
2365                 break;
2366         case SIBA_SPROMVAR_MDIO_ETH1:
2367                 siba->siba_sprom.mdio_eth1 = value;
2368                 break;
2369         case SIBA_SPROMVAR_BREV:
2370                 siba->siba_sprom.brev = value;
2371                 break;
2372         case SIBA_SPROMVAR_CCODE:
2373                 siba->siba_sprom.ccode = value;
2374                 break;
2375         case SIBA_SPROMVAR_ANT_A:
2376                 siba->siba_sprom.ant_a = value;
2377                 break;
2378         case SIBA_SPROMVAR_ANT_BG:
2379                 siba->siba_sprom.ant_bg = value;
2380                 break;
2381         case SIBA_SPROMVAR_PA0B0:
2382                 siba->siba_sprom.pa0b0 = value;
2383                 break;
2384         case SIBA_SPROMVAR_PA0B1:
2385                 siba->siba_sprom.pa0b1 = value;
2386                 break;
2387         case SIBA_SPROMVAR_PA0B2:
2388                 siba->siba_sprom.pa0b2 = value;
2389                 break;
2390         case SIBA_SPROMVAR_PA1B0:
2391                 siba->siba_sprom.pa1b0 = value;
2392                 break;
2393         case SIBA_SPROMVAR_PA1B1:
2394                 siba->siba_sprom.pa1b1 = value;
2395                 break;
2396         case SIBA_SPROMVAR_PA1B2:
2397                 siba->siba_sprom.pa1b2 = value;
2398                 break;
2399         case SIBA_SPROMVAR_PA1LOB0:
2400                 siba->siba_sprom.pa1lob0 = value;
2401                 break;
2402         case SIBA_SPROMVAR_PA1LOB1:
2403                 siba->siba_sprom.pa1lob1 = value;
2404                 break;
2405         case SIBA_SPROMVAR_PA1LOB2:
2406                 siba->siba_sprom.pa1lob2 = value;
2407                 break;
2408         case SIBA_SPROMVAR_PA1HIB0:
2409                 siba->siba_sprom.pa1hib0 = value;
2410                 break;
2411         case SIBA_SPROMVAR_PA1HIB1:
2412                 siba->siba_sprom.pa1hib1 = value;
2413                 break;
2414         case SIBA_SPROMVAR_PA1HIB2:
2415                 siba->siba_sprom.pa1hib2 = value;
2416                 break;
2417         case SIBA_SPROMVAR_GPIO0:
2418                 siba->siba_sprom.gpio0 = value;
2419                 break;
2420         case SIBA_SPROMVAR_GPIO1:
2421                 siba->siba_sprom.gpio1 = value;
2422                 break;
2423         case SIBA_SPROMVAR_GPIO2:
2424                 siba->siba_sprom.gpio2 = value;
2425                 break;
2426         case SIBA_SPROMVAR_GPIO3:
2427                 siba->siba_sprom.gpio3 = value;
2428                 break;
2429         case SIBA_SPROMVAR_MAXPWR_AL:
2430                 siba->siba_sprom.maxpwr_al = value;
2431                 break;
2432         case SIBA_SPROMVAR_MAXPWR_A:
2433                 siba->siba_sprom.maxpwr_a = value;
2434                 break;
2435         case SIBA_SPROMVAR_MAXPWR_AH:
2436                 siba->siba_sprom.maxpwr_ah = value;
2437                 break;
2438         case SIBA_SPROMVAR_MAXPWR_BG:
2439                 siba->siba_sprom.maxpwr_bg = value;
2440                 break;
2441         case SIBA_SPROMVAR_RXPO2G:
2442                 siba->siba_sprom.rxpo2g = value;
2443                 break;
2444         case SIBA_SPROMVAR_RXPO5G:
2445                 siba->siba_sprom.rxpo5g = value;
2446                 break;
2447         case SIBA_SPROMVAR_TSSI_A:
2448                 siba->siba_sprom.tssi_a = value;
2449                 break;
2450         case SIBA_SPROMVAR_TSSI_BG:
2451                 siba->siba_sprom.tssi_bg = value;
2452                 break;
2453         case SIBA_SPROMVAR_TRI2G:
2454                 siba->siba_sprom.tri2g = value;
2455                 break;
2456         case SIBA_SPROMVAR_TRI5GL:
2457                 siba->siba_sprom.tri5gl = value;
2458                 break;
2459         case SIBA_SPROMVAR_TRI5G:
2460                 siba->siba_sprom.tri5g = value;
2461                 break;
2462         case SIBA_SPROMVAR_TRI5GH:
2463                 siba->siba_sprom.tri5gh = value;
2464                 break;
2465         case SIBA_SPROMVAR_RSSISAV2G:
2466                 siba->siba_sprom.rssisav2g = value;
2467                 break;
2468         case SIBA_SPROMVAR_RSSISMC2G:
2469                 siba->siba_sprom.rssismc2g = value;
2470                 break;
2471         case SIBA_SPROMVAR_RSSISMF2G:
2472                 siba->siba_sprom.rssismf2g = value;
2473                 break;
2474         case SIBA_SPROMVAR_BXA2G:
2475                 siba->siba_sprom.bxa2g = value;
2476                 break;
2477         case SIBA_SPROMVAR_RSSISAV5G:
2478                 siba->siba_sprom.rssisav5g = value;
2479                 break;
2480         case SIBA_SPROMVAR_RSSISMC5G:
2481                 siba->siba_sprom.rssismc5g = value;
2482                 break;
2483         case SIBA_SPROMVAR_RSSISMF5G:
2484                 siba->siba_sprom.rssismf5g = value;
2485                 break;
2486         case SIBA_SPROMVAR_BXA5G:
2487                 siba->siba_sprom.bxa5g = value;
2488                 break;
2489         case SIBA_SPROMVAR_CCK2GPO:
2490                 siba->siba_sprom.cck2gpo = value;
2491                 break;
2492         case SIBA_SPROMVAR_OFDM2GPO:
2493                 siba->siba_sprom.ofdm2gpo = value;
2494                 break;
2495         case SIBA_SPROMVAR_OFDM5GLPO:
2496                 siba->siba_sprom.ofdm5glpo = value;
2497                 break;
2498         case SIBA_SPROMVAR_OFDM5GPO:
2499                 siba->siba_sprom.ofdm5gpo = value;
2500                 break;
2501         case SIBA_SPROMVAR_OFDM5GHPO:
2502                 siba->siba_sprom.ofdm5ghpo = value;
2503                 break;
2504         case SIBA_SPROMVAR_BF_LO:
2505                 siba->siba_sprom.bf_lo = value;
2506                 break;
2507         case SIBA_SPROMVAR_BF_HI:
2508                 siba->siba_sprom.bf_hi = value;
2509                 break;
2510         case SIBA_SPROMVAR_BF2_LO:
2511                 siba->siba_sprom.bf2_lo = value;
2512                 break;
2513         case SIBA_SPROMVAR_BF2_HI:
2514                 siba->siba_sprom.bf2_hi = value;
2515                 break;
2516         default:
2517                 return (ENOENT);
2518         }
2519         return (0);
2520 }
2521
2522 #define SIBA_GPIOCTL                    0x06c
2523
2524 uint32_t
2525 siba_gpio_get(device_t dev)
2526 {
2527         struct siba_dev_softc *sd = device_get_ivars(dev);
2528         struct siba_softc *siba = sd->sd_bus;
2529         struct siba_dev_softc *gpiodev, *pcidev = NULL;
2530
2531         pcidev = siba->siba_pci.spc_dev;
2532         gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
2533         if (!gpiodev)
2534                 return (-1);
2535         return (siba_read_4_sub(gpiodev, SIBA_GPIOCTL));
2536 }
2537
2538 void
2539 siba_gpio_set(device_t dev, uint32_t value)
2540 {
2541         struct siba_dev_softc *sd = device_get_ivars(dev);
2542         struct siba_softc *siba = sd->sd_bus;
2543         struct siba_dev_softc *gpiodev, *pcidev = NULL;
2544
2545         pcidev = siba->siba_pci.spc_dev;
2546         gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
2547         if (!gpiodev)
2548                 return;
2549         siba_write_4_sub(gpiodev, SIBA_GPIOCTL, value);
2550 }
2551
2552 void
2553 siba_fix_imcfglobug(device_t dev)
2554 {
2555         struct siba_dev_softc *sd = device_get_ivars(dev);
2556         struct siba_softc *siba = sd->sd_bus;
2557         uint32_t tmp;
2558
2559         if (siba->siba_pci.spc_dev == NULL)
2560                 return;
2561         if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI ||
2562             siba->siba_pci.spc_dev->sd_id.sd_rev > 5)
2563                 return;
2564
2565         tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) &
2566             ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO);
2567         switch (siba->siba_type) {
2568         case SIBA_TYPE_PCI:
2569         case SIBA_TYPE_PCMCIA:
2570                 tmp |= 0x32;
2571                 break;
2572         case SIBA_TYPE_SSB:
2573                 tmp |= 0x53;
2574                 break;
2575         }
2576         siba_write_4_sub(sd, SIBA_IMCFGLO, tmp);
2577 }