2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * the Sonics Silicon Backplane driver.
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/module.h>
40 #include <sys/kernel.h>
41 #include <sys/endian.h>
42 #include <sys/errno.h>
44 #include <sys/mutex.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
49 #include <sys/socket.h>
52 #include <net/if_media.h>
53 #include <net/if_arp.h>
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pcireg.h>
58 #include <dev/siba/siba_ids.h>
59 #include <dev/siba/sibareg.h>
60 #include <dev/siba/sibavar.h>
64 SIBA_DEBUG_SCAN = 0x00000001, /* scan */
65 SIBA_DEBUG_PMU = 0x00000002, /* PMU */
66 SIBA_DEBUG_PLL = 0x00000004, /* PLL */
67 SIBA_DEBUG_SWITCHCORE = 0x00000008, /* switching core */
68 SIBA_DEBUG_SPROM = 0x00000010, /* SPROM */
69 SIBA_DEBUG_CORE = 0x00000020, /* handling cores */
70 SIBA_DEBUG_ANY = 0xffffffff
72 #define DPRINTF(siba, m, fmt, ...) do { \
73 if (siba->siba_debug & (m)) \
74 printf(fmt, __VA_ARGS__); \
77 #define DPRINTF(siba, m, fmt, ...) do { (void) siba; } while (0)
79 #define N(a) (sizeof(a) / sizeof(a[0]))
81 static void siba_pci_gpio(struct siba_softc *, uint32_t, int);
82 static void siba_scan(struct siba_softc *);
83 static int siba_switchcore(struct siba_softc *, uint8_t);
84 static int siba_pci_switchcore_sub(struct siba_softc *, uint8_t);
85 static uint32_t siba_scan_read_4(struct siba_softc *, uint8_t, uint16_t);
86 static uint16_t siba_dev2chipid(struct siba_softc *);
87 static uint16_t siba_pci_read_2(struct siba_dev_softc *, uint16_t);
88 static uint32_t siba_pci_read_4(struct siba_dev_softc *, uint16_t);
89 static void siba_pci_write_2(struct siba_dev_softc *, uint16_t, uint16_t);
90 static void siba_pci_write_4(struct siba_dev_softc *, uint16_t, uint32_t);
91 static void siba_cc_clock(struct siba_cc *,
93 static void siba_cc_pmu_init(struct siba_cc *);
94 static void siba_cc_power_init(struct siba_cc *);
95 static void siba_cc_powerup_delay(struct siba_cc *);
96 static int siba_cc_clockfreq(struct siba_cc *, int);
97 static void siba_cc_pmu1_pll0_init(struct siba_cc *, uint32_t);
98 static void siba_cc_pmu0_pll0_init(struct siba_cc *, uint32_t);
99 static enum siba_clksrc siba_cc_clksrc(struct siba_cc *);
100 static const struct siba_cc_pmu1_plltab *siba_cc_pmu1_plltab_find(uint32_t);
101 static uint32_t siba_cc_pll_read(struct siba_cc *, uint32_t);
102 static void siba_cc_pll_write(struct siba_cc *, uint32_t,
104 static const struct siba_cc_pmu0_plltab *
105 siba_cc_pmu0_plltab_findentry(uint32_t);
106 static int siba_pci_sprom(struct siba_softc *, struct siba_sprom *);
107 static int siba_sprom_read(struct siba_softc *, uint16_t *, uint16_t);
108 static int sprom_check_crc(const uint16_t *, size_t);
109 static uint8_t siba_crc8(uint8_t, uint8_t);
110 static void siba_sprom_r123(struct siba_sprom *, const uint16_t *);
111 static void siba_sprom_r45(struct siba_sprom *, const uint16_t *);
112 static void siba_sprom_r8(struct siba_sprom *, const uint16_t *);
113 static int8_t siba_sprom_r123_antgain(uint8_t, const uint16_t *, uint16_t,
115 static uint32_t siba_tmslow_reject_bitmask(struct siba_dev_softc *);
116 static uint32_t siba_pcicore_read_4(struct siba_pci *, uint16_t);
117 static void siba_pcicore_write_4(struct siba_pci *, uint16_t, uint32_t);
118 static uint32_t siba_pcie_read(struct siba_pci *, uint32_t);
119 static void siba_pcie_write(struct siba_pci *, uint32_t, uint32_t);
120 static void siba_pcie_mdio_write(struct siba_pci *, uint8_t, uint8_t,
122 static void siba_pci_read_multi_1(struct siba_dev_softc *, void *, size_t,
124 static void siba_pci_read_multi_2(struct siba_dev_softc *, void *, size_t,
126 static void siba_pci_read_multi_4(struct siba_dev_softc *, void *, size_t,
128 static void siba_pci_write_multi_1(struct siba_dev_softc *, const void *,
130 static void siba_pci_write_multi_2(struct siba_dev_softc *, const void *,
132 static void siba_pci_write_multi_4(struct siba_dev_softc *, const void *,
134 static const char *siba_core_name(uint16_t);
135 static void siba_pcicore_init(struct siba_pci *);
136 static uint32_t siba_read_4_sub(struct siba_dev_softc *, uint16_t);
137 static void siba_write_4_sub(struct siba_dev_softc *, uint16_t, uint32_t);
138 static void siba_powerup_sub(struct siba_softc *, int);
139 static int siba_powerdown_sub(struct siba_softc *);
140 static int siba_dev_isup_sub(struct siba_dev_softc *);
141 static void siba_dev_up_sub(struct siba_dev_softc *, uint32_t);
142 static void siba_dev_down_sub(struct siba_dev_softc *, uint32_t);
143 int siba_core_attach(struct siba_softc *);
144 int siba_core_detach(struct siba_softc *);
145 int siba_core_suspend(struct siba_softc *);
146 int siba_core_resume(struct siba_softc *);
147 uint8_t siba_getncores(device_t, uint16_t);
149 static const struct siba_bus_ops siba_pci_ops = {
150 .read_2 = siba_pci_read_2,
151 .read_4 = siba_pci_read_4,
152 .write_2 = siba_pci_write_2,
153 .write_4 = siba_pci_write_4,
154 .read_multi_1 = siba_pci_read_multi_1,
155 .read_multi_2 = siba_pci_read_multi_2,
156 .read_multi_4 = siba_pci_read_multi_4,
157 .write_multi_1 = siba_pci_write_multi_1,
158 .write_multi_2 = siba_pci_write_multi_2,
159 .write_multi_4 = siba_pci_write_multi_4,
162 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4325_updown[] =
163 SIBA_CC_PMU_4325_RES_UPDOWN;
164 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4325_depend[] =
165 SIBA_CC_PMU_4325_RES_DEPEND;
166 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4328_updown[] =
167 SIBA_CC_PMU_4328_RES_UPDOWN;
168 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4328_depend[] =
169 SIBA_CC_PMU_4328_RES_DEPEND;
170 static const struct siba_cc_pmu0_plltab siba_cc_pmu0_plltab[] =
171 SIBA_CC_PMU0_PLLTAB_ENTRY;
172 static const struct siba_cc_pmu1_plltab siba_cc_pmu1_plltab[] =
173 SIBA_CC_PMU1_PLLTAB_ENTRY;
176 siba_core_attach(struct siba_softc *siba)
181 KASSERT(siba->siba_type == SIBA_TYPE_PCI,
182 ("unsupported BUS type (%#x)", siba->siba_type));
184 siba->siba_ops = &siba_pci_ops;
186 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1);
189 /* XXX init PCI or PCMCIA host devices */
191 siba_powerup_sub(siba, 0);
193 /* init ChipCommon */
194 scc = &siba->siba_cc;
195 if (scc->scc_dev != NULL) {
196 siba_cc_pmu_init(scc);
197 siba_cc_power_init(scc);
198 siba_cc_clock(scc, SIBA_CLOCK_FAST);
199 siba_cc_powerup_delay(scc);
202 error = siba_pci_sprom(siba, &siba->siba_sprom);
204 siba_powerdown_sub(siba);
208 siba_pcicore_init(&siba->siba_pci);
209 siba_powerdown_sub(siba);
211 return (bus_generic_attach(siba->siba_dev));
215 siba_core_detach(struct siba_softc *siba)
218 int devcnt, error = 0, i;
220 error = device_get_children(siba->siba_dev, &devlistp, &devcnt);
224 for ( i = 0 ; i < devcnt ; i++)
225 device_delete_child(siba->siba_dev, devlistp[i]);
226 free(devlistp, M_TEMP);
231 siba_pci_gpio(struct siba_softc *siba, uint32_t what, int on)
236 if (siba->siba_type != SIBA_TYPE_PCI)
239 out = pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4);
241 if (what & SIBA_GPIO_PLL)
242 out |= SIBA_GPIO_PLL;
243 if (what & SIBA_GPIO_CRYSTAL)
244 out &= ~SIBA_GPIO_CRYSTAL;
245 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
246 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT_EN,
247 pci_read_config(siba->siba_dev,
248 SIBA_GPIO_OUT_EN, 4) | what, 4);
252 in = pci_read_config(siba->siba_dev, SIBA_GPIO_IN, 4);
253 if ((in & SIBA_GPIO_CRYSTAL) != SIBA_GPIO_CRYSTAL) {
254 if (what & SIBA_GPIO_CRYSTAL) {
255 out |= SIBA_GPIO_CRYSTAL;
256 if (what & SIBA_GPIO_PLL)
257 out |= SIBA_GPIO_PLL;
258 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
259 pci_write_config(siba->siba_dev,
260 SIBA_GPIO_OUT_EN, pci_read_config(siba->siba_dev,
261 SIBA_GPIO_OUT_EN, 4) | what, 4);
264 if (what & SIBA_GPIO_PLL) {
265 out &= ~SIBA_GPIO_PLL;
266 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
271 status = pci_read_config(siba->siba_dev, PCIR_STATUS, 2);
272 status &= ~PCIM_STATUS_STABORT;
273 pci_write_config(siba->siba_dev, PCIR_STATUS, status, 2);
277 siba_scan(struct siba_softc *siba)
279 struct siba_dev_softc *sd;
282 int base, dev_i = 0, error, i, is_pcie, n_80211 = 0, n_cc = 0,
285 KASSERT(siba->siba_type == SIBA_TYPE_PCI,
286 ("unsupported BUS type (%#x)", siba->siba_type));
288 siba->siba_ndevs = 0;
289 error = siba_switchcore(siba, 0); /* need the first core */
293 idhi = siba_scan_read_4(siba, 0, SIBA_IDHIGH);
294 if (SIBA_IDHIGH_CORECODE(idhi) == SIBA_DEVID_CHIPCOMMON) {
295 tmp = siba_scan_read_4(siba, 0, SIBA_CC_CHIPID);
296 siba->siba_chipid = SIBA_CC_ID(tmp);
297 siba->siba_chiprev = SIBA_CC_REV(tmp);
298 siba->siba_chippkg = SIBA_CC_PKG(tmp);
299 if (SIBA_IDHIGH_REV(idhi) >= 4)
300 siba->siba_ndevs = SIBA_CC_NCORES(tmp);
301 siba->siba_cc.scc_caps = siba_scan_read_4(siba, 0,
304 if (siba->siba_type == SIBA_TYPE_PCI) {
305 siba->siba_chipid = siba_dev2chipid(siba);
306 siba->siba_chiprev = pci_read_config(siba->siba_dev,
308 siba->siba_chippkg = 0;
310 siba->siba_chipid = 0x4710;
311 siba->siba_chiprev = 0;
312 siba->siba_chippkg = 0;
315 if (siba->siba_ndevs == 0)
316 siba->siba_ndevs = siba_getncores(siba->siba_dev,
318 if (siba->siba_ndevs > SIBA_MAX_CORES) {
319 device_printf(siba->siba_dev,
320 "too many siba cores (max %d %d)\n",
321 SIBA_MAX_CORES, siba->siba_ndevs);
325 /* looking basic information about each cores/devices */
326 for (i = 0; i < siba->siba_ndevs; i++) {
327 error = siba_switchcore(siba, i);
330 sd = &(siba->siba_devs[dev_i]);
331 idhi = siba_scan_read_4(siba, i, SIBA_IDHIGH);
333 sd->sd_id.sd_device = SIBA_IDHIGH_CORECODE(idhi);
334 sd->sd_id.sd_rev = SIBA_IDHIGH_REV(idhi);
335 sd->sd_id.sd_vendor = SIBA_IDHIGH_VENDOR(idhi);
336 sd->sd_ops = siba->siba_ops;
339 DPRINTF(siba, SIBA_DEBUG_SCAN,
340 "core %d (%s) found (cc %#xrev %#x vendor %#x)\n",
341 i, siba_core_name(sd->sd_id.sd_device),
342 sd->sd_id.sd_device, sd->sd_id.sd_rev, sd->sd_id.vendor);
344 switch (sd->sd_id.sd_device) {
345 case SIBA_DEVID_CHIPCOMMON:
348 device_printf(siba->siba_dev,
349 "warn: multiple ChipCommon\n");
352 siba->siba_cc.scc_dev = sd;
354 case SIBA_DEVID_80211:
357 device_printf(siba->siba_dev,
358 "warn: multiple 802.11 core\n");
363 case SIBA_DEVID_PCIE:
365 error = pci_find_extcap(siba->siba_dev, PCIY_EXPRESS,
367 is_pcie = (error == 0) ? 1 : 0;
370 device_printf(siba->siba_dev,
371 "warn: multiple PCI(E) cores\n");
374 if (sd->sd_id.sd_device == SIBA_DEVID_PCI &&
377 if (sd->sd_id.sd_device == SIBA_DEVID_PCIE &&
380 siba->siba_pci.spc_dev = sd;
382 case SIBA_DEVID_MODEM:
383 case SIBA_DEVID_PCMCIA:
386 device_printf(siba->siba_dev,
387 "unsupported coreid (%s)\n",
388 siba_core_name(sd->sd_id.sd_device));
393 child = device_add_child(siba->siba_dev, NULL, -1);
395 device_printf(siba->siba_dev, "child attach failed\n");
399 device_set_ivars(child, sd);
401 siba->siba_ndevs = dev_i;
405 siba_switchcore(struct siba_softc *siba, uint8_t idx)
408 switch (siba->siba_type) {
410 return (siba_pci_switchcore_sub(siba, idx));
413 ("%s: unsupported bustype %#x", __func__,
420 siba_pci_switchcore_sub(struct siba_softc *siba, uint8_t idx)
426 dir = SIBA_REGWIN(idx);
428 for (i = 0; i < RETRY_MAX; i++) {
429 pci_write_config(siba->siba_dev, SIBA_BAR0, dir, 4);
430 if (pci_read_config(siba->siba_dev, SIBA_BAR0, 4) == dir)
439 siba_pci_switchcore(struct siba_softc *siba, struct siba_dev_softc *sd)
443 DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "Switching to %s core, index %d\n",
444 siba_core_name(sd->sd_id.sd_device), sd->sd_coreidx);
446 error = siba_pci_switchcore_sub(siba, sd->sd_coreidx);
448 siba->siba_curdev = sd;
454 siba_scan_read_4(struct siba_softc *siba, uint8_t coreidx,
459 KASSERT(siba->siba_type == SIBA_TYPE_PCI,
460 ("unsupported BUS type (%#x)", siba->siba_type));
462 return (SIBA_READ_4(siba, offset));
466 siba_dev2chipid(struct siba_softc *siba)
470 switch (siba->siba_pci_did) {
506 case PCI_DEVICE_ID_BCM4401:
507 case PCI_DEVICE_ID_BCM4401B0:
508 case PCI_DEVICE_ID_BCM4401B1:
512 device_printf(siba->siba_dev, "unknown PCI did (%d)\n",
520 * Earlier ChipCommon revisions have hardcoded number of cores
521 * present dependent on the ChipCommon ID.
524 siba_getncores(device_t dev, uint16_t chipid)
535 case SIBA_CCID_SENTRY5:
539 case SIBA_CCID_BCM4710:
541 case SIBA_CCID_BCM4704:
544 device_printf(dev, "unknown the chipset ID %#x\n", chipid);
551 siba_core_name(uint16_t coreid)
555 case SIBA_DEVID_CHIPCOMMON:
556 return ("ChipCommon");
557 case SIBA_DEVID_ILINE20:
559 case SIBA_DEVID_SDRAM:
563 case SIBA_DEVID_MIPS:
565 case SIBA_DEVID_ETHERNET:
566 return ("Fast Ethernet");
567 case SIBA_DEVID_MODEM:
569 case SIBA_DEVID_USB11_HOSTDEV:
570 return ("USB 1.1 Hostdev");
571 case SIBA_DEVID_ADSL:
573 case SIBA_DEVID_ILINE100:
574 return ("ILine 100");
575 case SIBA_DEVID_IPSEC:
577 case SIBA_DEVID_PCMCIA:
579 case SIBA_DEVID_INTERNAL_MEM:
580 return ("Internal Memory");
581 case SIBA_DEVID_SDRAMDDR:
582 return ("MEMC SDRAM");
583 case SIBA_DEVID_EXTIF:
585 case SIBA_DEVID_80211:
586 return ("IEEE 802.11");
587 case SIBA_DEVID_MIPS_3302:
588 return ("MIPS 3302");
589 case SIBA_DEVID_USB11_HOST:
590 return ("USB 1.1 Host");
591 case SIBA_DEVID_USB11_DEV:
592 return ("USB 1.1 Device");
593 case SIBA_DEVID_USB20_HOST:
594 return ("USB 2.0 Host");
595 case SIBA_DEVID_USB20_DEV:
596 return ("USB 2.0 Device");
597 case SIBA_DEVID_SDIO_HOST:
598 return ("SDIO Host");
599 case SIBA_DEVID_ROBOSWITCH:
600 return ("Roboswitch");
601 case SIBA_DEVID_PARA_ATA:
603 case SIBA_DEVID_SATA_XORDMA:
604 return ("SATA XOR-DMA");
605 case SIBA_DEVID_ETHERNET_GBIT:
606 return ("GBit Ethernet");
607 case SIBA_DEVID_PCIE:
608 return ("PCI-Express");
609 case SIBA_DEVID_MIMO_PHY:
611 case SIBA_DEVID_SRAM_CTRLR:
612 return ("SRAM Controller");
613 case SIBA_DEVID_MINI_MACPHY:
614 return ("Mini MACPHY");
615 case SIBA_DEVID_ARM_1176:
617 case SIBA_DEVID_ARM_7TDMI:
618 return ("ARM 7TDMI");
624 siba_pci_read_2(struct siba_dev_softc *sd, uint16_t offset)
626 struct siba_softc *siba = sd->sd_bus;
628 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
631 return (SIBA_READ_2(siba, offset));
635 siba_pci_read_4(struct siba_dev_softc *sd, uint16_t offset)
637 struct siba_softc *siba = sd->sd_bus;
639 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
642 return (SIBA_READ_4(siba, offset));
646 siba_pci_write_2(struct siba_dev_softc *sd, uint16_t offset, uint16_t value)
648 struct siba_softc *siba = sd->sd_bus;
650 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
653 SIBA_WRITE_2(siba, offset, value);
657 siba_pci_write_4(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
659 struct siba_softc *siba = sd->sd_bus;
661 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
664 SIBA_WRITE_4(siba, offset, value);
668 siba_pci_read_multi_1(struct siba_dev_softc *sd, void *buffer, size_t count,
671 struct siba_softc *siba = sd->sd_bus;
673 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
674 memset(buffer, 0xff, count);
678 SIBA_READ_MULTI_1(siba, offset, buffer, count);
682 siba_pci_read_multi_2(struct siba_dev_softc *sd, void *buffer, size_t count,
685 struct siba_softc *siba = sd->sd_bus;
687 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
688 memset(buffer, 0xff, count);
692 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__));
693 SIBA_READ_MULTI_2(siba, offset, buffer, count >> 1);
697 siba_pci_read_multi_4(struct siba_dev_softc *sd, void *buffer, size_t count,
700 struct siba_softc *siba = sd->sd_bus;
702 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
703 memset(buffer, 0xff, count);
707 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__));
708 SIBA_READ_MULTI_4(siba, offset, buffer, count >> 2);
712 siba_pci_write_multi_1(struct siba_dev_softc *sd, const void *buffer,
713 size_t count, uint16_t offset)
715 struct siba_softc *siba = sd->sd_bus;
717 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
720 SIBA_WRITE_MULTI_1(siba, offset, buffer, count);
724 siba_pci_write_multi_2(struct siba_dev_softc *sd, const void *buffer,
725 size_t count, uint16_t offset)
727 struct siba_softc *siba = sd->sd_bus;
729 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
732 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__));
733 SIBA_WRITE_MULTI_2(siba, offset, buffer, count >> 1);
737 siba_pci_write_multi_4(struct siba_dev_softc *sd, const void *buffer,
738 size_t count, uint16_t offset)
740 struct siba_softc *siba = sd->sd_bus;
742 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
745 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__));
746 SIBA_WRITE_MULTI_4(siba, offset, buffer, count >> 2);
750 siba_powerup(device_t dev, int dynamic)
752 struct siba_dev_softc *sd = device_get_ivars(dev);
753 struct siba_softc *siba = sd->sd_bus;
755 siba_powerup_sub(siba, dynamic);
759 siba_powerup_sub(struct siba_softc *siba, int dynamic)
762 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1);
763 siba_cc_clock(&siba->siba_cc,
764 (dynamic != 0) ? SIBA_CLOCK_DYNAMIC : SIBA_CLOCK_FAST);
768 siba_cc_clock(struct siba_cc *scc, enum siba_clock clock)
770 struct siba_dev_softc *sd = scc->scc_dev;
771 struct siba_softc *siba;
778 * chipcommon < r6 (no dynamic clock control)
779 * chipcommon >= r10 (unknown)
781 if (sd->sd_id.sd_rev < 6 || sd->sd_id.sd_rev >= 10 ||
782 (scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
786 case SIBA_CLOCK_DYNAMIC:
787 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) &
788 ~(SIBA_CC_CLKSLOW_ENXTAL | SIBA_CC_CLKSLOW_FSLOW |
789 SIBA_CC_CLKSLOW_IPLL);
790 if ((tmp & SIBA_CC_CLKSLOW_SRC) != SIBA_CC_CLKSLOW_SRC_CRYSTAL)
791 tmp |= SIBA_CC_CLKSLOW_ENXTAL;
792 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp);
793 if (tmp & SIBA_CC_CLKSLOW_ENXTAL)
794 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 0);
796 case SIBA_CLOCK_SLOW:
797 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
798 SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
799 SIBA_CC_CLKSLOW_FSLOW);
801 case SIBA_CLOCK_FAST:
803 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 1);
804 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
805 (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
806 SIBA_CC_CLKSLOW_IPLL) & ~SIBA_CC_CLKSLOW_FSLOW);
810 ("%s: unsupported clock %#x", __func__, clock));
815 siba_read_2(device_t dev, uint16_t offset)
817 struct siba_dev_softc *sd = device_get_ivars(dev);
819 return (sd->sd_ops->read_2(sd, offset));
823 siba_read_4(device_t dev, uint16_t offset)
825 struct siba_dev_softc *sd = device_get_ivars(dev);
827 return (siba_read_4_sub(sd, offset));
831 siba_read_4_sub(struct siba_dev_softc *sd, uint16_t offset)
834 return (sd->sd_ops->read_4(sd, offset));
838 siba_write_2(device_t dev, uint16_t offset, uint16_t value)
840 struct siba_dev_softc *sd = device_get_ivars(dev);
842 sd->sd_ops->write_2(sd, offset, value);
846 siba_write_4(device_t dev, uint16_t offset, uint32_t value)
848 struct siba_dev_softc *sd = device_get_ivars(dev);
850 return (siba_write_4_sub(sd, offset, value));
854 siba_write_4_sub(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
857 sd->sd_ops->write_4(sd, offset, value);
861 siba_read_multi_1(device_t dev, void *buffer, size_t count,
864 struct siba_dev_softc *sd = device_get_ivars(dev);
866 sd->sd_ops->read_multi_1(sd, buffer, count, offset);
870 siba_read_multi_2(device_t dev, void *buffer, size_t count,
873 struct siba_dev_softc *sd = device_get_ivars(dev);
875 sd->sd_ops->read_multi_2(sd, buffer, count, offset);
879 siba_read_multi_4(device_t dev, void *buffer, size_t count,
882 struct siba_dev_softc *sd = device_get_ivars(dev);
884 sd->sd_ops->read_multi_4(sd, buffer, count, offset);
888 siba_write_multi_1(device_t dev, const void *buffer, size_t count,
891 struct siba_dev_softc *sd = device_get_ivars(dev);
893 sd->sd_ops->write_multi_1(sd, buffer, count, offset);
897 siba_write_multi_2(device_t dev, const void *buffer, size_t count,
900 struct siba_dev_softc *sd = device_get_ivars(dev);
902 sd->sd_ops->write_multi_2(sd, buffer, count, offset);
906 siba_write_multi_4(device_t dev, const void *buffer, size_t count,
909 struct siba_dev_softc *sd = device_get_ivars(dev);
911 sd->sd_ops->write_multi_4(sd, buffer, count, offset);
915 siba_cc_pmu_init(struct siba_cc *scc)
917 const struct siba_cc_pmu_res_updown *updown = NULL;
918 const struct siba_cc_pmu_res_depend *depend = NULL;
919 struct siba_dev_softc *sd = scc->scc_dev;
920 struct siba_softc *siba = sd->sd_bus;
921 uint32_t min = 0, max = 0, pmucap;
922 unsigned int i, updown_size, depend_size;
924 if ((scc->scc_caps & SIBA_CC_CAPS_PMU) == 0)
927 pmucap = SIBA_CC_READ32(scc, SIBA_CC_PMUCAPS);
928 scc->scc_pmu.rev = (pmucap & SIBA_CC_PMUCAPS_REV);
930 DPRINTF(siba, SIBA_DEBUG_PMU, "PMU(r%u) found (caps %#x)\n",
931 scc->scc_pmu.rev, pmucap);
933 if (scc->scc_pmu.rev >= 1) {
934 if (siba->siba_chiprev < 2 && siba->siba_chipid == 0x4325)
935 SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL,
936 ~SIBA_CC_PMUCTL_NOILP);
938 SIBA_CC_SET32(scc, SIBA_CC_PMUCTL,
939 SIBA_CC_PMUCTL_NOILP);
942 /* initialize PLL & PMU resources */
943 switch (siba->siba_chipid) {
945 siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
946 /* use the default: min = 0xcbb max = 0x7ffff */
949 siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
951 updown = siba_cc_pmu_4325_updown;
952 updown_size = N(siba_cc_pmu_4325_updown);
953 depend = siba_cc_pmu_4325_depend;
954 depend_size = N(siba_cc_pmu_4325_depend);
956 min = (1 << SIBA_CC_PMU_4325_BURST) |
957 (1 << SIBA_CC_PMU_4325_LN);
958 if (SIBA_CC_READ32(scc, SIBA_CC_CHIPSTAT) &
959 SIBA_CC_CHST_4325_PMUTOP_2B)
960 min |= (1 << SIBA_CC_PMU_4325_CLBURST);
964 siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
966 updown = siba_cc_pmu_4328_updown;
967 updown_size = N(siba_cc_pmu_4328_updown);
968 depend = siba_cc_pmu_4328_depend;
969 depend_size = N(siba_cc_pmu_4328_depend);
971 min = (1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) |
972 (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM) |
973 (1 << SIBA_CC_PMU_4328_CRYSTAL_EN);
978 siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
983 device_printf(siba->siba_dev,
984 "unknown chipid %#x for PLL & PMU init\n",
989 for (i = 0; i < updown_size; i++) {
990 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
992 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_UPDNTM,
997 for (i = 0; i < depend_size; i++) {
998 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
1000 switch (depend[i].task) {
1001 case SIBA_CC_PMU_DEP_SET:
1002 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_DEPMSK,
1005 case SIBA_CC_PMU_DEP_ADD:
1006 SIBA_CC_SET32(scc, SIBA_CC_PMU_DEPMSK,
1009 case SIBA_CC_PMU_DEP_REMOVE:
1010 SIBA_CC_MASK32(scc, SIBA_CC_PMU_DEPMSK,
1011 ~(depend[i].depend));
1015 ("%s:%d: assertion failed",
1016 __func__, __LINE__));
1022 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MINRES, min);
1024 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MAXRES, max);
1028 siba_cc_power_init(struct siba_cc *scc)
1030 struct siba_softc *siba = scc->scc_dev->sd_bus;
1033 if (siba->siba_chipid == 0x4321) {
1034 if (siba->siba_chiprev == 0)
1035 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0x3a4);
1036 else if (siba->siba_chiprev == 1)
1037 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0xa4);
1040 if ((scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
1043 if (scc->scc_dev->sd_id.sd_rev >= 10)
1044 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSYSCTL,
1045 (SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) &
1048 maxfreq = siba_cc_clockfreq(scc, 1);
1049 SIBA_CC_WRITE32(scc, SIBA_CC_PLLONDELAY,
1050 (maxfreq * 150 + 999999) / 1000000);
1051 SIBA_CC_WRITE32(scc, SIBA_CC_FREFSELDELAY,
1052 (maxfreq * 15 + 999999) / 1000000);
1057 siba_cc_powerup_delay(struct siba_cc *scc)
1059 struct siba_softc *siba = scc->scc_dev->sd_bus;
1062 if (siba->siba_type != SIBA_TYPE_PCI ||
1063 !(scc->scc_caps & SIBA_CC_CAPS_PWCTL))
1066 min = siba_cc_clockfreq(scc, 0);
1067 scc->scc_powerup_delay =
1068 (((SIBA_CC_READ32(scc, SIBA_CC_PLLONDELAY) + 2) * 1000000) +
1073 siba_cc_clockfreq(struct siba_cc *scc, int max)
1075 enum siba_clksrc src;
1076 int div = 1, limit = 0;
1078 src = siba_cc_clksrc(scc);
1079 if (scc->scc_dev->sd_id.sd_rev < 6) {
1080 div = (src == SIBA_CC_CLKSRC_PCI) ? 64 :
1081 (src == SIBA_CC_CLKSRC_CRYSTAL) ? 32 : 1;
1083 ("%s: unknown clock %d", __func__, src));
1084 } else if (scc->scc_dev->sd_id.sd_rev < 10) {
1086 case SIBA_CC_CLKSRC_CRYSTAL:
1087 case SIBA_CC_CLKSRC_PCI:
1088 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) >> 16) +
1091 case SIBA_CC_CLKSRC_LOWPW:
1095 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) >> 16) + 1) * 4;
1098 case SIBA_CC_CLKSRC_CRYSTAL:
1099 limit = (max) ? 20200000 : 19800000;
1101 case SIBA_CC_CLKSRC_LOWPW:
1102 limit = (max) ? 43000 : 25000;
1104 case SIBA_CC_CLKSRC_PCI:
1105 limit = (max) ? 34000000 : 25000000;
1109 return (limit / div);
1113 siba_cc_pmu1_pll0_init(struct siba_cc *scc, uint32_t freq)
1115 struct siba_dev_softc *sd = scc->scc_dev;
1116 struct siba_softc *siba = sd->sd_bus;
1117 const struct siba_cc_pmu1_plltab *e = NULL;
1118 uint32_t bufsth = 0, pll, pmu;
1121 KASSERT(freq == 0, ("%s:%d: assertion vail", __func__, __LINE__));
1122 if (siba->siba_chipid == 0x4312) {
1123 scc->scc_pmu.freq = 20000;
1127 e = siba_cc_pmu1_plltab_find(SIBA_CC_PMU1_DEFAULT_FREQ);
1128 KASSERT(e != NULL, ("%s:%d: assertion vail", __func__, __LINE__));
1129 scc->scc_pmu.freq = e->freq;
1131 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1132 if (SIBA_CC_PMUCTL_XF_VAL(pmu) == e->xf)
1135 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n",
1136 (e->freq / 1000), (e->freq % 1000));
1139 switch (siba->siba_chipid) {
1142 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1143 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) |
1144 (1 << SIBA_CC_PMU_4325_HT)));
1145 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1146 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) |
1147 (1 << SIBA_CC_PMU_4325_HT)));
1151 ("%s:%d: assertion failed", __func__, __LINE__));
1153 for (i = 0; i < 1500; i++) {
1154 if (!(SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) &
1155 SIBA_CC_CLKCTLSTATUS_HT))
1159 if (SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & SIBA_CC_CLKCTLSTATUS_HT)
1160 device_printf(siba->siba_dev, "failed to turn PLL off!\n");
1162 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0);
1163 pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV);
1164 pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV;
1165 pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV;
1166 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll);
1168 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2);
1169 pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE);
1170 pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT;
1171 pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE;
1172 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, pll);
1174 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL3);
1175 pll &= ~SIBA_CC_PMU1_PLL3_NDIVFRAC;
1176 pll |= ((uint32_t)e->ndiv_frac << 0) & SIBA_CC_PMU1_PLL3_NDIVFRAC;
1177 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, pll);
1180 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL5);
1181 pll &= ~SIBA_CC_PMU1_PLL5_CLKDRV;
1182 pll |= (bufsth << 8) & SIBA_CC_PMU1_PLL5_CLKDRV;
1183 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, pll);
1186 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1187 pmu &= ~(SIBA_CC_PMUCTL_ILP | SIBA_CC_PMUCTL_XF);
1188 pmu |= ((((uint32_t)e->freq + 127) / 128 - 1) << 16) &
1190 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
1191 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
1195 siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq)
1197 struct siba_dev_softc *sd = scc->scc_dev;
1198 struct siba_softc *siba = sd->sd_bus;
1199 const struct siba_cc_pmu0_plltab *e = NULL;
1200 uint32_t pmu, tmp, pll;
1203 if ((siba->siba_chipid == 0x5354) && !xtalfreq)
1206 e = siba_cc_pmu0_plltab_findentry(xtalfreq);
1208 e = siba_cc_pmu0_plltab_findentry(
1209 SIBA_CC_PMU0_DEFAULT_XTALFREQ);
1210 KASSERT(e != NULL, ("%s:%d: fail", __func__, __LINE__));
1212 scc->scc_pmu.freq = e->freq;
1214 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1215 if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf)
1218 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u mhz\n",
1219 (xtalfreq / 1000), (xtalfreq % 1000));
1221 KASSERT(siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354,
1222 ("%s:%d: fail", __func__, __LINE__));
1224 switch (siba->siba_chipid) {
1226 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1227 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU));
1228 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1229 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU));
1232 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1233 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU));
1234 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1235 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU));
1238 for (i = 1500; i; i--) {
1239 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
1240 if (!(tmp & SIBA_CC_CLKCTLSTATUS_HT))
1244 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
1245 if (tmp & SIBA_CC_CLKCTLSTATUS_HT)
1246 device_printf(siba->siba_dev, "failed to turn PLL off!\n");
1249 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL0);
1250 if (xtalfreq >= SIBA_CC_PMU0_PLL0_PDIV_FREQ)
1251 pll |= SIBA_CC_PMU0_PLL0_PDIV_MSK;
1253 pll &= ~SIBA_CC_PMU0_PLL0_PDIV_MSK;
1254 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL0, pll);
1257 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL1);
1258 pll &= ~(SIBA_CC_PMU0_PLL1_STOPMOD | SIBA_CC_PMU0_PLL1_IMSK |
1259 SIBA_CC_PMU0_PLL1_FMSK);
1260 pll |= ((uint32_t)e->wb_int << 28) & SIBA_CC_PMU0_PLL1_IMSK;
1261 pll |= ((uint32_t)e->wb_frac << 8) & SIBA_CC_PMU0_PLL1_FMSK;
1262 if (e->wb_frac == 0)
1263 pll |= SIBA_CC_PMU0_PLL1_STOPMOD;
1264 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL1, pll);
1267 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL2);
1268 pll &= ~SIBA_CC_PMU0_PLL2_IMSKHI;
1269 pll |= (((uint32_t)e->wb_int >> 4) << 0) & SIBA_CC_PMU0_PLL2_IMSKHI;
1270 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL2, pll);
1272 /* set freq and divisor. */
1273 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1274 pmu &= ~SIBA_CC_PMUCTL_ILP;
1275 pmu |= (((xtalfreq + 127) / 128 - 1) << 16) & SIBA_CC_PMUCTL_ILP;
1276 pmu &= ~SIBA_CC_PMUCTL_XF;
1277 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
1278 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
1281 static enum siba_clksrc
1282 siba_cc_clksrc(struct siba_cc *scc)
1284 struct siba_dev_softc *sd = scc->scc_dev;
1285 struct siba_softc *siba = sd->sd_bus;
1287 if (sd->sd_id.sd_rev < 6) {
1288 if (siba->siba_type == SIBA_TYPE_PCI) {
1289 if (pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4) &
1291 return (SIBA_CC_CLKSRC_PCI);
1292 return (SIBA_CC_CLKSRC_CRYSTAL);
1294 if (siba->siba_type == SIBA_TYPE_SSB ||
1295 siba->siba_type == SIBA_TYPE_PCMCIA)
1296 return (SIBA_CC_CLKSRC_CRYSTAL);
1298 if (sd->sd_id.sd_rev < 10) {
1299 switch (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 0x7) {
1301 return (SIBA_CC_CLKSRC_LOWPW);
1303 return (SIBA_CC_CLKSRC_CRYSTAL);
1305 return (SIBA_CC_CLKSRC_PCI);
1311 return (SIBA_CC_CLKSRC_CRYSTAL);
1314 static const struct siba_cc_pmu1_plltab *
1315 siba_cc_pmu1_plltab_find(uint32_t crystalfreq)
1317 const struct siba_cc_pmu1_plltab *e;
1320 for (i = 0; i < N(siba_cc_pmu1_plltab); i++) {
1321 e = &siba_cc_pmu1_plltab[i];
1322 if (crystalfreq == e->freq)
1330 siba_cc_pll_read(struct siba_cc *scc, uint32_t offset)
1333 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
1334 return (SIBA_CC_READ32(scc, SIBA_CC_PLLCTL_DATA));
1338 siba_cc_pll_write(struct siba_cc *scc, uint32_t offset, uint32_t value)
1341 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
1342 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, value);
1345 static const struct siba_cc_pmu0_plltab *
1346 siba_cc_pmu0_plltab_findentry(uint32_t crystalfreq)
1348 const struct siba_cc_pmu0_plltab *e;
1351 for (i = 0; i < N(siba_cc_pmu0_plltab); i++) {
1352 e = &siba_cc_pmu0_plltab[i];
1353 if (e->freq == crystalfreq)
1361 siba_pci_sprom(struct siba_softc *siba, struct siba_sprom *sprom)
1366 buf = malloc(SIBA_SPROMSIZE_R123 * sizeof(uint16_t),
1367 M_DEVBUF, M_NOWAIT | M_ZERO);
1370 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R123);
1371 error = sprom_check_crc(buf, siba->siba_spromsize);
1373 free(buf, M_DEVBUF);
1374 buf = malloc(SIBA_SPROMSIZE_R4 * sizeof(uint16_t),
1375 M_DEVBUF, M_NOWAIT | M_ZERO);
1378 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R4);
1379 error = sprom_check_crc(buf, siba->siba_spromsize);
1381 device_printf(siba->siba_dev, "warn: bad SPROM CRC\n");
1384 bzero(sprom, sizeof(*sprom));
1386 sprom->rev = buf[siba->siba_spromsize - 1] & 0x00FF;
1387 DPRINTF(siba, SIBA_DEBUG_SPROM, "SPROM rev %d\n",
1389 memset(sprom->mac_eth, 0xff, 6);
1390 memset(sprom->mac_80211a, 0xff, 6);
1391 if ((siba->siba_chipid & 0xff00) == 0x4400) {
1393 siba_sprom_r123(sprom, buf);
1394 } else if (siba->siba_chipid == 0x4321) {
1396 siba_sprom_r45(sprom, buf);
1398 switch (sprom->rev) {
1402 siba_sprom_r123(sprom, buf);
1406 siba_sprom_r45(sprom, buf);
1409 siba_sprom_r8(sprom, buf);
1412 device_printf(siba->siba_dev,
1413 "unknown SPROM revision %d.\n", sprom->rev);
1414 siba_sprom_r123(sprom, buf);
1418 if (sprom->bf_lo == 0xffff)
1420 if (sprom->bf_hi == 0xffff)
1423 free(buf, M_DEVBUF);
1428 siba_sprom_read(struct siba_softc *siba, uint16_t *sprom, uint16_t len)
1432 for (i = 0; i < len; i++)
1433 sprom[i] = SIBA_READ_2(siba, SIBA_SPROM_BASE + (i * 2));
1435 siba->siba_spromsize = len;
1440 sprom_check_crc(const uint16_t *sprom, size_t size)
1443 uint8_t crc0, crc1 = 0xff;
1445 crc0 = (sprom[size - 1] & SIBA_SPROM_REV_CRC) >> 8;
1446 for (word = 0; word < size - 1; word++) {
1447 crc1 = siba_crc8(crc1, sprom[word] & 0x00ff);
1448 crc1 = siba_crc8(crc1, (sprom[word] & 0xff00) >> 8);
1450 crc1 = siba_crc8(crc1, sprom[size - 1] & 0x00ff);
1453 return ((crc0 != crc1) ? EPROTO : 0);
1457 siba_crc8(uint8_t crc, uint8_t data)
1459 static const uint8_t ct[] = {
1460 0x00, 0xf7, 0xb9, 0x4e, 0x25, 0xd2, 0x9c, 0x6b,
1461 0x4a, 0xbd, 0xf3, 0x04, 0x6f, 0x98, 0xd6, 0x21,
1462 0x94, 0x63, 0x2d, 0xda, 0xb1, 0x46, 0x08, 0xff,
1463 0xde, 0x29, 0x67, 0x90, 0xfb, 0x0c, 0x42, 0xb5,
1464 0x7f, 0x88, 0xc6, 0x31, 0x5a, 0xad, 0xe3, 0x14,
1465 0x35, 0xc2, 0x8c, 0x7b, 0x10, 0xe7, 0xa9, 0x5e,
1466 0xeb, 0x1c, 0x52, 0xa5, 0xce, 0x39, 0x77, 0x80,
1467 0xa1, 0x56, 0x18, 0xef, 0x84, 0x73, 0x3d, 0xca,
1468 0xfe, 0x09, 0x47, 0xb0, 0xdb, 0x2c, 0x62, 0x95,
1469 0xb4, 0x43, 0x0d, 0xfa, 0x91, 0x66, 0x28, 0xdf,
1470 0x6a, 0x9d, 0xd3, 0x24, 0x4f, 0xb8, 0xf6, 0x01,
1471 0x20, 0xd7, 0x99, 0x6e, 0x05, 0xf2, 0xbc, 0x4b,
1472 0x81, 0x76, 0x38, 0xcf, 0xa4, 0x53, 0x1d, 0xea,
1473 0xcb, 0x3c, 0x72, 0x85, 0xee, 0x19, 0x57, 0xa0,
1474 0x15, 0xe2, 0xac, 0x5b, 0x30, 0xc7, 0x89, 0x7e,
1475 0x5f, 0xa8, 0xe6, 0x11, 0x7a, 0x8d, 0xc3, 0x34,
1476 0xab, 0x5c, 0x12, 0xe5, 0x8e, 0x79, 0x37, 0xc0,
1477 0xe1, 0x16, 0x58, 0xaf, 0xc4, 0x33, 0x7d, 0x8a,
1478 0x3f, 0xc8, 0x86, 0x71, 0x1a, 0xed, 0xa3, 0x54,
1479 0x75, 0x82, 0xcc, 0x3b, 0x50, 0xa7, 0xe9, 0x1e,
1480 0xd4, 0x23, 0x6d, 0x9a, 0xf1, 0x06, 0x48, 0xbf,
1481 0x9e, 0x69, 0x27, 0xd0, 0xbb, 0x4c, 0x02, 0xf5,
1482 0x40, 0xb7, 0xf9, 0x0e, 0x65, 0x92, 0xdc, 0x2b,
1483 0x0a, 0xfd, 0xb3, 0x44, 0x2f, 0xd8, 0x96, 0x61,
1484 0x55, 0xa2, 0xec, 0x1b, 0x70, 0x87, 0xc9, 0x3e,
1485 0x1f, 0xe8, 0xa6, 0x51, 0x3a, 0xcd, 0x83, 0x74,
1486 0xc1, 0x36, 0x78, 0x8f, 0xe4, 0x13, 0x5d, 0xaa,
1487 0x8b, 0x7c, 0x32, 0xc5, 0xae, 0x59, 0x17, 0xe0,
1488 0x2a, 0xdd, 0x93, 0x64, 0x0f, 0xf8, 0xb6, 0x41,
1489 0x60, 0x97, 0xd9, 0x2e, 0x45, 0xb2, 0xfc, 0x0b,
1490 0xbe, 0x49, 0x07, 0xf0, 0x9b, 0x6c, 0x22, 0xd5,
1491 0xf4, 0x03, 0x4d, 0xba, 0xd1, 0x26, 0x68, 0x9f,
1493 return (ct[crc ^ data]);
1496 #define SIBA_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
1497 #define SIBA_OFFSET(offset) \
1498 (((offset) - SIBA_SPROM_BASE) / sizeof(uint16_t))
1499 #define SIBA_SHIFTOUT_SUB(__x, __mask) \
1500 (((__x) & (__mask)) / SIBA_LOWEST_SET_BIT(__mask))
1501 #define SIBA_SHIFTOUT(_var, _offset, _mask) \
1502 out->_var = SIBA_SHIFTOUT_SUB(in[SIBA_OFFSET(_offset)], (_mask))
1503 #define SIBA_SHIFTOUT_4(_var, _offset, _mask, _shift) \
1504 out->_var = ((((uint32_t)in[SIBA_OFFSET((_offset)+2)] << 16 | \
1505 in[SIBA_OFFSET(_offset)]) & (_mask)) >> (_shift))
1508 siba_sprom_r123(struct siba_sprom *out, const uint16_t *in)
1516 loc[0] = SIBA_SPROM3_MAC_80211BG;
1518 loc[0] = SIBA_SPROM1_MAC_80211BG;
1519 loc[1] = SIBA_SPROM1_MAC_ETH;
1520 loc[2] = SIBA_SPROM1_MAC_80211A;
1522 for (i = 0; i < 3; i++) {
1523 v = in[SIBA_OFFSET(loc[0]) + i];
1524 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1527 for (i = 0; i < 3; i++) {
1528 v = in[SIBA_OFFSET(loc[1]) + i];
1529 *(((uint16_t *)out->mac_eth) + i) = htobe16(v);
1531 for (i = 0; i < 3; i++) {
1532 v = in[SIBA_OFFSET(loc[2]) + i];
1533 *(((uint16_t *)out->mac_80211a) + i) = htobe16(v);
1536 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM1_ETHPHY,
1537 SIBA_SPROM1_ETHPHY_MII_ETH0);
1538 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM1_ETHPHY,
1539 SIBA_SPROM1_ETHPHY_MII_ETH1);
1540 SIBA_SHIFTOUT(mdio_eth0, SIBA_SPROM1_ETHPHY,
1541 SIBA_SPROM1_ETHPHY_MDIO_ETH0);
1542 SIBA_SHIFTOUT(mdio_eth1, SIBA_SPROM1_ETHPHY,
1543 SIBA_SPROM1_ETHPHY_MDIO_ETH1);
1544 SIBA_SHIFTOUT(brev, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_BREV);
1545 SIBA_SHIFTOUT(ccode, SIBA_SPROM1_BOARDINFO,
1546 SIBA_SPROM1_BOARDINFO_CCODE);
1547 SIBA_SHIFTOUT(ant_a, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_ANTA);
1548 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM1_BOARDINFO,
1549 SIBA_SPROM1_BOARDINFO_ANTBG);
1550 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM1_PA0B0, 0xffff);
1551 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM1_PA0B1, 0xffff);
1552 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM1_PA0B2, 0xffff);
1553 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM1_PA1B0, 0xffff);
1554 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM1_PA1B1, 0xffff);
1555 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM1_PA1B2, 0xffff);
1556 SIBA_SHIFTOUT(gpio0, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P0);
1557 SIBA_SHIFTOUT(gpio1, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P1);
1558 SIBA_SHIFTOUT(gpio2, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P2);
1559 SIBA_SHIFTOUT(gpio3, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P3);
1561 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_A);
1562 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_BG);
1563 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_A);
1564 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_BG);
1565 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM1_BFLOW, 0xffff);
1567 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM2_BFHIGH, 0xffff);
1570 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_BG, 0);
1571 out->again.ghz24.a0 = out->again.ghz24.a1 = gain;
1572 out->again.ghz24.a2 = out->again.ghz24.a3 = gain;
1573 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_A, 8);
1574 out->again.ghz5.a0 = out->again.ghz5.a1 = gain;
1575 out->again.ghz5.a2 = out->again.ghz5.a3 = gain;
1579 siba_sprom_r45(struct siba_sprom *out, const uint16_t *in)
1583 uint16_t mac_80211bg_offset;
1586 mac_80211bg_offset = SIBA_SPROM4_MAC_80211BG;
1588 mac_80211bg_offset = SIBA_SPROM5_MAC_80211BG;
1589 for (i = 0; i < 3; i++) {
1590 v = in[SIBA_OFFSET(mac_80211bg_offset) + i];
1591 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1593 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET0A);
1594 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET1A);
1595 if (out->rev == 4) {
1596 SIBA_SHIFTOUT(ccode, SIBA_SPROM4_CCODE, 0xffff);
1597 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM4_BFLOW, 0xffff);
1598 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM4_BFHIGH, 0xffff);
1600 SIBA_SHIFTOUT(ccode, SIBA_SPROM5_CCODE, 0xffff);
1601 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM5_BFLOW, 0xffff);
1602 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM5_BFHIGH, 0xffff);
1604 SIBA_SHIFTOUT(ant_a, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_A);
1605 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_BG);
1606 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_MAXP_BG_MASK);
1607 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_TSSI_BG);
1608 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_MAXP_A_MASK);
1609 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_TSSI_A);
1610 if (out->rev == 4) {
1611 SIBA_SHIFTOUT(gpio0, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P0);
1612 SIBA_SHIFTOUT(gpio1, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P1);
1613 SIBA_SHIFTOUT(gpio2, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P2);
1614 SIBA_SHIFTOUT(gpio3, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P3);
1616 SIBA_SHIFTOUT(gpio0, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P0);
1617 SIBA_SHIFTOUT(gpio1, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P1);
1618 SIBA_SHIFTOUT(gpio2, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P2);
1619 SIBA_SHIFTOUT(gpio3, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P3);
1623 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN0);
1624 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN1);
1625 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN2);
1626 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN3);
1627 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5));
1631 siba_sprom_r8(struct siba_sprom *out, const uint16_t *in)
1636 for (i = 0; i < 3; i++) {
1637 v = in[SIBA_OFFSET(SIBA_SPROM8_MAC_80211BG) + i];
1638 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1640 SIBA_SHIFTOUT(ccode, SIBA_SPROM8_CCODE, 0xffff);
1641 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM8_BFLOW, 0xffff);
1642 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM8_BFHIGH, 0xffff);
1643 SIBA_SHIFTOUT(bf2_lo, SIBA_SPROM8_BFL2LO, 0xffff);
1644 SIBA_SHIFTOUT(bf2_hi, SIBA_SPROM8_BFL2HI, 0xffff);
1645 SIBA_SHIFTOUT(ant_a, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_A);
1646 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_BG);
1647 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_MAXP_BG_MASK);
1648 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_TSSI_BG);
1649 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_MAXP_A_MASK);
1650 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_TSSI_A);
1651 SIBA_SHIFTOUT(maxpwr_ah, SIBA_SPROM8_MAXP_AHL,
1652 SIBA_SPROM8_MAXP_AH_MASK);
1653 SIBA_SHIFTOUT(maxpwr_al, SIBA_SPROM8_MAXP_AHL,
1654 SIBA_SPROM8_MAXP_AL_MASK);
1655 SIBA_SHIFTOUT(gpio0, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P0);
1656 SIBA_SHIFTOUT(gpio1, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P1);
1657 SIBA_SHIFTOUT(gpio2, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P2);
1658 SIBA_SHIFTOUT(gpio3, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P3);
1659 SIBA_SHIFTOUT(tri2g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI2G);
1660 SIBA_SHIFTOUT(tri5g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI5G);
1661 SIBA_SHIFTOUT(tri5gl, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GL);
1662 SIBA_SHIFTOUT(tri5gh, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GH);
1663 SIBA_SHIFTOUT(rxpo2g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO2G);
1664 SIBA_SHIFTOUT(rxpo5g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO5G);
1665 SIBA_SHIFTOUT(rssismf2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMF2G);
1666 SIBA_SHIFTOUT(rssismc2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMC2G);
1667 SIBA_SHIFTOUT(rssisav2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISAV2G);
1668 SIBA_SHIFTOUT(bxa2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_BXA2G);
1669 SIBA_SHIFTOUT(rssismf5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMF5G);
1670 SIBA_SHIFTOUT(rssismc5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMC5G);
1671 SIBA_SHIFTOUT(rssisav5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISAV5G);
1672 SIBA_SHIFTOUT(bxa5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_BXA5G);
1674 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM8_PA0B0, 0xffff);
1675 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM8_PA0B1, 0xffff);
1676 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM8_PA0B2, 0xffff);
1677 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM8_PA1B0, 0xffff);
1678 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM8_PA1B1, 0xffff);
1679 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM8_PA1B2, 0xffff);
1680 SIBA_SHIFTOUT(pa1lob0, SIBA_SPROM8_PA1LOB0, 0xffff);
1681 SIBA_SHIFTOUT(pa1lob1, SIBA_SPROM8_PA1LOB1, 0xffff);
1682 SIBA_SHIFTOUT(pa1lob2, SIBA_SPROM8_PA1LOB2, 0xffff);
1683 SIBA_SHIFTOUT(pa1hib0, SIBA_SPROM8_PA1HIB0, 0xffff);
1684 SIBA_SHIFTOUT(pa1hib1, SIBA_SPROM8_PA1HIB1, 0xffff);
1685 SIBA_SHIFTOUT(pa1hib2, SIBA_SPROM8_PA1HIB2, 0xffff);
1686 SIBA_SHIFTOUT(cck2gpo, SIBA_SPROM8_CCK2GPO, 0xffff);
1688 SIBA_SHIFTOUT_4(ofdm2gpo, SIBA_SPROM8_OFDM2GPO, 0xffffffff, 0);
1689 SIBA_SHIFTOUT_4(ofdm5glpo, SIBA_SPROM8_OFDM5GLPO, 0xffffffff, 0);
1690 SIBA_SHIFTOUT_4(ofdm5gpo, SIBA_SPROM8_OFDM5GPO, 0xffffffff, 0);
1691 SIBA_SHIFTOUT_4(ofdm5ghpo, SIBA_SPROM8_OFDM5GHPO, 0xffffffff, 0);
1694 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN0);
1695 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN1);
1696 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN2);
1697 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN3);
1698 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5));
1702 siba_sprom_r123_antgain(uint8_t sprom_revision, const uint16_t *in,
1703 uint16_t mask, uint16_t shift)
1708 v = in[SIBA_OFFSET(SIBA_SPROM1_AGAIN)];
1709 gain = (v & mask) >> shift;
1710 gain = (gain == 0xff) ? 2 : (sprom_revision == 1) ? gain << 2 :
1711 ((gain & 0xc0) >> 6) | ((gain & 0x3f) << 2);
1713 return ((int8_t)gain);
1716 #undef SIBA_LOWEST_SET_BIT
1718 #undef SIBA_SHIFTOUT_SUB
1719 #undef SIBA_SHIFTOUT
1722 siba_powerdown(device_t dev)
1724 struct siba_dev_softc *sd = device_get_ivars(dev);
1725 struct siba_softc *siba = sd->sd_bus;
1727 return (siba_powerdown_sub(siba));
1731 siba_powerdown_sub(struct siba_softc *siba)
1733 struct siba_cc *scc;
1735 if (siba->siba_type == SIBA_TYPE_SSB)
1738 scc = &siba->siba_cc;
1739 if (!scc->scc_dev || scc->scc_dev->sd_id.sd_rev < 5)
1741 siba_cc_clock(scc, SIBA_CLOCK_SLOW);
1742 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0);
1747 siba_pcicore_init(struct siba_pci *spc)
1749 struct siba_dev_softc *sd = spc->spc_dev;
1750 struct siba_softc *siba;
1756 if (!siba_dev_isup_sub(sd))
1757 siba_dev_up_sub(sd, 0);
1759 KASSERT(spc->spc_hostmode == 0,
1760 ("%s:%d: hostmode", __func__, __LINE__));
1761 /* disable PCI interrupt */
1762 siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0);
1766 siba_dev_isup(device_t dev)
1768 struct siba_dev_softc *sd = device_get_ivars(dev);
1770 return (siba_dev_isup_sub(sd));
1774 siba_dev_isup_sub(struct siba_dev_softc *sd)
1776 uint32_t reject, val;
1778 reject = siba_tmslow_reject_bitmask(sd);
1779 val = siba_read_4_sub(sd, SIBA_TGSLOW);
1780 val &= SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_RESET | reject;
1782 return (val == SIBA_TGSLOW_CLOCK);
1786 siba_dev_up(device_t dev, uint32_t flags)
1788 struct siba_dev_softc *sd = device_get_ivars(dev);
1790 siba_dev_up_sub(sd, flags);
1794 siba_dev_up_sub(struct siba_dev_softc *sd, uint32_t flags)
1798 siba_dev_down_sub(sd, flags);
1799 siba_write_4_sub(sd, SIBA_TGSLOW,
1800 SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
1801 siba_read_4_sub(sd, SIBA_TGSLOW);
1804 if (siba_read_4_sub(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR)
1805 siba_write_4_sub(sd, SIBA_TGSHIGH, 0);
1807 val = siba_read_4_sub(sd, SIBA_IAS);
1808 if (val & (SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT)) {
1809 val &= ~(SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT);
1810 siba_write_4_sub(sd, SIBA_IAS, val);
1813 siba_write_4_sub(sd, SIBA_TGSLOW,
1814 SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
1815 siba_read_4_sub(sd, SIBA_TGSLOW);
1818 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags);
1819 siba_read_4_sub(sd, SIBA_TGSLOW);
1824 siba_tmslow_reject_bitmask(struct siba_dev_softc *sd)
1826 uint32_t rev = siba_read_4_sub(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV;
1829 case SIBA_IDLOW_SSBREV_22:
1830 return (SIBA_TGSLOW_REJECT_22);
1831 case SIBA_IDLOW_SSBREV_23:
1832 return (SIBA_TGSLOW_REJECT_23);
1833 case SIBA_IDLOW_SSBREV_24:
1834 case SIBA_IDLOW_SSBREV_25:
1835 case SIBA_IDLOW_SSBREV_26:
1836 case SIBA_IDLOW_SSBREV_27:
1837 return (SIBA_TGSLOW_REJECT_23);
1840 ("%s:%d: unknown backplane rev %#x\n",
1841 __func__, __LINE__, rev));
1843 return (SIBA_TGSLOW_REJECT_22 | SIBA_TGSLOW_REJECT_23);
1847 siba_dev_down(device_t dev, uint32_t flags)
1849 struct siba_dev_softc *sd = device_get_ivars(dev);
1851 siba_dev_down_sub(sd, flags);
1855 siba_dev_down_sub(struct siba_dev_softc *sd, uint32_t flags)
1857 struct siba_softc *siba = sd->sd_bus;
1858 uint32_t reject, val;
1861 if (siba_read_4_sub(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET)
1864 reject = siba_tmslow_reject_bitmask(sd);
1865 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK);
1867 for (i = 0; i < 1000; i++) {
1868 val = siba_read_4_sub(sd, SIBA_TGSLOW);
1873 if ((val & reject) == 0) {
1874 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n",
1875 reject, SIBA_TGSLOW);
1877 for (i = 0; i < 1000; i++) {
1878 val = siba_read_4_sub(sd, SIBA_TGSHIGH);
1879 if (!(val & SIBA_TGSHIGH_BUSY))
1883 if ((val & SIBA_TGSHIGH_BUSY) != 0) {
1884 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n",
1885 SIBA_TGSHIGH_BUSY, SIBA_TGSHIGH);
1888 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK |
1889 reject | SIBA_TGSLOW_RESET | flags);
1890 siba_read_4_sub(sd, SIBA_TGSLOW);
1892 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags);
1893 siba_read_4_sub(sd, SIBA_TGSLOW);
1898 siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd)
1900 struct siba_dev_softc *psd = spc->spc_dev;
1901 struct siba_softc *siba = psd->sd_bus;
1904 if (psd->sd_id.sd_device == SIBA_DEVID_PCI) {
1905 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2,
1906 siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2) |
1907 SIBA_PCICORE_SBTOPCI_PREF | SIBA_PCICORE_SBTOPCI_BURST);
1909 if (psd->sd_id.sd_rev < 5) {
1910 tmp = siba_read_4_sub(psd, SIBA_IMCFGLO);
1911 tmp &= ~SIBA_IMCFGLO_SERTO;
1912 tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO;
1913 tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */;
1914 siba_write_4_sub(psd, SIBA_IMCFGLO, tmp);
1916 /* broadcast value */
1917 sd = (siba->siba_cc.scc_dev != NULL) ?
1918 siba->siba_cc.scc_dev : siba->siba_pci.spc_dev;
1920 siba_write_4_sub(sd, SIBA_PCICORE_BCAST_ADDR,
1922 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_ADDR);
1923 siba_write_4_sub(sd,
1924 SIBA_PCICORE_BCAST_DATA, 0);
1925 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_DATA);
1927 } else if (psd->sd_id.sd_rev >= 11) {
1928 tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2);
1929 tmp |= SIBA_PCICORE_SBTOPCI_MRM;
1930 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp);
1933 KASSERT(psd->sd_id.sd_device == SIBA_DEVID_PCIE, ("only PCIE"));
1934 if ((psd->sd_id.sd_rev == 0) || (psd->sd_id.sd_rev == 1))
1935 siba_pcie_write(spc, 0x4,
1936 siba_pcie_read(spc, 0x4) | 0x8);
1937 if (psd->sd_id.sd_rev == 0) {
1938 siba_pcie_mdio_write(spc, 0x1f, 2, 0x8128); /* Timer */
1939 siba_pcie_mdio_write(spc, 0x1f, 6, 0x0100); /* CDR */
1940 siba_pcie_mdio_write(spc, 0x1f, 7, 0x1466); /* CDR BW */
1941 } else if (psd->sd_id.sd_rev == 1)
1942 siba_pcie_write(spc, 0x100,
1943 siba_pcie_read(spc, 0x100) | 0x40);
1945 spc->spc_inited = 1;
1949 siba_pcicore_intr(device_t dev)
1951 struct siba_dev_softc *sd = device_get_ivars(dev);
1952 struct siba_softc *siba = sd->sd_bus;
1953 struct siba_pci *spc = &siba->siba_pci;
1954 struct siba_dev_softc *psd = spc->spc_dev;
1957 if (siba->siba_type != SIBA_TYPE_PCI || !psd)
1960 KASSERT(siba == psd->sd_bus, ("different pointers"));
1962 /* enable interrupts */
1963 if (siba->siba_dev != NULL &&
1964 (psd->sd_id.sd_rev >= 6 ||
1965 psd->sd_id.sd_device == SIBA_DEVID_PCIE)) {
1966 tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4);
1967 tmp |= (1 << sd->sd_coreidx) << 8;
1968 pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4);
1970 tmp = siba_read_4_sub(sd, SIBA_TPS);
1971 tmp &= SIBA_TPS_BPFLAG;
1972 siba_write_4_sub(psd, SIBA_INTR_MASK,
1973 siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp));
1977 if (spc->spc_inited == 0)
1978 siba_pcicore_setup(spc, sd);
1982 siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset)
1985 return (siba_read_4_sub(spc->spc_dev, offset));
1989 siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value)
1992 siba_write_4_sub(spc->spc_dev, offset, value);
1996 siba_pcie_read(struct siba_pci *spc, uint32_t address)
1999 siba_pcicore_write_4(spc, 0x130, address);
2000 return (siba_pcicore_read_4(spc, 0x134));
2004 siba_pcie_write(struct siba_pci *spc, uint32_t address, uint32_t data)
2007 siba_pcicore_write_4(spc, 0x130, address);
2008 siba_pcicore_write_4(spc, 0x134, data);
2012 siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address,
2017 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0x80 | 0x2);
2018 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_DATA,
2019 (1 << 30) | (1 << 28) |
2020 ((uint32_t)device << 22) | ((uint32_t)address << 18) |
2023 for (i = 0; i < 10; i++) {
2024 if (siba_pcicore_read_4(spc, SIBA_PCICORE_MDIO_CTL) & 0x100)
2028 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0);
2032 siba_dma_translation(device_t dev)
2035 struct siba_dev_softc *sd = device_get_ivars(dev);
2036 struct siba_softc *siba = sd->sd_bus;
2038 KASSERT(siba->siba_type == SIBA_TYPE_PCI,
2039 ("unsupported bustype %d\n", siba->siba_type));
2041 return (SIBA_PCI_DMA);
2045 siba_barrier(device_t dev, int flags)
2047 struct siba_dev_softc *sd = device_get_ivars(dev);
2048 struct siba_softc *siba = sd->sd_bus;
2050 SIBA_BARRIER(siba, flags);
2054 siba_cc_suspend(struct siba_cc *scc)
2057 siba_cc_clock(scc, SIBA_CLOCK_SLOW);
2061 siba_cc_resume(struct siba_cc *scc)
2064 siba_cc_power_init(scc);
2065 siba_cc_clock(scc, SIBA_CLOCK_FAST);
2069 siba_core_suspend(struct siba_softc *siba)
2072 siba_cc_suspend(&siba->siba_cc);
2073 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0);
2078 siba_core_resume(struct siba_softc *siba)
2081 siba->siba_pci.spc_inited = 0;
2082 siba->siba_curdev = NULL;
2084 siba_powerup_sub(siba, 0);
2085 /* XXX setup H/W for PCMCIA??? */
2086 siba_cc_resume(&siba->siba_cc);
2087 siba_powerdown_sub(siba);
2093 siba_cc_regctl_setmask(struct siba_cc *cc, uint32_t offset, uint32_t mask,
2097 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR);
2098 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_ADDR, offset);
2099 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR);
2100 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_DATA,
2101 (SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA) & mask) | set);
2102 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA);
2106 siba_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt)
2108 struct siba_dev_softc *sd = device_get_ivars(dev);
2109 struct siba_softc *siba = sd->sd_bus;
2110 struct siba_cc *scc = &siba->siba_cc;
2111 uint32_t *p = NULL, info[5][3] = {
2119 if (siba->siba_chipid == 0x4312) {
2120 if (id != SIBA_LDO_PAREF)
2123 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
2124 (volt & p[2]) << p[1]);
2127 if (siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354) {
2129 case SIBA_LDO_PAREF:
2132 case SIBA_LDO_VOLT1:
2135 case SIBA_LDO_VOLT2:
2138 case SIBA_LDO_VOLT3:
2143 ("%s: unsupported voltage ID %#x", __func__, id));
2146 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
2147 (volt & p[2]) << p[1]);
2152 siba_cc_pmu_set_ldoparef(device_t dev, uint8_t on)
2154 struct siba_dev_softc *sd = device_get_ivars(dev);
2155 struct siba_softc *siba = sd->sd_bus;
2156 struct siba_cc *scc = &siba->siba_cc;
2159 ldo = ((siba->siba_chipid == 0x4312) ? SIBA_CC_PMU_4312_PA_REF :
2160 ((siba->siba_chipid == 0x4328) ? SIBA_CC_PMU_4328_PA_REF :
2161 ((siba->siba_chipid == 0x5354) ? SIBA_CC_PMU_5354_PA_REF : -1)));
2166 SIBA_CC_SET32(scc, SIBA_CC_PMU_MINRES, 1 << ldo);
2168 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo));
2169 SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES);
2173 siba_read_sprom(device_t dev, device_t child, int which, uintptr_t *result)
2175 struct siba_dev_softc *sd = device_get_ivars(child);
2176 struct siba_softc *siba = sd->sd_bus;
2179 case SIBA_SPROMVAR_REV:
2180 *result = siba->siba_sprom.rev;
2182 case SIBA_SPROMVAR_MAC_80211BG:
2183 *((uint8_t **) result) = siba->siba_sprom.mac_80211bg;
2185 case SIBA_SPROMVAR_MAC_ETH:
2186 *((uint8_t **) result) = siba->siba_sprom.mac_eth;
2188 case SIBA_SPROMVAR_MAC_80211A:
2189 *((uint8_t **) result) = siba->siba_sprom.mac_80211a;
2191 case SIBA_SPROMVAR_MII_ETH0:
2192 *result = siba->siba_sprom.mii_eth0;
2194 case SIBA_SPROMVAR_MII_ETH1:
2195 *result = siba->siba_sprom.mii_eth1;
2197 case SIBA_SPROMVAR_MDIO_ETH0:
2198 *result = siba->siba_sprom.mdio_eth0;
2200 case SIBA_SPROMVAR_MDIO_ETH1:
2201 *result = siba->siba_sprom.mdio_eth1;
2203 case SIBA_SPROMVAR_BREV:
2204 *result = siba->siba_sprom.brev;
2206 case SIBA_SPROMVAR_CCODE:
2207 *result = siba->siba_sprom.ccode;
2209 case SIBA_SPROMVAR_ANT_A:
2210 *result = siba->siba_sprom.ant_a;
2212 case SIBA_SPROMVAR_ANT_BG:
2213 *result = siba->siba_sprom.ant_bg;
2215 case SIBA_SPROMVAR_PA0B0:
2216 *result = siba->siba_sprom.pa0b0;
2218 case SIBA_SPROMVAR_PA0B1:
2219 *result = siba->siba_sprom.pa0b1;
2221 case SIBA_SPROMVAR_PA0B2:
2222 *result = siba->siba_sprom.pa0b2;
2224 case SIBA_SPROMVAR_PA1B0:
2225 *result = siba->siba_sprom.pa1b0;
2227 case SIBA_SPROMVAR_PA1B1:
2228 *result = siba->siba_sprom.pa1b1;
2230 case SIBA_SPROMVAR_PA1B2:
2231 *result = siba->siba_sprom.pa1b2;
2233 case SIBA_SPROMVAR_PA1LOB0:
2234 *result = siba->siba_sprom.pa1lob0;
2236 case SIBA_SPROMVAR_PA1LOB1:
2237 *result = siba->siba_sprom.pa1lob1;
2239 case SIBA_SPROMVAR_PA1LOB2:
2240 *result = siba->siba_sprom.pa1lob2;
2242 case SIBA_SPROMVAR_PA1HIB0:
2243 *result = siba->siba_sprom.pa1hib0;
2245 case SIBA_SPROMVAR_PA1HIB1:
2246 *result = siba->siba_sprom.pa1hib1;
2248 case SIBA_SPROMVAR_PA1HIB2:
2249 *result = siba->siba_sprom.pa1hib2;
2251 case SIBA_SPROMVAR_GPIO0:
2252 *result = siba->siba_sprom.gpio0;
2254 case SIBA_SPROMVAR_GPIO1:
2255 *result = siba->siba_sprom.gpio1;
2257 case SIBA_SPROMVAR_GPIO2:
2258 *result = siba->siba_sprom.gpio2;
2260 case SIBA_SPROMVAR_GPIO3:
2261 *result = siba->siba_sprom.gpio3;
2263 case SIBA_SPROMVAR_MAXPWR_AL:
2264 *result = siba->siba_sprom.maxpwr_al;
2266 case SIBA_SPROMVAR_MAXPWR_A:
2267 *result = siba->siba_sprom.maxpwr_a;
2269 case SIBA_SPROMVAR_MAXPWR_AH:
2270 *result = siba->siba_sprom.maxpwr_ah;
2272 case SIBA_SPROMVAR_MAXPWR_BG:
2273 *result = siba->siba_sprom.maxpwr_bg;
2275 case SIBA_SPROMVAR_RXPO2G:
2276 *result = siba->siba_sprom.rxpo2g;
2278 case SIBA_SPROMVAR_RXPO5G:
2279 *result = siba->siba_sprom.rxpo5g;
2281 case SIBA_SPROMVAR_TSSI_A:
2282 *result = siba->siba_sprom.tssi_a;
2284 case SIBA_SPROMVAR_TSSI_BG:
2285 *result = siba->siba_sprom.tssi_bg;
2287 case SIBA_SPROMVAR_TRI2G:
2288 *result = siba->siba_sprom.tri2g;
2290 case SIBA_SPROMVAR_TRI5GL:
2291 *result = siba->siba_sprom.tri5gl;
2293 case SIBA_SPROMVAR_TRI5G:
2294 *result = siba->siba_sprom.tri5g;
2296 case SIBA_SPROMVAR_TRI5GH:
2297 *result = siba->siba_sprom.tri5gh;
2299 case SIBA_SPROMVAR_RSSISAV2G:
2300 *result = siba->siba_sprom.rssisav2g;
2302 case SIBA_SPROMVAR_RSSISMC2G:
2303 *result = siba->siba_sprom.rssismc2g;
2305 case SIBA_SPROMVAR_RSSISMF2G:
2306 *result = siba->siba_sprom.rssismf2g;
2308 case SIBA_SPROMVAR_BXA2G:
2309 *result = siba->siba_sprom.bxa2g;
2311 case SIBA_SPROMVAR_RSSISAV5G:
2312 *result = siba->siba_sprom.rssisav5g;
2314 case SIBA_SPROMVAR_RSSISMC5G:
2315 *result = siba->siba_sprom.rssismc5g;
2317 case SIBA_SPROMVAR_RSSISMF5G:
2318 *result = siba->siba_sprom.rssismf5g;
2320 case SIBA_SPROMVAR_BXA5G:
2321 *result = siba->siba_sprom.bxa5g;
2323 case SIBA_SPROMVAR_CCK2GPO:
2324 *result = siba->siba_sprom.cck2gpo;
2326 case SIBA_SPROMVAR_OFDM2GPO:
2327 *result = siba->siba_sprom.ofdm2gpo;
2329 case SIBA_SPROMVAR_OFDM5GLPO:
2330 *result = siba->siba_sprom.ofdm5glpo;
2332 case SIBA_SPROMVAR_OFDM5GPO:
2333 *result = siba->siba_sprom.ofdm5gpo;
2335 case SIBA_SPROMVAR_OFDM5GHPO:
2336 *result = siba->siba_sprom.ofdm5ghpo;
2338 case SIBA_SPROMVAR_BF_LO:
2339 *result = siba->siba_sprom.bf_lo;
2341 case SIBA_SPROMVAR_BF_HI:
2342 *result = siba->siba_sprom.bf_hi;
2344 case SIBA_SPROMVAR_BF2_LO:
2345 *result = siba->siba_sprom.bf2_lo;
2347 case SIBA_SPROMVAR_BF2_HI:
2348 *result = siba->siba_sprom.bf2_hi;
2357 siba_write_sprom(device_t dev, device_t child, int which, uintptr_t value)
2359 struct siba_dev_softc *sd = device_get_ivars(child);
2360 struct siba_softc *siba = sd->sd_bus;
2363 case SIBA_SPROMVAR_REV:
2364 siba->siba_sprom.rev = value;
2366 case SIBA_SPROMVAR_MII_ETH0:
2367 siba->siba_sprom.mii_eth0 = value;
2369 case SIBA_SPROMVAR_MII_ETH1:
2370 siba->siba_sprom.mii_eth1 = value;
2372 case SIBA_SPROMVAR_MDIO_ETH0:
2373 siba->siba_sprom.mdio_eth0 = value;
2375 case SIBA_SPROMVAR_MDIO_ETH1:
2376 siba->siba_sprom.mdio_eth1 = value;
2378 case SIBA_SPROMVAR_BREV:
2379 siba->siba_sprom.brev = value;
2381 case SIBA_SPROMVAR_CCODE:
2382 siba->siba_sprom.ccode = value;
2384 case SIBA_SPROMVAR_ANT_A:
2385 siba->siba_sprom.ant_a = value;
2387 case SIBA_SPROMVAR_ANT_BG:
2388 siba->siba_sprom.ant_bg = value;
2390 case SIBA_SPROMVAR_PA0B0:
2391 siba->siba_sprom.pa0b0 = value;
2393 case SIBA_SPROMVAR_PA0B1:
2394 siba->siba_sprom.pa0b1 = value;
2396 case SIBA_SPROMVAR_PA0B2:
2397 siba->siba_sprom.pa0b2 = value;
2399 case SIBA_SPROMVAR_PA1B0:
2400 siba->siba_sprom.pa1b0 = value;
2402 case SIBA_SPROMVAR_PA1B1:
2403 siba->siba_sprom.pa1b1 = value;
2405 case SIBA_SPROMVAR_PA1B2:
2406 siba->siba_sprom.pa1b2 = value;
2408 case SIBA_SPROMVAR_PA1LOB0:
2409 siba->siba_sprom.pa1lob0 = value;
2411 case SIBA_SPROMVAR_PA1LOB1:
2412 siba->siba_sprom.pa1lob1 = value;
2414 case SIBA_SPROMVAR_PA1LOB2:
2415 siba->siba_sprom.pa1lob2 = value;
2417 case SIBA_SPROMVAR_PA1HIB0:
2418 siba->siba_sprom.pa1hib0 = value;
2420 case SIBA_SPROMVAR_PA1HIB1:
2421 siba->siba_sprom.pa1hib1 = value;
2423 case SIBA_SPROMVAR_PA1HIB2:
2424 siba->siba_sprom.pa1hib2 = value;
2426 case SIBA_SPROMVAR_GPIO0:
2427 siba->siba_sprom.gpio0 = value;
2429 case SIBA_SPROMVAR_GPIO1:
2430 siba->siba_sprom.gpio1 = value;
2432 case SIBA_SPROMVAR_GPIO2:
2433 siba->siba_sprom.gpio2 = value;
2435 case SIBA_SPROMVAR_GPIO3:
2436 siba->siba_sprom.gpio3 = value;
2438 case SIBA_SPROMVAR_MAXPWR_AL:
2439 siba->siba_sprom.maxpwr_al = value;
2441 case SIBA_SPROMVAR_MAXPWR_A:
2442 siba->siba_sprom.maxpwr_a = value;
2444 case SIBA_SPROMVAR_MAXPWR_AH:
2445 siba->siba_sprom.maxpwr_ah = value;
2447 case SIBA_SPROMVAR_MAXPWR_BG:
2448 siba->siba_sprom.maxpwr_bg = value;
2450 case SIBA_SPROMVAR_RXPO2G:
2451 siba->siba_sprom.rxpo2g = value;
2453 case SIBA_SPROMVAR_RXPO5G:
2454 siba->siba_sprom.rxpo5g = value;
2456 case SIBA_SPROMVAR_TSSI_A:
2457 siba->siba_sprom.tssi_a = value;
2459 case SIBA_SPROMVAR_TSSI_BG:
2460 siba->siba_sprom.tssi_bg = value;
2462 case SIBA_SPROMVAR_TRI2G:
2463 siba->siba_sprom.tri2g = value;
2465 case SIBA_SPROMVAR_TRI5GL:
2466 siba->siba_sprom.tri5gl = value;
2468 case SIBA_SPROMVAR_TRI5G:
2469 siba->siba_sprom.tri5g = value;
2471 case SIBA_SPROMVAR_TRI5GH:
2472 siba->siba_sprom.tri5gh = value;
2474 case SIBA_SPROMVAR_RSSISAV2G:
2475 siba->siba_sprom.rssisav2g = value;
2477 case SIBA_SPROMVAR_RSSISMC2G:
2478 siba->siba_sprom.rssismc2g = value;
2480 case SIBA_SPROMVAR_RSSISMF2G:
2481 siba->siba_sprom.rssismf2g = value;
2483 case SIBA_SPROMVAR_BXA2G:
2484 siba->siba_sprom.bxa2g = value;
2486 case SIBA_SPROMVAR_RSSISAV5G:
2487 siba->siba_sprom.rssisav5g = value;
2489 case SIBA_SPROMVAR_RSSISMC5G:
2490 siba->siba_sprom.rssismc5g = value;
2492 case SIBA_SPROMVAR_RSSISMF5G:
2493 siba->siba_sprom.rssismf5g = value;
2495 case SIBA_SPROMVAR_BXA5G:
2496 siba->siba_sprom.bxa5g = value;
2498 case SIBA_SPROMVAR_CCK2GPO:
2499 siba->siba_sprom.cck2gpo = value;
2501 case SIBA_SPROMVAR_OFDM2GPO:
2502 siba->siba_sprom.ofdm2gpo = value;
2504 case SIBA_SPROMVAR_OFDM5GLPO:
2505 siba->siba_sprom.ofdm5glpo = value;
2507 case SIBA_SPROMVAR_OFDM5GPO:
2508 siba->siba_sprom.ofdm5gpo = value;
2510 case SIBA_SPROMVAR_OFDM5GHPO:
2511 siba->siba_sprom.ofdm5ghpo = value;
2513 case SIBA_SPROMVAR_BF_LO:
2514 siba->siba_sprom.bf_lo = value;
2516 case SIBA_SPROMVAR_BF_HI:
2517 siba->siba_sprom.bf_hi = value;
2519 case SIBA_SPROMVAR_BF2_LO:
2520 siba->siba_sprom.bf2_lo = value;
2522 case SIBA_SPROMVAR_BF2_HI:
2523 siba->siba_sprom.bf2_hi = value;
2531 #define SIBA_GPIOCTL 0x06c
2534 siba_gpio_get(device_t dev)
2536 struct siba_dev_softc *sd = device_get_ivars(dev);
2537 struct siba_softc *siba = sd->sd_bus;
2538 struct siba_dev_softc *gpiodev, *pcidev = NULL;
2540 pcidev = siba->siba_pci.spc_dev;
2541 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
2544 return (siba_read_4_sub(gpiodev, SIBA_GPIOCTL));
2548 siba_gpio_set(device_t dev, uint32_t value)
2550 struct siba_dev_softc *sd = device_get_ivars(dev);
2551 struct siba_softc *siba = sd->sd_bus;
2552 struct siba_dev_softc *gpiodev, *pcidev = NULL;
2554 pcidev = siba->siba_pci.spc_dev;
2555 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
2558 siba_write_4_sub(gpiodev, SIBA_GPIOCTL, value);
2562 siba_fix_imcfglobug(device_t dev)
2564 struct siba_dev_softc *sd = device_get_ivars(dev);
2565 struct siba_softc *siba = sd->sd_bus;
2568 if (siba->siba_pci.spc_dev == NULL)
2570 if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI ||
2571 siba->siba_pci.spc_dev->sd_id.sd_rev > 5)
2574 tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) &
2575 ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO);
2576 switch (siba->siba_type) {
2578 case SIBA_TYPE_PCMCIA:
2585 siba_write_4_sub(sd, SIBA_IMCFGLO, tmp);