sys/dev/siba/sibavar.h

   1 /*-
   2  * Copyright (c) 2007 Bruce M. Simpson.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #ifndef _SIBA_SIBAVAR_H_
  30 #define _SIBA_SIBAVAR_H_
  31
  32 #include <sys/rman.h>
  33
  34 struct siba_softc;
  35 struct siba_dev_softc;
  36
  37 enum siba_type {
  38         SIBA_TYPE_SSB,
  39         SIBA_TYPE_PCI,
  40         SIBA_TYPE_PCMCIA,
  41 };
  42
  43 enum siba_device_ivars {
  44         SIBA_IVAR_VENDOR,
  45         SIBA_IVAR_DEVICE,
  46         SIBA_IVAR_REVID,
  47         SIBA_IVAR_CORE_INDEX,
  48         SIBA_IVAR_PCI_VENDOR,
  49         SIBA_IVAR_PCI_DEVICE,
  50         SIBA_IVAR_PCI_SUBVENDOR,
  51         SIBA_IVAR_PCI_SUBDEVICE,
  52         SIBA_IVAR_PCI_REVID,
  53         SIBA_IVAR_CHIPID,
  54         SIBA_IVAR_CHIPREV,
  55         SIBA_IVAR_CHIPPKG,
  56         SIBA_IVAR_TYPE,
  57         SIBA_IVAR_CC_PMUFREQ,
  58         SIBA_IVAR_CC_CAPS,
  59         SIBA_IVAR_CC_POWERDELAY,
  60         SIBA_IVAR_PCICORE_REVID
  61 };
  62
  63 #define SIBA_ACCESSOR(var, ivar, type)                          \
  64         __BUS_ACCESSOR(siba, var, SIBA, ivar, type)
  65
  66 SIBA_ACCESSOR(vendor,           VENDOR,         uint16_t)
  67 SIBA_ACCESSOR(device,           DEVICE,         uint16_t)
  68 SIBA_ACCESSOR(revid,            REVID,          uint8_t)
  69 SIBA_ACCESSOR(core_index,       CORE_INDEX,     uint8_t)
  70 SIBA_ACCESSOR(pci_vendor,       PCI_VENDOR,     uint16_t)
  71 SIBA_ACCESSOR(pci_device,       PCI_DEVICE,     uint16_t)
  72 SIBA_ACCESSOR(pci_subvendor,    PCI_SUBVENDOR,  uint16_t)
  73 SIBA_ACCESSOR(pci_subdevice,    PCI_SUBDEVICE,  uint16_t)
  74 SIBA_ACCESSOR(pci_revid,        PCI_REVID,      uint8_t)
  75 SIBA_ACCESSOR(chipid,           CHIPID,         uint16_t)
  76 SIBA_ACCESSOR(chiprev,          CHIPREV,        uint16_t)
  77 SIBA_ACCESSOR(chippkg,          CHIPPKG,        uint8_t)
  78 SIBA_ACCESSOR(type,             TYPE,           enum siba_type)
  79 SIBA_ACCESSOR(cc_pmufreq,       CC_PMUFREQ,     uint32_t)
  80 SIBA_ACCESSOR(cc_caps,          CC_CAPS,        uint32_t)
  81 SIBA_ACCESSOR(cc_powerdelay,    CC_POWERDELAY,  uint16_t)
  82 SIBA_ACCESSOR(pcicore_revid,    PCICORE_REVID,  uint8_t)
  83
  84 #undef SIBA_ACCESSOR
  85
  86 /* XXX just for SPROM1? */
  87 enum {
  88         SIBA_CCODE_WORLD,
  89         SIBA_CCODE_THAILAND,
  90         SIBA_CCODE_ISRAEL,
  91         SIBA_CCODE_JORDAN,
  92         SIBA_CCODE_CHINA,
  93         SIBA_CCODE_JAPAN,
  94         SIBA_CCODE_USA_CANADA_ANZ,
  95         SIBA_CCODE_EUROPE,
  96         SIBA_CCODE_USA_LOW,
  97         SIBA_CCODE_JAPAN_HIGH,
  98         SIBA_CCODE_ALL,
  99         SIBA_CCODE_NONE,
 100 };
 101
 102 #define siba_mips_read_2(sc, core, reg)                         \
 103         bus_space_read_2((sc)->siba_mem_bt, (sc)->siba_mem_bh,  \
 104                          (core * SIBA_CORE_LEN) + (reg))
 105
 106 #define siba_mips_read_4(sc, core, reg)                         \
 107         bus_space_read_4((sc)->siba_mem_bt, (sc)->siba_mem_bh,  \
 108                          (core * SIBA_CORE_LEN) + (reg))
 109
 110 #define siba_mips_write_2(sc, core, reg, val)                   \
 111         bus_space_write_2((sc)->siba_mem_bt, (sc)->siba_mem_bh, \
 112                          (core * SIBA_CORE_LEN) + (reg), (val))
 113
 114 #define siba_mips_write_4(sc, core, reg, val)                   \
 115         bus_space_write_4((sc)->siba_mem_bt, (sc)->siba_mem_bh, \
 116                          (core * SIBA_CORE_LEN) + (reg), (val))
 117
 118 #define SIBA_READ_4(siba, reg)          \
 119         bus_space_read_4((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg))
 120 #define SIBA_READ_2(siba, reg)          \
 121         bus_space_read_2((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg))
 122 #define SIBA_READ_MULTI_1(siba, reg, addr, count)                       \
 123         bus_space_read_multi_1((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
 124             (reg), (addr), (count))
 125 #define SIBA_READ_MULTI_2(siba, reg, addr, count)                       \
 126         bus_space_read_multi_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
 127             (reg), (addr), (count))
 128 #define SIBA_READ_MULTI_4(siba, reg, addr, count)                       \
 129         bus_space_read_multi_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
 130             (reg), (addr), (count))
 131
 132 #define SIBA_WRITE_4(siba, reg, val)    \
 133         bus_space_write_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,     \
 134             (reg), (val))
 135 #define SIBA_WRITE_2(siba, reg, val)    \
 136         bus_space_write_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,     \
 137             (reg), (val))
 138 #define SIBA_WRITE_MULTI_1(siba, reg, addr, count)                      \
 139         bus_space_write_multi_1((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
 140             (reg), (addr), (count))
 141 #define SIBA_WRITE_MULTI_2(siba, reg, addr, count)                      \
 142         bus_space_write_multi_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
 143             (reg), (addr), (count))
 144 #define SIBA_WRITE_MULTI_4(siba, reg, addr, count)                      \
 145         bus_space_write_multi_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
 146             (reg), (addr), (count))
 147
 148 #define SIBA_BARRIER(siba, flags)                                       \
 149         bus_space_barrier((siba)->siba_mem_bt, (siba)->siba_mem_bh, (0),\
 150             (0), (flags))
 151
 152 #define SIBA_SETBITS_4(siba, reg, bits) \
 153         SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) | (bits))
 154 #define SIBA_SETBITS_2(siba, reg, bits) \
 155         SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) | (bits))
 156
 157 #define SIBA_FILT_SETBITS_4(siba, reg, filt, bits) \
 158         SIBA_WRITE_4((siba), (reg), (SIBA_READ_4((siba),        \
 159             (reg)) & (filt)) | (bits))
 160 #define SIBA_FILT_SETBITS_2(siba, reg, filt, bits)      \
 161         SIBA_WRITE_2((siba), (reg), (SIBA_READ_2((siba),        \
 162             (reg)) & (filt)) | (bits))
 163
 164 #define SIBA_CLRBITS_4(siba, reg, bits) \
 165         SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) & ~(bits))
 166 #define SIBA_CLRBITS_2(siba, reg, bits) \
 167         SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) & ~(bits))
 168
 169 #define SIBA_CC_READ32(scc, offset) \
 170         siba_read_4_sub((scc)->scc_dev, offset)
 171 #define SIBA_CC_WRITE32(scc, offset, val) \
 172         siba_write_4_sub((scc)->scc_dev, offset, val)
 173 #define SIBA_CC_MASK32(scc, offset, mask) \
 174         SIBA_CC_WRITE32(scc, offset, SIBA_CC_READ32(scc, offset) & (mask))
 175 #define SIBA_CC_SET32(scc, offset, set) \
 176         SIBA_CC_WRITE32(scc, offset, SIBA_CC_READ32(scc, offset) | (set))
 177 #define SIBA_CC_MASKSET32(scc, offset, mask, set)       \
 178         SIBA_CC_WRITE32(scc, offset,                    \
 179             (SIBA_CC_READ32(scc, offset) & (mask)) | (set))
 180
 181 enum siba_clock {
 182         SIBA_CLOCK_DYNAMIC,
 183         SIBA_CLOCK_SLOW,
 184         SIBA_CLOCK_FAST,
 185 };
 186
 187 enum siba_clksrc {
 188         SIBA_CC_CLKSRC_PCI,
 189         SIBA_CC_CLKSRC_CRYSTAL,
 190         SIBA_CC_CLKSRC_LOWPW,
 191 };
 192
 193 struct siba_cc_pmu0_plltab {
 194         uint16_t                freq;   /* in kHz.*/
 195         uint8_t                 xf;     /* crystal frequency */
 196         uint8_t                 wb_int;
 197         uint32_t                wb_frac;
 198 };
 199
 200 struct siba_cc_pmu1_plltab {
 201         uint16_t                freq;
 202         uint8_t                 xf;
 203         uint8_t                 p1div;
 204         uint8_t                 p2div;
 205         uint8_t                 ndiv_int;
 206         uint32_t                ndiv_frac;
 207 };
 208
 209 struct siba_cc_pmu_res_updown {
 210         uint8_t                 res;
 211         uint16_t                updown;
 212 };
 213
 214 #define SIBA_CC_PMU_DEP_SET     1
 215 #define SIBA_CC_PMU_DEP_ADD     2
 216 #define SIBA_CC_PMU_DEP_REMOVE  3
 217
 218 struct siba_cc_pmu_res_depend {
 219         uint8_t                 res;
 220         uint8_t                 task;
 221         uint32_t                depend;
 222 };
 223
 224 enum siba_sprom_vars {
 225         SIBA_SPROMVAR_REV,
 226         SIBA_SPROMVAR_MAC_80211BG,
 227         SIBA_SPROMVAR_MAC_ETH,
 228         SIBA_SPROMVAR_MAC_80211A,
 229         SIBA_SPROMVAR_MII_ETH0,
 230         SIBA_SPROMVAR_MII_ETH1,
 231         SIBA_SPROMVAR_MDIO_ETH0,
 232         SIBA_SPROMVAR_MDIO_ETH1,
 233         SIBA_SPROMVAR_BREV,
 234         SIBA_SPROMVAR_CCODE,
 235         SIBA_SPROMVAR_ANT_A,
 236         SIBA_SPROMVAR_ANT_BG,
 237         SIBA_SPROMVAR_PA0B0,
 238         SIBA_SPROMVAR_PA0B1,
 239         SIBA_SPROMVAR_PA0B2,
 240         SIBA_SPROMVAR_PA1B0,
 241         SIBA_SPROMVAR_PA1B1,
 242         SIBA_SPROMVAR_PA1B2,
 243         SIBA_SPROMVAR_PA1LOB0,
 244         SIBA_SPROMVAR_PA1LOB1,
 245         SIBA_SPROMVAR_PA1LOB2,
 246         SIBA_SPROMVAR_PA1HIB0,
 247         SIBA_SPROMVAR_PA1HIB1,
 248         SIBA_SPROMVAR_PA1HIB2,
 249         SIBA_SPROMVAR_GPIO0,
 250         SIBA_SPROMVAR_GPIO1,
 251         SIBA_SPROMVAR_GPIO2,
 252         SIBA_SPROMVAR_GPIO3,
 253         SIBA_SPROMVAR_MAXPWR_AL,
 254         SIBA_SPROMVAR_MAXPWR_A,
 255         SIBA_SPROMVAR_MAXPWR_AH,
 256         SIBA_SPROMVAR_MAXPWR_BG,
 257         SIBA_SPROMVAR_RXPO2G,
 258         SIBA_SPROMVAR_RXPO5G,
 259         SIBA_SPROMVAR_TSSI_A,
 260         SIBA_SPROMVAR_TSSI_BG,
 261         SIBA_SPROMVAR_TRI2G,
 262         SIBA_SPROMVAR_TRI5GL,
 263         SIBA_SPROMVAR_TRI5G,
 264         SIBA_SPROMVAR_TRI5GH,
 265         SIBA_SPROMVAR_RSSISAV2G,
 266         SIBA_SPROMVAR_RSSISMC2G,
 267         SIBA_SPROMVAR_RSSISMF2G,
 268         SIBA_SPROMVAR_BXA2G,
 269         SIBA_SPROMVAR_RSSISAV5G,
 270         SIBA_SPROMVAR_RSSISMC5G,
 271         SIBA_SPROMVAR_RSSISMF5G,
 272         SIBA_SPROMVAR_BXA5G,
 273         SIBA_SPROMVAR_CCK2GPO,
 274         SIBA_SPROMVAR_OFDM2GPO,
 275         SIBA_SPROMVAR_OFDM5GLPO,
 276         SIBA_SPROMVAR_OFDM5GPO,
 277         SIBA_SPROMVAR_OFDM5GHPO,
 278         SIBA_SPROMVAR_BF_LO,
 279         SIBA_SPROMVAR_BF_HI,
 280         SIBA_SPROMVAR_BF2_LO,
 281         SIBA_SPROMVAR_BF2_HI,
 282         SIBA_SPROMVAR_FEM_2GHZ_TSSIPOS,
 283         SIBA_SPROMVAR_FEM_2GHZ_EXTPAGAIN,
 284         SIBA_SPROMVAR_FEM_2GHZ_PDET_RANGE,
 285         SIBA_SPROMVAR_FEM_2GHZ_TR_ISO,
 286         SIBA_SPROMVAR_FEM_2GHZ_ANTSWLUT,
 287         SIBA_SPROMVAR_FEM_5GHZ_TSSIPOS,
 288         SIBA_SPROMVAR_FEM_5GHZ_EXTPAGAIN,
 289         SIBA_SPROMVAR_FEM_5GHZ_PDET_RANGE,
 290         SIBA_SPROMVAR_FEM_5GHZ_TR_ISO,
 291         SIBA_SPROMVAR_FEM_5GHZ_ANTSWLUT,
 292         SIBA_SPROMVAR_TXPID_2G_0,
 293         SIBA_SPROMVAR_TXPID_2G_1,
 294         SIBA_SPROMVAR_TXPID_2G_2,
 295         SIBA_SPROMVAR_TXPID_2G_3,
 296         SIBA_SPROMVAR_TXPID_5GL_0,
 297         SIBA_SPROMVAR_TXPID_5GL_1,
 298         SIBA_SPROMVAR_TXPID_5GL_2,
 299         SIBA_SPROMVAR_TXPID_5GL_3,
 300         SIBA_SPROMVAR_TXPID_5G_0,
 301         SIBA_SPROMVAR_TXPID_5G_1,
 302         SIBA_SPROMVAR_TXPID_5G_2,
 303         SIBA_SPROMVAR_TXPID_5G_3,
 304         SIBA_SPROMVAR_TXPID_5GH_0,
 305         SIBA_SPROMVAR_TXPID_5GH_1,
 306         SIBA_SPROMVAR_TXPID_5GH_2,
 307         SIBA_SPROMVAR_TXPID_5GH_3,
 308         SIBA_SPROMVAR_STBCPO,
 309         SIBA_SPROMVAR_CDDPO,
 310 };
 311
 312 int             siba_read_sprom(device_t, device_t, int, uintptr_t *);
 313 int             siba_write_sprom(device_t, device_t, int, uintptr_t);
 314
 315 /**
 316  * Generic sprom accessor generation macros for siba(4) drivers
 317  */
 318 #define __SPROM_ACCESSOR(varp, var, ivarp, ivar, type)                  \
 319                                                                         \
 320 static __inline type varp ## _get_ ## var(device_t dev)                 \
 321 {                                                                       \
 322         uintptr_t v;                                                    \
 323         siba_read_sprom(device_get_parent(dev), dev,                    \
 324             ivarp ## _SPROMVAR_ ## ivar, &v);                           \
 325         return ((type) v);                                              \
 326 }                                                                       \
 327                                                                         \
 328 static __inline void varp ## _set_ ## var(device_t dev, type t)         \
 329 {                                                                       \
 330         uintptr_t v = (uintptr_t) t;                                    \
 331         siba_write_sprom(device_get_parent(dev), dev,                   \
 332             ivarp ## _SPROMVAR_ ## ivar, v);                            \
 333 }
 334
 335 #define SIBA_SPROM_ACCESSOR(var, ivar, type)                            \
 336         __SPROM_ACCESSOR(siba_sprom, var, SIBA, ivar, type)
 337
 338 SIBA_SPROM_ACCESSOR(rev,        REV,            uint8_t);
 339 SIBA_SPROM_ACCESSOR(mac_80211bg,        MAC_80211BG,    uint8_t *);
 340 SIBA_SPROM_ACCESSOR(mac_eth,    MAC_ETH,        uint8_t *);
 341 SIBA_SPROM_ACCESSOR(mac_80211a, MAC_80211A,     uint8_t *);
 342 SIBA_SPROM_ACCESSOR(mii_eth0,   MII_ETH0,       uint8_t);
 343 SIBA_SPROM_ACCESSOR(mii_eth1,   MII_ETH1,       uint8_t);
 344 SIBA_SPROM_ACCESSOR(mdio_eth0,  MDIO_ETH0,      uint8_t);
 345 SIBA_SPROM_ACCESSOR(mdio_eth1,  MDIO_ETH1,      uint8_t);
 346 SIBA_SPROM_ACCESSOR(brev,       BREV,           uint8_t);
 347 SIBA_SPROM_ACCESSOR(ccode,      CCODE,          uint8_t);
 348 SIBA_SPROM_ACCESSOR(ant_a,      ANT_A,          uint8_t);
 349 SIBA_SPROM_ACCESSOR(ant_bg,     ANT_BG,         uint8_t);
 350 SIBA_SPROM_ACCESSOR(pa0b0,      PA0B0,          uint16_t);
 351 SIBA_SPROM_ACCESSOR(pa0b1,      PA0B1,          uint16_t);
 352 SIBA_SPROM_ACCESSOR(pa0b2,      PA0B2,          uint16_t);
 353 SIBA_SPROM_ACCESSOR(pa1b0,      PA1B0,          uint16_t);
 354 SIBA_SPROM_ACCESSOR(pa1b1,      PA1B1,          uint16_t);
 355 SIBA_SPROM_ACCESSOR(pa1b2,      PA1B2,          uint16_t);
 356 SIBA_SPROM_ACCESSOR(pa1lob0,    PA1LOB0,        uint16_t);
 357 SIBA_SPROM_ACCESSOR(pa1lob1,    PA1LOB1,        uint16_t);
 358 SIBA_SPROM_ACCESSOR(pa1lob2,    PA1LOB2,        uint16_t);
 359 SIBA_SPROM_ACCESSOR(pa1hib0,    PA1HIB0,        uint16_t);
 360 SIBA_SPROM_ACCESSOR(pa1hib1,    PA1HIB1,        uint16_t);
 361 SIBA_SPROM_ACCESSOR(pa1hib2,    PA1HIB2,        uint16_t);
 362 SIBA_SPROM_ACCESSOR(gpio0,      GPIO0,          uint8_t);
 363 SIBA_SPROM_ACCESSOR(gpio1,      GPIO1,          uint8_t);
 364 SIBA_SPROM_ACCESSOR(gpio2,      GPIO2,          uint8_t);
 365 SIBA_SPROM_ACCESSOR(gpio3,      GPIO3,          uint8_t);
 366 SIBA_SPROM_ACCESSOR(maxpwr_al,  MAXPWR_AL,      uint16_t);
 367 SIBA_SPROM_ACCESSOR(maxpwr_a,   MAXPWR_A,       uint16_t);
 368 SIBA_SPROM_ACCESSOR(maxpwr_ah,  MAXPWR_AH,      uint16_t);
 369 SIBA_SPROM_ACCESSOR(maxpwr_bg,  MAXPWR_BG,      uint16_t);
 370 SIBA_SPROM_ACCESSOR(rxpo2g,     RXPO2G,         uint8_t);
 371 SIBA_SPROM_ACCESSOR(rxpo5g,     RXPO5G,         uint8_t);
 372 SIBA_SPROM_ACCESSOR(tssi_a,     TSSI_A,         uint8_t);
 373 SIBA_SPROM_ACCESSOR(tssi_bg,    TSSI_BG,        uint8_t);
 374 SIBA_SPROM_ACCESSOR(tri2g,      TRI2G,          uint8_t);
 375 SIBA_SPROM_ACCESSOR(tri5gl,     TRI5GL,         uint8_t);
 376 SIBA_SPROM_ACCESSOR(tri5g,      TRI5G,          uint8_t);
 377 SIBA_SPROM_ACCESSOR(tri5gh,     TRI5GH,         uint8_t);
 378 SIBA_SPROM_ACCESSOR(rssisav2g,  RSSISAV2G,      uint8_t);
 379 SIBA_SPROM_ACCESSOR(rssismc2g,  RSSISMC2G,      uint8_t);
 380 SIBA_SPROM_ACCESSOR(rssismf2g,  RSSISMF2G,      uint8_t);
 381 SIBA_SPROM_ACCESSOR(bxa2g,      BXA2G,          uint8_t);
 382 SIBA_SPROM_ACCESSOR(rssisav5g,  RSSISAV5G,      uint8_t);
 383 SIBA_SPROM_ACCESSOR(rssismc5g,  RSSISMC5G,      uint8_t);
 384 SIBA_SPROM_ACCESSOR(rssismf5g,  RSSISMF5G,      uint8_t);
 385 SIBA_SPROM_ACCESSOR(bxa5g,      BXA5G,          uint8_t);
 386 SIBA_SPROM_ACCESSOR(cck2gpo,    CCK2GPO,        uint16_t);
 387 SIBA_SPROM_ACCESSOR(ofdm2gpo,   OFDM2GPO,       uint32_t);
 388 SIBA_SPROM_ACCESSOR(ofdm5glpo,  OFDM5GLPO,      uint32_t);
 389 SIBA_SPROM_ACCESSOR(ofdm5gpo,   OFDM5GPO,       uint32_t);
 390 SIBA_SPROM_ACCESSOR(ofdm5ghpo,  OFDM5GHPO,      uint32_t);
 391 SIBA_SPROM_ACCESSOR(bf_lo,      BF_LO,          uint16_t);
 392 SIBA_SPROM_ACCESSOR(bf_hi,      BF_HI,          uint16_t);
 393 SIBA_SPROM_ACCESSOR(bf2_lo,     BF2_LO,         uint16_t);
 394 SIBA_SPROM_ACCESSOR(bf2_hi,     BF2_HI,         uint16_t);
 395 /* 2GHz FEM */
 396 SIBA_SPROM_ACCESSOR(fem_2ghz_tssipos, FEM_2GHZ_TSSIPOS, uint8_t);
 397 SIBA_SPROM_ACCESSOR(fem_2ghz_extpa_gain, FEM_2GHZ_EXTPAGAIN, uint8_t);
 398 SIBA_SPROM_ACCESSOR(fem_2ghz_pdet_range, FEM_2GHZ_PDET_RANGE, uint8_t);
 399 SIBA_SPROM_ACCESSOR(fem_2ghz_tr_iso, FEM_2GHZ_TR_ISO, uint8_t);
 400 SIBA_SPROM_ACCESSOR(fem_2ghz_antswlut, FEM_2GHZ_ANTSWLUT, uint8_t);
 401 /* 5GHz FEM */
 402 SIBA_SPROM_ACCESSOR(fem_5ghz_tssipos, FEM_5GHZ_TSSIPOS, uint8_t);
 403 SIBA_SPROM_ACCESSOR(fem_5ghz_extpa_gain, FEM_5GHZ_EXTPAGAIN, uint8_t);
 404 SIBA_SPROM_ACCESSOR(fem_5ghz_pdet_range, FEM_5GHZ_PDET_RANGE, uint8_t);
 405 SIBA_SPROM_ACCESSOR(fem_5ghz_tr_iso, FEM_5GHZ_TR_ISO, uint8_t);
 406 SIBA_SPROM_ACCESSOR(fem_5ghz_antswlut, FEM_5GHZ_ANTSWLUT, uint8_t);
 407 /* TX power index */
 408 SIBA_SPROM_ACCESSOR(txpid_2g_0, TXPID_2G_0, uint8_t);
 409 SIBA_SPROM_ACCESSOR(txpid_2g_1, TXPID_2G_1, uint8_t);
 410 SIBA_SPROM_ACCESSOR(txpid_2g_2, TXPID_2G_2, uint8_t);
 411 SIBA_SPROM_ACCESSOR(txpid_2g_3, TXPID_2G_3, uint8_t);
 412 SIBA_SPROM_ACCESSOR(txpid_5gl_0, TXPID_5GL_0, uint8_t);
 413 SIBA_SPROM_ACCESSOR(txpid_5gl_1, TXPID_5GL_1, uint8_t);
 414 SIBA_SPROM_ACCESSOR(txpid_5gl_2, TXPID_5GL_2, uint8_t);
 415 SIBA_SPROM_ACCESSOR(txpid_5gl_3, TXPID_5GL_3, uint8_t);
 416 SIBA_SPROM_ACCESSOR(txpid_5g_0, TXPID_5G_0, uint8_t);
 417 SIBA_SPROM_ACCESSOR(txpid_5g_1, TXPID_5G_1, uint8_t);
 418 SIBA_SPROM_ACCESSOR(txpid_5g_2, TXPID_5G_2, uint8_t);
 419 SIBA_SPROM_ACCESSOR(txpid_5g_3, TXPID_5G_3, uint8_t);
 420 SIBA_SPROM_ACCESSOR(txpid_5gh_0, TXPID_5GH_0, uint8_t);
 421 SIBA_SPROM_ACCESSOR(txpid_5gh_1, TXPID_5GH_1, uint8_t);
 422 SIBA_SPROM_ACCESSOR(txpid_5gh_2, TXPID_5GH_2, uint8_t);
 423 SIBA_SPROM_ACCESSOR(txpid_5gh_3, TXPID_5GH_3, uint8_t);
 424 SIBA_SPROM_ACCESSOR(stbcpo, STBCPO, uint16_t);
 425 SIBA_SPROM_ACCESSOR(cddpo, CDDPO, uint16_t);
 426
 427 #undef SIBA_SPROM_ACCESSOR
 428
 429 struct siba_sprom_core_pwr_info {
 430         uint8_t itssi_2g, itssi_5g;
 431         uint8_t maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
 432         uint8_t pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
 433 };
 434
 435 struct siba_sprom {
 436         uint8_t                 rev;            /* revision */
 437         uint8_t                 mac_80211bg[6]; /* address for 802.11b/g */
 438         uint8_t                 mac_eth[6];     /* address for Ethernet */
 439         uint8_t                 mac_80211a[6];  /* address for 802.11a */
 440         uint8_t                 mii_eth0;       /* MII address for eth0 */
 441         uint8_t                 mii_eth1;       /* MII address for eth1 */
 442         uint8_t                 mdio_eth0;      /* MDIO for eth0 */
 443         uint8_t                 mdio_eth1;      /* MDIO for eth1 */
 444         uint8_t                 brev;           /* board revision */
 445         uint8_t                 ccode;          /* Country Code */
 446         uint8_t                 ant_a;          /* A-PHY antenna */
 447         uint8_t                 ant_bg;         /* B/G-PHY antenna */
 448         uint16_t                pa0b0;
 449         uint16_t                pa0b1;
 450         uint16_t                pa0b2;
 451         uint16_t                pa1b0;
 452         uint16_t                pa1b1;
 453         uint16_t                pa1b2;
 454         uint16_t                pa1lob0;
 455         uint16_t                pa1lob1;
 456         uint16_t                pa1lob2;
 457         uint16_t                pa1hib0;
 458         uint16_t                pa1hib1;
 459         uint16_t                pa1hib2;
 460         uint8_t                 gpio0;
 461         uint8_t                 gpio1;
 462         uint8_t                 gpio2;
 463         uint8_t                 gpio3;
 464         uint16_t                maxpwr_al;
 465         uint16_t                maxpwr_a;       /* A-PHY Max Power */
 466         uint16_t                maxpwr_ah;
 467         uint16_t                maxpwr_bg;      /* BG-PHY Max Power */
 468         uint8_t                 rxpo2g;
 469         uint8_t                 rxpo5g;
 470         uint8_t                 tssi_a;         /* Idle TSSI */
 471         uint8_t                 tssi_bg;        /* Idle TSSI */
 472         uint8_t                 tri2g;
 473         uint8_t                 tri5gl;
 474         uint8_t                 tri5g;
 475         uint8_t                 tri5gh;
 476         uint8_t                 txpid2g[4];     /* 2GHz TX power index */
 477         uint8_t                 txpid5gl[4];    /* 4.9 - 5.1GHz TX power index */
 478         uint8_t                 txpid5g[4];     /* 5.1 - 5.5GHz TX power index */
 479         uint8_t                 txpid5gh[4];    /* 5.5 - 5.9GHz TX power index */
 480         uint8_t                 rssisav2g;
 481         uint8_t                 rssismc2g;
 482         uint8_t                 rssismf2g;
 483         uint8_t                 bxa2g;
 484         uint8_t                 rssisav5g;
 485         uint8_t                 rssismc5g;
 486         uint8_t                 rssismf5g;
 487         uint8_t                 bxa5g;
 488         uint16_t                cck2gpo;
 489         uint32_t                ofdm2gpo;
 490         uint32_t                ofdm5glpo;
 491         uint32_t                ofdm5gpo;
 492         uint32_t                ofdm5ghpo;
 493         uint16_t                bf_lo;          /* boardflags */
 494         uint16_t                bf_hi;          /* boardflags */
 495         uint16_t                bf2_lo;
 496         uint16_t                bf2_hi;
 497
 498         struct siba_sprom_core_pwr_info core_pwr_info[4];
 499
 500         struct {
 501                 struct {
 502                         int8_t a0, a1, a2, a3;
 503                 } ghz24;
 504                 struct {
 505                         int8_t a0, a1, a2, a3;
 506                 } ghz5;
 507         } again;        /* antenna gain */
 508
 509         struct {
 510                 struct {
 511                         uint8_t tssipos, extpa_gain, pdet_range, tr_iso;
 512                         uint8_t antswlut;
 513                 } ghz2;
 514                 struct {
 515                         uint8_t tssipos, extpa_gain, pdet_range, tr_iso;
 516                         uint8_t antswlut;
 517                 } ghz5;
 518         } fem;
 519
 520         uint16_t mcs2gpo[8];
 521         uint16_t mcs5gpo[8];
 522         uint16_t mcs5glpo[8];
 523         uint16_t mcs5ghpo[8];
 524
 525         uint16_t cddpo;
 526         uint16_t stbcpo;
 527 };
 528
 529 #define SIBA_LDO_PAREF                  0
 530 #define SIBA_LDO_VOLT1                  1
 531 #define SIBA_LDO_VOLT2                  2
 532 #define SIBA_LDO_VOLT3                  3
 533
 534 struct siba_cc_pmu {
 535         uint8_t                         rev;    /* PMU rev */
 536         uint32_t                        freq;   /* crystal freq in kHz */
 537 };
 538
 539 struct siba_cc {
 540         struct siba_dev_softc           *scc_dev;
 541         uint32_t                        scc_caps;
 542         struct siba_cc_pmu              scc_pmu;
 543         uint16_t                        scc_powerup_delay;
 544 };
 545
 546 struct siba_pci {
 547         struct siba_dev_softc           *spc_dev;
 548         uint8_t                         spc_inited;
 549         uint8_t                         spc_hostmode;
 550 };
 551
 552 struct siba_bus_ops {
 553         uint16_t                (*read_2)(struct siba_dev_softc *,
 554                                     uint16_t);
 555         uint32_t                (*read_4)(struct siba_dev_softc *,
 556                                     uint16_t);
 557         void                    (*write_2)(struct siba_dev_softc *,
 558                                     uint16_t, uint16_t);
 559         void                    (*write_4)(struct siba_dev_softc *,
 560                                     uint16_t, uint32_t);
 561         void                    (*read_multi_1)(struct siba_dev_softc *,
 562                                     void *, size_t, uint16_t);
 563         void                    (*read_multi_2)(struct siba_dev_softc *,
 564                                     void *, size_t, uint16_t);
 565         void                    (*read_multi_4)(struct siba_dev_softc *,
 566                                     void *, size_t, uint16_t);
 567         void                    (*write_multi_1)(struct siba_dev_softc *,
 568                                     const void *, size_t, uint16_t);
 569         void                    (*write_multi_2)(struct siba_dev_softc *,
 570                                     const void *, size_t, uint16_t);
 571         void                    (*write_multi_4)(struct siba_dev_softc *,
 572                                     const void *, size_t, uint16_t);
 573 };
 574
 575 struct siba_dev_softc {
 576         struct siba_softc               *sd_bus;
 577         struct siba_devid               sd_id;
 578         const struct siba_bus_ops       *sd_ops;
 579
 580         uint8_t                         sd_coreidx;
 581 };
 582
 583 struct siba_devinfo {
 584         struct resource_list             sdi_rl;
 585         /*devhandle_t                    sdi_devhandle; XXX*/
 586         /*struct rman sdi_intr_rman;*/
 587
 588         /* Accessors are needed for ivars below. */
 589         uint16_t                         sdi_vid;
 590         uint16_t                         sdi_devid;
 591         uint8_t                          sdi_rev;
 592         uint8_t                          sdi_idx;       /* core index on bus */
 593         uint8_t                          sdi_irq;       /* TODO */
 594 };
 595
 596 struct siba_softc {
 597         /*
 598          * common variables which used for siba(4) bus and siba_bwn bridge.
 599          */
 600         device_t                        siba_dev;       /* Device ID */
 601         struct resource                 *siba_mem_res;
 602         bus_space_tag_t                 siba_mem_bt;
 603         bus_space_handle_t              siba_mem_bh;
 604         bus_addr_t                      siba_maddr;
 605         bus_size_t                      siba_msize;
 606         uint8_t                         siba_ncores;
 607         uint32_t                        siba_debug;
 608
 609         /*
 610          * the following variables are only used for siba_bwn bridge.
 611          */
 612
 613         enum siba_type                  siba_type;
 614         int                             siba_invalid;
 615
 616         struct siba_dev_softc           *siba_curdev;   /* only for PCI */
 617         struct siba_dev_softc           siba_devs[SIBA_MAX_CORES];
 618         int                             siba_ndevs;
 619
 620         uint16_t                        siba_pci_vid;
 621         uint16_t                        siba_pci_did;
 622         uint16_t                        siba_pci_subvid;
 623         uint16_t                        siba_pci_subdid;
 624         uint8_t                         siba_pci_revid;
 625         int                             siba_mem_rid;
 626
 627         uint16_t                        siba_chipid;    /* for CORE 0 */
 628         uint16_t                        siba_chiprev;
 629         uint8_t                         siba_chippkg;
 630
 631         struct siba_cc                  siba_cc;                /* ChipCommon */
 632         struct siba_pci                 siba_pci;       /* PCI-core */
 633         const struct siba_bus_ops       *siba_ops;
 634
 635         struct siba_sprom               siba_sprom;     /* SPROM */
 636         uint16_t                        siba_spromsize; /* in word size */
 637 };
 638
 639 void            siba_powerup(device_t, int);
 640 int             siba_powerdown(device_t);
 641 uint16_t        siba_read_2(device_t, uint16_t);
 642 void            siba_write_2(device_t, uint16_t, uint16_t);
 643 uint32_t        siba_read_4(device_t, uint16_t);
 644 void            siba_write_4(device_t, uint16_t, uint32_t);
 645 void            siba_dev_up(device_t, uint32_t);
 646 void            siba_dev_down(device_t, uint32_t);
 647 int             siba_dev_isup(device_t);
 648 void            siba_pcicore_intr(device_t);
 649 uint32_t        siba_dma_translation(device_t);
 650 void            siba_read_multi_1(device_t, void *, size_t, uint16_t);
 651 void            siba_read_multi_2(device_t, void *, size_t, uint16_t);
 652 void            siba_read_multi_4(device_t, void *, size_t, uint16_t);
 653 void            siba_write_multi_1(device_t, const void *, size_t, uint16_t);
 654 void            siba_write_multi_2(device_t, const void *, size_t, uint16_t);
 655 void            siba_write_multi_4(device_t, const void *, size_t, uint16_t);
 656 void            siba_barrier(device_t, int);
 657 void            siba_cc_pmu_set_ldovolt(device_t, int, uint32_t);
 658 void            siba_cc_pmu_set_ldoparef(device_t, uint8_t);
 659 void            siba_gpio_set(device_t, uint32_t);
 660 uint32_t        siba_gpio_get(device_t);
 661 void            siba_fix_imcfglobug(device_t);
 662 int             siba_sprom_get_core_power_info(device_t, int,
 663                     struct siba_sprom_core_pwr_info *);
 664 int             siba_sprom_get_mcs2gpo(device_t, uint16_t *);
 665 int             siba_sprom_get_mcs5glpo(device_t, uint16_t *);
 666 int             siba_sprom_get_mcs5gpo(device_t, uint16_t *);
 667 int             siba_sprom_get_mcs5ghpo(device_t, uint16_t *);
 668 void            siba_pmu_spuravoid_pllupdate(device_t, int);
 669 void            siba_cc_set32(device_t dev, uint32_t, uint32_t);
 670 void            siba_cc_mask32(device_t dev, uint32_t, uint32_t);
 671 uint32_t        siba_cc_read32(device_t dev, uint32_t);
 672 void            siba_cc_write32(device_t dev, uint32_t, uint32_t);
 673
 674 #endif /* _SIBA_SIBAVAR_H_ */