2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
30 * from: i386/isa sio.c,v 1.234
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include "opt_comconsole.h"
37 #include "opt_compat.h"
43 * Serial driver, based on 386BSD-0.1 com driver.
44 * Mostly rewritten to use pseudo-DMA.
45 * Works for National Semiconductor NS8250-NS16550AF UARTs.
46 * COM driver, based on HP dca driver.
48 * Changes for PC Card integration:
49 * - Added PC Card driver table and handlers
51 #include <sys/param.h>
52 #include <sys/systm.h>
55 #include <sys/fcntl.h>
56 #include <sys/interrupt.h>
58 #include <sys/kernel.h>
59 #include <sys/limits.h>
61 #include <sys/malloc.h>
62 #include <sys/module.h>
63 #include <sys/mutex.h>
65 #include <sys/reboot.h>
66 #include <sys/serial.h>
67 #include <sys/sysctl.h>
68 #include <sys/syslog.h>
70 #include <machine/bus.h>
72 #include <sys/timepps.h>
76 #include <isa/isavar.h>
78 #include <machine/resource.h>
80 #include <dev/sio/sioreg.h>
81 #include <dev/sio/siovar.h>
84 #include <dev/ic/esp.h>
86 #include <dev/ic/ns16550.h>
88 #define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
91 /* checks in flags for multiport and which is multiport "master chip"
94 #define COM_ISMULTIPORT(flags) ((flags) & 0x01)
95 #define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
96 #define COM_NOTAST4(flags) ((flags) & 0x04)
98 #define COM_ISMULTIPORT(flags) (0)
99 #endif /* COM_MULTIPORT */
101 #define COM_C_IIR_TXRDYBUG 0x80000
102 #define COM_CONSOLE(flags) ((flags) & 0x10)
103 #define COM_DEBUGGER(flags) ((flags) & 0x80)
104 #define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
105 #define COM_FORCECONSOLE(flags) ((flags) & 0x20)
106 #define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
107 #define COM_LLCONSOLE(flags) ((flags) & 0x40)
108 #define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
109 #define COM_NOFIFO(flags) ((flags) & 0x02)
110 #define COM_NOPROBE(flags) ((flags) & 0x40000)
111 #define COM_NOSCR(flags) ((flags) & 0x100000)
112 #define COM_PPSCTS(flags) ((flags) & 0x10000)
113 #define COM_ST16650A(flags) ((flags) & 0x20000)
114 #define COM_TI16754(flags) ((flags) & 0x200000)
116 #define sio_getreg(com, off) \
117 (bus_space_read_1((com)->bst, (com)->bsh, (off)))
118 #define sio_setreg(com, off, value) \
119 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
123 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
124 * than the other bits so that they can be tested as a group without masking
127 * The following com and tty flags correspond closely:
128 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
130 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
131 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
132 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
133 * TS_FLUSH is not used.
134 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
135 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
137 #define CS_BUSY 0x80 /* output in progress */
138 #define CS_TTGO 0x40 /* output not stopped by XOFF */
139 #define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
140 #define CS_CHECKMSR 1 /* check of MSR scheduled */
141 #define CS_CTS_OFLOW 2 /* use CTS output flow control */
142 #define CS_ODONE 4 /* output completed */
143 #define CS_RTS_IFLOW 8 /* use RTS input flow control */
144 #define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
146 static char const * const error_desc[] = {
149 #define CE_INTERRUPT_BUF_OVERFLOW 1
150 "interrupt-level buffer overflow",
151 #define CE_TTY_BUF_OVERFLOW 2
152 "tty-level buffer overflow",
156 #define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
158 /* types. XXX - should be elsewhere */
159 typedef u_int Port_t; /* hardware port */
160 typedef u_char bool_t; /* boolean */
162 /* queue of linear buffers */
164 u_char *l_head; /* next char to process */
165 u_char *l_tail; /* one past the last char to process */
166 struct lbq *l_next; /* next in queue */
167 bool_t l_queued; /* nonzero if queued */
170 /* com device structure */
172 u_char state; /* miscellaneous flag bits */
173 u_char cfcr_image; /* copy of value written to CFCR */
175 bool_t esp; /* is this unit a hayes esp board? */
177 u_char extra_state; /* more flag bits, separate for order trick */
178 u_char fifo_image; /* copy of value written to FIFO */
179 bool_t hasfifo; /* nonzero for 16550 UARTs */
180 bool_t loses_outints; /* nonzero if device loses output interrupts */
181 u_char mcr_image; /* copy of value written to MCR */
183 bool_t multiport; /* is this unit part of a multiport device? */
184 #endif /* COM_MULTIPORT */
185 bool_t no_irq; /* nonzero if irq is not attached */
186 bool_t gone; /* hardware disappeared */
187 bool_t poll; /* nonzero if polling is required */
188 bool_t poll_output; /* nonzero if polling for output is required */
189 bool_t st16650a; /* nonzero if Startech 16650A compatible */
190 int unit; /* unit number */
191 u_int flags; /* copy of device flags */
195 * The high level of the driver never reads status registers directly
196 * because there would be too many side effects to handle conveniently.
197 * Instead, it reads copies of the registers stored here by the
200 u_char last_modem_status; /* last MSR read by intr handler */
201 u_char prev_modem_status; /* last MSR handled by high level */
203 u_char *ibuf; /* start of input buffer */
204 u_char *ibufend; /* end of input buffer */
205 u_char *ibufold; /* old input buffer, to be freed */
206 u_char *ihighwater; /* threshold in input buffer */
207 u_char *iptr; /* next free spot in input buffer */
208 int ibufsize; /* size of ibuf (not include error bytes) */
209 int ierroff; /* offset of error bytes in ibuf */
211 struct lbq obufq; /* head of queue of output buffers */
212 struct lbq obufs[2]; /* output buffers */
215 bus_space_handle_t bsh;
217 Port_t data_port; /* i/o ports */
223 Port_t modem_ctl_port;
224 Port_t line_status_port;
225 Port_t modem_status_port;
227 struct tty *tp; /* cross reference */
229 struct pps_state pps;
231 #ifdef ALT_BREAK_TO_DEBUGGER
235 u_long bytes_in; /* statistics */
237 u_int delta_error_counts[CE_NTYPES];
238 u_long error_counts[CE_NTYPES];
242 struct resource *irqres;
243 struct resource *ioportres;
248 * Data area for output buffers. Someday we should build the output
249 * buffer queue without copying data.
256 static int espattach(struct com_s *com, Port_t esp_port);
259 static void combreak(struct tty *tp, int sig);
260 static timeout_t siobusycheck;
261 static u_int siodivisor(u_long rclk, speed_t speed);
262 static void comclose(struct tty *tp);
263 static int comopen(struct tty *tp, struct cdev *dev);
264 static void sioinput(struct com_s *com);
265 static void siointr1(struct com_s *com);
266 static void siointr(void *arg);
267 static int commodem(struct tty *tp, int sigon, int sigoff);
268 static int comparam(struct tty *tp, struct termios *t);
269 static void siopoll(void *);
270 static void siosettimeout(void);
271 static int siosetwater(struct com_s *com, speed_t speed);
272 static void comstart(struct tty *tp);
273 static void comstop(struct tty *tp, int rw);
274 static timeout_t comwakeup;
276 char sio_driver_name[] = "sio";
277 static struct mtx sio_lock;
278 static int sio_inited;
280 /* table and macro for fast conversion from a unit number to its com struct */
281 devclass_t sio_devclass;
282 #define com_addr(unit) ((struct com_s *) \
283 devclass_get_softc(sio_devclass, unit)) /* XXX */
286 static volatile speed_t comdefaultrate = CONSPEED;
287 static u_long comdefaultrclk = DEFAULT_RCLK;
288 SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, "");
289 static speed_t gdbdefaultrate = GDBSPEED;
290 SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW,
291 &gdbdefaultrate, GDBSPEED, "");
292 static u_int com_events; /* input chars + weighted output completions */
293 static Port_t siocniobase;
294 static int siocnunit = -1;
295 static void *sio_slow_ih;
296 static void *sio_fast_ih;
297 static int sio_timeout;
298 static int sio_timeouts_until_log;
299 static struct callout_handle sio_timeout_handle
300 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
301 static int sio_numunits;
304 static Port_t siogdbiobase = 0;
308 /* XXX configure this properly. */
309 /* XXX quite broken for new-bus. */
310 static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
311 static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
315 * handle sysctl read/write requests for console speed
317 * In addition to setting comdefaultrate for I/O through /dev/console,
318 * also set the initial and lock values for the /dev/ttyXX device
319 * if there is one associated with the console. Finally, if the /dev/tty
320 * device has already been open, change the speed on the open running port
325 sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS)
332 newspeed = comdefaultrate;
334 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
335 if (error || !req->newptr)
338 comdefaultrate = newspeed;
340 if (comconsole < 0) /* serial console not selected? */
343 com = com_addr(comconsole);
352 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
353 * (note, the lock rates really are boolean -- if non-zero, disallow
356 tp->t_init_in.c_ispeed = tp->t_init_in.c_ospeed =
357 tp->t_lock_in.c_ispeed = tp->t_lock_in.c_ospeed =
358 tp->t_init_out.c_ispeed = tp->t_init_out.c_ospeed =
359 tp->t_lock_out.c_ispeed = tp->t_lock_out.c_ospeed = comdefaultrate;
361 if (tp->t_state & TS_ISOPEN) {
362 tp->t_termios.c_ispeed =
363 tp->t_termios.c_ospeed = comdefaultrate;
365 error = comparam(tp, &tp->t_termios);
371 SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
372 0, 0, sysctl_machdep_comdefaultrate, "I", "");
373 /* TUNABLE_INT("machdep.conspeed", &comdefaultrate); */
375 #define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit))
376 #define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit))
379 * Unload the driver and clear the table.
380 * XXX this is mostly wrong.
382 * This is usually called when the card is ejected, but
383 * can be caused by a kldunload of a controller driver.
384 * The idea is to reset the driver's view of the device
385 * and ensure that any driver entry points such as
386 * read and write do not hang.
389 siodetach(device_t dev)
393 com = (struct com_s *) device_get_softc(dev);
395 device_printf(dev, "NULL com in siounload\n");
402 bus_teardown_intr(dev, com->irqres, com->cookie);
403 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
406 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid,
408 if (com->ibuf != NULL)
409 free(com->ibuf, M_DEVBUF);
411 device_set_softc(dev, NULL);
417 sioprobe(dev, xrid, rclk, noprobe)
424 static bool_t already_init;
433 intrmask_t irqmap[4];
438 u_int flags = device_get_flags(dev);
440 struct resource *port;
443 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
444 0, ~0, IO_COMSIZE, RF_ACTIVE);
448 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO);
450 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
453 device_set_softc(dev, com);
454 com->bst = rman_get_bustag(port);
455 com->bsh = rman_get_bushandle(port);
460 while (sio_inited != 2)
461 if (atomic_cmpset_int(&sio_inited, 0, 1)) {
462 mtx_init(&sio_lock, sio_driver_name, NULL,
464 MTX_SPIN | MTX_QUIET : MTX_SPIN);
465 atomic_store_rel_int(&sio_inited, 2);
470 * XXX this is broken - when we are first called, there are no
471 * previously configured IO ports. We could hard code
472 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
473 * This code has been doing nothing since the conversion since
474 * "count" is zero the first time around.
478 * Turn off MCR_IENABLE for all likely serial ports. An unused
479 * port with its MCR_IENABLE gate open will inhibit interrupts
480 * from any used port that shares the interrupt vector.
481 * XXX the gate enable is elsewhere for some multiports.
484 int count, i, xioport;
486 devclass_get_devices(sio_devclass, &devs, &count);
487 for (i = 0; i < count; i++) {
489 if (device_is_enabled(xdev) &&
490 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
492 outb(xioport + com_mcr, 0);
499 if (COM_LLCONSOLE(flags)) {
500 printf("sio%d: reserved for low-level i/o\n",
501 device_get_unit(dev));
502 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
503 device_set_softc(dev, NULL);
509 * If the device is on a multiport card and has an AST/4
510 * compatible interrupt control register, initialize this
511 * register and prepare to leave MCR_IENABLE clear in the mcr.
512 * Otherwise, prepare to set MCR_IENABLE in the mcr.
513 * Point idev to the device struct giving the correct id_irq.
514 * This is the struct for the master device if there is one.
517 mcr_image = MCR_IENABLE;
519 if (COM_ISMULTIPORT(flags)) {
523 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
525 printf("sio%d: master device %d not configured\n",
526 device_get_unit(dev), COM_MPMASTER(flags));
529 if (!COM_NOTAST4(flags)) {
530 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
533 if (bus_get_resource(idev, SYS_RES_IRQ, 0,
535 outb(xiobase + com_scr, 0x80);
537 outb(xiobase + com_scr, 0);
542 #endif /* COM_MULTIPORT */
543 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
546 bzero(failures, sizeof failures);
547 iobase = rman_get_start(port);
550 * We don't want to get actual interrupts, just masked ones.
551 * Interrupts from this line should already be masked in the ICU,
552 * but mask them in the processor as well in case there are some
553 * (misconfigured) shared interrupts.
555 mtx_lock_spin(&sio_lock);
559 * For the TI16754 chips, set prescaler to 1 (4 is often the
560 * default after-reset value) as otherwise it's impossible to
561 * get highest baudrates.
563 if (COM_TI16754(flags)) {
566 cfcr = sio_getreg(com, com_cfcr);
567 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
568 efr = sio_getreg(com, com_efr);
569 /* Unlock extended features to turn off prescaler. */
570 sio_setreg(com, com_efr, efr | EFR_EFE);
572 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0);
573 /* Turn off prescaler. */
574 sio_setreg(com, com_mcr,
575 sio_getreg(com, com_mcr) & ~MCR_PRESCALE);
576 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
577 sio_setreg(com, com_efr, efr);
578 sio_setreg(com, com_cfcr, cfcr);
582 * Initialize the speed and the word size and wait long enough to
583 * drain the maximum of 16 bytes of junk in device output queues.
584 * The speed is undefined after a master reset and must be set
585 * before relying on anything related to output. There may be
586 * junk after a (very fast) soft reboot and (apparently) after
588 * XXX what about the UART bug avoided by waiting in comparam()?
589 * We don't want to to wait long enough to drain at 2 bps.
591 if (iobase == siocniobase)
592 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
594 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
595 divisor = siodivisor(rclk, SIO_TEST_SPEED);
596 sio_setreg(com, com_dlbl, divisor & 0xff);
597 sio_setreg(com, com_dlbh, divisor >> 8);
598 sio_setreg(com, com_cfcr, CFCR_8BITS);
599 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
603 * Enable the interrupt gate and disable device interupts. This
604 * should leave the device driving the interrupt line low and
605 * guarantee an edge trigger if an interrupt can be generated.
608 sio_setreg(com, com_mcr, mcr_image);
609 sio_setreg(com, com_ier, 0);
610 DELAY(1000); /* XXX */
611 irqmap[0] = isa_irq_pending();
614 * Attempt to set loopback mode so that we can send a null byte
615 * without annoying any external device.
618 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
621 * Attempt to generate an output interrupt. On 8250's, setting
622 * IER_ETXRDY generates an interrupt independent of the current
623 * setting and independent of whether the THR is empty. On 16450's,
624 * setting IER_ETXRDY generates an interrupt independent of the
625 * current setting. On 16550A's, setting IER_ETXRDY only
626 * generates an interrupt when IER_ETXRDY is not already set.
628 sio_setreg(com, com_ier, IER_ETXRDY);
631 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
632 * an interrupt. They'd better generate one for actually doing
633 * output. Loopback may be broken on the same incompatibles but
634 * it's unlikely to do more than allow the null byte out.
636 sio_setreg(com, com_data, 0);
637 if (iobase == siocniobase)
638 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10));
640 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
643 * Turn off loopback mode so that the interrupt gate works again
644 * (MCR_IENABLE was hidden). This should leave the device driving
645 * an interrupt line high. It doesn't matter if the interrupt
646 * line oscillates while we are not looking at it, since interrupts
650 sio_setreg(com, com_mcr, mcr_image);
653 * It seems my Xircom CBEM56G Cardbus modem wants to be reset
654 * to 8 bits *again*, or else probe test 0 will fail.
655 * gwk@sgi.com, 4/19/2001
657 sio_setreg(com, com_cfcr, CFCR_8BITS);
660 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug",
661 * so we probe for a buggy IIR_TXRDY implementation even in the
662 * noprobe case. We don't probe for it in the !noprobe case because
663 * noprobe is always set for PCMCIA cards and the problem is not
664 * known to affect any other cards.
667 /* Read IIR a few times. */
668 for (fn = 0; fn < 2; fn ++) {
670 failures[6] = sio_getreg(com, com_iir);
673 /* IIR_TXRDY should be clear. Is it? */
675 if (failures[6] & IIR_TXRDY) {
677 * No. We seem to have the bug. Does our fix for
680 sio_setreg(com, com_ier, 0);
681 if (sio_getreg(com, com_iir) & IIR_NOPEND) {
682 /* Yes. We discovered the TXRDY bug! */
683 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
685 /* No. Just fail. XXX */
687 sio_setreg(com, com_mcr, 0);
691 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
693 sio_setreg(com, com_ier, 0);
694 sio_setreg(com, com_cfcr, CFCR_8BITS);
695 mtx_unlock_spin(&sio_lock);
696 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
697 if (iobase == siocniobase)
700 device_set_softc(dev, NULL);
708 * o the CFCR, IER and MCR in UART hold the values written to them
709 * (the values happen to be all distinct - this is good for
710 * avoiding false positive tests from bus echoes).
711 * o an output interrupt is generated and its vector is correct.
712 * o the interrupt goes away when the IIR in the UART is read.
715 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
716 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
717 failures[2] = sio_getreg(com, com_mcr) - mcr_image;
718 DELAY(10000); /* Some internal modems need this time */
719 irqmap[1] = isa_irq_pending();
720 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
721 DELAY(1000); /* XXX */
722 irqmap[2] = isa_irq_pending();
723 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
726 * Turn off all device interrupts and check that they go off properly.
727 * Leave MCR_IENABLE alone. For ports without a master port, it gates
728 * the OUT2 output of the UART to
729 * the ICU input. Closing the gate would give a floating ICU input
730 * (unless there is another device driving it) and spurious interrupts.
731 * (On the system that this was first tested on, the input floats high
732 * and gives a (masked) interrupt as soon as the gate is closed.)
734 sio_setreg(com, com_ier, 0);
735 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
736 failures[7] = sio_getreg(com, com_ier);
737 DELAY(1000); /* XXX */
738 irqmap[3] = isa_irq_pending();
739 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
741 mtx_unlock_spin(&sio_lock);
743 irqs = irqmap[1] & ~irqmap[0];
744 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
745 ((1 << xirq) & irqs) == 0) {
747 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
748 device_get_unit(dev), xirq, irqs);
750 "sio%d: port may not be enabled\n",
751 device_get_unit(dev));
754 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
755 device_get_unit(dev),
756 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
759 for (fn = 0; fn < sizeof failures; ++fn)
761 sio_setreg(com, com_mcr, 0);
764 printf("sio%d: probe failed test(s):",
765 device_get_unit(dev));
766 for (fn = 0; fn < sizeof failures; ++fn)
773 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
774 if (iobase == siocniobase)
777 device_set_softc(dev, NULL);
785 espattach(com, esp_port)
793 * Check the ESP-specific I/O port to see if we're an ESP
794 * card. If not, return failure immediately.
796 if ((inb(esp_port) & 0xf3) == 0) {
797 printf(" port 0x%x is not an ESP board?\n", esp_port);
802 * We've got something that claims to be a Hayes ESP card.
806 /* Get the dip-switch configuration */
807 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
808 dips = inb(esp_port + ESP_STATUS1);
811 * Bits 0,1 of dips say which COM port we are.
813 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
816 printf(" esp_port has com %d\n", dips & 0x03);
821 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
823 outb(esp_port + ESP_CMD1, ESP_GETTEST);
824 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
825 val = inb(esp_port + ESP_STATUS2);
826 if ((val & 0x70) < 0x20) {
827 printf("-old (%o)", val & 0x70);
832 * Check for ability to emulate 16550: bit 7 == 1
834 if ((dips & 0x80) == 0) {
840 * Okay, we seem to be a Hayes ESP card. Whee.
843 com->esp_port = esp_port;
849 sioattach(dev, xrid, rclk)
862 struct resource *port;
868 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
869 0, ~0, IO_COMSIZE, RF_ACTIVE);
873 iobase = rman_get_start(port);
874 unit = device_get_unit(dev);
875 com = device_get_softc(dev);
876 flags = device_get_flags(dev);
878 if (unit >= sio_numunits)
879 sio_numunits = unit + 1;
881 * sioprobe() has initialized the device registers as follows:
882 * o cfcr = CFCR_8BITS.
883 * It is most important that CFCR_DLAB is off, so that the
884 * data port is not hidden when we enable interrupts.
886 * Interrupts are only enabled when the line is open.
887 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
888 * interrupt control register or the config specifies no irq.
889 * Keeping MCR_DTR and MCR_RTS off might stop the external
890 * device from sending before we are ready.
892 bzero(com, sizeof *com);
894 com->ioportres = port;
895 com->ioportrid = rid;
896 com->bst = rman_get_bustag(port);
897 com->bsh = rman_get_bushandle(port);
898 com->cfcr_image = CFCR_8BITS;
899 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
900 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
901 com->tx_fifo_size = 1;
902 com->obufs[0].l_head = com->obuf1;
903 com->obufs[1].l_head = com->obuf2;
905 com->data_port = iobase + com_data;
906 com->int_ctl_port = iobase + com_ier;
907 com->int_id_port = iobase + com_iir;
908 com->modem_ctl_port = iobase + com_mcr;
909 com->mcr_image = inb(com->modem_ctl_port);
910 com->line_status_port = iobase + com_lsr;
911 com->modem_status_port = iobase + com_msr;
913 tp = com->tp = ttyalloc();
914 tp->t_oproc = comstart;
915 tp->t_param = comparam;
916 tp->t_stop = comstop;
917 tp->t_modem = commodem;
918 tp->t_break = combreak;
919 tp->t_close = comclose;
920 tp->t_open = comopen;
927 if (unit == comconsole)
928 ttyconsolemode(tp, comdefaultrate);
929 error = siosetwater(com, tp->t_init_in.c_ispeed);
930 mtx_unlock_spin(&sio_lock);
933 * Leave i/o resources allocated if this is a `cn'-level
934 * console, so that other devices can't snarf them.
936 if (iobase != siocniobase)
937 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
941 /* attempt to determine UART type */
942 printf("sio%d: type", unit);
944 if (!COM_ISMULTIPORT(flags) &&
945 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) {
950 scr = sio_getreg(com, com_scr);
951 sio_setreg(com, com_scr, 0xa5);
952 scr1 = sio_getreg(com, com_scr);
953 sio_setreg(com, com_scr, 0x5a);
954 scr2 = sio_getreg(com, com_scr);
955 sio_setreg(com, com_scr, scr);
956 if (scr1 != 0xa5 || scr2 != 0x5a) {
957 printf(" 8250 or not responding");
958 goto determined_type;
961 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
963 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
974 if (COM_NOFIFO(flags)) {
975 printf(" 16550A fifo disabled");
979 if (COM_ST16650A(flags)) {
981 com->st16650a = TRUE;
982 com->tx_fifo_size = 32;
985 if (COM_TI16754(flags)) {
987 com->tx_fifo_size = 64;
992 for (espp = likely_esp_ports; *espp != 0; espp++)
993 if (espattach(com, *espp)) {
994 com->tx_fifo_size = 1024;
1000 com->tx_fifo_size = COM_FIFOSIZE(flags);
1001 if (com->tx_fifo_size == 0)
1002 com->tx_fifo_size = 16;
1004 printf(" lookalike with %u bytes FIFO",
1011 * Set 16550 compatibility mode.
1012 * We don't use the ESP_MODE_SCALE bit to increase the
1013 * fifo trigger levels because we can't handle large
1015 * XXX flow control should be set in comparam(), not here.
1017 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1018 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1020 /* Set RTS/CTS flow control. */
1021 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1022 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1023 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1025 /* Set flow-control levels. */
1026 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1027 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1028 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1029 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1030 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1032 #endif /* COM_ESP */
1033 sio_setreg(com, com_fifo, 0);
1036 #ifdef COM_MULTIPORT
1037 if (COM_ISMULTIPORT(flags)) {
1040 com->multiport = TRUE;
1041 printf(" (multiport");
1042 if (unit == COM_MPMASTER(flags))
1045 masterdev = devclass_get_device(sio_devclass,
1046 COM_MPMASTER(flags));
1047 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
1048 SYS_RES_IRQ, 0, NULL, NULL) != 0);
1050 #endif /* COM_MULTIPORT */
1051 if (unit == comconsole)
1052 printf(", console");
1053 if (COM_IIR_TXRDYBUG(flags))
1054 printf(" with a buggy IIR_TXRDY implementation");
1057 if (sio_fast_ih == NULL) {
1058 swi_add(&tty_ithd, "sio", siopoll, NULL, SWI_TTY, 0,
1060 swi_add(&clk_ithd, "sio", siopoll, NULL, SWI_CLOCK, 0,
1065 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1066 tp->t_pps = &com->pps;
1068 if (COM_PPSCTS(flags))
1069 com->pps_bit = MSR_CTS;
1071 com->pps_bit = MSR_DCD;
1072 pps_init(&com->pps);
1075 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
1077 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
1078 INTR_TYPE_TTY | INTR_FAST,
1079 siointr, com, &com->cookie);
1081 ret = BUS_SETUP_INTR(device_get_parent(dev), dev,
1082 com->irqres, INTR_TYPE_TTY,
1083 siointr, com, &com->cookie);
1085 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n");
1088 device_printf(dev, "could not activate interrupt\n");
1089 #if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \
1090 defined(ALT_BREAK_TO_DEBUGGER))
1092 * Enable interrupts for early break-to-debugger support
1095 if (ret == 0 && unit == comconsole)
1096 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS |
1101 /* We're ready, open the doors... */
1102 ttycreate(tp, TS_CALLOUT, "d%r", unit);
1108 comopen(struct tty *tp, struct cdev *dev)
1114 com->poll = com->no_irq;
1115 com->poll_output = com->loses_outints;
1118 * (Re)enable and drain fifos.
1120 * Certain SMC chips cause problems if the fifos
1121 * are enabled while input is ready. Turn off the
1122 * fifo if necessary to clear the input. We test
1123 * the input ready bit after enabling the fifos
1124 * since we've already enabled them in comparam()
1125 * and to handle races between enabling and fresh
1128 for (i = 0; i < 500; i++) {
1129 sio_setreg(com, com_fifo,
1130 FIFO_RCV_RST | FIFO_XMT_RST
1133 * XXX the delays are for superstitious
1134 * historical reasons. It must be less than
1135 * the character time at the maximum
1136 * supported speed (87 usec at 115200 bps
1137 * 8N1). Otherwise we might loop endlessly
1138 * if data is streaming in. We used to use
1139 * delays of 100. That usually worked
1140 * because DELAY(100) used to usually delay
1141 * for about 85 usec instead of 100.
1144 if (!(inb(com->line_status_port) & LSR_RXRDY))
1146 sio_setreg(com, com_fifo, 0);
1148 (void) inb(com->data_port);
1154 mtx_lock_spin(&sio_lock);
1155 (void) inb(com->line_status_port);
1156 (void) inb(com->data_port);
1157 com->prev_modem_status = com->last_modem_status
1158 = inb(com->modem_status_port);
1159 outb(com->int_ctl_port,
1160 IER_ERXRDY | IER_ERLS | IER_EMSC
1161 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY));
1162 mtx_unlock_spin(&sio_lock);
1164 /* XXX: should be generic ? */
1165 if (com->prev_modem_status & MSR_DCD || ISCALLOUT(dev))
1180 com->poll_output = FALSE;
1181 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1183 #if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \
1184 defined(ALT_BREAK_TO_DEBUGGER))
1186 * Leave interrupts enabled and don't clear DTR if this is the
1187 * console. This allows us to detect break-to-debugger events
1188 * while the console device is closed.
1190 if (com->unit != comconsole)
1193 sio_setreg(com, com_ier, 0);
1194 if (tp->t_cflag & HUPCL
1196 * XXX we will miss any carrier drop between here and the
1197 * next open. Perhaps we should watch DCD even when the
1198 * port is closed; it is not sufficient to check it at
1199 * the next open because it might go up and down while
1200 * we're not watching.
1203 && !(com->prev_modem_status & MSR_DCD)
1204 && !(tp->t_init_in.c_cflag & CLOCAL))
1205 || !(tp->t_state & TS_ISOPEN)) {
1206 (void)commodem(tp, 0, SER_DTR);
1207 ttydtrwaitstart(tp);
1212 * Disable fifos so that they are off after controlled
1213 * reboots. Some BIOSes fail to detect 16550s when the
1214 * fifos are enabled.
1216 sio_setreg(com, com_fifo, 0);
1218 tp->t_actout = FALSE;
1219 wakeup(&tp->t_actout);
1220 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
1232 com = (struct com_s *)chan;
1235 * Clear TS_BUSY if low-level output is complete.
1236 * spl locking is sufficient because siointr1() does not set CS_BUSY.
1237 * If siointr1() clears CS_BUSY after we look at it, then we'll get
1238 * called again. Reading the line status port outside of siointr1()
1239 * is safe because CS_BUSY is clear so there are no output interrupts
1243 if (com->state & CS_BUSY)
1244 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
1245 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
1246 == (LSR_TSRE | LSR_TXRDY)) {
1247 com->tp->t_state &= ~TS_BUSY;
1249 com->extra_state &= ~CSE_BUSYCHECK;
1251 timeout(siobusycheck, com, hz / 100);
1256 siodivisor(rclk, speed)
1266 #if UINT_MAX > (ULONG_MAX - 1) / 8
1267 if (speed > (ULONG_MAX - 1) / 8)
1270 divisor = (rclk / (8UL * speed) + 1) / 2;
1271 if (divisor == 0 || divisor >= 65536)
1273 actual_speed = rclk / (16UL * divisor);
1275 /* 10 times error in percent: */
1276 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2;
1278 /* 3.0% maximum error tolerance: */
1279 if (error < -30 || error > 30)
1286 * Call this function with the sio_lock mutex held. It will return with the
1301 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
1302 com_events -= (com->iptr - com->ibuf);
1303 com->iptr = com->ibuf;
1306 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
1308 * Avoid the grotesquely inefficient lineswitch routine
1309 * (ttyinput) in "raw" mode. It usually takes about 450
1310 * instructions (that's without canonical processing or echo!).
1311 * slinput is reasonably fast (usually 40 instructions plus
1316 * This may look odd, but it is using save-and-enable
1317 * semantics instead of the save-and-disable semantics
1318 * that are used everywhere else.
1320 mtx_unlock_spin(&sio_lock);
1321 incc = com->iptr - buf;
1322 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
1323 && (com->state & CS_RTS_IFLOW
1324 || tp->t_iflag & IXOFF)
1325 && !(tp->t_state & TS_TBLOCK))
1327 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
1328 += b_to_q((char *)buf, incc, &tp->t_rawq);
1332 tp->t_rawcc += incc;
1334 if (tp->t_state & TS_TTSTOP
1335 && (tp->t_iflag & IXANY
1336 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
1337 tp->t_state &= ~TS_TTSTOP;
1338 tp->t_lflag &= ~FLUSHO;
1341 mtx_lock_spin(&sio_lock);
1342 } while (buf < com->iptr);
1346 * This may look odd, but it is using save-and-enable
1347 * semantics instead of the save-and-disable semantics
1348 * that are used everywhere else.
1350 mtx_unlock_spin(&sio_lock);
1351 line_status = buf[com->ierroff];
1354 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
1355 if (line_status & LSR_BI)
1356 recv_data |= TTY_BI;
1357 if (line_status & LSR_FE)
1358 recv_data |= TTY_FE;
1359 if (line_status & LSR_OE)
1360 recv_data |= TTY_OE;
1361 if (line_status & LSR_PE)
1362 recv_data |= TTY_PE;
1364 ttyld_rint(tp, recv_data);
1365 mtx_lock_spin(&sio_lock);
1366 } while (buf < com->iptr);
1368 com_events -= (com->iptr - com->ibuf);
1369 com->iptr = com->ibuf;
1372 * There is now room for another low-level buffer full of input,
1373 * so enable RTS if it is now disabled and there is room in the
1374 * high-level buffer.
1376 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
1377 !(tp->t_state & TS_TBLOCK))
1378 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
1387 #ifndef COM_MULTIPORT
1388 com = (struct com_s *)arg;
1390 mtx_lock_spin(&sio_lock);
1392 mtx_unlock_spin(&sio_lock);
1393 #else /* COM_MULTIPORT */
1394 bool_t possibly_more_intrs;
1398 * Loop until there is no activity on any port. This is necessary
1399 * to get an interrupt edge more than to avoid another interrupt.
1400 * If the IRQ signal is just an OR of the IRQ signals from several
1401 * devices, then the edge from one may be lost because another is
1404 mtx_lock_spin(&sio_lock);
1406 possibly_more_intrs = FALSE;
1407 for (unit = 0; unit < sio_numunits; ++unit) {
1408 com = com_addr(unit);
1411 * would it work here, or be counter-productive?
1415 && (inb(com->int_id_port) & IIR_IMASK)
1418 possibly_more_intrs = TRUE;
1420 /* XXX COM_UNLOCK(); */
1422 } while (possibly_more_intrs);
1423 mtx_unlock_spin(&sio_lock);
1424 #endif /* COM_MULTIPORT */
1427 static struct timespec siots[8];
1429 static int volatile siotsunit = -1;
1432 sysctl_siots(SYSCTL_HANDLER_ARGS)
1439 for (i = 1, tso = siotso; i < tso; i++) {
1440 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) *
1442 (siots[i].tv_nsec - siots[i - 1].tv_nsec);
1443 len = sprintf(buf, "%lld\n", delta);
1444 if (delta >= 110000)
1445 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n",
1446 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1;
1448 buf[len - 1] = '\0';
1449 error = SYSCTL_OUT(req, buf, len);
1457 SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD,
1458 0, 0, sysctl_siots, "A", "sio timestamps");
1467 u_char modem_status;
1471 if (COM_IIR_TXRDYBUG(com->flags)) {
1472 int_ctl = inb(com->int_ctl_port);
1473 int_ctl_new = int_ctl;
1479 while (!com->gone) {
1480 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
1481 modem_status = inb(com->modem_status_port);
1482 if ((modem_status ^ com->last_modem_status) &
1484 pps_capture(&com->pps);
1485 pps_event(&com->pps,
1486 (modem_status & com->pps_bit) ?
1487 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
1490 line_status = inb(com->line_status_port);
1492 /* input event? (check first to help avoid overruns) */
1493 while (line_status & LSR_RCV_MASK) {
1494 /* break/unnattached error bits or real input? */
1495 if (!(line_status & LSR_RXRDY))
1498 recv_data = inb(com->data_port);
1500 #ifdef ALT_BREAK_TO_DEBUGGER
1501 if (com->unit == comconsole &&
1502 kdb_alt_break(recv_data, &com->alt_brk_state) != 0)
1503 kdb_enter("Break sequence on console");
1504 #endif /* ALT_BREAK_TO_DEBUGGER */
1506 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
1508 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
1509 * Otherwise, push the work to a higher level
1510 * (to handle PARMRK) if we're bypassing.
1511 * Otherwise, convert BI/FE and PE+INPCK to 0.
1513 * This makes bypassing work right in the
1514 * usual "raw" case (IGNBRK set, and IGNPAR
1517 * Note: BI together with FE/PE means just BI.
1519 if (line_status & LSR_BI) {
1520 #if defined(KDB) && defined(BREAK_TO_DEBUGGER)
1521 if (com->unit == comconsole) {
1522 kdb_enter("Line break on console");
1527 || com->tp->t_iflag & IGNBRK)
1531 || com->tp->t_iflag & IGNPAR)
1534 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
1535 && (line_status & (LSR_BI | LSR_FE)
1536 || com->tp->t_iflag & INPCK))
1540 if (com->tp != NULL &&
1541 com->tp->t_hotchar != 0 && recv_data == com->tp->t_hotchar)
1542 swi_sched(sio_fast_ih, 0);
1544 if (ioptr >= com->ibufend)
1545 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
1547 if (com->tp != NULL && com->tp->t_do_timestamp)
1548 microtime(&com->tp->t_timestamp);
1550 swi_sched(sio_slow_ih, SWI_DELAY);
1551 #if 0 /* for testing input latency vs efficiency */
1552 if (com->iptr - com->ibuf == 8)
1553 swi_sched(sio_fast_ih, 0);
1555 ioptr[0] = recv_data;
1556 ioptr[com->ierroff] = line_status;
1557 com->iptr = ++ioptr;
1558 if (ioptr == com->ihighwater
1559 && com->state & CS_RTS_IFLOW)
1560 outb(com->modem_ctl_port,
1561 com->mcr_image &= ~MCR_RTS);
1562 if (line_status & LSR_OE)
1563 CE_RECORD(com, CE_OVERRUN);
1566 if (line_status & LSR_TXRDY
1567 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY))
1571 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
1572 * jump from the top of the loop to here
1574 line_status = inb(com->line_status_port) & 0x7F;
1577 /* modem status change? (always check before doing output) */
1578 modem_status = inb(com->modem_status_port);
1579 if (modem_status != com->last_modem_status) {
1581 * Schedule high level to handle DCD changes. Note
1582 * that we don't use the delta bits anywhere. Some
1583 * UARTs mess them up, and it's easy to remember the
1584 * previous bits and calculate the delta.
1586 com->last_modem_status = modem_status;
1587 if (!(com->state & CS_CHECKMSR)) {
1588 com_events += LOTS_OF_EVENTS;
1589 com->state |= CS_CHECKMSR;
1590 swi_sched(sio_fast_ih, 0);
1593 /* handle CTS change immediately for crisp flow ctl */
1594 if (com->state & CS_CTS_OFLOW) {
1595 if (modem_status & MSR_CTS)
1596 com->state |= CS_ODEVREADY;
1598 com->state &= ~CS_ODEVREADY;
1603 /* output queued and everything ready? */
1604 if (line_status & LSR_TXRDY
1605 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
1606 ioptr = com->obufq.l_head;
1607 if (com->tx_fifo_size > 1 && com->unit != siotsunit) {
1610 ocount = com->obufq.l_tail - ioptr;
1611 if (ocount > com->tx_fifo_size)
1612 ocount = com->tx_fifo_size;
1613 com->bytes_out += ocount;
1615 outb(com->data_port, *ioptr++);
1616 while (--ocount != 0);
1618 outb(com->data_port, *ioptr++);
1620 if (com->unit == siotsunit
1621 && siotso < sizeof siots / sizeof siots[0])
1622 nanouptime(&siots[siotso++]);
1624 com->obufq.l_head = ioptr;
1625 if (COM_IIR_TXRDYBUG(com->flags))
1626 int_ctl_new = int_ctl | IER_ETXRDY;
1627 if (ioptr >= com->obufq.l_tail) {
1630 qp = com->obufq.l_next;
1631 qp->l_queued = FALSE;
1634 com->obufq.l_head = qp->l_head;
1635 com->obufq.l_tail = qp->l_tail;
1636 com->obufq.l_next = qp;
1638 /* output just completed */
1639 if (COM_IIR_TXRDYBUG(com->flags))
1640 int_ctl_new = int_ctl
1642 com->state &= ~CS_BUSY;
1644 if (!(com->state & CS_ODONE)) {
1645 com_events += LOTS_OF_EVENTS;
1646 com->state |= CS_ODONE;
1647 /* handle at high level ASAP */
1648 swi_sched(sio_fast_ih, 0);
1651 if (COM_IIR_TXRDYBUG(com->flags)
1652 && int_ctl != int_ctl_new)
1653 outb(com->int_ctl_port, int_ctl_new);
1657 #ifndef COM_MULTIPORT
1658 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
1659 #endif /* COM_MULTIPORT */
1664 /* software interrupt handler for SWI_TTY */
1666 siopoll(void *dummy)
1670 if (com_events == 0)
1673 for (unit = 0; unit < sio_numunits; ++unit) {
1678 com = com_addr(unit);
1682 if (tp == NULL || com->gone) {
1684 * Discard any events related to never-opened or
1685 * going-away devices.
1687 mtx_lock_spin(&sio_lock);
1688 incc = com->iptr - com->ibuf;
1689 com->iptr = com->ibuf;
1690 if (com->state & CS_CHECKMSR) {
1691 incc += LOTS_OF_EVENTS;
1692 com->state &= ~CS_CHECKMSR;
1695 mtx_unlock_spin(&sio_lock);
1698 if (com->iptr != com->ibuf) {
1699 mtx_lock_spin(&sio_lock);
1701 mtx_unlock_spin(&sio_lock);
1703 if (com->state & CS_CHECKMSR) {
1704 u_char delta_modem_status;
1706 mtx_lock_spin(&sio_lock);
1707 delta_modem_status = com->last_modem_status
1708 ^ com->prev_modem_status;
1709 com->prev_modem_status = com->last_modem_status;
1710 com_events -= LOTS_OF_EVENTS;
1711 com->state &= ~CS_CHECKMSR;
1712 mtx_unlock_spin(&sio_lock);
1713 if (delta_modem_status & MSR_DCD)
1715 com->prev_modem_status & MSR_DCD);
1717 if (com->state & CS_ODONE) {
1718 mtx_lock_spin(&sio_lock);
1719 com_events -= LOTS_OF_EVENTS;
1720 com->state &= ~CS_ODONE;
1721 mtx_unlock_spin(&sio_lock);
1722 if (!(com->state & CS_BUSY)
1723 && !(com->extra_state & CSE_BUSYCHECK)) {
1724 timeout(siobusycheck, com, hz / 100);
1725 com->extra_state |= CSE_BUSYCHECK;
1729 if (com_events == 0)
1732 if (com_events >= LOTS_OF_EVENTS)
1746 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
1748 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1762 u_char efr_flowbits;
1769 /* check requested parameters */
1770 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed))
1772 divisor = siodivisor(com->rclk, t->c_ispeed);
1776 /* parameters are OK, convert them to the com struct and the device */
1778 if (t->c_ospeed == 0)
1779 (void)commodem(tp, 0, SER_DTR); /* hang up line */
1781 (void)commodem(tp, SER_DTR, 0);
1783 switch (cflag & CSIZE) {
1797 if (cflag & PARENB) {
1799 if (!(cflag & PARODD))
1807 * Use a fifo trigger level low enough so that the input
1808 * latency from the fifo is less than about 16 msec and
1809 * the total latency is less than about 30 msec. These
1810 * latencies are reasonable for humans. Serial comms
1811 * protocols shouldn't expect anything better since modem
1812 * latencies are larger.
1814 * The fifo trigger level cannot be set at RX_HIGH for high
1815 * speed connections without further work on reducing
1816 * interrupt disablement times in other parts of the system,
1817 * without producing silo overflow errors.
1819 com->fifo_image = com->unit == siotsunit ? 0
1820 : t->c_ispeed <= 4800
1821 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH;
1824 * The Hayes ESP card needs the fifo DMA mode bit set
1825 * in compatibility mode. If not, it will interrupt
1826 * for each character received.
1829 com->fifo_image |= FIFO_DMA_MODE;
1831 sio_setreg(com, com_fifo, com->fifo_image);
1835 * This returns with interrupts disabled so that we can complete
1836 * the speed change atomically. Keeping interrupts disabled is
1837 * especially important while com_data is hidden.
1839 (void) siosetwater(com, t->c_ispeed);
1841 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
1843 * Only set the divisor registers if they would change, since on
1844 * some 16550 incompatibles (UMC8669F), setting them while input
1845 * is arriving loses sync until data stops arriving.
1847 dlbl = divisor & 0xFF;
1848 if (sio_getreg(com, com_dlbl) != dlbl)
1849 sio_setreg(com, com_dlbl, dlbl);
1850 dlbh = divisor >> 8;
1851 if (sio_getreg(com, com_dlbh) != dlbh)
1852 sio_setreg(com, com_dlbh, dlbh);
1856 if (cflag & CRTS_IFLOW) {
1857 com->state |= CS_RTS_IFLOW;
1858 efr_flowbits |= EFR_AUTORTS;
1860 * If CS_RTS_IFLOW just changed from off to on, the change
1861 * needs to be propagated to MCR_RTS. This isn't urgent,
1862 * so do it later by calling comstart() instead of repeating
1863 * a lot of code from comstart() here.
1865 } else if (com->state & CS_RTS_IFLOW) {
1866 com->state &= ~CS_RTS_IFLOW;
1868 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
1869 * on here, since comstart() won't do it later.
1871 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
1875 * Set up state to handle output flow control.
1876 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
1877 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
1879 com->state |= CS_ODEVREADY;
1880 com->state &= ~CS_CTS_OFLOW;
1881 if (cflag & CCTS_OFLOW) {
1882 com->state |= CS_CTS_OFLOW;
1883 efr_flowbits |= EFR_AUTOCTS;
1884 if (!(com->last_modem_status & MSR_CTS))
1885 com->state &= ~CS_ODEVREADY;
1888 if (com->st16650a) {
1889 sio_setreg(com, com_lcr, LCR_EFR_ENABLE);
1890 sio_setreg(com, com_efr,
1891 (sio_getreg(com, com_efr)
1892 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits);
1894 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
1896 /* XXX shouldn't call functions while intrs are disabled. */
1899 mtx_unlock_spin(&sio_lock);
1902 if (com->ibufold != NULL) {
1903 free(com->ibufold, M_DEVBUF);
1904 com->ibufold = NULL;
1910 * This function must be called with the sio_lock mutex released and will
1911 * return with it obtained.
1914 siosetwater(com, speed)
1924 * Make the buffer size large enough to handle a softtty interrupt
1925 * latency of about 2 ticks without loss of throughput or data
1926 * (about 3 ticks if input flow control is not used or not honoured,
1927 * but a bit less for CS5-CS7 modes).
1929 cp4ticks = speed / 10 / hz * 4;
1930 for (ibufsize = 128; ibufsize < cp4ticks;)
1932 if (ibufsize == com->ibufsize) {
1933 mtx_lock_spin(&sio_lock);
1938 * Allocate input buffer. The extra factor of 2 in the size is
1939 * to allow for an error byte for each input byte.
1941 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
1943 mtx_lock_spin(&sio_lock);
1947 /* Initialize non-critical variables. */
1948 com->ibufold = com->ibuf;
1949 com->ibufsize = ibufsize;
1952 tp->t_ififosize = 2 * ibufsize;
1953 tp->t_ispeedwat = (speed_t)-1;
1954 tp->t_ospeedwat = (speed_t)-1;
1958 * Read current input buffer, if any. Continue with interrupts
1961 mtx_lock_spin(&sio_lock);
1962 if (com->iptr != com->ibuf)
1966 * Initialize critical variables, including input buffer watermarks.
1967 * The external device is asked to stop sending when the buffer
1968 * exactly reaches high water, or when the high level requests it.
1969 * The high level is notified immediately (rather than at a later
1970 * clock tick) when this watermark is reached.
1971 * The buffer size is chosen so the watermark should almost never
1973 * The low watermark is invisibly 0 since the buffer is always
1974 * emptied all at once.
1976 com->iptr = com->ibuf = ibuf;
1977 com->ibufend = ibuf + ibufsize;
1978 com->ierroff = ibufsize;
1979 com->ihighwater = ibuf + 3 * ibufsize / 4;
1994 mtx_lock_spin(&sio_lock);
1995 if (tp->t_state & TS_TTSTOP)
1996 com->state &= ~CS_TTGO;
1998 com->state |= CS_TTGO;
1999 if (tp->t_state & TS_TBLOCK) {
2000 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
2001 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
2003 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
2004 && com->state & CS_RTS_IFLOW)
2005 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2007 mtx_unlock_spin(&sio_lock);
2008 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
2013 if (tp->t_outq.c_cc != 0) {
2017 if (!com->obufs[0].l_queued) {
2018 com->obufs[0].l_tail
2019 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
2021 com->obufs[0].l_next = NULL;
2022 com->obufs[0].l_queued = TRUE;
2023 mtx_lock_spin(&sio_lock);
2024 if (com->state & CS_BUSY) {
2025 qp = com->obufq.l_next;
2026 while ((next = qp->l_next) != NULL)
2028 qp->l_next = &com->obufs[0];
2030 com->obufq.l_head = com->obufs[0].l_head;
2031 com->obufq.l_tail = com->obufs[0].l_tail;
2032 com->obufq.l_next = &com->obufs[0];
2033 com->state |= CS_BUSY;
2035 mtx_unlock_spin(&sio_lock);
2037 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
2038 com->obufs[1].l_tail
2039 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
2041 com->obufs[1].l_next = NULL;
2042 com->obufs[1].l_queued = TRUE;
2043 mtx_lock_spin(&sio_lock);
2044 if (com->state & CS_BUSY) {
2045 qp = com->obufq.l_next;
2046 while ((next = qp->l_next) != NULL)
2048 qp->l_next = &com->obufs[1];
2050 com->obufq.l_head = com->obufs[1].l_head;
2051 com->obufq.l_tail = com->obufs[1].l_tail;
2052 com->obufq.l_next = &com->obufs[1];
2053 com->state |= CS_BUSY;
2055 mtx_unlock_spin(&sio_lock);
2057 tp->t_state |= TS_BUSY;
2059 mtx_lock_spin(&sio_lock);
2060 if (com->state >= (CS_BUSY | CS_TTGO))
2061 siointr1(com); /* fake interrupt to start output */
2062 mtx_unlock_spin(&sio_lock);
2075 if (com == NULL || com->gone)
2077 mtx_lock_spin(&sio_lock);
2081 /* XXX avoid h/w bug. */
2084 sio_setreg(com, com_fifo,
2085 FIFO_XMT_RST | com->fifo_image);
2086 com->obufs[0].l_queued = FALSE;
2087 com->obufs[1].l_queued = FALSE;
2088 if (com->state & CS_ODONE)
2089 com_events -= LOTS_OF_EVENTS;
2090 com->state &= ~(CS_ODONE | CS_BUSY);
2091 com->tp->t_state &= ~TS_BUSY;
2096 /* XXX avoid h/w bug. */
2099 sio_setreg(com, com_fifo,
2100 FIFO_RCV_RST | com->fifo_image);
2101 com_events -= (com->iptr - com->ibuf);
2102 com->iptr = com->ibuf;
2104 mtx_unlock_spin(&sio_lock);
2109 commodem(struct tty *tp, int sigon, int sigoff)
2112 int bitand, bitor, msr;
2117 if (sigon != 0 || sigoff != 0) {
2119 if (sigoff & SER_DTR)
2121 if (sigoff & SER_RTS)
2123 if (sigon & SER_DTR)
2125 if (sigon & SER_RTS)
2128 mtx_lock_spin(&sio_lock);
2129 com->mcr_image &= bitand;
2130 com->mcr_image |= bitor;
2131 outb(com->modem_ctl_port, com->mcr_image);
2132 mtx_unlock_spin(&sio_lock);
2136 if (com->mcr_image & MCR_DTR)
2138 if (com->mcr_image & MCR_RTS)
2140 msr = com->prev_modem_status;
2149 if (msr & (MSR_RI | MSR_TERI))
2163 * Set our timeout period to 1 second if no polled devices are open.
2164 * Otherwise set it to max(1/200, 1/hz).
2165 * Enable timeouts iff some device is open.
2167 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2170 for (unit = 0; unit < sio_numunits; ++unit) {
2171 com = com_addr(unit);
2172 if (com != NULL && com->tp != NULL
2173 && com->tp->t_state & TS_ISOPEN && !com->gone) {
2175 if (com->poll || com->poll_output) {
2176 sio_timeout = hz > 200 ? hz / 200 : 1;
2182 sio_timeouts_until_log = hz / sio_timeout;
2183 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
2186 /* Flush error messages, if any. */
2187 sio_timeouts_until_log = 1;
2188 comwakeup((void *)NULL);
2189 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2200 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
2203 * Recover from lost output interrupts.
2204 * Poll any lines that don't use interrupts.
2206 for (unit = 0; unit < sio_numunits; ++unit) {
2207 com = com_addr(unit);
2208 if (com != NULL && !com->gone
2209 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
2210 mtx_lock_spin(&sio_lock);
2212 mtx_unlock_spin(&sio_lock);
2217 * Check for and log errors, but not too often.
2219 if (--sio_timeouts_until_log > 0)
2221 sio_timeouts_until_log = hz / sio_timeout;
2222 for (unit = 0; unit < sio_numunits; ++unit) {
2225 com = com_addr(unit);
2230 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
2234 mtx_lock_spin(&sio_lock);
2235 delta = com->delta_error_counts[errnum];
2236 com->delta_error_counts[errnum] = 0;
2237 mtx_unlock_spin(&sio_lock);
2240 total = com->error_counts[errnum] += delta;
2241 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
2242 unit, delta, error_desc[errnum],
2243 delta == 1 ? "" : "s", total);
2249 * Following are all routines needed for SIO to act as console
2260 * This is a function in order to not replicate "ttyd%d" more
2261 * places than absolutely necessary.
2264 siocnset(struct consdev *cd, int unit)
2268 sprintf(cd->cn_name, "ttyd%d", unit);
2271 static speed_t siocngetspeed(Port_t, u_long rclk);
2272 static void siocnclose(struct siocnstate *sp, Port_t iobase);
2273 static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed);
2274 static void siocntxwait(Port_t iobase);
2276 static cn_probe_t siocnprobe;
2277 static cn_init_t siocninit;
2278 static cn_term_t siocnterm;
2279 static cn_checkc_t siocncheckc;
2280 static cn_getc_t siocngetc;
2281 static cn_putc_t siocnputc;
2283 CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc,
2293 * Wait for any pending transmission to finish. Required to avoid
2294 * the UART lockup bug when the speed is changed, and for normal
2298 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
2299 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
2304 * Read the serial port specified and try to figure out what speed
2305 * it's currently running at. We're assuming the serial port has
2306 * been initialized and is basicly idle. This routine is only intended
2307 * to be run at system startup.
2309 * If the value read from the serial port doesn't make sense, return 0.
2313 siocngetspeed(iobase, rclk)
2322 cfcr = inb(iobase + com_cfcr);
2323 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2325 dlbl = inb(iobase + com_dlbl);
2326 dlbh = inb(iobase + com_dlbh);
2328 outb(iobase + com_cfcr, cfcr);
2330 divisor = dlbh << 8 | dlbl;
2332 /* XXX there should be more sanity checking. */
2335 return (rclk / (16UL * divisor));
2339 siocnopen(sp, iobase, speed)
2340 struct siocnstate *sp;
2349 * Save all the device control registers except the fifo register
2350 * and set our default ones (cs8 -parenb speed=comdefaultrate).
2351 * We can't save the fifo register since it is read-only.
2353 sp->ier = inb(iobase + com_ier);
2354 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
2355 siocntxwait(iobase);
2356 sp->cfcr = inb(iobase + com_cfcr);
2357 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2358 sp->dlbl = inb(iobase + com_dlbl);
2359 sp->dlbh = inb(iobase + com_dlbh);
2361 * Only set the divisor registers if they would change, since on
2362 * some 16550 incompatibles (Startech), setting them clears the
2363 * data input register. This also reduces the effects of the
2366 divisor = siodivisor(comdefaultrclk, speed);
2367 dlbl = divisor & 0xFF;
2368 if (sp->dlbl != dlbl)
2369 outb(iobase + com_dlbl, dlbl);
2370 dlbh = divisor >> 8;
2371 if (sp->dlbh != dlbh)
2372 outb(iobase + com_dlbh, dlbh);
2373 outb(iobase + com_cfcr, CFCR_8BITS);
2374 sp->mcr = inb(iobase + com_mcr);
2376 * We don't want interrupts, but must be careful not to "disable"
2377 * them by clearing the MCR_IENABLE bit, since that might cause
2378 * an interrupt by floating the IRQ line.
2380 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
2384 siocnclose(sp, iobase)
2385 struct siocnstate *sp;
2389 * Restore the device control registers.
2391 siocntxwait(iobase);
2392 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2393 if (sp->dlbl != inb(iobase + com_dlbl))
2394 outb(iobase + com_dlbl, sp->dlbl);
2395 if (sp->dlbh != inb(iobase + com_dlbh))
2396 outb(iobase + com_dlbh, sp->dlbh);
2397 outb(iobase + com_cfcr, sp->cfcr);
2399 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
2401 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
2402 outb(iobase + com_ier, sp->ier);
2413 struct siocnstate sp;
2416 * Find our first enabled console, if any. If it is a high-level
2417 * console device, then initialize it and return successfully.
2418 * If it is a low-level console device, then initialize it and
2419 * return unsuccessfully. It must be initialized in both cases
2420 * for early use by console drivers and debuggers. Initializing
2421 * the hardware is not necessary in all cases, since the i/o
2422 * routines initialize it on the fly, but it is necessary if
2423 * input might arrive while the hardware is switched back to an
2424 * uninitialized state. We can't handle multiple console devices
2425 * yet because our low-level routines don't take a device arg.
2426 * We trust the user to set the console flags properly so that we
2427 * don't need to probe.
2429 cp->cn_pri = CN_DEAD;
2431 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
2434 if (resource_disabled("sio", unit))
2436 if (resource_int_value("sio", unit, "flags", &flags))
2438 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
2442 if (resource_int_value("sio", unit, "port", &port))
2446 if (boothowto & RB_SERIAL) {
2448 siocngetspeed(iobase, comdefaultrclk);
2450 comdefaultrate = boot_speed;
2454 * Initialize the divisor latch. We can't rely on
2455 * siocnopen() to do this the first time, since it
2456 * avoids writing to the latch if the latch appears
2457 * to have the correct value. Also, if we didn't
2458 * just read the speed from the hardware, then we
2459 * need to set the speed in hardware so that
2460 * switching it later is null.
2462 cfcr = inb(iobase + com_cfcr);
2463 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2464 divisor = siodivisor(comdefaultrclk, comdefaultrate);
2465 outb(iobase + com_dlbl, divisor & 0xff);
2466 outb(iobase + com_dlbh, divisor >> 8);
2467 outb(iobase + com_cfcr, cfcr);
2469 siocnopen(&sp, iobase, comdefaultrate);
2472 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
2474 cp->cn_pri = COM_FORCECONSOLE(flags)
2475 || boothowto & RB_SERIAL
2476 ? CN_REMOTE : CN_NORMAL;
2477 siocniobase = iobase;
2481 if (COM_DEBUGGER(flags))
2482 siogdbiobase = iobase;
2492 comconsole = cp->cn_unit;
2503 siocncheckc(struct consdev *cd)
2508 struct siocnstate sp;
2511 if (cd != NULL && cd->cn_unit == siocnunit) {
2512 iobase = siocniobase;
2513 speed = comdefaultrate;
2516 iobase = siogdbiobase;
2517 speed = gdbdefaultrate;
2523 siocnopen(&sp, iobase, speed);
2524 if (inb(iobase + com_lsr) & LSR_RXRDY)
2525 c = inb(iobase + com_data);
2528 siocnclose(&sp, iobase);
2534 siocngetc(struct consdev *cd)
2539 struct siocnstate sp;
2542 if (cd != NULL && cd->cn_unit == siocnunit) {
2543 iobase = siocniobase;
2544 speed = comdefaultrate;
2547 iobase = siogdbiobase;
2548 speed = gdbdefaultrate;
2554 siocnopen(&sp, iobase, speed);
2555 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
2557 c = inb(iobase + com_data);
2558 siocnclose(&sp, iobase);
2564 siocnputc(struct consdev *cd, int c)
2568 struct siocnstate sp;
2572 if (cd != NULL && cd->cn_unit == siocnunit) {
2573 iobase = siocniobase;
2574 speed = comdefaultrate;
2577 iobase = siogdbiobase;
2578 speed = gdbdefaultrate;
2585 if (!kdb_active && sio_inited == 2 && !mtx_owned(&sio_lock)) {
2586 mtx_lock_spin(&sio_lock);
2589 siocnopen(&sp, iobase, speed);
2590 siocntxwait(iobase);
2591 outb(iobase + com_data, c);
2592 siocnclose(&sp, iobase);
2594 mtx_unlock_spin(&sio_lock);
2599 * Remote gdb(1) support.
2604 #include <gdb/gdb.h>
2606 static gdb_probe_f siogdbprobe;
2607 static gdb_init_f siogdbinit;
2608 static gdb_term_f siogdbterm;
2609 static gdb_getc_f siogdbgetc;
2610 static gdb_checkc_f siogdbcheckc;
2611 static gdb_putc_f siogdbputc;
2613 GDB_DBGPORT(sio, siogdbprobe, siogdbinit, siogdbterm, siogdbcheckc,
2614 siogdbgetc, siogdbputc);
2619 return ((siogdbiobase != 0) ? 0 : -1);
2641 return (siocncheckc(NULL));
2647 return (siocngetc(NULL));