2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
3 * Copyright (c) 1997, 1998, 1999
4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
39 * available from http://www.sis.com.tw.
41 * This driver also supports the NatSemi DP83815. Datasheets are
42 * available from http://www.national.com.
44 * Written by Bill Paul <wpaul@ee.columbia.edu>
45 * Electrical Engineering Department
46 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #ifdef HAVE_KERNEL_OPTION_HEADERS
62 #include "opt_device_polling.h"
65 #include <sys/param.h>
66 #include <sys/systm.h>
68 #include <sys/endian.h>
69 #include <sys/kernel.h>
71 #include <sys/malloc.h>
73 #include <sys/module.h>
74 #include <sys/socket.h>
75 #include <sys/sockio.h>
76 #include <sys/sysctl.h>
79 #include <net/if_var.h>
80 #include <net/if_arp.h>
81 #include <net/ethernet.h>
82 #include <net/if_dl.h>
83 #include <net/if_media.h>
84 #include <net/if_types.h>
85 #include <net/if_vlan_var.h>
89 #include <machine/bus.h>
90 #include <machine/resource.h>
93 #include <dev/mii/mii.h>
94 #include <dev/mii/mii_bitbang.h>
95 #include <dev/mii/miivar.h>
97 #include <dev/pci/pcireg.h>
98 #include <dev/pci/pcivar.h>
100 #define SIS_USEIOSPACE
102 #include <dev/sis/if_sisreg.h>
104 MODULE_DEPEND(sis, pci, 1, 1, 1);
105 MODULE_DEPEND(sis, ether, 1, 1, 1);
106 MODULE_DEPEND(sis, miibus, 1, 1, 1);
108 /* "device miibus" required. See GENERIC if you get errors here. */
109 #include "miibus_if.h"
111 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
112 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
113 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
116 * register space access macros
118 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
120 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
122 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
124 #define CSR_BARRIER(sc, reg, length, flags) \
125 bus_barrier(sc->sis_res[0], reg, length, flags)
128 * Various supported device vendors/types and their names.
130 static const struct sis_type sis_devs[] = {
131 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
132 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
133 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
137 static int sis_detach(device_t);
138 static __inline void sis_discard_rxbuf(struct sis_rxdesc *);
139 static int sis_dma_alloc(struct sis_softc *);
140 static void sis_dma_free(struct sis_softc *);
141 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t,
142 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
143 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int);
144 #ifndef __NO_STRICT_ALIGNMENT
145 static __inline void sis_fixup_rx(struct mbuf *);
147 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
148 static int sis_ifmedia_upd(struct ifnet *);
149 static void sis_init(void *);
150 static void sis_initl(struct sis_softc *);
151 static void sis_intr(void *);
152 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
153 static uint32_t sis_mii_bitbang_read(device_t);
154 static void sis_mii_bitbang_write(device_t, uint32_t);
155 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
156 static int sis_resume(device_t);
157 static int sis_rxeof(struct sis_softc *);
158 static void sis_rxfilter(struct sis_softc *);
159 static void sis_rxfilter_ns(struct sis_softc *);
160 static void sis_rxfilter_sis(struct sis_softc *);
161 static void sis_start(struct ifnet *);
162 static void sis_startl(struct ifnet *);
163 static void sis_stop(struct sis_softc *);
164 static int sis_suspend(device_t);
165 static void sis_add_sysctls(struct sis_softc *);
166 static void sis_watchdog(struct sis_softc *);
167 static void sis_wol(struct sis_softc *);
172 static const struct mii_bitbang_ops sis_mii_bitbang_ops = {
173 sis_mii_bitbang_read,
174 sis_mii_bitbang_write,
176 SIS_MII_DATA, /* MII_BIT_MDO */
177 SIS_MII_DATA, /* MII_BIT_MDI */
178 SIS_MII_CLK, /* MII_BIT_MDC */
179 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
180 0, /* MII_BIT_DIR_PHY_HOST */
184 static struct resource_spec sis_res_spec[] = {
185 #ifdef SIS_USEIOSPACE
186 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE},
188 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE},
190 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
194 #define SIS_SETBIT(sc, reg, x) \
195 CSR_WRITE_4(sc, reg, \
196 CSR_READ_4(sc, reg) | (x))
198 #define SIS_CLRBIT(sc, reg, x) \
199 CSR_WRITE_4(sc, reg, \
200 CSR_READ_4(sc, reg) & ~(x))
203 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
206 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
209 * Routine to reverse the bits in a word. Stolen almost
210 * verbatim from /usr/games/fortune.
213 sis_reverse(uint16_t n)
215 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
216 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
217 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
218 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
224 sis_delay(struct sis_softc *sc)
228 for (idx = (300 / 33) + 1; idx > 0; idx--)
229 CSR_READ_4(sc, SIS_CSR);
233 sis_eeprom_idle(struct sis_softc *sc)
237 SIO_SET(SIS_EECTL_CSEL);
239 SIO_SET(SIS_EECTL_CLK);
242 for (i = 0; i < 25; i++) {
243 SIO_CLR(SIS_EECTL_CLK);
245 SIO_SET(SIS_EECTL_CLK);
249 SIO_CLR(SIS_EECTL_CLK);
251 SIO_CLR(SIS_EECTL_CSEL);
253 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
257 * Send a read command and address to the EEPROM, check for ACK.
260 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
264 d = addr | SIS_EECMD_READ;
267 * Feed in each bit and stobe the clock.
269 for (i = 0x400; i; i >>= 1) {
271 SIO_SET(SIS_EECTL_DIN);
273 SIO_CLR(SIS_EECTL_DIN);
276 SIO_SET(SIS_EECTL_CLK);
278 SIO_CLR(SIS_EECTL_CLK);
284 * Read a word of data stored in the EEPROM at address 'addr.'
287 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
292 /* Force EEPROM to idle state. */
295 /* Enter EEPROM access mode. */
297 SIO_CLR(SIS_EECTL_CLK);
299 SIO_SET(SIS_EECTL_CSEL);
303 * Send address of word we want to read.
305 sis_eeprom_putbyte(sc, addr);
308 * Start reading bits from EEPROM.
310 for (i = 0x8000; i; i >>= 1) {
311 SIO_SET(SIS_EECTL_CLK);
313 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
316 SIO_CLR(SIS_EECTL_CLK);
320 /* Turn off EEPROM access mode. */
327 * Read a sequence of words from the EEPROM.
330 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
333 uint16_t word = 0, *ptr;
335 for (i = 0; i < cnt; i++) {
336 sis_eeprom_getword(sc, off + i, &word);
337 ptr = (uint16_t *)(dest + (i * 2));
345 #if defined(__i386__) || defined(__amd64__)
347 sis_find_bridge(device_t dev)
349 devclass_t pci_devclass;
350 device_t *pci_devices;
352 device_t *pci_children;
353 int pci_childcount = 0;
354 device_t *busp, *childp;
355 device_t child = NULL;
358 if ((pci_devclass = devclass_find("pci")) == NULL)
361 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
363 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
364 if (device_get_children(*busp, &pci_children, &pci_childcount))
366 for (j = 0, childp = pci_children;
367 j < pci_childcount; j++, childp++) {
368 if (pci_get_vendor(*childp) == SIS_VENDORID &&
369 pci_get_device(*childp) == 0x0008) {
371 free(pci_children, M_TEMP);
375 free(pci_children, M_TEMP);
379 free(pci_devices, M_TEMP);
384 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
389 bus_space_tag_t btag;
391 bridge = sis_find_bridge(dev);
394 reg = pci_read_config(bridge, 0x48, 1);
395 pci_write_config(bridge, 0x48, reg|0x40, 1);
398 #if defined(__amd64__) || defined(__i386__)
399 btag = X86_BUS_SPACE_IO;
402 for (i = 0; i < cnt; i++) {
403 bus_space_write_1(btag, 0x0, 0x70, i + off);
404 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
407 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
411 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
413 uint32_t filtsave, csrsave;
415 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
416 csrsave = CSR_READ_4(sc, SIS_CSR);
418 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
419 CSR_WRITE_4(sc, SIS_CSR, 0);
421 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
423 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
424 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
425 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
426 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
427 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
428 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
430 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
431 CSR_WRITE_4(sc, SIS_CSR, csrsave);
436 * Read the MII serial port for the MII bit-bang module.
439 sis_mii_bitbang_read(device_t dev)
441 struct sis_softc *sc;
444 sc = device_get_softc(dev);
446 val = CSR_READ_4(sc, SIS_EECTL);
447 CSR_BARRIER(sc, SIS_EECTL, 4,
448 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
453 * Write the MII serial port for the MII bit-bang module.
456 sis_mii_bitbang_write(device_t dev, uint32_t val)
458 struct sis_softc *sc;
460 sc = device_get_softc(dev);
462 CSR_WRITE_4(sc, SIS_EECTL, val);
463 CSR_BARRIER(sc, SIS_EECTL, 4,
464 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
468 sis_miibus_readreg(device_t dev, int phy, int reg)
470 struct sis_softc *sc;
472 sc = device_get_softc(dev);
474 if (sc->sis_type == SIS_TYPE_83815) {
478 * The NatSemi chip can take a while after
479 * a reset to come ready, during which the BMSR
480 * returns a value of 0. This is *never* supposed
481 * to happen: some of the BMSR bits are meant to
482 * be hardwired in the on position, and this can
483 * confuse the miibus code a bit during the probe
484 * and attach phase. So we make an effort to check
485 * for this condition and wait for it to clear.
487 if (!CSR_READ_4(sc, NS_BMSR))
489 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
493 * Chipsets < SIS_635 seem not to be able to read/write
494 * through mdio. Use the enhanced PHY access register
497 if (sc->sis_type == SIS_TYPE_900 &&
498 sc->sis_rev < SIS_REV_635) {
504 CSR_WRITE_4(sc, SIS_PHYCTL,
505 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
506 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
508 for (i = 0; i < SIS_TIMEOUT; i++) {
509 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
513 if (i == SIS_TIMEOUT) {
514 device_printf(sc->sis_dev,
515 "PHY failed to come ready\n");
519 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
526 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy,
531 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
533 struct sis_softc *sc;
535 sc = device_get_softc(dev);
537 if (sc->sis_type == SIS_TYPE_83815) {
540 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
545 * Chipsets < SIS_635 seem not to be able to read/write
546 * through mdio. Use the enhanced PHY access register
549 if (sc->sis_type == SIS_TYPE_900 &&
550 sc->sis_rev < SIS_REV_635) {
556 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
557 (reg << 6) | SIS_PHYOP_WRITE);
558 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
560 for (i = 0; i < SIS_TIMEOUT; i++) {
561 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
565 if (i == SIS_TIMEOUT)
566 device_printf(sc->sis_dev,
567 "PHY failed to come ready\n");
569 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg,
575 sis_miibus_statchg(device_t dev)
577 struct sis_softc *sc;
578 struct mii_data *mii;
582 sc = device_get_softc(dev);
585 mii = device_get_softc(sc->sis_miibus);
587 if (mii == NULL || ifp == NULL ||
588 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
591 sc->sis_flags &= ~SIS_FLAG_LINK;
592 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
593 (IFM_ACTIVE | IFM_AVALID)) {
594 switch (IFM_SUBTYPE(mii->mii_media_active)) {
596 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
597 sc->sis_flags |= SIS_FLAG_LINK;
600 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
601 sc->sis_flags |= SIS_FLAG_LINK;
608 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) {
610 * Stopping MACs seem to reset SIS_TX_LISTPTR and
611 * SIS_RX_LISTPTR which in turn requires resetting
612 * TX/RX buffers. So just don't do anything for
618 /* Set full/half duplex mode. */
619 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
620 SIS_SETBIT(sc, SIS_TX_CFG,
621 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
622 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
624 SIS_CLRBIT(sc, SIS_TX_CFG,
625 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
626 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
629 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
631 * MPII03.D: Half Duplex Excessive Collisions.
632 * Also page 49 in 83816 manual
634 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
637 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
638 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
640 * Short Cable Receive Errors (MP21.E)
642 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
643 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
644 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
646 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
647 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
648 device_printf(sc->sis_dev,
649 "Applying short cable fix (reg=%x)\n", reg);
650 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
651 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
653 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
655 /* Enable TX/RX MACs. */
656 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
657 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE);
661 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
665 /* Compute CRC for the address value. */
666 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
669 * return the filter bit position
671 * The NatSemi chip has a 512-bit filter, which is
672 * different than the SiS, so we special-case it.
674 if (sc->sis_type == SIS_TYPE_83815)
676 else if (sc->sis_rev >= SIS_REV_635 ||
677 sc->sis_rev == SIS_REV_900B)
684 sis_rxfilter(struct sis_softc *sc)
689 if (sc->sis_type == SIS_TYPE_83815)
692 sis_rxfilter_sis(sc);
696 sis_rxfilter_ns(struct sis_softc *sc)
699 struct ifmultiaddr *ifma;
700 uint32_t h, i, filter;
704 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
705 if (filter & SIS_RXFILTCTL_ENABLE) {
707 * Filter should be disabled to program other bits.
709 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
710 CSR_READ_4(sc, SIS_RXFILT_CTL);
712 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT |
713 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
714 SIS_RXFILTCTL_ALLMULTI);
716 if (ifp->if_flags & IFF_BROADCAST)
717 filter |= SIS_RXFILTCTL_BROAD;
719 * For the NatSemi chip, we have to explicitly enable the
720 * reception of ARP frames, as well as turn on the 'perfect
721 * match' filter where we store the station address, otherwise
722 * we won't receive unicasts meant for this host.
724 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT;
726 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
727 filter |= SIS_RXFILTCTL_ALLMULTI;
728 if (ifp->if_flags & IFF_PROMISC)
729 filter |= SIS_RXFILTCTL_ALLPHYS;
732 * We have to explicitly enable the multicast hash table
733 * on the NatSemi chip if we want to use it, which we do.
735 filter |= NS_RXFILTCTL_MCHASH;
737 /* first, zot all the existing hash bits */
738 for (i = 0; i < 32; i++) {
739 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
741 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
745 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
746 if (ifma->ifma_addr->sa_family != AF_LINK)
749 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
752 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
756 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
758 if_maddr_runlock(ifp);
761 /* Turn the receive filter on */
762 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
763 CSR_READ_4(sc, SIS_RXFILT_CTL);
767 sis_rxfilter_sis(struct sis_softc *sc)
770 struct ifmultiaddr *ifma;
771 uint32_t filter, h, i, n;
776 /* hash table size */
777 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
782 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
783 if (filter & SIS_RXFILTCTL_ENABLE) {
784 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
785 CSR_READ_4(sc, SIS_RXFILT_CTL);
787 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
788 SIS_RXFILTCTL_ALLMULTI);
789 if (ifp->if_flags & IFF_BROADCAST)
790 filter |= SIS_RXFILTCTL_BROAD;
792 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
793 filter |= SIS_RXFILTCTL_ALLMULTI;
794 if (ifp->if_flags & IFF_PROMISC)
795 filter |= SIS_RXFILTCTL_ALLPHYS;
796 for (i = 0; i < n; i++)
799 for (i = 0; i < n; i++)
803 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
804 if (ifma->ifma_addr->sa_family != AF_LINK)
807 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
808 hashes[h >> 4] |= 1 << (h & 0xf);
811 if_maddr_runlock(ifp);
813 filter |= SIS_RXFILTCTL_ALLMULTI;
814 for (i = 0; i < n; i++)
819 for (i = 0; i < n; i++) {
820 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
821 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
824 /* Turn the receive filter on */
825 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
826 CSR_READ_4(sc, SIS_RXFILT_CTL);
830 sis_reset(struct sis_softc *sc)
834 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
836 for (i = 0; i < SIS_TIMEOUT; i++) {
837 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
841 if (i == SIS_TIMEOUT)
842 device_printf(sc->sis_dev, "reset never completed\n");
844 /* Wait a little while for the chip to get its brains in order. */
848 * If this is a NetSemi chip, make sure to clear
851 if (sc->sis_type == SIS_TYPE_83815) {
852 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
853 CSR_WRITE_4(sc, NS_CLKRUN, 0);
855 /* Disable WOL functions. */
856 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0);
861 * Probe for an SiS chip. Check the PCI vendor and device
862 * IDs against our list and return a device name if we find a match.
865 sis_probe(device_t dev)
867 const struct sis_type *t;
871 while (t->sis_name != NULL) {
872 if ((pci_get_vendor(dev) == t->sis_vid) &&
873 (pci_get_device(dev) == t->sis_did)) {
874 device_set_desc(dev, t->sis_name);
875 return (BUS_PROBE_DEFAULT);
884 * Attach the interface. Allocate softc structures, do ifmedia
885 * setup and ethernet/BPF attach.
888 sis_attach(device_t dev)
890 u_char eaddr[ETHER_ADDR_LEN];
891 struct sis_softc *sc;
893 int error = 0, pmc, waittime = 0;
896 sc = device_get_softc(dev);
900 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
902 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
904 if (pci_get_device(dev) == SIS_DEVICEID_900)
905 sc->sis_type = SIS_TYPE_900;
906 if (pci_get_device(dev) == SIS_DEVICEID_7016)
907 sc->sis_type = SIS_TYPE_7016;
908 if (pci_get_vendor(dev) == NS_VENDORID)
909 sc->sis_type = SIS_TYPE_83815;
911 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
913 * Map control/status registers.
915 pci_enable_busmaster(dev);
917 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
919 device_printf(dev, "couldn't allocate resources\n");
923 /* Reset the adapter. */
926 if (sc->sis_type == SIS_TYPE_900 &&
927 (sc->sis_rev == SIS_REV_635 ||
928 sc->sis_rev == SIS_REV_900B)) {
929 SIO_SET(SIS_CFG_RND_CNT);
930 SIO_SET(SIS_CFG_PERR_DETECT);
934 * Get station address from the EEPROM.
936 switch (pci_get_vendor(dev)) {
938 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
940 /* We can't update the device description, so spew */
941 if (sc->sis_srr == NS_SRR_15C)
942 device_printf(dev, "Silicon Revision: DP83815C\n");
943 else if (sc->sis_srr == NS_SRR_15D)
944 device_printf(dev, "Silicon Revision: DP83815D\n");
945 else if (sc->sis_srr == NS_SRR_16A)
946 device_printf(dev, "Silicon Revision: DP83816A\n");
948 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
951 * Reading the MAC address out of the EEPROM on
952 * the NatSemi chip takes a bit more work than
953 * you'd expect. The address spans 4 16-bit words,
954 * with the first word containing only a single bit.
955 * You have to shift everything over one bit to
956 * get it aligned properly. Also, the bits are
957 * stored backwards (the LSB is really the MSB,
958 * and so on) so you have to reverse them in order
959 * to get the MAC address into the form we want.
960 * Why? Who the hell knows.
965 sis_read_eeprom(sc, (caddr_t)&tmp,
966 NS_EE_NODEADDR, 4, 0);
968 /* Shift everything over one bit. */
969 tmp[3] = tmp[3] >> 1;
970 tmp[3] |= tmp[2] << 15;
971 tmp[2] = tmp[2] >> 1;
972 tmp[2] |= tmp[1] << 15;
973 tmp[1] = tmp[1] >> 1;
974 tmp[1] |= tmp[0] << 15;
976 /* Now reverse all the bits. */
977 tmp[3] = sis_reverse(tmp[3]);
978 tmp[2] = sis_reverse(tmp[2]);
979 tmp[1] = sis_reverse(tmp[1]);
981 eaddr[0] = (tmp[1] >> 0) & 0xFF;
982 eaddr[1] = (tmp[1] >> 8) & 0xFF;
983 eaddr[2] = (tmp[2] >> 0) & 0xFF;
984 eaddr[3] = (tmp[2] >> 8) & 0xFF;
985 eaddr[4] = (tmp[3] >> 0) & 0xFF;
986 eaddr[5] = (tmp[3] >> 8) & 0xFF;
991 #if defined(__i386__) || defined(__amd64__)
993 * If this is a SiS 630E chipset with an embedded
994 * SiS 900 controller, we have to read the MAC address
995 * from the APC CMOS RAM. Our method for doing this
996 * is very ugly since we have to reach out and grab
997 * ahold of hardware for which we cannot properly
998 * allocate resources. This code is only compiled on
999 * the i386 architecture since the SiS 630E chipset
1000 * is for x86 motherboards only. Note that there are
1001 * a lot of magic numbers in this hack. These are
1002 * taken from SiS's Linux driver. I'd like to replace
1003 * them with proper symbolic definitions, but that
1004 * requires some datasheets that I don't have access
1007 if (sc->sis_rev == SIS_REV_630S ||
1008 sc->sis_rev == SIS_REV_630E ||
1009 sc->sis_rev == SIS_REV_630EA1)
1010 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1012 else if (sc->sis_rev == SIS_REV_635 ||
1013 sc->sis_rev == SIS_REV_630ET)
1014 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1015 else if (sc->sis_rev == SIS_REV_96x) {
1016 /* Allow to read EEPROM from LAN. It is shared
1017 * between a 1394 controller and the NIC and each
1018 * time we access it, we need to set SIS_EECMD_REQ.
1020 SIO_SET(SIS_EECMD_REQ);
1021 for (waittime = 0; waittime < SIS_TIMEOUT;
1023 /* Force EEPROM to idle state. */
1024 sis_eeprom_idle(sc);
1025 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1026 sis_read_eeprom(sc, (caddr_t)&eaddr,
1027 SIS_EE_NODEADDR, 3, 0);
1033 * Set SIS_EECTL_CLK to high, so a other master
1034 * can operate on the i2c bus.
1036 SIO_SET(SIS_EECTL_CLK);
1037 /* Refuse EEPROM access by LAN */
1038 SIO_SET(SIS_EECMD_DONE);
1041 sis_read_eeprom(sc, (caddr_t)&eaddr,
1042 SIS_EE_NODEADDR, 3, 0);
1046 sis_add_sysctls(sc);
1048 /* Allocate DMA'able memory. */
1049 if ((error = sis_dma_alloc(sc)) != 0)
1052 ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
1054 device_printf(dev, "can not if_alloc()\n");
1059 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1060 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1061 ifp->if_ioctl = sis_ioctl;
1062 ifp->if_start = sis_start;
1063 ifp->if_init = sis_init;
1064 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1065 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
1066 IFQ_SET_READY(&ifp->if_snd);
1068 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
1069 if (sc->sis_type == SIS_TYPE_83815)
1070 ifp->if_capabilities |= IFCAP_WOL;
1072 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1073 ifp->if_capenable = ifp->if_capabilities;
1079 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd,
1080 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1082 device_printf(dev, "attaching PHYs failed\n");
1087 * Call MI attach routine.
1089 ether_ifattach(ifp, eaddr);
1092 * Tell the upper layer(s) we support long frames.
1094 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1095 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1096 ifp->if_capenable = ifp->if_capabilities;
1097 #ifdef DEVICE_POLLING
1098 ifp->if_capabilities |= IFCAP_POLLING;
1101 /* Hook interrupt last to avoid having to lock softc */
1102 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
1103 NULL, sis_intr, sc, &sc->sis_intrhand);
1106 device_printf(dev, "couldn't set up irq\n");
1107 ether_ifdetach(ifp);
1119 * Shutdown hardware and free up resources. This can be called any
1120 * time after the mutex has been initialized. It is called in both
1121 * the error case in attach and the normal detach case so it needs
1122 * to be careful about only freeing resources that have actually been
1126 sis_detach(device_t dev)
1128 struct sis_softc *sc;
1131 sc = device_get_softc(dev);
1132 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1135 #ifdef DEVICE_POLLING
1136 if (ifp->if_capenable & IFCAP_POLLING)
1137 ether_poll_deregister(ifp);
1140 /* These should only be active if attach succeeded. */
1141 if (device_is_attached(dev)) {
1145 callout_drain(&sc->sis_stat_ch);
1146 ether_ifdetach(ifp);
1149 device_delete_child(dev, sc->sis_miibus);
1150 bus_generic_detach(dev);
1152 if (sc->sis_intrhand)
1153 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
1154 bus_release_resources(dev, sis_res_spec, sc->sis_res);
1161 mtx_destroy(&sc->sis_mtx);
1166 struct sis_dmamap_arg {
1167 bus_addr_t sis_busaddr;
1171 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1173 struct sis_dmamap_arg *ctx;
1178 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1180 ctx = (struct sis_dmamap_arg *)arg;
1181 ctx->sis_busaddr = segs[0].ds_addr;
1185 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment,
1186 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
1187 bus_addr_t *paddr, const char *msg)
1189 struct sis_dmamap_arg ctx;
1192 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0,
1193 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1,
1194 maxsize, 0, NULL, NULL, tag);
1196 device_printf(sc->sis_dev,
1197 "could not create %s dma tag\n", msg);
1200 /* Allocate DMA'able memory for ring. */
1201 error = bus_dmamem_alloc(*tag, (void **)ring,
1202 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1204 device_printf(sc->sis_dev,
1205 "could not allocate DMA'able memory for %s\n", msg);
1208 /* Load the address of the ring. */
1209 ctx.sis_busaddr = 0;
1210 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb,
1211 &ctx, BUS_DMA_NOWAIT);
1213 device_printf(sc->sis_dev,
1214 "could not load DMA'able memory for %s\n", msg);
1217 *paddr = ctx.sis_busaddr;
1222 sis_dma_alloc(struct sis_softc *sc)
1224 struct sis_rxdesc *rxd;
1225 struct sis_txdesc *txd;
1228 /* Allocate the parent bus DMA tag appropriate for PCI. */
1229 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev),
1230 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1231 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
1232 0, NULL, NULL, &sc->sis_parent_tag);
1234 device_printf(sc->sis_dev,
1235 "could not allocate parent dma tag\n");
1239 /* Create RX ring. */
1240 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ,
1241 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list,
1242 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring");
1246 /* Create TX ring. */
1247 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ,
1248 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list,
1249 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring");
1253 /* Create tag for RX mbufs. */
1254 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0,
1255 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1256 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag);
1258 device_printf(sc->sis_dev, "could not allocate RX dma tag\n");
1262 /* Create tag for TX mbufs. */
1263 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0,
1264 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1265 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1268 device_printf(sc->sis_dev, "could not allocate TX dma tag\n");
1272 /* Create DMA maps for RX buffers. */
1273 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap);
1275 device_printf(sc->sis_dev,
1276 "can't create spare DMA map for RX\n");
1279 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1280 rxd = &sc->sis_rxdesc[i];
1282 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap);
1284 device_printf(sc->sis_dev,
1285 "can't create DMA map for RX\n");
1290 /* Create DMA maps for TX buffers. */
1291 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1292 txd = &sc->sis_txdesc[i];
1294 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap);
1296 device_printf(sc->sis_dev,
1297 "can't create DMA map for TX\n");
1306 sis_dma_free(struct sis_softc *sc)
1308 struct sis_rxdesc *rxd;
1309 struct sis_txdesc *txd;
1312 /* Destroy DMA maps for RX buffers. */
1313 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1314 rxd = &sc->sis_rxdesc[i];
1316 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap);
1318 if (sc->sis_rx_sparemap)
1319 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap);
1321 /* Destroy DMA maps for TX buffers. */
1322 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1323 txd = &sc->sis_txdesc[i];
1325 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap);
1329 bus_dma_tag_destroy(sc->sis_rx_tag);
1331 bus_dma_tag_destroy(sc->sis_tx_tag);
1333 /* Destroy RX ring. */
1334 if (sc->sis_rx_paddr)
1335 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map);
1336 if (sc->sis_rx_list)
1337 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list,
1338 sc->sis_rx_list_map);
1340 if (sc->sis_rx_list_tag)
1341 bus_dma_tag_destroy(sc->sis_rx_list_tag);
1343 /* Destroy TX ring. */
1344 if (sc->sis_tx_paddr)
1345 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map);
1347 if (sc->sis_tx_list)
1348 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list,
1349 sc->sis_tx_list_map);
1351 if (sc->sis_tx_list_tag)
1352 bus_dma_tag_destroy(sc->sis_tx_list_tag);
1354 /* Destroy the parent tag. */
1355 if (sc->sis_parent_tag)
1356 bus_dma_tag_destroy(sc->sis_parent_tag);
1360 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
1361 * we arrange the descriptors in a closed ring, so that the last descriptor
1362 * points back to the first.
1365 sis_ring_init(struct sis_softc *sc)
1367 struct sis_rxdesc *rxd;
1368 struct sis_txdesc *txd;
1372 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ);
1373 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1374 txd = &sc->sis_txdesc[i];
1376 if (i == SIS_TX_LIST_CNT - 1)
1377 next = SIS_TX_RING_ADDR(sc, 0);
1379 next = SIS_TX_RING_ADDR(sc, i + 1);
1380 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next));
1382 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
1383 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1386 sc->sis_rx_cons = 0;
1387 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ);
1388 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1389 rxd = &sc->sis_rxdesc[i];
1390 rxd->rx_desc = &sc->sis_rx_list[i];
1391 if (i == SIS_RX_LIST_CNT - 1)
1392 next = SIS_RX_RING_ADDR(sc, 0);
1394 next = SIS_RX_RING_ADDR(sc, i + 1);
1395 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next));
1396 error = sis_newbuf(sc, rxd);
1400 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1401 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1407 * Initialize an RX descriptor and attach an MBUF cluster.
1410 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd)
1413 bus_dma_segment_t segs[1];
1417 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1420 m->m_len = m->m_pkthdr.len = SIS_RXLEN;
1421 #ifndef __NO_STRICT_ALIGNMENT
1422 m_adj(m, SIS_RX_BUF_ALIGN);
1425 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m,
1426 segs, &nsegs, 0) != 0) {
1430 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1432 if (rxd->rx_m != NULL) {
1433 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
1434 BUS_DMASYNC_POSTREAD);
1435 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
1437 map = rxd->rx_dmamap;
1438 rxd->rx_dmamap = sc->sis_rx_sparemap;
1439 sc->sis_rx_sparemap = map;
1440 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD);
1442 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr));
1443 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1447 static __inline void
1448 sis_discard_rxbuf(struct sis_rxdesc *rxd)
1451 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1454 #ifndef __NO_STRICT_ALIGNMENT
1455 static __inline void
1456 sis_fixup_rx(struct mbuf *m)
1458 uint16_t *src, *dst;
1461 src = mtod(m, uint16_t *);
1462 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src);
1464 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1467 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN;
1472 * A frame has been uploaded: pass the resulting mbuf chain up to
1473 * the higher level protocols.
1476 sis_rxeof(struct sis_softc *sc)
1480 struct sis_rxdesc *rxd;
1481 struct sis_desc *cur_rx;
1482 int prog, rx_cons, rx_npkts = 0, total_len;
1485 SIS_LOCK_ASSERT(sc);
1487 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1488 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1490 rx_cons = sc->sis_rx_cons;
1493 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
1494 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) {
1495 #ifdef DEVICE_POLLING
1496 if (ifp->if_capenable & IFCAP_POLLING) {
1497 if (sc->rxcycles <= 0)
1502 cur_rx = &sc->sis_rx_list[rx_cons];
1503 rxstat = le32toh(cur_rx->sis_cmdsts);
1504 if ((rxstat & SIS_CMDSTS_OWN) == 0)
1506 rxd = &sc->sis_rxdesc[rx_cons];
1508 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN;
1509 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 &&
1510 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN -
1512 rxstat &= ~SIS_RXSTAT_GIANT;
1513 if (SIS_RXSTAT_ERROR(rxstat) != 0) {
1514 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1515 if (rxstat & SIS_RXSTAT_COLL)
1516 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1517 sis_discard_rxbuf(rxd);
1521 /* Add a new receive buffer to the ring. */
1523 if (sis_newbuf(sc, rxd) != 0) {
1524 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1525 sis_discard_rxbuf(rxd);
1529 /* No errors; receive the packet. */
1530 m->m_pkthdr.len = m->m_len = total_len;
1531 #ifndef __NO_STRICT_ALIGNMENT
1533 * On architectures without alignment problems we try to
1534 * allocate a new buffer for the receive ring, and pass up
1535 * the one where the packet is already, saving the expensive
1540 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1541 m->m_pkthdr.rcvif = ifp;
1544 (*ifp->if_input)(ifp, m);
1550 sc->sis_rx_cons = rx_cons;
1551 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1552 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1559 * A frame was downloaded to the chip. It's safe for us to clean up
1564 sis_txeof(struct sis_softc *sc)
1567 struct sis_desc *cur_tx;
1568 struct sis_txdesc *txd;
1569 uint32_t cons, txstat;
1571 SIS_LOCK_ASSERT(sc);
1573 cons = sc->sis_tx_cons;
1574 if (cons == sc->sis_tx_prod)
1578 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1579 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1582 * Go through our tx list and free mbufs for those
1583 * frames that have been transmitted.
1585 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) {
1586 cur_tx = &sc->sis_tx_list[cons];
1587 txstat = le32toh(cur_tx->sis_cmdsts);
1588 if ((txstat & SIS_CMDSTS_OWN) != 0)
1590 txd = &sc->sis_txdesc[cons];
1591 if (txd->tx_m != NULL) {
1592 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
1593 BUS_DMASYNC_POSTWRITE);
1594 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1597 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) {
1598 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1599 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1600 (txstat & SIS_TXSTAT_COLLCNT) >> 16);
1602 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1603 if (txstat & SIS_TXSTAT_EXCESSCOLLS)
1604 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1605 if (txstat & SIS_TXSTAT_OUTOFWINCOLL)
1606 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1610 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1612 sc->sis_tx_cons = cons;
1613 if (sc->sis_tx_cnt == 0)
1614 sc->sis_watchdog_timer = 0;
1620 struct sis_softc *sc;
1621 struct mii_data *mii;
1624 SIS_LOCK_ASSERT(sc);
1626 mii = device_get_softc(sc->sis_miibus);
1629 if ((sc->sis_flags & SIS_FLAG_LINK) == 0)
1630 sis_miibus_statchg(sc->sis_dev);
1631 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1634 #ifdef DEVICE_POLLING
1635 static poll_handler_t sis_poll;
1638 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1640 struct sis_softc *sc = ifp->if_softc;
1644 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1650 * On the sis, reading the status register also clears it.
1651 * So before returning to intr mode we must make sure that all
1652 * possible pending sources of interrupts have been served.
1653 * In practice this means run to completion the *eof routines,
1654 * and then call the interrupt routine
1656 sc->rxcycles = count;
1657 rx_npkts = sis_rxeof(sc);
1659 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1662 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1665 /* Reading the ISR register clears all interrupts. */
1666 status = CSR_READ_4(sc, SIS_ISR);
1668 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1669 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1671 if (status & (SIS_ISR_RX_IDLE))
1672 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1674 if (status & SIS_ISR_SYSERR) {
1675 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1683 #endif /* DEVICE_POLLING */
1688 struct sis_softc *sc;
1696 #ifdef DEVICE_POLLING
1697 if (ifp->if_capenable & IFCAP_POLLING) {
1703 /* Reading the ISR register clears all interrupts. */
1704 status = CSR_READ_4(sc, SIS_ISR);
1705 if ((status & SIS_INTRS) == 0) {
1711 /* Disable interrupts. */
1712 CSR_WRITE_4(sc, SIS_IER, 0);
1714 for (;(status & SIS_INTRS) != 0;) {
1715 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1718 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1719 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1722 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK |
1723 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE))
1726 if (status & SIS_ISR_RX_OFLOW)
1727 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1729 if (status & (SIS_ISR_RX_IDLE))
1730 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1732 if (status & SIS_ISR_SYSERR) {
1733 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1738 status = CSR_READ_4(sc, SIS_ISR);
1741 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1742 /* Re-enable interrupts. */
1743 CSR_WRITE_4(sc, SIS_IER, 1);
1745 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1753 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1754 * pointers to the fragment pointers.
1757 sis_encap(struct sis_softc *sc, struct mbuf **m_head)
1760 struct sis_txdesc *txd;
1762 bus_dma_segment_t segs[SIS_MAXTXSEGS];
1764 int error, i, frag, nsegs, prod;
1767 prod = sc->sis_tx_prod;
1768 txd = &sc->sis_txdesc[prod];
1769 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 &&
1770 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) {
1772 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len;
1773 if (M_WRITABLE(m) == 0) {
1774 /* Get a writable copy. */
1775 m = m_dup(*m_head, M_NOWAIT);
1783 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
1784 m = m_defrag(m, M_NOWAIT);
1792 * Manually pad short frames, and zero the pad space
1793 * to avoid leaking data.
1795 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1796 m->m_pkthdr.len += padlen;
1797 m->m_len = m->m_pkthdr.len;
1800 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1801 *m_head, segs, &nsegs, 0);
1802 if (error == EFBIG) {
1803 m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS);
1810 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1811 *m_head, segs, &nsegs, 0);
1817 } else if (error != 0)
1820 /* Check for descriptor overruns. */
1821 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) {
1822 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1826 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE);
1829 for (i = 0; i < nsegs; i++) {
1830 f = &sc->sis_tx_list[prod];
1832 f->sis_cmdsts = htole32(segs[i].ds_len |
1835 f->sis_cmdsts = htole32(segs[i].ds_len |
1836 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE);
1837 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr));
1838 SIS_INC(prod, SIS_TX_LIST_CNT);
1842 /* Update producer index. */
1843 sc->sis_tx_prod = prod;
1845 /* Remove MORE flag on the last descriptor. */
1846 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1);
1847 f = &sc->sis_tx_list[prod];
1848 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE);
1850 /* Lastly transfer ownership of packet to the controller. */
1851 f = &sc->sis_tx_list[frag];
1852 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN);
1854 /* Swap the last and the first dmamaps. */
1855 map = txd->tx_dmamap;
1856 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap;
1857 sc->sis_txdesc[prod].tx_dmamap = map;
1858 sc->sis_txdesc[prod].tx_m = *m_head;
1864 sis_start(struct ifnet *ifp)
1866 struct sis_softc *sc;
1875 sis_startl(struct ifnet *ifp)
1877 struct sis_softc *sc;
1878 struct mbuf *m_head;
1883 SIS_LOCK_ASSERT(sc);
1885 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1886 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0)
1889 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1890 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) {
1891 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1895 if (sis_encap(sc, &m_head) != 0) {
1898 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1899 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1906 * If there's a BPF listener, bounce a copy of this frame
1909 BPF_MTAP(ifp, m_head);
1914 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1915 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1916 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1919 * Set a timeout in case the chip goes out to lunch.
1921 sc->sis_watchdog_timer = 5;
1928 struct sis_softc *sc = xsc;
1936 sis_initl(struct sis_softc *sc)
1938 struct ifnet *ifp = sc->sis_ifp;
1939 struct mii_data *mii;
1942 SIS_LOCK_ASSERT(sc);
1944 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1948 * Cancel pending I/O and free all RX/TX buffers.
1952 * Reset the chip to a known state.
1956 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
1958 * Configure 400usec of interrupt holdoff. This is based
1959 * on emperical tests on a Soekris 4801.
1961 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
1965 mii = device_get_softc(sc->sis_miibus);
1967 /* Set MAC address */
1968 eaddr = IF_LLADDR(sc->sis_ifp);
1969 if (sc->sis_type == SIS_TYPE_83815) {
1970 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1971 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1972 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1973 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1974 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1975 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1977 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1978 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1979 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1980 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1981 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1982 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1985 /* Init circular TX/RX lists. */
1986 if (sis_ring_init(sc) != 0) {
1987 device_printf(sc->sis_dev,
1988 "initialization failed: no memory for rx buffers\n");
1993 if (sc->sis_type == SIS_TYPE_83815) {
1994 if (sc->sis_manual_pad != 0)
1995 sc->sis_flags |= SIS_FLAG_MANUAL_PAD;
1997 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD;
2001 * Short Cable Receive Errors (MP21.E)
2002 * also: Page 78 of the DP83815 data sheet (september 2002 version)
2003 * recommends the following register settings "for optimum
2004 * performance." for rev 15C. Set this also for 15D parts as
2005 * they require it in practice.
2007 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
2008 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2009 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2010 /* set val for c2 */
2011 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2013 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2014 /* rais SD off, from 4 to c */
2015 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2016 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2022 * Load the address of the RX and TX lists.
2024 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr));
2025 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr));
2027 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
2028 * the PCI bus. When this bit is set, the Max DMA Burst Size
2029 * for TX/RX DMA should be no larger than 16 double words.
2031 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
2032 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
2034 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
2037 /* Accept Long Packets for VLAN support */
2038 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
2041 * Assume 100Mbps link, actual MAC configuration is done
2042 * after getting a valid link.
2044 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
2047 * Enable interrupts.
2049 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2050 #ifdef DEVICE_POLLING
2052 * ... only enable interrupts if we are not polling, make sure
2053 * they are off otherwise.
2055 if (ifp->if_capenable & IFCAP_POLLING)
2056 CSR_WRITE_4(sc, SIS_IER, 0);
2059 CSR_WRITE_4(sc, SIS_IER, 1);
2061 /* Clear MAC disable. */
2062 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
2064 sc->sis_flags &= ~SIS_FLAG_LINK;
2067 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2068 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2070 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2074 * Set media options.
2077 sis_ifmedia_upd(struct ifnet *ifp)
2079 struct sis_softc *sc;
2080 struct mii_data *mii;
2081 struct mii_softc *miisc;
2087 mii = device_get_softc(sc->sis_miibus);
2088 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2090 error = mii_mediachg(mii);
2097 * Report current media status.
2100 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2102 struct sis_softc *sc;
2103 struct mii_data *mii;
2108 mii = device_get_softc(sc->sis_miibus);
2110 ifmr->ifm_active = mii->mii_media_active;
2111 ifmr->ifm_status = mii->mii_media_status;
2116 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2118 struct sis_softc *sc = ifp->if_softc;
2119 struct ifreq *ifr = (struct ifreq *) data;
2120 struct mii_data *mii;
2121 int error = 0, mask;
2126 if (ifp->if_flags & IFF_UP) {
2127 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2128 ((ifp->if_flags ^ sc->sis_if_flags) &
2129 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2133 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2135 sc->sis_if_flags = ifp->if_flags;
2141 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2147 mii = device_get_softc(sc->sis_miibus);
2148 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2152 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2153 #ifdef DEVICE_POLLING
2154 if ((mask & IFCAP_POLLING) != 0 &&
2155 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
2156 ifp->if_capenable ^= IFCAP_POLLING;
2157 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
2158 error = ether_poll_register(sis_poll, ifp);
2163 /* Disable interrupts. */
2164 CSR_WRITE_4(sc, SIS_IER, 0);
2166 error = ether_poll_deregister(ifp);
2167 /* Enable interrupts. */
2168 CSR_WRITE_4(sc, SIS_IER, 1);
2171 #endif /* DEVICE_POLLING */
2172 if ((mask & IFCAP_WOL) != 0 &&
2173 (ifp->if_capabilities & IFCAP_WOL) != 0) {
2174 if ((mask & IFCAP_WOL_UCAST) != 0)
2175 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2176 if ((mask & IFCAP_WOL_MCAST) != 0)
2177 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2178 if ((mask & IFCAP_WOL_MAGIC) != 0)
2179 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2184 error = ether_ioctl(ifp, command, data);
2192 sis_watchdog(struct sis_softc *sc)
2195 SIS_LOCK_ASSERT(sc);
2197 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
2200 device_printf(sc->sis_dev, "watchdog timeout\n");
2201 if_inc_counter(sc->sis_ifp, IFCOUNTER_OERRORS, 1);
2203 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2206 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd))
2207 sis_startl(sc->sis_ifp);
2211 * Stop the adapter and free any mbufs allocated to the
2215 sis_stop(struct sis_softc *sc)
2218 struct sis_rxdesc *rxd;
2219 struct sis_txdesc *txd;
2222 SIS_LOCK_ASSERT(sc);
2225 sc->sis_watchdog_timer = 0;
2227 callout_stop(&sc->sis_stat_ch);
2229 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2230 CSR_WRITE_4(sc, SIS_IER, 0);
2231 CSR_WRITE_4(sc, SIS_IMR, 0);
2232 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
2233 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2235 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2236 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2238 sc->sis_flags &= ~SIS_FLAG_LINK;
2241 * Free data in the RX lists.
2243 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2244 rxd = &sc->sis_rxdesc[i];
2245 if (rxd->rx_m != NULL) {
2246 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
2247 BUS_DMASYNC_POSTREAD);
2248 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
2255 * Free the TX list buffers.
2257 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2258 txd = &sc->sis_txdesc[i];
2259 if (txd->tx_m != NULL) {
2260 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
2261 BUS_DMASYNC_POSTWRITE);
2262 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
2270 * Stop all chip I/O so that the kernel's probe routines don't
2271 * get confused by errant DMAs when rebooting.
2274 sis_shutdown(device_t dev)
2277 return (sis_suspend(dev));
2281 sis_suspend(device_t dev)
2283 struct sis_softc *sc;
2285 sc = device_get_softc(dev);
2294 sis_resume(device_t dev)
2296 struct sis_softc *sc;
2299 sc = device_get_softc(dev);
2302 if ((ifp->if_flags & IFF_UP) != 0) {
2303 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2311 sis_wol(struct sis_softc *sc)
2319 if ((ifp->if_capenable & IFCAP_WOL) == 0)
2322 if (sc->sis_type == SIS_TYPE_83815) {
2324 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2326 /* Configure WOL events. */
2327 CSR_READ_4(sc, NS_WCSR);
2329 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2330 val |= NS_WCSR_WAKE_UCAST;
2331 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2332 val |= NS_WCSR_WAKE_MCAST;
2333 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2334 val |= NS_WCSR_WAKE_MAGIC;
2335 CSR_WRITE_4(sc, NS_WCSR, val);
2336 /* Enable PME and clear PMESTS. */
2337 val = CSR_READ_4(sc, NS_CLKRUN);
2338 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS;
2339 CSR_WRITE_4(sc, NS_CLKRUN, val);
2340 /* Enable silent RX mode. */
2341 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2343 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
2346 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2347 val |= SIS_PWRMAN_WOL_MAGIC;
2348 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val);
2350 pmstat = pci_read_config(sc->sis_dev,
2351 pmc + PCIR_POWER_STATUS, 2);
2352 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2353 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2354 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2355 pci_write_config(sc->sis_dev,
2356 pmc + PCIR_POWER_STATUS, pmstat, 2);
2361 sis_add_sysctls(struct sis_softc *sc)
2363 struct sysctl_ctx_list *ctx;
2364 struct sysctl_oid_list *children;
2367 ctx = device_get_sysctl_ctx(sc->sis_dev);
2368 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev));
2370 unit = device_get_unit(sc->sis_dev);
2372 * Unlike most other controllers, NS DP83815/DP83816 controllers
2373 * seem to pad with 0xFF when it encounter short frames. According
2374 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable
2375 * on will have driver pad manully but it's disabled by default
2376 * because it will consume extra CPU cycles for short frames.
2378 sc->sis_manual_pad = 0;
2379 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad",
2380 CTLFLAG_RWTUN, &sc->sis_manual_pad, 0, "Manually pad short frames");
2383 static device_method_t sis_methods[] = {
2384 /* Device interface */
2385 DEVMETHOD(device_probe, sis_probe),
2386 DEVMETHOD(device_attach, sis_attach),
2387 DEVMETHOD(device_detach, sis_detach),
2388 DEVMETHOD(device_shutdown, sis_shutdown),
2389 DEVMETHOD(device_suspend, sis_suspend),
2390 DEVMETHOD(device_resume, sis_resume),
2393 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
2394 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
2395 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
2400 static driver_t sis_driver = {
2403 sizeof(struct sis_softc)
2406 static devclass_t sis_devclass;
2408 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
2409 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);