2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
3 * Copyright (c) 1997, 1998, 1999
4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
39 * available from http://www.sis.com.tw.
41 * This driver also supports the NatSemi DP83815. Datasheets are
42 * available from http://www.national.com.
44 * Written by Bill Paul <wpaul@ee.columbia.edu>
45 * Electrical Engineering Department
46 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #ifdef HAVE_KERNEL_OPTION_HEADERS
62 #include "opt_device_polling.h"
65 #include <sys/param.h>
66 #include <sys/systm.h>
68 #include <sys/endian.h>
69 #include <sys/kernel.h>
71 #include <sys/malloc.h>
73 #include <sys/module.h>
74 #include <sys/socket.h>
75 #include <sys/sockio.h>
76 #include <sys/sysctl.h>
79 #include <net/if_arp.h>
80 #include <net/ethernet.h>
81 #include <net/if_dl.h>
82 #include <net/if_media.h>
83 #include <net/if_types.h>
84 #include <net/if_vlan_var.h>
88 #include <machine/bus.h>
89 #include <machine/resource.h>
93 #include <dev/mii/mii.h>
94 #include <dev/mii/miivar.h>
96 #include <dev/pci/pcireg.h>
97 #include <dev/pci/pcivar.h>
99 #define SIS_USEIOSPACE
101 #include <dev/sis/if_sisreg.h>
103 MODULE_DEPEND(sis, pci, 1, 1, 1);
104 MODULE_DEPEND(sis, ether, 1, 1, 1);
105 MODULE_DEPEND(sis, miibus, 1, 1, 1);
107 /* "device miibus" required. See GENERIC if you get errors here. */
108 #include "miibus_if.h"
110 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
111 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
112 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
115 * register space access macros
117 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
119 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
121 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
124 * Various supported device vendors/types and their names.
126 static struct sis_type sis_devs[] = {
127 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
128 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
129 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
133 static int sis_detach(device_t);
134 static __inline void sis_discard_rxbuf(struct sis_rxdesc *);
135 static int sis_dma_alloc(struct sis_softc *);
136 static void sis_dma_free(struct sis_softc *);
137 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t,
138 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
139 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int);
140 #ifndef __NO_STRICT_ALIGNMENT
141 static __inline void sis_fixup_rx(struct mbuf *);
143 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
144 static int sis_ifmedia_upd(struct ifnet *);
145 static void sis_init(void *);
146 static void sis_initl(struct sis_softc *);
147 static void sis_intr(void *);
148 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
149 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
150 static int sis_resume(device_t);
151 static int sis_rxeof(struct sis_softc *);
152 static void sis_rxfilter(struct sis_softc *);
153 static void sis_rxfilter_ns(struct sis_softc *);
154 static void sis_rxfilter_sis(struct sis_softc *);
155 static void sis_start(struct ifnet *);
156 static void sis_startl(struct ifnet *);
157 static void sis_stop(struct sis_softc *);
158 static int sis_suspend(device_t);
159 static void sis_add_sysctls(struct sis_softc *);
160 static void sis_watchdog(struct sis_softc *);
161 static void sis_wol(struct sis_softc *);
164 static struct resource_spec sis_res_spec[] = {
165 #ifdef SIS_USEIOSPACE
166 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE},
168 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE},
170 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
174 #define SIS_SETBIT(sc, reg, x) \
175 CSR_WRITE_4(sc, reg, \
176 CSR_READ_4(sc, reg) | (x))
178 #define SIS_CLRBIT(sc, reg, x) \
179 CSR_WRITE_4(sc, reg, \
180 CSR_READ_4(sc, reg) & ~(x))
183 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
186 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
189 * Routine to reverse the bits in a word. Stolen almost
190 * verbatim from /usr/games/fortune.
193 sis_reverse(uint16_t n)
195 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
196 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
197 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
198 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
204 sis_delay(struct sis_softc *sc)
208 for (idx = (300 / 33) + 1; idx > 0; idx--)
209 CSR_READ_4(sc, SIS_CSR);
213 sis_eeprom_idle(struct sis_softc *sc)
217 SIO_SET(SIS_EECTL_CSEL);
219 SIO_SET(SIS_EECTL_CLK);
222 for (i = 0; i < 25; i++) {
223 SIO_CLR(SIS_EECTL_CLK);
225 SIO_SET(SIS_EECTL_CLK);
229 SIO_CLR(SIS_EECTL_CLK);
231 SIO_CLR(SIS_EECTL_CSEL);
233 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
237 * Send a read command and address to the EEPROM, check for ACK.
240 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
244 d = addr | SIS_EECMD_READ;
247 * Feed in each bit and stobe the clock.
249 for (i = 0x400; i; i >>= 1) {
251 SIO_SET(SIS_EECTL_DIN);
253 SIO_CLR(SIS_EECTL_DIN);
256 SIO_SET(SIS_EECTL_CLK);
258 SIO_CLR(SIS_EECTL_CLK);
264 * Read a word of data stored in the EEPROM at address 'addr.'
267 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
272 /* Force EEPROM to idle state. */
275 /* Enter EEPROM access mode. */
277 SIO_CLR(SIS_EECTL_CLK);
279 SIO_SET(SIS_EECTL_CSEL);
283 * Send address of word we want to read.
285 sis_eeprom_putbyte(sc, addr);
288 * Start reading bits from EEPROM.
290 for (i = 0x8000; i; i >>= 1) {
291 SIO_SET(SIS_EECTL_CLK);
293 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
296 SIO_CLR(SIS_EECTL_CLK);
300 /* Turn off EEPROM access mode. */
307 * Read a sequence of words from the EEPROM.
310 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
313 uint16_t word = 0, *ptr;
315 for (i = 0; i < cnt; i++) {
316 sis_eeprom_getword(sc, off + i, &word);
317 ptr = (uint16_t *)(dest + (i * 2));
325 #if defined(__i386__) || defined(__amd64__)
327 sis_find_bridge(device_t dev)
329 devclass_t pci_devclass;
330 device_t *pci_devices;
332 device_t *pci_children;
333 int pci_childcount = 0;
334 device_t *busp, *childp;
335 device_t child = NULL;
338 if ((pci_devclass = devclass_find("pci")) == NULL)
341 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
343 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
344 if (device_get_children(*busp, &pci_children, &pci_childcount))
346 for (j = 0, childp = pci_children;
347 j < pci_childcount; j++, childp++) {
348 if (pci_get_vendor(*childp) == SIS_VENDORID &&
349 pci_get_device(*childp) == 0x0008) {
351 free(pci_children, M_TEMP);
355 free(pci_children, M_TEMP);
359 free(pci_devices, M_TEMP);
364 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
369 bus_space_tag_t btag;
371 bridge = sis_find_bridge(dev);
374 reg = pci_read_config(bridge, 0x48, 1);
375 pci_write_config(bridge, 0x48, reg|0x40, 1);
378 #if defined(__i386__)
379 btag = I386_BUS_SPACE_IO;
380 #elif defined(__amd64__)
381 btag = AMD64_BUS_SPACE_IO;
384 for (i = 0; i < cnt; i++) {
385 bus_space_write_1(btag, 0x0, 0x70, i + off);
386 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
389 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
393 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
395 uint32_t filtsave, csrsave;
397 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
398 csrsave = CSR_READ_4(sc, SIS_CSR);
400 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
401 CSR_WRITE_4(sc, SIS_CSR, 0);
403 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
405 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
406 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
407 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
408 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
409 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
410 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
412 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
413 CSR_WRITE_4(sc, SIS_CSR, csrsave);
418 * Sync the PHYs by setting data bit and strobing the clock 32 times.
421 sis_mii_sync(struct sis_softc *sc)
425 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
427 for (i = 0; i < 32; i++) {
428 SIO_SET(SIS_MII_CLK);
430 SIO_CLR(SIS_MII_CLK);
436 * Clock a series of bits through the MII.
439 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
443 SIO_CLR(SIS_MII_CLK);
445 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
447 SIO_SET(SIS_MII_DATA);
449 SIO_CLR(SIS_MII_DATA);
452 SIO_CLR(SIS_MII_CLK);
454 SIO_SET(SIS_MII_CLK);
459 * Read an PHY register through the MII.
462 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
467 * Set up frame for RX.
469 frame->mii_stdelim = SIS_MII_STARTDELIM;
470 frame->mii_opcode = SIS_MII_READOP;
471 frame->mii_turnaround = 0;
477 SIO_SET(SIS_MII_DIR);
482 * Send command/address info.
484 sis_mii_send(sc, frame->mii_stdelim, 2);
485 sis_mii_send(sc, frame->mii_opcode, 2);
486 sis_mii_send(sc, frame->mii_phyaddr, 5);
487 sis_mii_send(sc, frame->mii_regaddr, 5);
490 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
492 SIO_SET(SIS_MII_CLK);
496 SIO_CLR(SIS_MII_DIR);
499 SIO_CLR(SIS_MII_CLK);
501 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
502 SIO_SET(SIS_MII_CLK);
506 * Now try reading data bits. If the ack failed, we still
507 * need to clock through 16 cycles to keep the PHY(s) in sync.
510 for (i = 0; i < 16; i++) {
511 SIO_CLR(SIS_MII_CLK);
513 SIO_SET(SIS_MII_CLK);
519 for (i = 0x8000; i; i >>= 1) {
520 SIO_CLR(SIS_MII_CLK);
523 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
524 frame->mii_data |= i;
527 SIO_SET(SIS_MII_CLK);
533 SIO_CLR(SIS_MII_CLK);
535 SIO_SET(SIS_MII_CLK);
544 * Write to a PHY register through the MII.
547 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
551 * Set up frame for TX.
554 frame->mii_stdelim = SIS_MII_STARTDELIM;
555 frame->mii_opcode = SIS_MII_WRITEOP;
556 frame->mii_turnaround = SIS_MII_TURNAROUND;
559 * Turn on data output.
561 SIO_SET(SIS_MII_DIR);
565 sis_mii_send(sc, frame->mii_stdelim, 2);
566 sis_mii_send(sc, frame->mii_opcode, 2);
567 sis_mii_send(sc, frame->mii_phyaddr, 5);
568 sis_mii_send(sc, frame->mii_regaddr, 5);
569 sis_mii_send(sc, frame->mii_turnaround, 2);
570 sis_mii_send(sc, frame->mii_data, 16);
573 SIO_SET(SIS_MII_CLK);
575 SIO_CLR(SIS_MII_CLK);
581 SIO_CLR(SIS_MII_DIR);
587 sis_miibus_readreg(device_t dev, int phy, int reg)
589 struct sis_softc *sc;
590 struct sis_mii_frame frame;
592 sc = device_get_softc(dev);
594 if (sc->sis_type == SIS_TYPE_83815) {
598 * The NatSemi chip can take a while after
599 * a reset to come ready, during which the BMSR
600 * returns a value of 0. This is *never* supposed
601 * to happen: some of the BMSR bits are meant to
602 * be hardwired in the on position, and this can
603 * confuse the miibus code a bit during the probe
604 * and attach phase. So we make an effort to check
605 * for this condition and wait for it to clear.
607 if (!CSR_READ_4(sc, NS_BMSR))
609 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
613 * Chipsets < SIS_635 seem not to be able to read/write
614 * through mdio. Use the enhanced PHY access register
617 if (sc->sis_type == SIS_TYPE_900 &&
618 sc->sis_rev < SIS_REV_635) {
624 CSR_WRITE_4(sc, SIS_PHYCTL,
625 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
626 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
628 for (i = 0; i < SIS_TIMEOUT; i++) {
629 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
633 if (i == SIS_TIMEOUT) {
634 device_printf(sc->sis_dev, "PHY failed to come ready\n");
638 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
645 bzero((char *)&frame, sizeof(frame));
647 frame.mii_phyaddr = phy;
648 frame.mii_regaddr = reg;
649 sis_mii_readreg(sc, &frame);
651 return (frame.mii_data);
656 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
658 struct sis_softc *sc;
659 struct sis_mii_frame frame;
661 sc = device_get_softc(dev);
663 if (sc->sis_type == SIS_TYPE_83815) {
666 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
671 * Chipsets < SIS_635 seem not to be able to read/write
672 * through mdio. Use the enhanced PHY access register
675 if (sc->sis_type == SIS_TYPE_900 &&
676 sc->sis_rev < SIS_REV_635) {
682 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
683 (reg << 6) | SIS_PHYOP_WRITE);
684 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
686 for (i = 0; i < SIS_TIMEOUT; i++) {
687 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
691 if (i == SIS_TIMEOUT)
692 device_printf(sc->sis_dev, "PHY failed to come ready\n");
694 bzero((char *)&frame, sizeof(frame));
696 frame.mii_phyaddr = phy;
697 frame.mii_regaddr = reg;
698 frame.mii_data = data;
699 sis_mii_writereg(sc, &frame);
705 sis_miibus_statchg(device_t dev)
707 struct sis_softc *sc;
708 struct mii_data *mii;
712 sc = device_get_softc(dev);
715 mii = device_get_softc(sc->sis_miibus);
717 if (mii == NULL || ifp == NULL ||
718 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
721 sc->sis_flags &= ~SIS_FLAG_LINK;
722 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
723 (IFM_ACTIVE | IFM_AVALID)) {
724 switch (IFM_SUBTYPE(mii->mii_media_active)) {
726 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
727 sc->sis_flags |= SIS_FLAG_LINK;
730 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
731 sc->sis_flags |= SIS_FLAG_LINK;
738 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) {
740 * Stopping MACs seem to reset SIS_TX_LISTPTR and
741 * SIS_RX_LISTPTR which in turn requires resetting
742 * TX/RX buffers. So just don't do anything for
748 /* Set full/half duplex mode. */
749 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
750 SIS_SETBIT(sc, SIS_TX_CFG,
751 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
752 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
754 SIS_CLRBIT(sc, SIS_TX_CFG,
755 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
756 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
759 if (sc->sis_type == SIS_TYPE_83816) {
761 * MPII03.D: Half Duplex Excessive Collisions.
762 * Also page 49 in 83816 manual
764 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
767 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
768 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
770 * Short Cable Receive Errors (MP21.E)
772 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
773 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
774 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
776 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
777 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
778 device_printf(sc->sis_dev,
779 "Applying short cable fix (reg=%x)\n", reg);
780 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
781 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
783 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
785 /* Enable TX/RX MACs. */
786 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
787 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE);
791 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
795 /* Compute CRC for the address value. */
796 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
799 * return the filter bit position
801 * The NatSemi chip has a 512-bit filter, which is
802 * different than the SiS, so we special-case it.
804 if (sc->sis_type == SIS_TYPE_83815)
806 else if (sc->sis_rev >= SIS_REV_635 ||
807 sc->sis_rev == SIS_REV_900B)
814 sis_rxfilter(struct sis_softc *sc)
819 if (sc->sis_type == SIS_TYPE_83815)
822 sis_rxfilter_sis(sc);
826 sis_rxfilter_ns(struct sis_softc *sc)
829 struct ifmultiaddr *ifma;
830 uint32_t h, i, filter;
834 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
835 if (filter & SIS_RXFILTCTL_ENABLE) {
837 * Filter should be disabled to program other bits.
839 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
840 CSR_READ_4(sc, SIS_RXFILT_CTL);
842 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT |
843 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
844 SIS_RXFILTCTL_ALLMULTI);
846 if (ifp->if_flags & IFF_BROADCAST)
847 filter |= SIS_RXFILTCTL_BROAD;
849 * For the NatSemi chip, we have to explicitly enable the
850 * reception of ARP frames, as well as turn on the 'perfect
851 * match' filter where we store the station address, otherwise
852 * we won't receive unicasts meant for this host.
854 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT;
856 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
857 filter |= SIS_RXFILTCTL_ALLMULTI;
858 if (ifp->if_flags & IFF_PROMISC)
859 filter |= SIS_RXFILTCTL_ALLPHYS;
862 * We have to explicitly enable the multicast hash table
863 * on the NatSemi chip if we want to use it, which we do.
865 filter |= NS_RXFILTCTL_MCHASH;
867 /* first, zot all the existing hash bits */
868 for (i = 0; i < 32; i++) {
869 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
871 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
875 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
876 if (ifma->ifma_addr->sa_family != AF_LINK)
879 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
882 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
886 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
888 if_maddr_runlock(ifp);
891 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter);
892 CSR_READ_4(sc, SIS_RXFILT_CTL);
896 sis_rxfilter_sis(struct sis_softc *sc)
899 struct ifmultiaddr *ifma;
900 uint32_t filter, h, i, n;
905 /* hash table size */
906 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
911 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
912 if (filter & SIS_RXFILTCTL_ENABLE) {
913 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILT_CTL);
914 CSR_READ_4(sc, SIS_RXFILT_CTL);
916 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
917 SIS_RXFILTCTL_ALLMULTI);
918 if (ifp->if_flags & IFF_BROADCAST)
919 filter |= SIS_RXFILTCTL_BROAD;
921 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
922 filter |= SIS_RXFILTCTL_ALLMULTI;
923 if (ifp->if_flags & IFF_PROMISC)
924 filter |= SIS_RXFILTCTL_ALLPHYS;
925 for (i = 0; i < n; i++)
928 for (i = 0; i < n; i++)
932 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
933 if (ifma->ifma_addr->sa_family != AF_LINK)
936 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
937 hashes[h >> 4] |= 1 << (h & 0xf);
940 if_maddr_runlock(ifp);
942 filter |= SIS_RXFILTCTL_ALLMULTI;
943 for (i = 0; i < n; i++)
948 for (i = 0; i < n; i++) {
949 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
950 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
953 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter);
954 CSR_READ_4(sc, SIS_RXFILT_CTL);
958 sis_reset(struct sis_softc *sc)
962 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
964 for (i = 0; i < SIS_TIMEOUT; i++) {
965 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
969 if (i == SIS_TIMEOUT)
970 device_printf(sc->sis_dev, "reset never completed\n");
972 /* Wait a little while for the chip to get its brains in order. */
976 * If this is a NetSemi chip, make sure to clear
979 if (sc->sis_type == SIS_TYPE_83815) {
980 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
981 CSR_WRITE_4(sc, NS_CLKRUN, 0);
983 /* Disable WOL functions. */
984 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0);
989 * Probe for an SiS chip. Check the PCI vendor and device
990 * IDs against our list and return a device name if we find a match.
993 sis_probe(device_t dev)
999 while (t->sis_name != NULL) {
1000 if ((pci_get_vendor(dev) == t->sis_vid) &&
1001 (pci_get_device(dev) == t->sis_did)) {
1002 device_set_desc(dev, t->sis_name);
1003 return (BUS_PROBE_DEFAULT);
1012 * Attach the interface. Allocate softc structures, do ifmedia
1013 * setup and ethernet/BPF attach.
1016 sis_attach(device_t dev)
1018 u_char eaddr[ETHER_ADDR_LEN];
1019 struct sis_softc *sc;
1021 int error = 0, pmc, waittime = 0;
1024 sc = device_get_softc(dev);
1028 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1030 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
1032 if (pci_get_device(dev) == SIS_DEVICEID_900)
1033 sc->sis_type = SIS_TYPE_900;
1034 if (pci_get_device(dev) == SIS_DEVICEID_7016)
1035 sc->sis_type = SIS_TYPE_7016;
1036 if (pci_get_vendor(dev) == NS_VENDORID)
1037 sc->sis_type = SIS_TYPE_83815;
1039 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
1041 * Map control/status registers.
1043 pci_enable_busmaster(dev);
1045 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
1047 device_printf(dev, "couldn't allocate resources\n");
1051 /* Reset the adapter. */
1054 if (sc->sis_type == SIS_TYPE_900 &&
1055 (sc->sis_rev == SIS_REV_635 ||
1056 sc->sis_rev == SIS_REV_900B)) {
1057 SIO_SET(SIS_CFG_RND_CNT);
1058 SIO_SET(SIS_CFG_PERR_DETECT);
1062 * Get station address from the EEPROM.
1064 switch (pci_get_vendor(dev)) {
1066 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
1068 /* We can't update the device description, so spew */
1069 if (sc->sis_srr == NS_SRR_15C)
1070 device_printf(dev, "Silicon Revision: DP83815C\n");
1071 else if (sc->sis_srr == NS_SRR_15D)
1072 device_printf(dev, "Silicon Revision: DP83815D\n");
1073 else if (sc->sis_srr == NS_SRR_16A)
1074 device_printf(dev, "Silicon Revision: DP83816A\n");
1076 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
1079 * Reading the MAC address out of the EEPROM on
1080 * the NatSemi chip takes a bit more work than
1081 * you'd expect. The address spans 4 16-bit words,
1082 * with the first word containing only a single bit.
1083 * You have to shift everything over one bit to
1084 * get it aligned properly. Also, the bits are
1085 * stored backwards (the LSB is really the MSB,
1086 * and so on) so you have to reverse them in order
1087 * to get the MAC address into the form we want.
1088 * Why? Who the hell knows.
1093 sis_read_eeprom(sc, (caddr_t)&tmp,
1094 NS_EE_NODEADDR, 4, 0);
1096 /* Shift everything over one bit. */
1097 tmp[3] = tmp[3] >> 1;
1098 tmp[3] |= tmp[2] << 15;
1099 tmp[2] = tmp[2] >> 1;
1100 tmp[2] |= tmp[1] << 15;
1101 tmp[1] = tmp[1] >> 1;
1102 tmp[1] |= tmp[0] << 15;
1104 /* Now reverse all the bits. */
1105 tmp[3] = sis_reverse(tmp[3]);
1106 tmp[2] = sis_reverse(tmp[2]);
1107 tmp[1] = sis_reverse(tmp[1]);
1109 eaddr[0] = (tmp[1] >> 0) & 0xFF;
1110 eaddr[1] = (tmp[1] >> 8) & 0xFF;
1111 eaddr[2] = (tmp[2] >> 0) & 0xFF;
1112 eaddr[3] = (tmp[2] >> 8) & 0xFF;
1113 eaddr[4] = (tmp[3] >> 0) & 0xFF;
1114 eaddr[5] = (tmp[3] >> 8) & 0xFF;
1119 #if defined(__i386__) || defined(__amd64__)
1121 * If this is a SiS 630E chipset with an embedded
1122 * SiS 900 controller, we have to read the MAC address
1123 * from the APC CMOS RAM. Our method for doing this
1124 * is very ugly since we have to reach out and grab
1125 * ahold of hardware for which we cannot properly
1126 * allocate resources. This code is only compiled on
1127 * the i386 architecture since the SiS 630E chipset
1128 * is for x86 motherboards only. Note that there are
1129 * a lot of magic numbers in this hack. These are
1130 * taken from SiS's Linux driver. I'd like to replace
1131 * them with proper symbolic definitions, but that
1132 * requires some datasheets that I don't have access
1135 if (sc->sis_rev == SIS_REV_630S ||
1136 sc->sis_rev == SIS_REV_630E ||
1137 sc->sis_rev == SIS_REV_630EA1)
1138 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1140 else if (sc->sis_rev == SIS_REV_635 ||
1141 sc->sis_rev == SIS_REV_630ET)
1142 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1143 else if (sc->sis_rev == SIS_REV_96x) {
1144 /* Allow to read EEPROM from LAN. It is shared
1145 * between a 1394 controller and the NIC and each
1146 * time we access it, we need to set SIS_EECMD_REQ.
1148 SIO_SET(SIS_EECMD_REQ);
1149 for (waittime = 0; waittime < SIS_TIMEOUT;
1151 /* Force EEPROM to idle state. */
1152 sis_eeprom_idle(sc);
1153 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1154 sis_read_eeprom(sc, (caddr_t)&eaddr,
1155 SIS_EE_NODEADDR, 3, 0);
1161 * Set SIS_EECTL_CLK to high, so a other master
1162 * can operate on the i2c bus.
1164 SIO_SET(SIS_EECTL_CLK);
1165 /* Refuse EEPROM access by LAN */
1166 SIO_SET(SIS_EECMD_DONE);
1169 sis_read_eeprom(sc, (caddr_t)&eaddr,
1170 SIS_EE_NODEADDR, 3, 0);
1174 sis_add_sysctls(sc);
1176 /* Allocate DMA'able memory. */
1177 if ((error = sis_dma_alloc(sc)) != 0)
1180 ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
1182 device_printf(dev, "can not if_alloc()\n");
1187 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1188 ifp->if_mtu = ETHERMTU;
1189 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1190 ifp->if_ioctl = sis_ioctl;
1191 ifp->if_start = sis_start;
1192 ifp->if_init = sis_init;
1193 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1194 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
1195 IFQ_SET_READY(&ifp->if_snd);
1197 if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
1198 if (sc->sis_type == SIS_TYPE_83815)
1199 ifp->if_capabilities |= IFCAP_WOL;
1201 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1202 ifp->if_capenable = ifp->if_capabilities;
1208 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd,
1209 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1211 device_printf(dev, "attaching PHYs failed\n");
1216 * Call MI attach routine.
1218 ether_ifattach(ifp, eaddr);
1221 * Tell the upper layer(s) we support long frames.
1223 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1224 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1225 ifp->if_capenable = ifp->if_capabilities;
1226 #ifdef DEVICE_POLLING
1227 ifp->if_capabilities |= IFCAP_POLLING;
1230 /* Hook interrupt last to avoid having to lock softc */
1231 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
1232 NULL, sis_intr, sc, &sc->sis_intrhand);
1235 device_printf(dev, "couldn't set up irq\n");
1236 ether_ifdetach(ifp);
1248 * Shutdown hardware and free up resources. This can be called any
1249 * time after the mutex has been initialized. It is called in both
1250 * the error case in attach and the normal detach case so it needs
1251 * to be careful about only freeing resources that have actually been
1255 sis_detach(device_t dev)
1257 struct sis_softc *sc;
1260 sc = device_get_softc(dev);
1261 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1264 #ifdef DEVICE_POLLING
1265 if (ifp->if_capenable & IFCAP_POLLING)
1266 ether_poll_deregister(ifp);
1269 /* These should only be active if attach succeeded. */
1270 if (device_is_attached(dev)) {
1274 callout_drain(&sc->sis_stat_ch);
1275 ether_ifdetach(ifp);
1278 device_delete_child(dev, sc->sis_miibus);
1279 bus_generic_detach(dev);
1281 if (sc->sis_intrhand)
1282 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
1283 bus_release_resources(dev, sis_res_spec, sc->sis_res);
1290 mtx_destroy(&sc->sis_mtx);
1295 struct sis_dmamap_arg {
1296 bus_addr_t sis_busaddr;
1300 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1302 struct sis_dmamap_arg *ctx;
1307 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1309 ctx = (struct sis_dmamap_arg *)arg;
1310 ctx->sis_busaddr = segs[0].ds_addr;
1314 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment,
1315 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
1316 bus_addr_t *paddr, const char *msg)
1318 struct sis_dmamap_arg ctx;
1321 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0,
1322 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1,
1323 maxsize, 0, NULL, NULL, tag);
1325 device_printf(sc->sis_dev,
1326 "could not create %s dma tag\n", msg);
1329 /* Allocate DMA'able memory for ring. */
1330 error = bus_dmamem_alloc(*tag, (void **)ring,
1331 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1333 device_printf(sc->sis_dev,
1334 "could not allocate DMA'able memory for %s\n", msg);
1337 /* Load the address of the ring. */
1338 ctx.sis_busaddr = 0;
1339 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb,
1340 &ctx, BUS_DMA_NOWAIT);
1342 device_printf(sc->sis_dev,
1343 "could not load DMA'able memory for %s\n", msg);
1346 *paddr = ctx.sis_busaddr;
1351 sis_dma_alloc(struct sis_softc *sc)
1353 struct sis_rxdesc *rxd;
1354 struct sis_txdesc *txd;
1357 /* Allocate the parent bus DMA tag appropriate for PCI. */
1358 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev),
1359 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1360 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
1361 0, NULL, NULL, &sc->sis_parent_tag);
1363 device_printf(sc->sis_dev,
1364 "could not allocate parent dma tag\n");
1368 /* Create RX ring. */
1369 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ,
1370 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list,
1371 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring");
1375 /* Create TX ring. */
1376 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ,
1377 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list,
1378 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring");
1382 /* Create tag for RX mbufs. */
1383 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0,
1384 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1385 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag);
1387 device_printf(sc->sis_dev, "could not allocate RX dma tag\n");
1391 /* Create tag for TX mbufs. */
1392 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0,
1393 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1394 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1397 device_printf(sc->sis_dev, "could not allocate TX dma tag\n");
1401 /* Create DMA maps for RX buffers. */
1402 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap);
1404 device_printf(sc->sis_dev,
1405 "can't create spare DMA map for RX\n");
1408 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1409 rxd = &sc->sis_rxdesc[i];
1411 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap);
1413 device_printf(sc->sis_dev,
1414 "can't create DMA map for RX\n");
1419 /* Create DMA maps for TX buffers. */
1420 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1421 txd = &sc->sis_txdesc[i];
1423 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap);
1425 device_printf(sc->sis_dev,
1426 "can't create DMA map for TX\n");
1435 sis_dma_free(struct sis_softc *sc)
1437 struct sis_rxdesc *rxd;
1438 struct sis_txdesc *txd;
1441 /* Destroy DMA maps for RX buffers. */
1442 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1443 rxd = &sc->sis_rxdesc[i];
1445 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap);
1447 if (sc->sis_rx_sparemap)
1448 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap);
1450 /* Destroy DMA maps for TX buffers. */
1451 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1452 txd = &sc->sis_txdesc[i];
1454 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap);
1458 bus_dma_tag_destroy(sc->sis_rx_tag);
1460 bus_dma_tag_destroy(sc->sis_tx_tag);
1462 /* Destroy RX ring. */
1463 if (sc->sis_rx_list_map)
1464 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map);
1465 if (sc->sis_rx_list_map && sc->sis_rx_list)
1466 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list,
1467 sc->sis_rx_list_map);
1469 if (sc->sis_rx_list_tag)
1470 bus_dma_tag_destroy(sc->sis_rx_list_tag);
1472 /* Destroy TX ring. */
1473 if (sc->sis_tx_list_map)
1474 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map);
1476 if (sc->sis_tx_list_map && sc->sis_tx_list)
1477 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list,
1478 sc->sis_tx_list_map);
1480 if (sc->sis_tx_list_tag)
1481 bus_dma_tag_destroy(sc->sis_tx_list_tag);
1483 /* Destroy the parent tag. */
1484 if (sc->sis_parent_tag)
1485 bus_dma_tag_destroy(sc->sis_parent_tag);
1489 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
1490 * we arrange the descriptors in a closed ring, so that the last descriptor
1491 * points back to the first.
1494 sis_ring_init(struct sis_softc *sc)
1496 struct sis_rxdesc *rxd;
1497 struct sis_txdesc *txd;
1501 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ);
1502 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1503 txd = &sc->sis_txdesc[i];
1505 if (i == SIS_TX_LIST_CNT - 1)
1506 next = SIS_TX_RING_ADDR(sc, 0);
1508 next = SIS_TX_RING_ADDR(sc, i + 1);
1509 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next));
1511 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
1512 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1513 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1515 sc->sis_rx_cons = 0;
1516 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ);
1517 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1518 rxd = &sc->sis_rxdesc[i];
1519 rxd->rx_desc = &sc->sis_rx_list[i];
1520 if (i == SIS_RX_LIST_CNT - 1)
1521 next = SIS_RX_RING_ADDR(sc, 0);
1523 next = SIS_RX_RING_ADDR(sc, i + 1);
1524 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next));
1525 error = sis_newbuf(sc, rxd);
1529 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1530 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1536 * Initialize an RX descriptor and attach an MBUF cluster.
1539 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd)
1542 bus_dma_segment_t segs[1];
1546 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1549 m->m_len = m->m_pkthdr.len = SIS_RXLEN;
1550 #ifndef __NO_STRICT_ALIGNMENT
1551 m_adj(m, SIS_RX_BUF_ALIGN);
1554 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m,
1555 segs, &nsegs, 0) != 0) {
1559 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1561 if (rxd->rx_m != NULL) {
1562 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
1563 BUS_DMASYNC_POSTREAD);
1564 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
1566 map = rxd->rx_dmamap;
1567 rxd->rx_dmamap = sc->sis_rx_sparemap;
1568 sc->sis_rx_sparemap = map;
1569 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD);
1571 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1572 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr));
1576 static __inline void
1577 sis_discard_rxbuf(struct sis_rxdesc *rxd)
1580 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1583 #ifndef __NO_STRICT_ALIGNMENT
1584 static __inline void
1585 sis_fixup_rx(struct mbuf *m)
1587 uint16_t *src, *dst;
1590 src = mtod(m, uint16_t *);
1591 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src);
1593 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1596 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN;
1601 * A frame has been uploaded: pass the resulting mbuf chain up to
1602 * the higher level protocols.
1605 sis_rxeof(struct sis_softc *sc)
1609 struct sis_rxdesc *rxd;
1610 struct sis_desc *cur_rx;
1611 int prog, rx_cons, rx_npkts = 0, total_len;
1614 SIS_LOCK_ASSERT(sc);
1616 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1617 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1619 rx_cons = sc->sis_rx_cons;
1622 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
1623 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) {
1624 #ifdef DEVICE_POLLING
1625 if (ifp->if_capenable & IFCAP_POLLING) {
1626 if (sc->rxcycles <= 0)
1631 cur_rx = &sc->sis_rx_list[rx_cons];
1632 rxstat = le32toh(cur_rx->sis_cmdsts);
1633 if ((rxstat & SIS_CMDSTS_OWN) == 0)
1635 rxd = &sc->sis_rxdesc[rx_cons];
1637 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN;
1638 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 &&
1639 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN -
1641 rxstat &= ~SIS_RXSTAT_GIANT;
1642 if (SIS_RXSTAT_ERROR(rxstat) != 0) {
1644 if (rxstat & SIS_RXSTAT_COLL)
1645 ifp->if_collisions++;
1646 sis_discard_rxbuf(rxd);
1650 /* Add a new receive buffer to the ring. */
1652 if (sis_newbuf(sc, rxd) != 0) {
1654 sis_discard_rxbuf(rxd);
1658 /* No errors; receive the packet. */
1659 m->m_pkthdr.len = m->m_len = total_len;
1660 #ifndef __NO_STRICT_ALIGNMENT
1662 * On architectures without alignment problems we try to
1663 * allocate a new buffer for the receive ring, and pass up
1664 * the one where the packet is already, saving the expensive
1670 m->m_pkthdr.rcvif = ifp;
1673 (*ifp->if_input)(ifp, m);
1679 sc->sis_rx_cons = rx_cons;
1680 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1681 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1688 * A frame was downloaded to the chip. It's safe for us to clean up
1693 sis_txeof(struct sis_softc *sc)
1696 struct sis_desc *cur_tx;
1697 struct sis_txdesc *txd;
1698 uint32_t cons, txstat;
1700 SIS_LOCK_ASSERT(sc);
1702 cons = sc->sis_tx_cons;
1703 if (cons == sc->sis_tx_prod)
1707 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1708 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1711 * Go through our tx list and free mbufs for those
1712 * frames that have been transmitted.
1714 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) {
1715 cur_tx = &sc->sis_tx_list[cons];
1716 txstat = le32toh(cur_tx->sis_cmdsts);
1717 if ((txstat & SIS_CMDSTS_OWN) != 0)
1719 txd = &sc->sis_txdesc[cons];
1720 if (txd->tx_m != NULL) {
1721 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
1722 BUS_DMASYNC_POSTWRITE);
1723 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1726 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) {
1728 ifp->if_collisions +=
1729 (txstat & SIS_TXSTAT_COLLCNT) >> 16;
1732 if (txstat & SIS_TXSTAT_EXCESSCOLLS)
1733 ifp->if_collisions++;
1734 if (txstat & SIS_TXSTAT_OUTOFWINCOLL)
1735 ifp->if_collisions++;
1739 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1741 sc->sis_tx_cons = cons;
1742 if (sc->sis_tx_cnt == 0)
1743 sc->sis_watchdog_timer = 0;
1749 struct sis_softc *sc;
1750 struct mii_data *mii;
1754 SIS_LOCK_ASSERT(sc);
1757 mii = device_get_softc(sc->sis_miibus);
1760 if ((sc->sis_flags & SIS_FLAG_LINK) == 0)
1761 sis_miibus_statchg(sc->sis_dev);
1762 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1765 #ifdef DEVICE_POLLING
1766 static poll_handler_t sis_poll;
1769 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1771 struct sis_softc *sc = ifp->if_softc;
1775 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1781 * On the sis, reading the status register also clears it.
1782 * So before returning to intr mode we must make sure that all
1783 * possible pending sources of interrupts have been served.
1784 * In practice this means run to completion the *eof routines,
1785 * and then call the interrupt routine
1787 sc->rxcycles = count;
1788 rx_npkts = sis_rxeof(sc);
1790 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1793 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1796 /* Reading the ISR register clears all interrupts. */
1797 status = CSR_READ_4(sc, SIS_ISR);
1799 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1802 if (status & (SIS_ISR_RX_IDLE))
1803 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1805 if (status & SIS_ISR_SYSERR) {
1806 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1814 #endif /* DEVICE_POLLING */
1819 struct sis_softc *sc;
1827 #ifdef DEVICE_POLLING
1828 if (ifp->if_capenable & IFCAP_POLLING) {
1834 /* Reading the ISR register clears all interrupts. */
1835 status = CSR_READ_4(sc, SIS_ISR);
1836 if ((status & SIS_INTRS) == 0) {
1842 /* Disable interrupts. */
1843 CSR_WRITE_4(sc, SIS_IER, 0);
1845 for (;(status & SIS_INTRS) != 0;) {
1846 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1849 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1850 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1853 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK |
1854 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE))
1857 if (status & SIS_ISR_RX_OFLOW)
1860 if (status & (SIS_ISR_RX_IDLE))
1861 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1863 if (status & SIS_ISR_SYSERR) {
1864 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1869 status = CSR_READ_4(sc, SIS_ISR);
1872 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1873 /* Re-enable interrupts. */
1874 CSR_WRITE_4(sc, SIS_IER, 1);
1876 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1884 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1885 * pointers to the fragment pointers.
1888 sis_encap(struct sis_softc *sc, struct mbuf **m_head)
1891 struct sis_txdesc *txd;
1893 bus_dma_segment_t segs[SIS_MAXTXSEGS];
1895 int error, i, frag, nsegs, prod;
1898 prod = sc->sis_tx_prod;
1899 txd = &sc->sis_txdesc[prod];
1900 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 &&
1901 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) {
1903 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len;
1904 if (M_WRITABLE(m) == 0) {
1905 /* Get a writable copy. */
1906 m = m_dup(*m_head, M_DONTWAIT);
1914 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
1915 m = m_defrag(m, M_DONTWAIT);
1923 * Manually pad short frames, and zero the pad space
1924 * to avoid leaking data.
1926 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1927 m->m_pkthdr.len += padlen;
1928 m->m_len = m->m_pkthdr.len;
1931 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1932 *m_head, segs, &nsegs, 0);
1933 if (error == EFBIG) {
1934 m = m_collapse(*m_head, M_DONTWAIT, SIS_MAXTXSEGS);
1941 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1942 *m_head, segs, &nsegs, 0);
1948 } else if (error != 0)
1951 /* Check for descriptor overruns. */
1952 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) {
1953 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1957 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE);
1960 for (i = 0; i < nsegs; i++) {
1961 f = &sc->sis_tx_list[prod];
1963 f->sis_cmdsts = htole32(segs[i].ds_len |
1966 f->sis_cmdsts = htole32(segs[i].ds_len |
1967 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE);
1968 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr));
1969 SIS_INC(prod, SIS_TX_LIST_CNT);
1973 /* Update producer index. */
1974 sc->sis_tx_prod = prod;
1976 /* Remove MORE flag on the last descriptor. */
1977 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1);
1978 f = &sc->sis_tx_list[prod];
1979 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE);
1981 /* Lastly transfer ownership of packet to the controller. */
1982 f = &sc->sis_tx_list[frag];
1983 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN);
1985 /* Swap the last and the first dmamaps. */
1986 map = txd->tx_dmamap;
1987 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap;
1988 sc->sis_txdesc[prod].tx_dmamap = map;
1989 sc->sis_txdesc[prod].tx_m = *m_head;
1995 sis_start(struct ifnet *ifp)
1997 struct sis_softc *sc;
2006 sis_startl(struct ifnet *ifp)
2008 struct sis_softc *sc;
2009 struct mbuf *m_head;
2014 SIS_LOCK_ASSERT(sc);
2016 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2017 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0)
2020 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2021 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) {
2022 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2026 if (sis_encap(sc, &m_head) != 0) {
2029 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2030 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2037 * If there's a BPF listener, bounce a copy of this frame
2040 BPF_MTAP(ifp, m_head);
2045 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
2046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2047 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
2050 * Set a timeout in case the chip goes out to lunch.
2052 sc->sis_watchdog_timer = 5;
2059 struct sis_softc *sc = xsc;
2067 sis_initl(struct sis_softc *sc)
2069 struct ifnet *ifp = sc->sis_ifp;
2070 struct mii_data *mii;
2073 SIS_LOCK_ASSERT(sc);
2075 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2079 * Cancel pending I/O and free all RX/TX buffers.
2083 * Reset the chip to a known state.
2087 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
2089 * Configure 400usec of interrupt holdoff. This is based
2090 * on emperical tests on a Soekris 4801.
2092 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
2096 mii = device_get_softc(sc->sis_miibus);
2098 /* Set MAC address */
2099 eaddr = IF_LLADDR(sc->sis_ifp);
2100 if (sc->sis_type == SIS_TYPE_83815) {
2101 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
2102 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
2103 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
2104 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
2105 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
2106 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
2108 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
2109 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
2110 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
2111 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
2112 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
2113 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
2116 /* Init circular TX/RX lists. */
2117 if (sis_ring_init(sc) != 0) {
2118 device_printf(sc->sis_dev,
2119 "initialization failed: no memory for rx buffers\n");
2124 if (sc->sis_type == SIS_TYPE_83815 || sc->sis_type == SIS_TYPE_83816) {
2125 if (sc->sis_manual_pad != 0)
2126 sc->sis_flags |= SIS_FLAG_MANUAL_PAD;
2128 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD;
2132 * Short Cable Receive Errors (MP21.E)
2133 * also: Page 78 of the DP83815 data sheet (september 2002 version)
2134 * recommends the following register settings "for optimum
2135 * performance." for rev 15C. Set this also for 15D parts as
2136 * they require it in practice.
2138 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
2139 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2140 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2141 /* set val for c2 */
2142 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2144 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2145 /* rais SD off, from 4 to c */
2146 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2147 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2151 /* Turn the receive filter on */
2152 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
2155 * Load the address of the RX and TX lists.
2157 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr));
2158 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr));
2160 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
2161 * the PCI bus. When this bit is set, the Max DMA Burst Size
2162 * for TX/RX DMA should be no larger than 16 double words.
2164 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
2165 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
2167 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
2170 /* Accept Long Packets for VLAN support */
2171 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
2174 * Assume 100Mbps link, actual MAC configuration is done
2175 * after getting a valid link.
2177 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
2180 * Enable interrupts.
2182 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2183 #ifdef DEVICE_POLLING
2185 * ... only enable interrupts if we are not polling, make sure
2186 * they are off otherwise.
2188 if (ifp->if_capenable & IFCAP_POLLING)
2189 CSR_WRITE_4(sc, SIS_IER, 0);
2192 CSR_WRITE_4(sc, SIS_IER, 1);
2194 /* Clear MAC disable. */
2195 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
2197 sc->sis_flags &= ~SIS_FLAG_LINK;
2200 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2201 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2203 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2207 * Set media options.
2210 sis_ifmedia_upd(struct ifnet *ifp)
2212 struct sis_softc *sc;
2213 struct mii_data *mii;
2219 mii = device_get_softc(sc->sis_miibus);
2220 if (mii->mii_instance) {
2221 struct mii_softc *miisc;
2222 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2223 mii_phy_reset(miisc);
2225 error = mii_mediachg(mii);
2232 * Report current media status.
2235 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2237 struct sis_softc *sc;
2238 struct mii_data *mii;
2243 mii = device_get_softc(sc->sis_miibus);
2246 ifmr->ifm_active = mii->mii_media_active;
2247 ifmr->ifm_status = mii->mii_media_status;
2251 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2253 struct sis_softc *sc = ifp->if_softc;
2254 struct ifreq *ifr = (struct ifreq *) data;
2255 struct mii_data *mii;
2256 int error = 0, mask;
2261 if (ifp->if_flags & IFF_UP) {
2262 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2263 ((ifp->if_flags ^ sc->sis_if_flags) &
2264 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2268 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2270 sc->sis_if_flags = ifp->if_flags;
2281 mii = device_get_softc(sc->sis_miibus);
2282 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2286 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2287 #ifdef DEVICE_POLLING
2288 if ((mask & IFCAP_POLLING) != 0 &&
2289 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
2290 ifp->if_capenable ^= IFCAP_POLLING;
2291 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
2292 error = ether_poll_register(sis_poll, ifp);
2297 /* Disable interrupts. */
2298 CSR_WRITE_4(sc, SIS_IER, 0);
2300 error = ether_poll_deregister(ifp);
2301 /* Enable interrupts. */
2302 CSR_WRITE_4(sc, SIS_IER, 1);
2305 #endif /* DEVICE_POLLING */
2306 if ((mask & IFCAP_WOL) != 0 &&
2307 (ifp->if_capabilities & IFCAP_WOL) != 0) {
2308 if ((mask & IFCAP_WOL_UCAST) != 0)
2309 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2310 if ((mask & IFCAP_WOL_MCAST) != 0)
2311 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2312 if ((mask & IFCAP_WOL_MAGIC) != 0)
2313 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2318 error = ether_ioctl(ifp, command, data);
2326 sis_watchdog(struct sis_softc *sc)
2329 SIS_LOCK_ASSERT(sc);
2331 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
2334 device_printf(sc->sis_dev, "watchdog timeout\n");
2335 sc->sis_ifp->if_oerrors++;
2337 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2340 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd))
2341 sis_startl(sc->sis_ifp);
2345 * Stop the adapter and free any mbufs allocated to the
2349 sis_stop(struct sis_softc *sc)
2352 struct sis_rxdesc *rxd;
2353 struct sis_txdesc *txd;
2356 SIS_LOCK_ASSERT(sc);
2359 sc->sis_watchdog_timer = 0;
2361 callout_stop(&sc->sis_stat_ch);
2363 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2364 CSR_WRITE_4(sc, SIS_IER, 0);
2365 CSR_WRITE_4(sc, SIS_IMR, 0);
2366 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
2367 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2369 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2370 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2372 sc->sis_flags &= ~SIS_FLAG_LINK;
2375 * Free data in the RX lists.
2377 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2378 rxd = &sc->sis_rxdesc[i];
2379 if (rxd->rx_m != NULL) {
2380 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
2381 BUS_DMASYNC_POSTREAD);
2382 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
2389 * Free the TX list buffers.
2391 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2392 txd = &sc->sis_txdesc[i];
2393 if (txd->tx_m != NULL) {
2394 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
2395 BUS_DMASYNC_POSTWRITE);
2396 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
2404 * Stop all chip I/O so that the kernel's probe routines don't
2405 * get confused by errant DMAs when rebooting.
2408 sis_shutdown(device_t dev)
2411 return (sis_suspend(dev));
2415 sis_suspend(device_t dev)
2417 struct sis_softc *sc;
2419 sc = device_get_softc(dev);
2428 sis_resume(device_t dev)
2430 struct sis_softc *sc;
2433 sc = device_get_softc(dev);
2436 if ((ifp->if_flags & IFF_UP) != 0) {
2437 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2445 sis_wol(struct sis_softc *sc)
2453 if ((ifp->if_capenable & IFCAP_WOL) == 0)
2456 if (sc->sis_type == SIS_TYPE_83815) {
2458 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2460 /* Configure WOL events. */
2461 CSR_READ_4(sc, NS_WCSR);
2463 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2464 val |= NS_WCSR_WAKE_UCAST;
2465 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2466 val |= NS_WCSR_WAKE_MCAST;
2467 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2468 val |= NS_WCSR_WAKE_MAGIC;
2469 CSR_WRITE_4(sc, NS_WCSR, val);
2470 /* Enable PME and clear PMESTS. */
2471 val = CSR_READ_4(sc, NS_CLKRUN);
2472 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS;
2473 CSR_WRITE_4(sc, NS_CLKRUN, val);
2474 /* Enable silent RX mode. */
2475 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2477 if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
2480 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2481 val |= SIS_PWRMAN_WOL_MAGIC;
2482 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val);
2484 pmstat = pci_read_config(sc->sis_dev,
2485 pmc + PCIR_POWER_STATUS, 2);
2486 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2487 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2488 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2489 pci_write_config(sc->sis_dev,
2490 pmc + PCIR_POWER_STATUS, pmstat, 2);
2495 sis_add_sysctls(struct sis_softc *sc)
2497 struct sysctl_ctx_list *ctx;
2498 struct sysctl_oid_list *children;
2502 ctx = device_get_sysctl_ctx(sc->sis_dev);
2503 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev));
2505 unit = device_get_unit(sc->sis_dev);
2507 * Unlike most other controllers, NS DP83815/DP83816 controllers
2508 * seem to pad with 0xFF when it encounter short frames. According
2509 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable
2510 * on will have driver pad manully but it's disabled by default
2511 * because it will consume extra CPU cycles for short frames.
2513 sc->sis_manual_pad = 0;
2514 snprintf(tn, sizeof(tn), "dev.sis.%d.manual_pad", unit);
2515 TUNABLE_INT_FETCH(tn, &sc->sis_manual_pad);
2516 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad",
2517 CTLFLAG_RW, &sc->sis_manual_pad, 0, "Manually pad short frames");
2520 static device_method_t sis_methods[] = {
2521 /* Device interface */
2522 DEVMETHOD(device_probe, sis_probe),
2523 DEVMETHOD(device_attach, sis_attach),
2524 DEVMETHOD(device_detach, sis_detach),
2525 DEVMETHOD(device_shutdown, sis_shutdown),
2526 DEVMETHOD(device_suspend, sis_suspend),
2527 DEVMETHOD(device_resume, sis_resume),
2530 DEVMETHOD(bus_print_child, bus_generic_print_child),
2531 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
2534 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
2535 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
2536 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
2541 static driver_t sis_driver = {
2544 sizeof(struct sis_softc)
2547 static devclass_t sis_devclass;
2549 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
2550 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);