2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
5 * Copyright (c) 1997, 1998, 1999
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
41 * available from http://www.sis.com.tw.
43 * This driver also supports the NatSemi DP83815. Datasheets are
44 * available from http://www.national.com.
46 * Written by Bill Paul <wpaul@ee.columbia.edu>
47 * Electrical Engineering Department
48 * Columbia University, New York City
51 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
52 * simple TX and RX descriptors of 3 longwords in size. The receiver
53 * has a single perfect filter entry for the station address and a
54 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
55 * transceiver while the 7016 requires an external transceiver chip.
56 * Both chips offer the standard bit-bang MII interface as well as
57 * an enchanced PHY interface which simplifies accessing MII registers.
59 * The only downside to this chipset is that RX descriptors must be
63 #ifdef HAVE_KERNEL_OPTION_HEADERS
64 #include "opt_device_polling.h"
67 #include <sys/param.h>
68 #include <sys/systm.h>
70 #include <sys/endian.h>
71 #include <sys/kernel.h>
73 #include <sys/malloc.h>
75 #include <sys/module.h>
76 #include <sys/socket.h>
77 #include <sys/sockio.h>
78 #include <sys/sysctl.h>
81 #include <net/if_var.h>
82 #include <net/if_arp.h>
83 #include <net/ethernet.h>
84 #include <net/if_dl.h>
85 #include <net/if_media.h>
86 #include <net/if_types.h>
87 #include <net/if_vlan_var.h>
91 #include <machine/bus.h>
92 #include <machine/resource.h>
95 #include <dev/mii/mii.h>
96 #include <dev/mii/mii_bitbang.h>
97 #include <dev/mii/miivar.h>
99 #include <dev/pci/pcireg.h>
100 #include <dev/pci/pcivar.h>
102 #define SIS_USEIOSPACE
104 #include <dev/sis/if_sisreg.h>
106 MODULE_DEPEND(sis, pci, 1, 1, 1);
107 MODULE_DEPEND(sis, ether, 1, 1, 1);
108 MODULE_DEPEND(sis, miibus, 1, 1, 1);
110 /* "device miibus" required. See GENERIC if you get errors here. */
111 #include "miibus_if.h"
113 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
114 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
115 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
118 * register space access macros
120 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
122 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
124 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
126 #define CSR_BARRIER(sc, reg, length, flags) \
127 bus_barrier(sc->sis_res[0], reg, length, flags)
130 * Various supported device vendors/types and their names.
132 static const struct sis_type sis_devs[] = {
133 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
134 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
135 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
139 static int sis_detach(device_t);
140 static __inline void sis_discard_rxbuf(struct sis_rxdesc *);
141 static int sis_dma_alloc(struct sis_softc *);
142 static void sis_dma_free(struct sis_softc *);
143 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t,
144 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
145 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int);
146 #ifndef __NO_STRICT_ALIGNMENT
147 static __inline void sis_fixup_rx(struct mbuf *);
149 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
150 static int sis_ifmedia_upd(struct ifnet *);
151 static void sis_init(void *);
152 static void sis_initl(struct sis_softc *);
153 static void sis_intr(void *);
154 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
155 static uint32_t sis_mii_bitbang_read(device_t);
156 static void sis_mii_bitbang_write(device_t, uint32_t);
157 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
158 static int sis_resume(device_t);
159 static int sis_rxeof(struct sis_softc *);
160 static void sis_rxfilter(struct sis_softc *);
161 static void sis_rxfilter_ns(struct sis_softc *);
162 static void sis_rxfilter_sis(struct sis_softc *);
163 static void sis_start(struct ifnet *);
164 static void sis_startl(struct ifnet *);
165 static void sis_stop(struct sis_softc *);
166 static int sis_suspend(device_t);
167 static void sis_add_sysctls(struct sis_softc *);
168 static void sis_watchdog(struct sis_softc *);
169 static void sis_wol(struct sis_softc *);
174 static const struct mii_bitbang_ops sis_mii_bitbang_ops = {
175 sis_mii_bitbang_read,
176 sis_mii_bitbang_write,
178 SIS_MII_DATA, /* MII_BIT_MDO */
179 SIS_MII_DATA, /* MII_BIT_MDI */
180 SIS_MII_CLK, /* MII_BIT_MDC */
181 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
182 0, /* MII_BIT_DIR_PHY_HOST */
186 static struct resource_spec sis_res_spec[] = {
187 #ifdef SIS_USEIOSPACE
188 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE},
190 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE},
192 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
196 #define SIS_SETBIT(sc, reg, x) \
197 CSR_WRITE_4(sc, reg, \
198 CSR_READ_4(sc, reg) | (x))
200 #define SIS_CLRBIT(sc, reg, x) \
201 CSR_WRITE_4(sc, reg, \
202 CSR_READ_4(sc, reg) & ~(x))
205 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
208 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
211 * Routine to reverse the bits in a word. Stolen almost
212 * verbatim from /usr/games/fortune.
215 sis_reverse(uint16_t n)
217 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
218 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
219 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
220 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
226 sis_delay(struct sis_softc *sc)
230 for (idx = (300 / 33) + 1; idx > 0; idx--)
231 CSR_READ_4(sc, SIS_CSR);
235 sis_eeprom_idle(struct sis_softc *sc)
239 SIO_SET(SIS_EECTL_CSEL);
241 SIO_SET(SIS_EECTL_CLK);
244 for (i = 0; i < 25; i++) {
245 SIO_CLR(SIS_EECTL_CLK);
247 SIO_SET(SIS_EECTL_CLK);
251 SIO_CLR(SIS_EECTL_CLK);
253 SIO_CLR(SIS_EECTL_CSEL);
255 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
259 * Send a read command and address to the EEPROM, check for ACK.
262 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
266 d = addr | SIS_EECMD_READ;
269 * Feed in each bit and stobe the clock.
271 for (i = 0x400; i; i >>= 1) {
273 SIO_SET(SIS_EECTL_DIN);
275 SIO_CLR(SIS_EECTL_DIN);
278 SIO_SET(SIS_EECTL_CLK);
280 SIO_CLR(SIS_EECTL_CLK);
286 * Read a word of data stored in the EEPROM at address 'addr.'
289 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
294 /* Force EEPROM to idle state. */
297 /* Enter EEPROM access mode. */
299 SIO_CLR(SIS_EECTL_CLK);
301 SIO_SET(SIS_EECTL_CSEL);
305 * Send address of word we want to read.
307 sis_eeprom_putbyte(sc, addr);
310 * Start reading bits from EEPROM.
312 for (i = 0x8000; i; i >>= 1) {
313 SIO_SET(SIS_EECTL_CLK);
315 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
318 SIO_CLR(SIS_EECTL_CLK);
322 /* Turn off EEPROM access mode. */
329 * Read a sequence of words from the EEPROM.
332 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
335 uint16_t word = 0, *ptr;
337 for (i = 0; i < cnt; i++) {
338 sis_eeprom_getword(sc, off + i, &word);
339 ptr = (uint16_t *)(dest + (i * 2));
347 #if defined(__i386__) || defined(__amd64__)
349 sis_find_bridge(device_t dev)
351 devclass_t pci_devclass;
352 device_t *pci_devices;
354 device_t *pci_children;
355 int pci_childcount = 0;
356 device_t *busp, *childp;
357 device_t child = NULL;
360 if ((pci_devclass = devclass_find("pci")) == NULL)
363 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
365 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
366 if (device_get_children(*busp, &pci_children, &pci_childcount))
368 for (j = 0, childp = pci_children;
369 j < pci_childcount; j++, childp++) {
370 if (pci_get_vendor(*childp) == SIS_VENDORID &&
371 pci_get_device(*childp) == 0x0008) {
373 free(pci_children, M_TEMP);
377 free(pci_children, M_TEMP);
381 free(pci_devices, M_TEMP);
386 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
391 bus_space_tag_t btag;
393 bridge = sis_find_bridge(dev);
396 reg = pci_read_config(bridge, 0x48, 1);
397 pci_write_config(bridge, 0x48, reg|0x40, 1);
400 #if defined(__amd64__) || defined(__i386__)
401 btag = X86_BUS_SPACE_IO;
404 for (i = 0; i < cnt; i++) {
405 bus_space_write_1(btag, 0x0, 0x70, i + off);
406 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
409 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
413 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
415 uint32_t filtsave, csrsave;
417 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
418 csrsave = CSR_READ_4(sc, SIS_CSR);
420 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
421 CSR_WRITE_4(sc, SIS_CSR, 0);
423 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
425 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
426 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
427 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
428 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
430 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
432 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
433 CSR_WRITE_4(sc, SIS_CSR, csrsave);
438 * Read the MII serial port for the MII bit-bang module.
441 sis_mii_bitbang_read(device_t dev)
443 struct sis_softc *sc;
446 sc = device_get_softc(dev);
448 val = CSR_READ_4(sc, SIS_EECTL);
449 CSR_BARRIER(sc, SIS_EECTL, 4,
450 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
455 * Write the MII serial port for the MII bit-bang module.
458 sis_mii_bitbang_write(device_t dev, uint32_t val)
460 struct sis_softc *sc;
462 sc = device_get_softc(dev);
464 CSR_WRITE_4(sc, SIS_EECTL, val);
465 CSR_BARRIER(sc, SIS_EECTL, 4,
466 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
470 sis_miibus_readreg(device_t dev, int phy, int reg)
472 struct sis_softc *sc;
474 sc = device_get_softc(dev);
476 if (sc->sis_type == SIS_TYPE_83815) {
480 * The NatSemi chip can take a while after
481 * a reset to come ready, during which the BMSR
482 * returns a value of 0. This is *never* supposed
483 * to happen: some of the BMSR bits are meant to
484 * be hardwired in the on position, and this can
485 * confuse the miibus code a bit during the probe
486 * and attach phase. So we make an effort to check
487 * for this condition and wait for it to clear.
489 if (!CSR_READ_4(sc, NS_BMSR))
491 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
495 * Chipsets < SIS_635 seem not to be able to read/write
496 * through mdio. Use the enhanced PHY access register
499 if (sc->sis_type == SIS_TYPE_900 &&
500 sc->sis_rev < SIS_REV_635) {
506 CSR_WRITE_4(sc, SIS_PHYCTL,
507 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
508 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
510 for (i = 0; i < SIS_TIMEOUT; i++) {
511 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
515 if (i == SIS_TIMEOUT) {
516 device_printf(sc->sis_dev,
517 "PHY failed to come ready\n");
521 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
528 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy,
533 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
535 struct sis_softc *sc;
537 sc = device_get_softc(dev);
539 if (sc->sis_type == SIS_TYPE_83815) {
542 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
547 * Chipsets < SIS_635 seem not to be able to read/write
548 * through mdio. Use the enhanced PHY access register
551 if (sc->sis_type == SIS_TYPE_900 &&
552 sc->sis_rev < SIS_REV_635) {
558 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
559 (reg << 6) | SIS_PHYOP_WRITE);
560 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
562 for (i = 0; i < SIS_TIMEOUT; i++) {
563 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
567 if (i == SIS_TIMEOUT)
568 device_printf(sc->sis_dev,
569 "PHY failed to come ready\n");
571 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg,
577 sis_miibus_statchg(device_t dev)
579 struct sis_softc *sc;
580 struct mii_data *mii;
584 sc = device_get_softc(dev);
587 mii = device_get_softc(sc->sis_miibus);
589 if (mii == NULL || ifp == NULL ||
590 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
593 sc->sis_flags &= ~SIS_FLAG_LINK;
594 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
595 (IFM_ACTIVE | IFM_AVALID)) {
596 switch (IFM_SUBTYPE(mii->mii_media_active)) {
598 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
599 sc->sis_flags |= SIS_FLAG_LINK;
602 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
603 sc->sis_flags |= SIS_FLAG_LINK;
610 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) {
612 * Stopping MACs seem to reset SIS_TX_LISTPTR and
613 * SIS_RX_LISTPTR which in turn requires resetting
614 * TX/RX buffers. So just don't do anything for
620 /* Set full/half duplex mode. */
621 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
622 SIS_SETBIT(sc, SIS_TX_CFG,
623 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
624 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
626 SIS_CLRBIT(sc, SIS_TX_CFG,
627 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
628 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
631 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
633 * MPII03.D: Half Duplex Excessive Collisions.
634 * Also page 49 in 83816 manual
636 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
639 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
640 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
642 * Short Cable Receive Errors (MP21.E)
644 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
645 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
646 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
648 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
649 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
650 device_printf(sc->sis_dev,
651 "Applying short cable fix (reg=%x)\n", reg);
652 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
653 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
655 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
657 /* Enable TX/RX MACs. */
658 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
659 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE);
663 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
667 /* Compute CRC for the address value. */
668 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
671 * return the filter bit position
673 * The NatSemi chip has a 512-bit filter, which is
674 * different than the SiS, so we special-case it.
676 if (sc->sis_type == SIS_TYPE_83815)
678 else if (sc->sis_rev >= SIS_REV_635 ||
679 sc->sis_rev == SIS_REV_900B)
686 sis_rxfilter(struct sis_softc *sc)
691 if (sc->sis_type == SIS_TYPE_83815)
694 sis_rxfilter_sis(sc);
698 sis_rxfilter_ns(struct sis_softc *sc)
701 struct ifmultiaddr *ifma;
702 uint32_t h, i, filter;
706 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
707 if (filter & SIS_RXFILTCTL_ENABLE) {
709 * Filter should be disabled to program other bits.
711 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
712 CSR_READ_4(sc, SIS_RXFILT_CTL);
714 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT |
715 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
716 SIS_RXFILTCTL_ALLMULTI);
718 if (ifp->if_flags & IFF_BROADCAST)
719 filter |= SIS_RXFILTCTL_BROAD;
721 * For the NatSemi chip, we have to explicitly enable the
722 * reception of ARP frames, as well as turn on the 'perfect
723 * match' filter where we store the station address, otherwise
724 * we won't receive unicasts meant for this host.
726 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT;
728 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
729 filter |= SIS_RXFILTCTL_ALLMULTI;
730 if (ifp->if_flags & IFF_PROMISC)
731 filter |= SIS_RXFILTCTL_ALLPHYS;
734 * We have to explicitly enable the multicast hash table
735 * on the NatSemi chip if we want to use it, which we do.
737 filter |= NS_RXFILTCTL_MCHASH;
739 /* first, zot all the existing hash bits */
740 for (i = 0; i < 32; i++) {
741 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
743 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
747 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
748 if (ifma->ifma_addr->sa_family != AF_LINK)
751 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
754 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
758 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
760 if_maddr_runlock(ifp);
763 /* Turn the receive filter on */
764 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
765 CSR_READ_4(sc, SIS_RXFILT_CTL);
769 sis_rxfilter_sis(struct sis_softc *sc)
772 struct ifmultiaddr *ifma;
773 uint32_t filter, h, i, n;
778 /* hash table size */
779 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
784 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
785 if (filter & SIS_RXFILTCTL_ENABLE) {
786 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
787 CSR_READ_4(sc, SIS_RXFILT_CTL);
789 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
790 SIS_RXFILTCTL_ALLMULTI);
791 if (ifp->if_flags & IFF_BROADCAST)
792 filter |= SIS_RXFILTCTL_BROAD;
794 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
795 filter |= SIS_RXFILTCTL_ALLMULTI;
796 if (ifp->if_flags & IFF_PROMISC)
797 filter |= SIS_RXFILTCTL_ALLPHYS;
798 for (i = 0; i < n; i++)
801 for (i = 0; i < n; i++)
805 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
806 if (ifma->ifma_addr->sa_family != AF_LINK)
809 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
810 hashes[h >> 4] |= 1 << (h & 0xf);
813 if_maddr_runlock(ifp);
815 filter |= SIS_RXFILTCTL_ALLMULTI;
816 for (i = 0; i < n; i++)
821 for (i = 0; i < n; i++) {
822 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
823 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
826 /* Turn the receive filter on */
827 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
828 CSR_READ_4(sc, SIS_RXFILT_CTL);
832 sis_reset(struct sis_softc *sc)
836 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
838 for (i = 0; i < SIS_TIMEOUT; i++) {
839 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
843 if (i == SIS_TIMEOUT)
844 device_printf(sc->sis_dev, "reset never completed\n");
846 /* Wait a little while for the chip to get its brains in order. */
850 * If this is a NetSemi chip, make sure to clear
853 if (sc->sis_type == SIS_TYPE_83815) {
854 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
855 CSR_WRITE_4(sc, NS_CLKRUN, 0);
857 /* Disable WOL functions. */
858 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0);
863 * Probe for an SiS chip. Check the PCI vendor and device
864 * IDs against our list and return a device name if we find a match.
867 sis_probe(device_t dev)
869 const struct sis_type *t;
873 while (t->sis_name != NULL) {
874 if ((pci_get_vendor(dev) == t->sis_vid) &&
875 (pci_get_device(dev) == t->sis_did)) {
876 device_set_desc(dev, t->sis_name);
877 return (BUS_PROBE_DEFAULT);
886 * Attach the interface. Allocate softc structures, do ifmedia
887 * setup and ethernet/BPF attach.
890 sis_attach(device_t dev)
892 u_char eaddr[ETHER_ADDR_LEN];
893 struct sis_softc *sc;
895 int error = 0, pmc, waittime = 0;
898 sc = device_get_softc(dev);
902 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
904 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
906 if (pci_get_device(dev) == SIS_DEVICEID_900)
907 sc->sis_type = SIS_TYPE_900;
908 if (pci_get_device(dev) == SIS_DEVICEID_7016)
909 sc->sis_type = SIS_TYPE_7016;
910 if (pci_get_vendor(dev) == NS_VENDORID)
911 sc->sis_type = SIS_TYPE_83815;
913 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
915 * Map control/status registers.
917 pci_enable_busmaster(dev);
919 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
921 device_printf(dev, "couldn't allocate resources\n");
925 /* Reset the adapter. */
928 if (sc->sis_type == SIS_TYPE_900 &&
929 (sc->sis_rev == SIS_REV_635 ||
930 sc->sis_rev == SIS_REV_900B)) {
931 SIO_SET(SIS_CFG_RND_CNT);
932 SIO_SET(SIS_CFG_PERR_DETECT);
936 * Get station address from the EEPROM.
938 switch (pci_get_vendor(dev)) {
940 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
942 /* We can't update the device description, so spew */
943 if (sc->sis_srr == NS_SRR_15C)
944 device_printf(dev, "Silicon Revision: DP83815C\n");
945 else if (sc->sis_srr == NS_SRR_15D)
946 device_printf(dev, "Silicon Revision: DP83815D\n");
947 else if (sc->sis_srr == NS_SRR_16A)
948 device_printf(dev, "Silicon Revision: DP83816A\n");
950 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
953 * Reading the MAC address out of the EEPROM on
954 * the NatSemi chip takes a bit more work than
955 * you'd expect. The address spans 4 16-bit words,
956 * with the first word containing only a single bit.
957 * You have to shift everything over one bit to
958 * get it aligned properly. Also, the bits are
959 * stored backwards (the LSB is really the MSB,
960 * and so on) so you have to reverse them in order
961 * to get the MAC address into the form we want.
962 * Why? Who the hell knows.
967 sis_read_eeprom(sc, (caddr_t)&tmp,
968 NS_EE_NODEADDR, 4, 0);
970 /* Shift everything over one bit. */
971 tmp[3] = tmp[3] >> 1;
972 tmp[3] |= tmp[2] << 15;
973 tmp[2] = tmp[2] >> 1;
974 tmp[2] |= tmp[1] << 15;
975 tmp[1] = tmp[1] >> 1;
976 tmp[1] |= tmp[0] << 15;
978 /* Now reverse all the bits. */
979 tmp[3] = sis_reverse(tmp[3]);
980 tmp[2] = sis_reverse(tmp[2]);
981 tmp[1] = sis_reverse(tmp[1]);
983 eaddr[0] = (tmp[1] >> 0) & 0xFF;
984 eaddr[1] = (tmp[1] >> 8) & 0xFF;
985 eaddr[2] = (tmp[2] >> 0) & 0xFF;
986 eaddr[3] = (tmp[2] >> 8) & 0xFF;
987 eaddr[4] = (tmp[3] >> 0) & 0xFF;
988 eaddr[5] = (tmp[3] >> 8) & 0xFF;
993 #if defined(__i386__) || defined(__amd64__)
995 * If this is a SiS 630E chipset with an embedded
996 * SiS 900 controller, we have to read the MAC address
997 * from the APC CMOS RAM. Our method for doing this
998 * is very ugly since we have to reach out and grab
999 * ahold of hardware for which we cannot properly
1000 * allocate resources. This code is only compiled on
1001 * the i386 architecture since the SiS 630E chipset
1002 * is for x86 motherboards only. Note that there are
1003 * a lot of magic numbers in this hack. These are
1004 * taken from SiS's Linux driver. I'd like to replace
1005 * them with proper symbolic definitions, but that
1006 * requires some datasheets that I don't have access
1009 if (sc->sis_rev == SIS_REV_630S ||
1010 sc->sis_rev == SIS_REV_630E ||
1011 sc->sis_rev == SIS_REV_630EA1)
1012 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1014 else if (sc->sis_rev == SIS_REV_635 ||
1015 sc->sis_rev == SIS_REV_630ET)
1016 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1017 else if (sc->sis_rev == SIS_REV_96x) {
1018 /* Allow to read EEPROM from LAN. It is shared
1019 * between a 1394 controller and the NIC and each
1020 * time we access it, we need to set SIS_EECMD_REQ.
1022 SIO_SET(SIS_EECMD_REQ);
1023 for (waittime = 0; waittime < SIS_TIMEOUT;
1025 /* Force EEPROM to idle state. */
1026 sis_eeprom_idle(sc);
1027 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1028 sis_read_eeprom(sc, (caddr_t)&eaddr,
1029 SIS_EE_NODEADDR, 3, 0);
1035 * Set SIS_EECTL_CLK to high, so a other master
1036 * can operate on the i2c bus.
1038 SIO_SET(SIS_EECTL_CLK);
1039 /* Refuse EEPROM access by LAN */
1040 SIO_SET(SIS_EECMD_DONE);
1043 sis_read_eeprom(sc, (caddr_t)&eaddr,
1044 SIS_EE_NODEADDR, 3, 0);
1048 sis_add_sysctls(sc);
1050 /* Allocate DMA'able memory. */
1051 if ((error = sis_dma_alloc(sc)) != 0)
1054 ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
1056 device_printf(dev, "can not if_alloc()\n");
1061 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1062 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1063 ifp->if_ioctl = sis_ioctl;
1064 ifp->if_start = sis_start;
1065 ifp->if_init = sis_init;
1066 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1067 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
1068 IFQ_SET_READY(&ifp->if_snd);
1070 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
1071 if (sc->sis_type == SIS_TYPE_83815)
1072 ifp->if_capabilities |= IFCAP_WOL;
1074 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1075 ifp->if_capenable = ifp->if_capabilities;
1081 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd,
1082 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1084 device_printf(dev, "attaching PHYs failed\n");
1089 * Call MI attach routine.
1091 ether_ifattach(ifp, eaddr);
1094 * Tell the upper layer(s) we support long frames.
1096 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1097 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1098 ifp->if_capenable = ifp->if_capabilities;
1099 #ifdef DEVICE_POLLING
1100 ifp->if_capabilities |= IFCAP_POLLING;
1103 /* Hook interrupt last to avoid having to lock softc */
1104 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
1105 NULL, sis_intr, sc, &sc->sis_intrhand);
1108 device_printf(dev, "couldn't set up irq\n");
1109 ether_ifdetach(ifp);
1121 * Shutdown hardware and free up resources. This can be called any
1122 * time after the mutex has been initialized. It is called in both
1123 * the error case in attach and the normal detach case so it needs
1124 * to be careful about only freeing resources that have actually been
1128 sis_detach(device_t dev)
1130 struct sis_softc *sc;
1133 sc = device_get_softc(dev);
1134 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1137 #ifdef DEVICE_POLLING
1138 if (ifp->if_capenable & IFCAP_POLLING)
1139 ether_poll_deregister(ifp);
1142 /* These should only be active if attach succeeded. */
1143 if (device_is_attached(dev)) {
1147 callout_drain(&sc->sis_stat_ch);
1148 ether_ifdetach(ifp);
1151 device_delete_child(dev, sc->sis_miibus);
1152 bus_generic_detach(dev);
1154 if (sc->sis_intrhand)
1155 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
1156 bus_release_resources(dev, sis_res_spec, sc->sis_res);
1163 mtx_destroy(&sc->sis_mtx);
1168 struct sis_dmamap_arg {
1169 bus_addr_t sis_busaddr;
1173 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1175 struct sis_dmamap_arg *ctx;
1180 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1182 ctx = (struct sis_dmamap_arg *)arg;
1183 ctx->sis_busaddr = segs[0].ds_addr;
1187 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment,
1188 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
1189 bus_addr_t *paddr, const char *msg)
1191 struct sis_dmamap_arg ctx;
1194 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0,
1195 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1,
1196 maxsize, 0, NULL, NULL, tag);
1198 device_printf(sc->sis_dev,
1199 "could not create %s dma tag\n", msg);
1202 /* Allocate DMA'able memory for ring. */
1203 error = bus_dmamem_alloc(*tag, (void **)ring,
1204 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1206 device_printf(sc->sis_dev,
1207 "could not allocate DMA'able memory for %s\n", msg);
1210 /* Load the address of the ring. */
1211 ctx.sis_busaddr = 0;
1212 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb,
1213 &ctx, BUS_DMA_NOWAIT);
1215 device_printf(sc->sis_dev,
1216 "could not load DMA'able memory for %s\n", msg);
1219 *paddr = ctx.sis_busaddr;
1224 sis_dma_alloc(struct sis_softc *sc)
1226 struct sis_rxdesc *rxd;
1227 struct sis_txdesc *txd;
1230 /* Allocate the parent bus DMA tag appropriate for PCI. */
1231 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev),
1232 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1233 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
1234 0, NULL, NULL, &sc->sis_parent_tag);
1236 device_printf(sc->sis_dev,
1237 "could not allocate parent dma tag\n");
1241 /* Create RX ring. */
1242 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ,
1243 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list,
1244 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring");
1248 /* Create TX ring. */
1249 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ,
1250 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list,
1251 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring");
1255 /* Create tag for RX mbufs. */
1256 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0,
1257 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1258 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag);
1260 device_printf(sc->sis_dev, "could not allocate RX dma tag\n");
1264 /* Create tag for TX mbufs. */
1265 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0,
1266 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1267 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1270 device_printf(sc->sis_dev, "could not allocate TX dma tag\n");
1274 /* Create DMA maps for RX buffers. */
1275 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap);
1277 device_printf(sc->sis_dev,
1278 "can't create spare DMA map for RX\n");
1281 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1282 rxd = &sc->sis_rxdesc[i];
1284 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap);
1286 device_printf(sc->sis_dev,
1287 "can't create DMA map for RX\n");
1292 /* Create DMA maps for TX buffers. */
1293 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1294 txd = &sc->sis_txdesc[i];
1296 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap);
1298 device_printf(sc->sis_dev,
1299 "can't create DMA map for TX\n");
1308 sis_dma_free(struct sis_softc *sc)
1310 struct sis_rxdesc *rxd;
1311 struct sis_txdesc *txd;
1314 /* Destroy DMA maps for RX buffers. */
1315 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1316 rxd = &sc->sis_rxdesc[i];
1318 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap);
1320 if (sc->sis_rx_sparemap)
1321 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap);
1323 /* Destroy DMA maps for TX buffers. */
1324 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1325 txd = &sc->sis_txdesc[i];
1327 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap);
1331 bus_dma_tag_destroy(sc->sis_rx_tag);
1333 bus_dma_tag_destroy(sc->sis_tx_tag);
1335 /* Destroy RX ring. */
1336 if (sc->sis_rx_paddr)
1337 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map);
1338 if (sc->sis_rx_list)
1339 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list,
1340 sc->sis_rx_list_map);
1342 if (sc->sis_rx_list_tag)
1343 bus_dma_tag_destroy(sc->sis_rx_list_tag);
1345 /* Destroy TX ring. */
1346 if (sc->sis_tx_paddr)
1347 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map);
1349 if (sc->sis_tx_list)
1350 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list,
1351 sc->sis_tx_list_map);
1353 if (sc->sis_tx_list_tag)
1354 bus_dma_tag_destroy(sc->sis_tx_list_tag);
1356 /* Destroy the parent tag. */
1357 if (sc->sis_parent_tag)
1358 bus_dma_tag_destroy(sc->sis_parent_tag);
1362 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
1363 * we arrange the descriptors in a closed ring, so that the last descriptor
1364 * points back to the first.
1367 sis_ring_init(struct sis_softc *sc)
1369 struct sis_rxdesc *rxd;
1370 struct sis_txdesc *txd;
1374 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ);
1375 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1376 txd = &sc->sis_txdesc[i];
1378 if (i == SIS_TX_LIST_CNT - 1)
1379 next = SIS_TX_RING_ADDR(sc, 0);
1381 next = SIS_TX_RING_ADDR(sc, i + 1);
1382 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next));
1384 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
1385 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1386 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1388 sc->sis_rx_cons = 0;
1389 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ);
1390 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1391 rxd = &sc->sis_rxdesc[i];
1392 rxd->rx_desc = &sc->sis_rx_list[i];
1393 if (i == SIS_RX_LIST_CNT - 1)
1394 next = SIS_RX_RING_ADDR(sc, 0);
1396 next = SIS_RX_RING_ADDR(sc, i + 1);
1397 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next));
1398 error = sis_newbuf(sc, rxd);
1402 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1403 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1409 * Initialize an RX descriptor and attach an MBUF cluster.
1412 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd)
1415 bus_dma_segment_t segs[1];
1419 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1422 m->m_len = m->m_pkthdr.len = SIS_RXLEN;
1423 #ifndef __NO_STRICT_ALIGNMENT
1424 m_adj(m, SIS_RX_BUF_ALIGN);
1427 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m,
1428 segs, &nsegs, 0) != 0) {
1432 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1434 if (rxd->rx_m != NULL) {
1435 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
1436 BUS_DMASYNC_POSTREAD);
1437 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
1439 map = rxd->rx_dmamap;
1440 rxd->rx_dmamap = sc->sis_rx_sparemap;
1441 sc->sis_rx_sparemap = map;
1442 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD);
1444 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr));
1445 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1449 static __inline void
1450 sis_discard_rxbuf(struct sis_rxdesc *rxd)
1453 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1456 #ifndef __NO_STRICT_ALIGNMENT
1457 static __inline void
1458 sis_fixup_rx(struct mbuf *m)
1460 uint16_t *src, *dst;
1463 src = mtod(m, uint16_t *);
1464 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src);
1466 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1469 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN;
1474 * A frame has been uploaded: pass the resulting mbuf chain up to
1475 * the higher level protocols.
1478 sis_rxeof(struct sis_softc *sc)
1482 struct sis_rxdesc *rxd;
1483 struct sis_desc *cur_rx;
1484 int prog, rx_cons, rx_npkts = 0, total_len;
1487 SIS_LOCK_ASSERT(sc);
1489 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1490 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1492 rx_cons = sc->sis_rx_cons;
1495 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
1496 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) {
1497 #ifdef DEVICE_POLLING
1498 if (ifp->if_capenable & IFCAP_POLLING) {
1499 if (sc->rxcycles <= 0)
1504 cur_rx = &sc->sis_rx_list[rx_cons];
1505 rxstat = le32toh(cur_rx->sis_cmdsts);
1506 if ((rxstat & SIS_CMDSTS_OWN) == 0)
1508 rxd = &sc->sis_rxdesc[rx_cons];
1510 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN;
1511 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 &&
1512 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN -
1514 rxstat &= ~SIS_RXSTAT_GIANT;
1515 if (SIS_RXSTAT_ERROR(rxstat) != 0) {
1516 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1517 if (rxstat & SIS_RXSTAT_COLL)
1518 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1519 sis_discard_rxbuf(rxd);
1523 /* Add a new receive buffer to the ring. */
1525 if (sis_newbuf(sc, rxd) != 0) {
1526 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1527 sis_discard_rxbuf(rxd);
1531 /* No errors; receive the packet. */
1532 m->m_pkthdr.len = m->m_len = total_len;
1533 #ifndef __NO_STRICT_ALIGNMENT
1535 * On architectures without alignment problems we try to
1536 * allocate a new buffer for the receive ring, and pass up
1537 * the one where the packet is already, saving the expensive
1542 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1543 m->m_pkthdr.rcvif = ifp;
1546 (*ifp->if_input)(ifp, m);
1552 sc->sis_rx_cons = rx_cons;
1553 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1554 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1561 * A frame was downloaded to the chip. It's safe for us to clean up
1566 sis_txeof(struct sis_softc *sc)
1569 struct sis_desc *cur_tx;
1570 struct sis_txdesc *txd;
1571 uint32_t cons, txstat;
1573 SIS_LOCK_ASSERT(sc);
1575 cons = sc->sis_tx_cons;
1576 if (cons == sc->sis_tx_prod)
1580 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1581 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1584 * Go through our tx list and free mbufs for those
1585 * frames that have been transmitted.
1587 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) {
1588 cur_tx = &sc->sis_tx_list[cons];
1589 txstat = le32toh(cur_tx->sis_cmdsts);
1590 if ((txstat & SIS_CMDSTS_OWN) != 0)
1592 txd = &sc->sis_txdesc[cons];
1593 if (txd->tx_m != NULL) {
1594 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
1595 BUS_DMASYNC_POSTWRITE);
1596 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1599 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) {
1600 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1601 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1602 (txstat & SIS_TXSTAT_COLLCNT) >> 16);
1604 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1605 if (txstat & SIS_TXSTAT_EXCESSCOLLS)
1606 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1607 if (txstat & SIS_TXSTAT_OUTOFWINCOLL)
1608 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1612 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1614 sc->sis_tx_cons = cons;
1615 if (sc->sis_tx_cnt == 0)
1616 sc->sis_watchdog_timer = 0;
1622 struct sis_softc *sc;
1623 struct mii_data *mii;
1626 SIS_LOCK_ASSERT(sc);
1628 mii = device_get_softc(sc->sis_miibus);
1631 if ((sc->sis_flags & SIS_FLAG_LINK) == 0)
1632 sis_miibus_statchg(sc->sis_dev);
1633 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1636 #ifdef DEVICE_POLLING
1637 static poll_handler_t sis_poll;
1640 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1642 struct sis_softc *sc = ifp->if_softc;
1646 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1652 * On the sis, reading the status register also clears it.
1653 * So before returning to intr mode we must make sure that all
1654 * possible pending sources of interrupts have been served.
1655 * In practice this means run to completion the *eof routines,
1656 * and then call the interrupt routine
1658 sc->rxcycles = count;
1659 rx_npkts = sis_rxeof(sc);
1661 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1664 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1667 /* Reading the ISR register clears all interrupts. */
1668 status = CSR_READ_4(sc, SIS_ISR);
1670 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1671 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1673 if (status & (SIS_ISR_RX_IDLE))
1674 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1676 if (status & SIS_ISR_SYSERR) {
1677 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1685 #endif /* DEVICE_POLLING */
1690 struct sis_softc *sc;
1698 #ifdef DEVICE_POLLING
1699 if (ifp->if_capenable & IFCAP_POLLING) {
1705 /* Reading the ISR register clears all interrupts. */
1706 status = CSR_READ_4(sc, SIS_ISR);
1707 if ((status & SIS_INTRS) == 0) {
1713 /* Disable interrupts. */
1714 CSR_WRITE_4(sc, SIS_IER, 0);
1716 for (;(status & SIS_INTRS) != 0;) {
1717 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1720 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1721 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1724 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK |
1725 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE))
1728 if (status & SIS_ISR_RX_OFLOW)
1729 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1731 if (status & (SIS_ISR_RX_IDLE))
1732 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1734 if (status & SIS_ISR_SYSERR) {
1735 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1740 status = CSR_READ_4(sc, SIS_ISR);
1743 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1744 /* Re-enable interrupts. */
1745 CSR_WRITE_4(sc, SIS_IER, 1);
1747 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1755 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1756 * pointers to the fragment pointers.
1759 sis_encap(struct sis_softc *sc, struct mbuf **m_head)
1762 struct sis_txdesc *txd;
1764 bus_dma_segment_t segs[SIS_MAXTXSEGS];
1766 int error, i, frag, nsegs, prod;
1769 prod = sc->sis_tx_prod;
1770 txd = &sc->sis_txdesc[prod];
1771 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 &&
1772 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) {
1774 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len;
1775 if (M_WRITABLE(m) == 0) {
1776 /* Get a writable copy. */
1777 m = m_dup(*m_head, M_NOWAIT);
1785 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
1786 m = m_defrag(m, M_NOWAIT);
1794 * Manually pad short frames, and zero the pad space
1795 * to avoid leaking data.
1797 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1798 m->m_pkthdr.len += padlen;
1799 m->m_len = m->m_pkthdr.len;
1802 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1803 *m_head, segs, &nsegs, 0);
1804 if (error == EFBIG) {
1805 m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS);
1812 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1813 *m_head, segs, &nsegs, 0);
1819 } else if (error != 0)
1822 /* Check for descriptor overruns. */
1823 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) {
1824 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1828 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE);
1831 for (i = 0; i < nsegs; i++) {
1832 f = &sc->sis_tx_list[prod];
1834 f->sis_cmdsts = htole32(segs[i].ds_len |
1837 f->sis_cmdsts = htole32(segs[i].ds_len |
1838 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE);
1839 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr));
1840 SIS_INC(prod, SIS_TX_LIST_CNT);
1844 /* Update producer index. */
1845 sc->sis_tx_prod = prod;
1847 /* Remove MORE flag on the last descriptor. */
1848 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1);
1849 f = &sc->sis_tx_list[prod];
1850 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE);
1852 /* Lastly transfer ownership of packet to the controller. */
1853 f = &sc->sis_tx_list[frag];
1854 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN);
1856 /* Swap the last and the first dmamaps. */
1857 map = txd->tx_dmamap;
1858 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap;
1859 sc->sis_txdesc[prod].tx_dmamap = map;
1860 sc->sis_txdesc[prod].tx_m = *m_head;
1866 sis_start(struct ifnet *ifp)
1868 struct sis_softc *sc;
1877 sis_startl(struct ifnet *ifp)
1879 struct sis_softc *sc;
1880 struct mbuf *m_head;
1885 SIS_LOCK_ASSERT(sc);
1887 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1888 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0)
1891 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1892 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) {
1893 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1897 if (sis_encap(sc, &m_head) != 0) {
1900 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1901 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1908 * If there's a BPF listener, bounce a copy of this frame
1911 BPF_MTAP(ifp, m_head);
1916 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1917 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1918 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1921 * Set a timeout in case the chip goes out to lunch.
1923 sc->sis_watchdog_timer = 5;
1930 struct sis_softc *sc = xsc;
1938 sis_initl(struct sis_softc *sc)
1940 struct ifnet *ifp = sc->sis_ifp;
1941 struct mii_data *mii;
1944 SIS_LOCK_ASSERT(sc);
1946 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1950 * Cancel pending I/O and free all RX/TX buffers.
1954 * Reset the chip to a known state.
1958 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
1960 * Configure 400usec of interrupt holdoff. This is based
1961 * on emperical tests on a Soekris 4801.
1963 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
1967 mii = device_get_softc(sc->sis_miibus);
1969 /* Set MAC address */
1970 eaddr = IF_LLADDR(sc->sis_ifp);
1971 if (sc->sis_type == SIS_TYPE_83815) {
1972 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1973 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1974 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1975 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1976 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1977 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1979 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1980 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1981 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1982 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1983 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1984 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1987 /* Init circular TX/RX lists. */
1988 if (sis_ring_init(sc) != 0) {
1989 device_printf(sc->sis_dev,
1990 "initialization failed: no memory for rx buffers\n");
1995 if (sc->sis_type == SIS_TYPE_83815) {
1996 if (sc->sis_manual_pad != 0)
1997 sc->sis_flags |= SIS_FLAG_MANUAL_PAD;
1999 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD;
2003 * Short Cable Receive Errors (MP21.E)
2004 * also: Page 78 of the DP83815 data sheet (september 2002 version)
2005 * recommends the following register settings "for optimum
2006 * performance." for rev 15C. Set this also for 15D parts as
2007 * they require it in practice.
2009 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
2010 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2011 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2012 /* set val for c2 */
2013 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2015 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2016 /* rais SD off, from 4 to c */
2017 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2018 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2024 * Load the address of the RX and TX lists.
2026 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr));
2027 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr));
2029 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
2030 * the PCI bus. When this bit is set, the Max DMA Burst Size
2031 * for TX/RX DMA should be no larger than 16 double words.
2033 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
2034 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
2036 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
2039 /* Accept Long Packets for VLAN support */
2040 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
2043 * Assume 100Mbps link, actual MAC configuration is done
2044 * after getting a valid link.
2046 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
2049 * Enable interrupts.
2051 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2052 #ifdef DEVICE_POLLING
2054 * ... only enable interrupts if we are not polling, make sure
2055 * they are off otherwise.
2057 if (ifp->if_capenable & IFCAP_POLLING)
2058 CSR_WRITE_4(sc, SIS_IER, 0);
2061 CSR_WRITE_4(sc, SIS_IER, 1);
2063 /* Clear MAC disable. */
2064 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
2066 sc->sis_flags &= ~SIS_FLAG_LINK;
2069 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2070 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2072 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2076 * Set media options.
2079 sis_ifmedia_upd(struct ifnet *ifp)
2081 struct sis_softc *sc;
2082 struct mii_data *mii;
2083 struct mii_softc *miisc;
2089 mii = device_get_softc(sc->sis_miibus);
2090 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2092 error = mii_mediachg(mii);
2099 * Report current media status.
2102 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2104 struct sis_softc *sc;
2105 struct mii_data *mii;
2110 mii = device_get_softc(sc->sis_miibus);
2112 ifmr->ifm_active = mii->mii_media_active;
2113 ifmr->ifm_status = mii->mii_media_status;
2118 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2120 struct sis_softc *sc = ifp->if_softc;
2121 struct ifreq *ifr = (struct ifreq *) data;
2122 struct mii_data *mii;
2123 int error = 0, mask;
2128 if (ifp->if_flags & IFF_UP) {
2129 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2130 ((ifp->if_flags ^ sc->sis_if_flags) &
2131 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2135 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2137 sc->sis_if_flags = ifp->if_flags;
2143 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2149 mii = device_get_softc(sc->sis_miibus);
2150 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2154 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2155 #ifdef DEVICE_POLLING
2156 if ((mask & IFCAP_POLLING) != 0 &&
2157 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
2158 ifp->if_capenable ^= IFCAP_POLLING;
2159 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
2160 error = ether_poll_register(sis_poll, ifp);
2165 /* Disable interrupts. */
2166 CSR_WRITE_4(sc, SIS_IER, 0);
2168 error = ether_poll_deregister(ifp);
2169 /* Enable interrupts. */
2170 CSR_WRITE_4(sc, SIS_IER, 1);
2173 #endif /* DEVICE_POLLING */
2174 if ((mask & IFCAP_WOL) != 0 &&
2175 (ifp->if_capabilities & IFCAP_WOL) != 0) {
2176 if ((mask & IFCAP_WOL_UCAST) != 0)
2177 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2178 if ((mask & IFCAP_WOL_MCAST) != 0)
2179 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2180 if ((mask & IFCAP_WOL_MAGIC) != 0)
2181 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2186 error = ether_ioctl(ifp, command, data);
2194 sis_watchdog(struct sis_softc *sc)
2197 SIS_LOCK_ASSERT(sc);
2199 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
2202 device_printf(sc->sis_dev, "watchdog timeout\n");
2203 if_inc_counter(sc->sis_ifp, IFCOUNTER_OERRORS, 1);
2205 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2208 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd))
2209 sis_startl(sc->sis_ifp);
2213 * Stop the adapter and free any mbufs allocated to the
2217 sis_stop(struct sis_softc *sc)
2220 struct sis_rxdesc *rxd;
2221 struct sis_txdesc *txd;
2224 SIS_LOCK_ASSERT(sc);
2227 sc->sis_watchdog_timer = 0;
2229 callout_stop(&sc->sis_stat_ch);
2231 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2232 CSR_WRITE_4(sc, SIS_IER, 0);
2233 CSR_WRITE_4(sc, SIS_IMR, 0);
2234 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
2235 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2237 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2238 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2240 sc->sis_flags &= ~SIS_FLAG_LINK;
2243 * Free data in the RX lists.
2245 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2246 rxd = &sc->sis_rxdesc[i];
2247 if (rxd->rx_m != NULL) {
2248 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
2249 BUS_DMASYNC_POSTREAD);
2250 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
2257 * Free the TX list buffers.
2259 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2260 txd = &sc->sis_txdesc[i];
2261 if (txd->tx_m != NULL) {
2262 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
2263 BUS_DMASYNC_POSTWRITE);
2264 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
2272 * Stop all chip I/O so that the kernel's probe routines don't
2273 * get confused by errant DMAs when rebooting.
2276 sis_shutdown(device_t dev)
2279 return (sis_suspend(dev));
2283 sis_suspend(device_t dev)
2285 struct sis_softc *sc;
2287 sc = device_get_softc(dev);
2296 sis_resume(device_t dev)
2298 struct sis_softc *sc;
2301 sc = device_get_softc(dev);
2304 if ((ifp->if_flags & IFF_UP) != 0) {
2305 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2313 sis_wol(struct sis_softc *sc)
2321 if ((ifp->if_capenable & IFCAP_WOL) == 0)
2324 if (sc->sis_type == SIS_TYPE_83815) {
2326 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2328 /* Configure WOL events. */
2329 CSR_READ_4(sc, NS_WCSR);
2331 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2332 val |= NS_WCSR_WAKE_UCAST;
2333 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2334 val |= NS_WCSR_WAKE_MCAST;
2335 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2336 val |= NS_WCSR_WAKE_MAGIC;
2337 CSR_WRITE_4(sc, NS_WCSR, val);
2338 /* Enable PME and clear PMESTS. */
2339 val = CSR_READ_4(sc, NS_CLKRUN);
2340 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS;
2341 CSR_WRITE_4(sc, NS_CLKRUN, val);
2342 /* Enable silent RX mode. */
2343 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2345 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
2348 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2349 val |= SIS_PWRMAN_WOL_MAGIC;
2350 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val);
2352 pmstat = pci_read_config(sc->sis_dev,
2353 pmc + PCIR_POWER_STATUS, 2);
2354 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2355 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2356 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2357 pci_write_config(sc->sis_dev,
2358 pmc + PCIR_POWER_STATUS, pmstat, 2);
2363 sis_add_sysctls(struct sis_softc *sc)
2365 struct sysctl_ctx_list *ctx;
2366 struct sysctl_oid_list *children;
2369 ctx = device_get_sysctl_ctx(sc->sis_dev);
2370 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev));
2372 unit = device_get_unit(sc->sis_dev);
2374 * Unlike most other controllers, NS DP83815/DP83816 controllers
2375 * seem to pad with 0xFF when it encounter short frames. According
2376 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable
2377 * on will have driver pad manully but it's disabled by default
2378 * because it will consume extra CPU cycles for short frames.
2380 sc->sis_manual_pad = 0;
2381 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad",
2382 CTLFLAG_RWTUN, &sc->sis_manual_pad, 0, "Manually pad short frames");
2385 static device_method_t sis_methods[] = {
2386 /* Device interface */
2387 DEVMETHOD(device_probe, sis_probe),
2388 DEVMETHOD(device_attach, sis_attach),
2389 DEVMETHOD(device_detach, sis_detach),
2390 DEVMETHOD(device_shutdown, sis_shutdown),
2391 DEVMETHOD(device_suspend, sis_suspend),
2392 DEVMETHOD(device_resume, sis_resume),
2395 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
2396 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
2397 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
2402 static driver_t sis_driver = {
2405 sizeof(struct sis_softc)
2408 static devclass_t sis_devclass;
2410 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
2411 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);