2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * Register definitions for the SiS 900 and SiS 7016 chipsets. The
37 * 7016 is actually an older chip and some of its registers differ
38 * from the 900, however the core operational registers are the same:
39 * the differences lie in the OnNow/Wake on LAN stuff which we don't
40 * use anyway. The 7016 needs an external MII compliant PHY while the
41 * SiS 900 has one built in. All registers are 32-bits wide.
44 /* Registers common to SiS 900 and SiS 7016 */
47 #define SIS_EECTL 0x08
48 #define SIS_PCICTL 0x0C
52 #define SIS_PHYCTL 0x1C
53 #define SIS_TX_LISTPTR 0x20
54 #define SIS_TX_CFG 0x24
55 #define SIS_RX_LISTPTR 0x30
56 #define SIS_RX_CFG 0x34
57 #define SIS_FLOWCTL 0x38
58 #define SIS_RXFILT_CTL 0x48
59 #define SIS_RXFILT_DATA 0x4C
60 #define SIS_PWRMAN_CTL 0xB0
61 #define SIS_PWERMAN_WKUP_EVENT 0xB4
62 #define SIS_WKUP_FRAME_CRC 0xBC
63 #define SIS_WKUP_FRAME_MASK0 0xC0
64 #define SIS_WKUP_FRAME_MASKXX 0xEC
66 /* SiS 7016 specific registers */
67 #define SIS_SILICON_REV 0x5C
68 #define SIS_MIB_CTL0 0x60
69 #define SIS_MIB_CTL1 0x64
70 #define SIS_MIB_CTL2 0x68
71 #define SIS_MIB_CTL3 0x6C
73 #define SIS_LINKSTS 0xA0
74 #define SIS_TIMEUNIT 0xA4
77 /* NS DP83815/6 registers */
79 #define NS_CLKRUN 0x3C
83 #define NS_PHYIDR1 0x88
84 #define NS_PHYIDR2 0x8C
86 #define NS_ANLPAR 0x94
88 #define NS_ANNPTR 0x9C
90 #define NS_PHY_CR 0xE4
91 #define NS_PHY_10BTSCR 0xE8
92 #define NS_PHY_PAGE 0xCC
93 #define NS_PHY_EXTCFG 0xF0
94 #define NS_PHY_DSPCFG 0xF4
95 #define NS_PHY_SDCFG 0xF8
96 #define NS_PHY_TDATA 0xFC
98 #define NS_CLKRUN_PMESTS 0x00008000
99 #define NS_CLKRUN_PMEENB 0x00000100
100 #define NS_CLNRUN_CLKRUN_ENB 0x00000001
102 /* NS silicon revisions */
103 #define NS_SRR_15C 0x302
104 #define NS_SRR_15D 0x403
105 #define NS_SRR_16A 0x505
107 #define SIS_CSR_TX_ENABLE 0x00000001
108 #define SIS_CSR_TX_DISABLE 0x00000002
109 #define SIS_CSR_RX_ENABLE 0x00000004
110 #define SIS_CSR_RX_DISABLE 0x00000008
111 #define SIS_CSR_TX_RESET 0x00000010
112 #define SIS_CSR_RX_RESET 0x00000020
113 #define SIS_CSR_SOFTINTR 0x00000080
114 #define SIS_CSR_RESET 0x00000100
115 #define SIS_CSR_ACCESS_MODE 0x00000200
116 #define SIS_CSR_RELOAD 0x00000400
118 #define SIS_CFG_BIGENDIAN 0x00000001
119 #define SIS_CFG_PERR_DETECT 0x00000008
120 #define SIS_CFG_DEFER_DISABLE 0x00000010
121 #define SIS_CFG_OUTOFWIN_TIMER 0x00000020
122 #define SIS_CFG_SINGLE_BACKOFF 0x00000040
123 #define SIS_CFG_PCIREQ_ALG 0x00000080
124 #define SIS_CFG_FAIR_BACKOFF 0x00000200 /* 635 & 900B Specific */
125 #define SIS_CFG_RND_CNT 0x00000400 /* 635 & 900B Specific */
126 #define SIS_CFG_EDB_MASTER_EN 0x00002000
128 #define SIS_EECTL_DIN 0x00000001
129 #define SIS_EECTL_DOUT 0x00000002
130 #define SIS_EECTL_CLK 0x00000004
131 #define SIS_EECTL_CSEL 0x00000008
133 #define SIS_MII_CLK 0x00000040
134 #define SIS_MII_DIR 0x00000020
135 #define SIS_MII_DATA 0x00000010
137 #define SIS_EECMD_WRITE 0x140
138 #define SIS_EECMD_READ 0x180
139 #define SIS_EECMD_ERASE 0x1c0
142 * EEPROM Commands for SiS96x
145 #define SIS_EECMD_REQ 0x00000400
146 #define SIS_EECMD_DONE 0x00000200
147 #define SIS_EECMD_GNT 0x00000100
149 #define SIS_EE_NODEADDR 0x8
150 #define NS_EE_NODEADDR 0x6
152 #define SIS_PCICTL_SRAMADDR 0x0000001F
153 #define SIS_PCICTL_RAMTSTENB 0x00000020
154 #define SIS_PCICTL_TXTSTENB 0x00000040
155 #define SIS_PCICTL_RXTSTENB 0x00000080
156 #define SIS_PCICTL_BMTSTENB 0x00000200
157 #define SIS_PCICTL_RAMADDR 0x001F0000
158 #define SIS_PCICTL_ROMTIME 0x0F000000
159 #define SIS_PCICTL_DISCTEST 0x40000000
161 #define SIS_ISR_RX_OK 0x00000001
162 #define SIS_ISR_RX_DESC_OK 0x00000002
163 #define SIS_ISR_RX_ERR 0x00000004
164 #define SIS_ISR_RX_EARLY 0x00000008
165 #define SIS_ISR_RX_IDLE 0x00000010
166 #define SIS_ISR_RX_OFLOW 0x00000020
167 #define SIS_ISR_TX_OK 0x00000040
168 #define SIS_ISR_TX_DESC_OK 0x00000080
169 #define SIS_ISR_TX_ERR 0x00000100
170 #define SIS_ISR_TX_IDLE 0x00000200
171 #define SIS_ISR_TX_UFLOW 0x00000400
172 #define SIS_ISR_SOFTINTR 0x00000800
173 #define SIS_ISR_HIBITS 0x00008000
174 #define SIS_ISR_RX_FIFO_OFLOW 0x00010000
175 #define SIS_ISR_TGT_ABRT 0x00100000
176 #define SIS_ISR_BM_ABRT 0x00200000
177 #define SIS_ISR_SYSERR 0x00400000
178 #define SIS_ISR_PARITY_ERR 0x00800000
179 #define SIS_ISR_RX_RESET_DONE 0x01000000
180 #define SIS_ISR_TX_RESET_DONE 0x02000000
181 #define SIS_ISR_TX_PAUSE_START 0x04000000
182 #define SIS_ISR_TX_PAUSE_DONE 0x08000000
183 #define SIS_ISR_WAKE_EVENT 0x10000000
185 #define SIS_IMR_RX_OK 0x00000001
186 #define SIS_IMR_RX_DESC_OK 0x00000002
187 #define SIS_IMR_RX_ERR 0x00000004
188 #define SIS_IMR_RX_EARLY 0x00000008
189 #define SIS_IMR_RX_IDLE 0x00000010
190 #define SIS_IMR_RX_OFLOW 0x00000020
191 #define SIS_IMR_TX_OK 0x00000040
192 #define SIS_IMR_TX_DESC_OK 0x00000080
193 #define SIS_IMR_TX_ERR 0x00000100
194 #define SIS_IMR_TX_IDLE 0x00000200
195 #define SIS_IMR_TX_UFLOW 0x00000400
196 #define SIS_IMR_SOFTINTR 0x00000800
197 #define SIS_IMR_HIBITS 0x00008000
198 #define SIS_IMR_RX_FIFO_OFLOW 0x00010000
199 #define SIS_IMR_TGT_ABRT 0x00100000
200 #define SIS_IMR_BM_ABRT 0x00200000
201 #define SIS_IMR_SYSERR 0x00400000
202 #define SIS_IMR_PARITY_ERR 0x00800000
203 #define SIS_IMR_RX_RESET_DONE 0x01000000
204 #define SIS_IMR_TX_RESET_DONE 0x02000000
205 #define SIS_IMR_TX_PAUSE_START 0x04000000
206 #define SIS_IMR_TX_PAUSE_DONE 0x08000000
207 #define SIS_IMR_WAKE_EVENT 0x10000000
210 (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\
211 SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\
215 #define SIS_IER_INTRENB 0x00000001
217 #define SIS_PHYCTL_ACCESS 0x00000010
218 #define SIS_PHYCTL_OP 0x00000020
219 #define SIS_PHYCTL_REGADDR 0x000007C0
220 #define SIS_PHYCTL_PHYADDR 0x0000F800
221 #define SIS_PHYCTL_PHYDATA 0xFFFF0000
223 #define SIS_PHYOP_READ 0x00000020
224 #define SIS_PHYOP_WRITE 0x00000000
226 #define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */
227 #define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */
228 #define SIS_TXCFG_DMABURST 0x00700000
229 #define SIS_TXCFG_AUTOPAD 0x10000000
230 #define SIS_TXCFG_LOOPBK 0x20000000
231 #define SIS_TXCFG_IGN_HBEAT 0x40000000
232 #define SIS_TXCFG_IGN_CARR 0x80000000
234 #define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH)
235 #define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH)
237 #define SIS_TXDMA_512BYTES 0x00000000
238 #define SIS_TXDMA_4BYTES 0x00100000
239 #define SIS_TXDMA_8BYTES 0x00200000
240 #define SIS_TXDMA_16BYTES 0x00300000
241 #define SIS_TXDMA_32BYTES 0x00400000
242 #define SIS_TXDMA_64BYTES 0x00500000
243 #define SIS_TXDMA_128BYTES 0x00600000
244 #define SIS_TXDMA_256BYTES 0x00700000
246 #define SIS_TXCFG_100 \
247 (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\
248 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
250 #define SIS_TXCFG_10 \
251 (SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\
252 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
254 #define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */
255 #define SIS_TXCFG_MPII03D 0x00040000 /* "Must be 1" */
256 #define SIS_RXCFG_DMABURST 0x00700000
257 #define SIS_RXCFG_RX_JABBER 0x08000000
258 #define SIS_RXCFG_RX_TXPKTS 0x10000000
259 #define SIS_RXCFG_RX_RUNTS 0x40000000
260 #define SIS_RXCFG_RX_GIANTS 0x80000000
262 #define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH)
264 #define SIS_RXDMA_512BYTES 0x00000000
265 #define SIS_RXDMA_4BYTES 0x00100000
266 #define SIS_RXDMA_8BYTES 0x00200000
267 #define SIS_RXDMA_16BYTES 0x00300000
268 #define SIS_RXDMA_32BYTES 0x00400000
269 #define SIS_RXDMA_64BYTES 0x00500000
270 #define SIS_RXDMA_128BYTES 0x00600000
271 #define SIS_RXDMA_256BYTES 0x00700000
273 #define SIS_RXCFG256 \
274 (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES)
275 #define SIS_RXCFG64 \
276 (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_64BYTES)
278 #define SIS_RXFILTCTL_ADDR 0x000F0000
279 #define NS_RXFILTCTL_MCHASH 0x00200000
280 #define NS_RXFILTCTL_ARP 0x00400000
281 #define NS_RXFILTCTL_PERFECT 0x08000000
282 #define SIS_RXFILTCTL_ALLPHYS 0x10000000
283 #define SIS_RXFILTCTL_ALLMULTI 0x20000000
284 #define SIS_RXFILTCTL_BROAD 0x40000000
285 #define SIS_RXFILTCTL_ENABLE 0x80000000
287 #define SIS_FILTADDR_PAR0 0x00000000
288 #define SIS_FILTADDR_PAR1 0x00010000
289 #define SIS_FILTADDR_PAR2 0x00020000
290 #define SIS_FILTADDR_MAR0 0x00040000
291 #define SIS_FILTADDR_MAR1 0x00050000
292 #define SIS_FILTADDR_MAR2 0x00060000
293 #define SIS_FILTADDR_MAR3 0x00070000
294 #define SIS_FILTADDR_MAR4 0x00080000
295 #define SIS_FILTADDR_MAR5 0x00090000
296 #define SIS_FILTADDR_MAR6 0x000A0000
297 #define SIS_FILTADDR_MAR7 0x000B0000
299 #define NS_FILTADDR_PAR0 0x00000000
300 #define NS_FILTADDR_PAR1 0x00000002
301 #define NS_FILTADDR_PAR2 0x00000004
303 #define NS_FILTADDR_FMEM_LO 0x00000200
304 #define NS_FILTADDR_FMEM_HI 0x000003FE
307 * DMA descriptor structures. The first part of the descriptor
308 * is the hardware descriptor format, which is just three longwords.
309 * After this, we include some additional structure members for
310 * use by the driver. Note that for this structure will be a different
311 * size on the alpha, but that's okay as long as it's a multiple of 4
315 /* SiS hardware descriptor section */
317 u_int32_t sis_cmdsts;
318 #define sis_rxstat sis_cmdsts
319 #define sis_txstat sis_cmdsts
320 #define sis_ctl sis_cmdsts
322 /* Driver software section */
323 struct mbuf *sis_mbuf;
324 struct sis_desc *sis_nextdesc;
325 bus_dmamap_t sis_map;
328 #define SIS_CMDSTS_BUFLEN 0x00000FFF
329 #define SIS_CMDSTS_PKT_OK 0x08000000
330 #define SIS_CMDSTS_CRC 0x10000000
331 #define SIS_CMDSTS_INTR 0x20000000
332 #define SIS_CMDSTS_MORE 0x40000000
333 #define SIS_CMDSTS_OWN 0x80000000
335 #define SIS_LASTDESC(x) (!((x)->sis_ctl & SIS_CMDSTS_MORE))
336 #define SIS_OWNDESC(x) ((x)->sis_ctl & SIS_CMDSTS_OWN)
337 #define SIS_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1
338 #define SIS_RXBYTES(x) (((x)->sis_ctl & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN)
340 #define SIS_RXSTAT_COLL 0x00010000
341 #define SIS_RXSTAT_LOOPBK 0x00020000
342 #define SIS_RXSTAT_ALIGNERR 0x00040000
343 #define SIS_RXSTAT_CRCERR 0x00080000
344 #define SIS_RXSTAT_SYMBOLERR 0x00100000
345 #define SIS_RXSTAT_RUNT 0x00200000
346 #define SIS_RXSTAT_GIANT 0x00400000
347 #define SIS_RXSTAT_DSTCLASS 0x01800000
348 #define SIS_RXSTAT_OVERRUN 0x02000000
349 #define SIS_RXSTAT_RX_ABORT 0x04000000
351 #define SIS_DSTCLASS_REJECT 0x00000000
352 #define SIS_DSTCLASS_UNICAST 0x00800000
353 #define SIS_DSTCLASS_MULTICAST 0x01000000
354 #define SIS_DSTCLASS_BROADCAST 0x02000000
356 #define SIS_TXSTAT_COLLCNT 0x000F0000
357 #define SIS_TXSTAT_EXCESSCOLLS 0x00100000
358 #define SIS_TXSTAT_OUTOFWINCOLL 0x00200000
359 #define SIS_TXSTAT_EXCESS_DEFER 0x00400000
360 #define SIS_TXSTAT_DEFERED 0x00800000
361 #define SIS_TXSTAT_CARR_LOST 0x01000000
362 #define SIS_TXSTAT_UNDERRUN 0x02000000
363 #define SIS_TXSTAT_TX_ABORT 0x04000000
365 #define SIS_RX_LIST_CNT 64
366 #define SIS_TX_LIST_CNT 128
368 #define SIS_RX_LIST_SZ SIS_RX_LIST_CNT * sizeof(struct sis_desc)
369 #define SIS_TX_LIST_SZ SIS_TX_LIST_CNT * sizeof(struct sis_desc)
374 #define SIS_VENDORID 0x1039
379 #define SIS_DEVICEID_900 0x0900
380 #define SIS_DEVICEID_7016 0x7016
383 * SiS 900 PCI revision codes.
385 #define SIS_REV_900B 0x0003
386 #define SIS_REV_630A 0x0080
387 #define SIS_REV_630E 0x0081
388 #define SIS_REV_630S 0x0082
389 #define SIS_REV_630EA1 0x0083
390 #define SIS_REV_630ET 0x0084
391 #define SIS_REV_635 0x0090
392 #define SIS_REV_96x 0x0091
397 #define NS_VENDORID 0x100B
402 #define NS_DEVICEID_DP83815 0x0020
410 struct sis_mii_frame {
411 u_int8_t mii_stdelim;
413 u_int8_t mii_phyaddr;
414 u_int8_t mii_regaddr;
415 u_int8_t mii_turnaround;
422 #define SIS_MII_STARTDELIM 0x01
423 #define SIS_MII_READOP 0x02
424 #define SIS_MII_WRITEOP 0x01
425 #define SIS_MII_TURNAROUND 0x02
427 #define SIS_TYPE_900 1
428 #define SIS_TYPE_7016 2
429 #define SIS_TYPE_83815 3
430 #define SIS_TYPE_83816 4
433 struct ifnet *sis_ifp; /* interface info */
434 struct resource *sis_res[2];
442 struct sis_desc *sis_rx_list;
443 struct sis_desc *sis_tx_list;
444 bus_dma_tag_t sis_rx_tag;
445 bus_dmamap_t sis_rx_dmamap;
446 bus_dma_tag_t sis_tx_tag;
447 bus_dmamap_t sis_tx_dmamap;
448 bus_dma_tag_t sis_parent_tag;
449 bus_dma_tag_t sis_tag;
450 struct sis_desc *sis_rx_pdsc;
454 u_int32_t sis_rx_paddr;
455 u_int32_t sis_tx_paddr;
456 struct callout sis_stat_ch;
457 int sis_watchdog_timer;
459 #ifdef DEVICE_POLLING
466 #define SIS_TIMEOUT 1000
467 #define ETHER_ALIGN 2
468 #define SIS_RXLEN 1536
469 #define SIS_MIN_FRAMELEN 60
472 * PCI low memory base and low I/O base register, and
473 * other PCI registers.
476 #define SIS_PCI_VENDOR_ID 0x00
477 #define SIS_PCI_DEVICE_ID 0x02
478 #define SIS_PCI_COMMAND 0x04
479 #define SIS_PCI_STATUS 0x06
480 #define SIS_PCI_REVID 0x08
481 #define SIS_PCI_CLASSCODE 0x09
482 #define SIS_PCI_CACHELEN 0x0C
483 #define SIS_PCI_LATENCY_TIMER 0x0D
484 #define SIS_PCI_HEADER_TYPE 0x0E
485 #define SIS_PCI_LOIO 0x10
486 #define SIS_PCI_LOMEM 0x14
487 #define SIS_PCI_BIOSROM 0x30
488 #define SIS_PCI_INTLINE 0x3C
489 #define SIS_PCI_INTPIN 0x3D
490 #define SIS_PCI_MINGNT 0x3E
491 #define SIS_PCI_MINLAT 0x0F
492 #define SIS_PCI_RESETOPT 0x48
493 #define SIS_PCI_EEPROM_DATA 0x4C
495 /* power management registers */
496 #define SIS_PCI_CAPID 0x50 /* 8 bits */
497 #define SIS_PCI_NEXTPTR 0x51 /* 8 bits */
498 #define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */
499 #define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
501 #define SIS_PSTATE_MASK 0x0003
502 #define SIS_PSTATE_D0 0x0000
503 #define SIS_PSTATE_D1 0x0001
504 #define SIS_PSTATE_D2 0x0002
505 #define SIS_PSTATE_D3 0x0003
506 #define SIS_PME_EN 0x0010
507 #define SIS_PME_STATUS 0x8000