2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
38 * Register definitions for the SiS 900 and SiS 7016 chipsets. The
39 * 7016 is actually an older chip and some of its registers differ
40 * from the 900, however the core operational registers are the same:
41 * the differences lie in the OnNow/Wake on LAN stuff which we don't
42 * use anyway. The 7016 needs an external MII compliant PHY while the
43 * SiS 900 has one built in. All registers are 32-bits wide.
46 /* Registers common to SiS 900 and SiS 7016 */
49 #define SIS_EECTL 0x08
50 #define SIS_PCICTL 0x0C
54 #define SIS_PHYCTL 0x1C
55 #define SIS_TX_LISTPTR 0x20
56 #define SIS_TX_CFG 0x24
57 #define SIS_RX_LISTPTR 0x30
58 #define SIS_RX_CFG 0x34
59 #define SIS_FLOWCTL 0x38
60 #define SIS_RXFILT_CTL 0x48
61 #define SIS_RXFILT_DATA 0x4C
62 #define SIS_PWRMAN_CTL 0xB0
63 #define SIS_PWERMAN_WKUP_EVENT 0xB4
64 #define SIS_WKUP_FRAME_CRC 0xBC
65 #define SIS_WKUP_FRAME_MASK0 0xC0
66 #define SIS_WKUP_FRAME_MASKXX 0xEC
68 /* SiS 7016 specific registers */
69 #define SIS_SILICON_REV 0x5C
70 #define SIS_MIB_CTL0 0x60
71 #define SIS_MIB_CTL1 0x64
72 #define SIS_MIB_CTL2 0x68
73 #define SIS_MIB_CTL3 0x6C
75 #define SIS_LINKSTS 0xA0
76 #define SIS_TIMEUNIT 0xA4
79 /* NS DP83815/6 registers */
81 #define NS_CLKRUN 0x3C
86 #define NS_PHYIDR1 0x88
87 #define NS_PHYIDR2 0x8C
89 #define NS_ANLPAR 0x94
91 #define NS_ANNPTR 0x9C
93 #define NS_PHY_CR 0xE4
94 #define NS_PHY_10BTSCR 0xE8
95 #define NS_PHY_PAGE 0xCC
96 #define NS_PHY_EXTCFG 0xF0
97 #define NS_PHY_DSPCFG 0xF4
98 #define NS_PHY_SDCFG 0xF8
99 #define NS_PHY_TDATA 0xFC
101 #define NS_CLKRUN_PMESTS 0x00008000
102 #define NS_CLKRUN_PMEENB 0x00000100
103 #define NS_CLNRUN_CLKRUN_ENB 0x00000001
105 #define NS_WCSR_WAKE_PHYINTR 0x00000001
106 #define NS_WCSR_WAKE_UCAST 0x00000002
107 #define NS_WCSR_WAKE_MCAST 0x00000004
108 #define NS_WCSR_WAKE_BCAST 0x00000008
109 #define NS_WCSR_WAKE_ARP 0x00000010
110 #define NS_WCSR_WAKE_PATTERN0 0x00000020
111 #define NS_WCSR_WAKE_PATTERN1 0x00000040
112 #define NS_WCSR_WAKE_PATTERN2 0x00000080
113 #define NS_WCSR_WAKE_PATTERN3 0x00000100
114 #define NS_WCSR_WAKE_MAGIC 0x00000200
115 #define NS_WCSR_WAKE_MAGIC_SEC 0x00000400
116 #define NS_WCSR_DET_MAGIC_SECH 0x00100000
117 #define NS_WCSR_DET_PHYINTR 0x00400000
118 #define NS_WCSR_DET_UCAST 0x00800000
119 #define NS_WCSR_DET_MCAST 0x01000000
120 #define NS_WCSR_DET_BCAST 0x02000000
121 #define NS_WCSR_DET_ARP 0x04000000
122 #define NS_WCSR_DET_PATTERN0 0x08000000
123 #define NS_WCSR_DET_PATTERN1 0x10000000
124 #define NS_WCSR_DET_PATTERN2 0x20000000
125 #define NS_WCSR_DET_PATTERN3 0x40000000
126 #define NS_WCSR_DET_MAGIC 0x80000000
128 /* NS silicon revisions */
129 #define NS_SRR_15C 0x302
130 #define NS_SRR_15D 0x403
131 #define NS_SRR_16A 0x505
133 #define SIS_CSR_TX_ENABLE 0x00000001
134 #define SIS_CSR_TX_DISABLE 0x00000002
135 #define SIS_CSR_RX_ENABLE 0x00000004
136 #define SIS_CSR_RX_DISABLE 0x00000008
137 #define SIS_CSR_TX_RESET 0x00000010
138 #define SIS_CSR_RX_RESET 0x00000020
139 #define SIS_CSR_SOFTINTR 0x00000080
140 #define SIS_CSR_RESET 0x00000100
141 #define SIS_CSR_ACCESS_MODE 0x00000200
142 #define SIS_CSR_RELOAD 0x00000400
144 #define SIS_CFG_BIGENDIAN 0x00000001
145 #define SIS_CFG_PERR_DETECT 0x00000008
146 #define SIS_CFG_DEFER_DISABLE 0x00000010
147 #define SIS_CFG_OUTOFWIN_TIMER 0x00000020
148 #define SIS_CFG_SINGLE_BACKOFF 0x00000040
149 #define SIS_CFG_PCIREQ_ALG 0x00000080
150 #define SIS_CFG_FAIR_BACKOFF 0x00000200 /* 635 & 900B Specific */
151 #define SIS_CFG_RND_CNT 0x00000400 /* 635 & 900B Specific */
152 #define SIS_CFG_EDB_MASTER_EN 0x00002000
154 #define SIS_EECTL_DIN 0x00000001
155 #define SIS_EECTL_DOUT 0x00000002
156 #define SIS_EECTL_CLK 0x00000004
157 #define SIS_EECTL_CSEL 0x00000008
159 #define SIS_MII_CLK 0x00000040
160 #define SIS_MII_DIR 0x00000020
161 #define SIS_MII_DATA 0x00000010
163 #define SIS_EECMD_WRITE 0x140
164 #define SIS_EECMD_READ 0x180
165 #define SIS_EECMD_ERASE 0x1c0
168 * EEPROM Commands for SiS96x
171 #define SIS_EECMD_REQ 0x00000400
172 #define SIS_EECMD_DONE 0x00000200
173 #define SIS_EECMD_GNT 0x00000100
175 #define SIS_EE_NODEADDR 0x8
176 #define NS_EE_NODEADDR 0x6
178 #define SIS_PCICTL_SRAMADDR 0x0000001F
179 #define SIS_PCICTL_RAMTSTENB 0x00000020
180 #define SIS_PCICTL_TXTSTENB 0x00000040
181 #define SIS_PCICTL_RXTSTENB 0x00000080
182 #define SIS_PCICTL_BMTSTENB 0x00000200
183 #define SIS_PCICTL_RAMADDR 0x001F0000
184 #define SIS_PCICTL_ROMTIME 0x0F000000
185 #define SIS_PCICTL_DISCTEST 0x40000000
187 #define SIS_ISR_RX_OK 0x00000001
188 #define SIS_ISR_RX_DESC_OK 0x00000002
189 #define SIS_ISR_RX_ERR 0x00000004
190 #define SIS_ISR_RX_EARLY 0x00000008
191 #define SIS_ISR_RX_IDLE 0x00000010
192 #define SIS_ISR_RX_OFLOW 0x00000020
193 #define SIS_ISR_TX_OK 0x00000040
194 #define SIS_ISR_TX_DESC_OK 0x00000080
195 #define SIS_ISR_TX_ERR 0x00000100
196 #define SIS_ISR_TX_IDLE 0x00000200
197 #define SIS_ISR_TX_UFLOW 0x00000400
198 #define SIS_ISR_SOFTINTR 0x00000800
199 #define SIS_ISR_HIBITS 0x00008000
200 #define SIS_ISR_RX_FIFO_OFLOW 0x00010000
201 #define SIS_ISR_TGT_ABRT 0x00100000
202 #define SIS_ISR_BM_ABRT 0x00200000
203 #define SIS_ISR_SYSERR 0x00400000
204 #define SIS_ISR_PARITY_ERR 0x00800000
205 #define SIS_ISR_RX_RESET_DONE 0x01000000
206 #define SIS_ISR_TX_RESET_DONE 0x02000000
207 #define SIS_ISR_TX_PAUSE_START 0x04000000
208 #define SIS_ISR_TX_PAUSE_DONE 0x08000000
209 #define SIS_ISR_WAKE_EVENT 0x10000000
211 #define SIS_IMR_RX_OK 0x00000001
212 #define SIS_IMR_RX_DESC_OK 0x00000002
213 #define SIS_IMR_RX_ERR 0x00000004
214 #define SIS_IMR_RX_EARLY 0x00000008
215 #define SIS_IMR_RX_IDLE 0x00000010
216 #define SIS_IMR_RX_OFLOW 0x00000020
217 #define SIS_IMR_TX_OK 0x00000040
218 #define SIS_IMR_TX_DESC_OK 0x00000080
219 #define SIS_IMR_TX_ERR 0x00000100
220 #define SIS_IMR_TX_IDLE 0x00000200
221 #define SIS_IMR_TX_UFLOW 0x00000400
222 #define SIS_IMR_SOFTINTR 0x00000800
223 #define SIS_IMR_HIBITS 0x00008000
224 #define SIS_IMR_RX_FIFO_OFLOW 0x00010000
225 #define SIS_IMR_TGT_ABRT 0x00100000
226 #define SIS_IMR_BM_ABRT 0x00200000
227 #define SIS_IMR_SYSERR 0x00400000
228 #define SIS_IMR_PARITY_ERR 0x00800000
229 #define SIS_IMR_RX_RESET_DONE 0x01000000
230 #define SIS_IMR_TX_RESET_DONE 0x02000000
231 #define SIS_IMR_TX_PAUSE_START 0x04000000
232 #define SIS_IMR_TX_PAUSE_DONE 0x08000000
233 #define SIS_IMR_WAKE_EVENT 0x10000000
236 (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\
237 SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\
241 #define SIS_IER_INTRENB 0x00000001
243 #define SIS_PHYCTL_ACCESS 0x00000010
244 #define SIS_PHYCTL_OP 0x00000020
245 #define SIS_PHYCTL_REGADDR 0x000007C0
246 #define SIS_PHYCTL_PHYADDR 0x0000F800
247 #define SIS_PHYCTL_PHYDATA 0xFFFF0000
249 #define SIS_PHYOP_READ 0x00000020
250 #define SIS_PHYOP_WRITE 0x00000000
252 #define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */
253 #define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */
254 #define SIS_TXCFG_DMABURST 0x00700000
255 #define SIS_TXCFG_AUTOPAD 0x10000000
256 #define SIS_TXCFG_LOOPBK 0x20000000
257 #define SIS_TXCFG_IGN_HBEAT 0x40000000
258 #define SIS_TXCFG_IGN_CARR 0x80000000
260 #define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH)
261 #define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH)
263 #define SIS_TXDMA_512BYTES 0x00000000
264 #define SIS_TXDMA_4BYTES 0x00100000
265 #define SIS_TXDMA_8BYTES 0x00200000
266 #define SIS_TXDMA_16BYTES 0x00300000
267 #define SIS_TXDMA_32BYTES 0x00400000
268 #define SIS_TXDMA_64BYTES 0x00500000
269 #define SIS_TXDMA_128BYTES 0x00600000
270 #define SIS_TXDMA_256BYTES 0x00700000
272 #define SIS_TXCFG_100 \
273 (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\
274 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
276 #define SIS_TXCFG_10 \
277 (SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\
278 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
280 #define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */
281 #define SIS_TXCFG_MPII03D 0x00040000 /* "Must be 1" */
282 #define SIS_RXCFG_DMABURST 0x00700000
283 #define SIS_RXCFG_RX_JABBER 0x08000000
284 #define SIS_RXCFG_RX_TXPKTS 0x10000000
285 #define SIS_RXCFG_RX_RUNTS 0x40000000
286 #define SIS_RXCFG_RX_GIANTS 0x80000000
288 #define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH)
290 #define SIS_RXDMA_512BYTES 0x00000000
291 #define SIS_RXDMA_4BYTES 0x00100000
292 #define SIS_RXDMA_8BYTES 0x00200000
293 #define SIS_RXDMA_16BYTES 0x00300000
294 #define SIS_RXDMA_32BYTES 0x00400000
295 #define SIS_RXDMA_64BYTES 0x00500000
296 #define SIS_RXDMA_128BYTES 0x00600000
297 #define SIS_RXDMA_256BYTES 0x00700000
299 #define SIS_RXCFG256 \
300 (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES)
301 #define SIS_RXCFG64 \
302 (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_64BYTES)
304 #define SIS_RXFILTCTL_ADDR 0x000F0000
305 #define NS_RXFILTCTL_MCHASH 0x00200000
306 #define NS_RXFILTCTL_ARP 0x00400000
307 #define NS_RXFILTCTL_PERFECT 0x08000000
308 #define SIS_RXFILTCTL_ALLPHYS 0x10000000
309 #define SIS_RXFILTCTL_ALLMULTI 0x20000000
310 #define SIS_RXFILTCTL_BROAD 0x40000000
311 #define SIS_RXFILTCTL_ENABLE 0x80000000
313 #define SIS_FILTADDR_PAR0 0x00000000
314 #define SIS_FILTADDR_PAR1 0x00010000
315 #define SIS_FILTADDR_PAR2 0x00020000
316 #define SIS_FILTADDR_MAR0 0x00040000
317 #define SIS_FILTADDR_MAR1 0x00050000
318 #define SIS_FILTADDR_MAR2 0x00060000
319 #define SIS_FILTADDR_MAR3 0x00070000
320 #define SIS_FILTADDR_MAR4 0x00080000
321 #define SIS_FILTADDR_MAR5 0x00090000
322 #define SIS_FILTADDR_MAR6 0x000A0000
323 #define SIS_FILTADDR_MAR7 0x000B0000
325 #define NS_FILTADDR_PAR0 0x00000000
326 #define NS_FILTADDR_PAR1 0x00000002
327 #define NS_FILTADDR_PAR2 0x00000004
329 #define NS_FILTADDR_FMEM_LO 0x00000200
330 #define NS_FILTADDR_FMEM_HI 0x000003FE
332 #define SIS_PWRMAN_WOL_LINK_OFF 0x00000001
333 #define SIS_PWRMAN_WOL_LINK_ON 0x00000002
334 #define SIS_PWRMAN_WOL_MAGIC 0x00000400
337 * TX/RX DMA descriptor structures.
340 /* SiS hardware descriptor section */
342 volatile uint32_t sis_cmdsts;
343 volatile uint32_t sis_ptr;
346 #define SIS_CMDSTS_BUFLEN 0x00000FFF
347 #define SIS_CMDSTS_PKT_OK 0x08000000
348 #define SIS_CMDSTS_CRC 0x10000000
349 #define SIS_CMDSTS_INTR 0x20000000
350 #define SIS_CMDSTS_MORE 0x40000000
351 #define SIS_CMDSTS_OWN 0x80000000
353 #define SIS_RXSTAT_COLL 0x00010000
354 #define SIS_RXSTAT_LOOPBK 0x00020000
355 #define SIS_RXSTAT_ALIGNERR 0x00040000
356 #define SIS_RXSTAT_CRCERR 0x00080000
357 #define SIS_RXSTAT_SYMBOLERR 0x00100000
358 #define SIS_RXSTAT_RUNT 0x00200000
359 #define SIS_RXSTAT_GIANT 0x00400000
360 #define SIS_RXSTAT_DSTCLASS 0x01800000
361 #define SIS_RXSTAT_OVERRUN 0x02000000
362 #define SIS_RXSTAT_RX_ABORT 0x04000000
364 #define SIS_RXSTAT_ERROR(x) \
365 ((x) & (SIS_RXSTAT_RX_ABORT | SIS_RXSTAT_OVERRUN | \
366 SIS_RXSTAT_GIANT | SIS_RXSTAT_SYMBOLERR | SIS_RXSTAT_RUNT | \
367 SIS_RXSTAT_CRCERR | SIS_RXSTAT_ALIGNERR))
369 #define SIS_DSTCLASS_REJECT 0x00000000
370 #define SIS_DSTCLASS_UNICAST 0x00800000
371 #define SIS_DSTCLASS_MULTICAST 0x01000000
372 #define SIS_DSTCLASS_BROADCAST 0x02000000
374 #define SIS_TXSTAT_COLLCNT 0x000F0000
375 #define SIS_TXSTAT_EXCESSCOLLS 0x00100000
376 #define SIS_TXSTAT_OUTOFWINCOLL 0x00200000
377 #define SIS_TXSTAT_EXCESS_DEFER 0x00400000
378 #define SIS_TXSTAT_DEFERED 0x00800000
379 #define SIS_TXSTAT_CARR_LOST 0x01000000
380 #define SIS_TXSTAT_UNDERRUN 0x02000000
381 #define SIS_TXSTAT_TX_ABORT 0x04000000
383 #define SIS_DESC_ALIGN 16
384 #define SIS_RX_BUF_ALIGN 4
385 #define SIS_MAXTXSEGS 16
386 #define SIS_RX_LIST_CNT 64
387 #define SIS_TX_LIST_CNT 128
389 #define SIS_RX_LIST_SZ SIS_RX_LIST_CNT * sizeof(struct sis_desc)
390 #define SIS_TX_LIST_SZ SIS_TX_LIST_CNT * sizeof(struct sis_desc)
392 #define SIS_ADDR_LO(x) ((uint64_t) (x) & 0xffffffff)
393 #define SIS_ADDR_HI(x) ((uint64_t) (x) >> 32)
395 #define SIS_RX_RING_ADDR(sc, i) \
396 ((sc)->sis_rx_paddr + sizeof(struct sis_desc) * (i))
397 #define SIS_TX_RING_ADDR(sc, i) \
398 ((sc)->sis_tx_paddr + sizeof(struct sis_desc) * (i))
400 #define SIS_INC(x, y) (x) = (x + 1) % (y)
405 #define SIS_VENDORID 0x1039
410 #define SIS_DEVICEID_900 0x0900
411 #define SIS_DEVICEID_7016 0x7016
414 * SiS 900 PCI revision codes.
416 #define SIS_REV_900B 0x0003
417 #define SIS_REV_630A 0x0080
418 #define SIS_REV_630E 0x0081
419 #define SIS_REV_630S 0x0082
420 #define SIS_REV_630EA1 0x0083
421 #define SIS_REV_630ET 0x0084
422 #define SIS_REV_635 0x0090
423 #define SIS_REV_96x 0x0091
428 #define NS_VENDORID 0x100B
433 #define NS_DEVICEID_DP83815 0x0020
438 const char *sis_name;
441 #define SIS_TYPE_900 1
442 #define SIS_TYPE_7016 2
443 #define SIS_TYPE_83815 3
447 bus_dmamap_t tx_dmamap;
452 bus_dmamap_t rx_dmamap;
453 struct sis_desc *rx_desc;
457 if_t sis_ifp; /* interface info */
458 struct resource *sis_res[2];
465 #define SIS_FLAG_MANUAL_PAD 0x0800
466 #define SIS_FLAG_LINK 0x8000
469 struct sis_desc *sis_rx_list;
470 struct sis_desc *sis_tx_list;
471 bus_dma_tag_t sis_rx_list_tag;
472 bus_dmamap_t sis_rx_list_map;
473 bus_dma_tag_t sis_tx_list_tag;
474 bus_dmamap_t sis_tx_list_map;
475 bus_dma_tag_t sis_parent_tag;
476 bus_dma_tag_t sis_rx_tag;
477 bus_dmamap_t sis_rx_sparemap;
478 bus_dma_tag_t sis_tx_tag;
479 struct sis_rxdesc sis_rxdesc[SIS_RX_LIST_CNT];
480 struct sis_txdesc sis_txdesc[SIS_TX_LIST_CNT];
485 bus_addr_t sis_rx_paddr;
486 bus_addr_t sis_tx_paddr;
487 struct callout sis_stat_ch;
488 int sis_watchdog_timer;
490 #ifdef DEVICE_POLLING
496 #define SIS_TIMEOUT 1000
497 #define ETHER_ALIGN 2
498 #define SIS_RXLEN 1536
499 #define SIS_MIN_FRAMELEN 60
502 * PCI low memory base and low I/O base register, and
503 * other PCI registers.
506 #define SIS_PCI_VENDOR_ID 0x00
507 #define SIS_PCI_DEVICE_ID 0x02
508 #define SIS_PCI_COMMAND 0x04
509 #define SIS_PCI_STATUS 0x06
510 #define SIS_PCI_REVID 0x08
511 #define SIS_PCI_CLASSCODE 0x09
512 #define SIS_PCI_CACHELEN 0x0C
513 #define SIS_PCI_LATENCY_TIMER 0x0D
514 #define SIS_PCI_HEADER_TYPE 0x0E
515 #define SIS_PCI_LOIO 0x10
516 #define SIS_PCI_LOMEM 0x14
517 #define SIS_PCI_BIOSROM 0x30
518 #define SIS_PCI_INTLINE 0x3C
519 #define SIS_PCI_INTPIN 0x3D
520 #define SIS_PCI_MINGNT 0x3E
521 #define SIS_PCI_MINLAT 0x0F
522 #define SIS_PCI_RESETOPT 0x48
523 #define SIS_PCI_EEPROM_DATA 0x4C
525 /* power management registers */
526 #define SIS_PCI_CAPID 0x50 /* 8 bits */
527 #define SIS_PCI_NEXTPTR 0x51 /* 8 bits */
528 #define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */
529 #define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
531 #define SIS_PSTATE_MASK 0x0003
532 #define SIS_PSTATE_D0 0x0000
533 #define SIS_PSTATE_D1 0x0001
534 #define SIS_PSTATE_D2 0x0002
535 #define SIS_PSTATE_D3 0x0003
536 #define SIS_PME_EN 0x0010
537 #define SIS_PME_STATUS 0x8000