sys/dev/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*-
   4  * SPDX-License-Identifier: BSD-4-Clause
   5  *
   6  * Copyright (c) 1997, 1998, 1999, 2000
   7  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed by Bill Paul.
  20  * 4. Neither the name of the author nor the names of any co-contributors
  21  *    may be used to endorse or promote products derived from this software
  22  *    without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  34  * THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36 /*-
  37  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  38  *
  39  * Permission to use, copy, modify, and distribute this software for any
  40  * purpose with or without fee is hereby granted, provided that the above
  41  * copyright notice and this permission notice appear in all copies.
  42  *
  43  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  44  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  45  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  46  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  47  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  48  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  49  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  50  */
  51
  52 #include <sys/cdefs.h>
  53 __FBSDID("$FreeBSD$");
  54
  55 /*
  56  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  57  * the SK-984x series adapters, both single port and dual port.
  58  * References:
  59  *      The XaQti XMAC II datasheet,
  60  *  https://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  61  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  62  *
  63  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
  64  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  65  * convenience to others until Vitesse corrects this problem:
  66  *
  67  * https://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  68  *
  69  * Written by Bill Paul <wpaul@ee.columbia.edu>
  70  * Department of Electrical Engineering
  71  * Columbia University, New York City
  72  */
  73 /*
  74  * The SysKonnect gigabit ethernet adapters consist of two main
  75  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  76  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  77  * components and a PHY while the GEnesis controller provides a PCI
  78  * interface with DMA support. Each card may have between 512K and
  79  * 2MB of SRAM on board depending on the configuration.
  80  *
  81  * The SysKonnect GEnesis controller can have either one or two XMAC
  82  * chips connected to it, allowing single or dual port NIC configurations.
  83  * SysKonnect has the distinction of being the only vendor on the market
  84  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  85  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  86  * XMAC registers. This driver takes advantage of these features to allow
  87  * both XMACs to operate as independent interfaces.
  88  */
  89
  90 #include <sys/param.h>
  91 #include <sys/systm.h>
  92 #include <sys/bus.h>
  93 #include <sys/endian.h>
  94 #include <sys/mbuf.h>
  95 #include <sys/malloc.h>
  96 #include <sys/kernel.h>
  97 #include <sys/module.h>
  98 #include <sys/socket.h>
  99 #include <sys/sockio.h>
 100 #include <sys/queue.h>
 101 #include <sys/sysctl.h>
 102
 103 #include <net/bpf.h>
 104 #include <net/ethernet.h>
 105 #include <net/if.h>
 106 #include <net/if_var.h>
 107 #include <net/if_arp.h>
 108 #include <net/if_dl.h>
 109 #include <net/if_media.h>
 110 #include <net/if_types.h>
 111 #include <net/if_vlan_var.h>
 112
 113 #include <netinet/in.h>
 114 #include <netinet/in_systm.h>
 115 #include <netinet/ip.h>
 116
 117 #include <machine/bus.h>
 118 #include <machine/in_cksum.h>
 119 #include <machine/resource.h>
 120 #include <sys/rman.h>
 121
 122 #include <dev/mii/mii.h>
 123 #include <dev/mii/miivar.h>
 124 #include <dev/mii/brgphyreg.h>
 125
 126 #include <dev/pci/pcireg.h>
 127 #include <dev/pci/pcivar.h>
 128
 129 #if 0
 130 #define SK_USEIOSPACE
 131 #endif
 132
 133 #include <dev/sk/if_skreg.h>
 134 #include <dev/sk/xmaciireg.h>
 135 #include <dev/sk/yukonreg.h>
 136
 137 MODULE_DEPEND(sk, pci, 1, 1, 1);
 138 MODULE_DEPEND(sk, ether, 1, 1, 1);
 139 MODULE_DEPEND(sk, miibus, 1, 1, 1);
 140
 141 /* "device miibus" required.  See GENERIC if you get errors here. */
 142 #include "miibus_if.h"
 143
 144 static const struct sk_type sk_devs[] = {
 145         {
 146                 VENDORID_SK,
 147                 DEVICEID_SK_V1,
 148                 "SysKonnect Gigabit Ethernet (V1.0)"
 149         },
 150         {
 151                 VENDORID_SK,
 152                 DEVICEID_SK_V2,
 153                 "SysKonnect Gigabit Ethernet (V2.0)"
 154         },
 155         {
 156                 VENDORID_MARVELL,
 157                 DEVICEID_SK_V2,
 158                 "Marvell Gigabit Ethernet"
 159         },
 160         {
 161                 VENDORID_MARVELL,
 162                 DEVICEID_BELKIN_5005,
 163                 "Belkin F5D5005 Gigabit Ethernet"
 164         },
 165         {
 166                 VENDORID_3COM,
 167                 DEVICEID_3COM_3C940,
 168                 "3Com 3C940 Gigabit Ethernet"
 169         },
 170         {
 171                 VENDORID_LINKSYS,
 172                 DEVICEID_LINKSYS_EG1032,
 173                 "Linksys EG1032 Gigabit Ethernet"
 174         },
 175         {
 176                 VENDORID_DLINK,
 177                 DEVICEID_DLINK_DGE530T_A1,
 178                 "D-Link DGE-530T Gigabit Ethernet"
 179         },
 180         {
 181                 VENDORID_DLINK,
 182                 DEVICEID_DLINK_DGE530T_B1,
 183                 "D-Link DGE-530T Gigabit Ethernet"
 184         },
 185         { 0, 0, NULL }
 186 };
 187
 188 static int skc_probe(device_t);
 189 static int skc_attach(device_t);
 190 static int skc_detach(device_t);
 191 static int skc_shutdown(device_t);
 192 static int skc_suspend(device_t);
 193 static int skc_resume(device_t);
 194 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t);
 195 static int sk_detach(device_t);
 196 static int sk_probe(device_t);
 197 static int sk_attach(device_t);
 198 static void sk_tick(void *);
 199 static void sk_yukon_tick(void *);
 200 static void sk_intr(void *);
 201 static void sk_intr_xmac(struct sk_if_softc *);
 202 static void sk_intr_bcom(struct sk_if_softc *);
 203 static void sk_intr_yukon(struct sk_if_softc *);
 204 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
 205 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
 206 static void sk_rxeof(struct sk_if_softc *);
 207 static void sk_jumbo_rxeof(struct sk_if_softc *);
 208 static void sk_txeof(struct sk_if_softc *);
 209 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
 210 static int sk_encap(struct sk_if_softc *, struct mbuf **);
 211 static void sk_start(struct ifnet *);
 212 static void sk_start_locked(struct ifnet *);
 213 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
 214 static void sk_init(void *);
 215 static void sk_init_locked(struct sk_if_softc *);
 216 static void sk_init_xmac(struct sk_if_softc *);
 217 static void sk_init_yukon(struct sk_if_softc *);
 218 static void sk_stop(struct sk_if_softc *);
 219 static void sk_watchdog(void *);
 220 static int sk_ifmedia_upd(struct ifnet *);
 221 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 222 static void sk_reset(struct sk_softc *);
 223 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
 224 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
 225 static int sk_newbuf(struct sk_if_softc *, int);
 226 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
 227 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 228 static int sk_dma_alloc(struct sk_if_softc *);
 229 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
 230 static void sk_dma_free(struct sk_if_softc *);
 231 static void sk_dma_jumbo_free(struct sk_if_softc *);
 232 static int sk_init_rx_ring(struct sk_if_softc *);
 233 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
 234 static void sk_init_tx_ring(struct sk_if_softc *);
 235 static u_int32_t sk_win_read_4(struct sk_softc *, int);
 236 static u_int16_t sk_win_read_2(struct sk_softc *, int);
 237 static u_int8_t sk_win_read_1(struct sk_softc *, int);
 238 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
 239 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
 240 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
 241
 242 static int sk_miibus_readreg(device_t, int, int);
 243 static int sk_miibus_writereg(device_t, int, int, int);
 244 static void sk_miibus_statchg(device_t);
 245
 246 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
 247 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
 248                                                 int);
 249 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
 250
 251 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
 252 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
 253                                                 int);
 254 static void sk_marv_miibus_statchg(struct sk_if_softc *);
 255
 256 static uint32_t sk_xmchash(const uint8_t *);
 257 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
 258 static void sk_rxfilter(struct sk_if_softc *);
 259 static void sk_rxfilter_genesis(struct sk_if_softc *);
 260 static void sk_rxfilter_yukon(struct sk_if_softc *);
 261
 262 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
 263 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
 264
 265 /* Tunables. */
 266 static int jumbo_disable = 0;
 267 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
 268
 269 /*
 270  * It seems that SK-NET GENESIS supports very simple checksum offload
 271  * capability for Tx and I believe it can generate 0 checksum value for
 272  * UDP packets in Tx as the hardware can't differenciate UDP packets from
 273  * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
 274  * means sender didn't perforam checksum computation. For the safety I
 275  * disabled UDP checksum offload capability at the moment. Alternatively
 276  * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
 277  * offload routine.
 278  */
 279 #define SK_CSUM_FEATURES        (CSUM_TCP)
 280
 281 /*
 282  * Note that we have newbus methods for both the GEnesis controller
 283  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 284  * the miibus code is a child of the XMACs. We need to do it this way
 285  * so that the miibus drivers can access the PHY registers on the
 286  * right PHY. It's not quite what I had in mind, but it's the only
 287  * design that achieves the desired effect.
 288  */
 289 static device_method_t skc_methods[] = {
 290         /* Device interface */
 291         DEVMETHOD(device_probe,         skc_probe),
 292         DEVMETHOD(device_attach,        skc_attach),
 293         DEVMETHOD(device_detach,        skc_detach),
 294         DEVMETHOD(device_suspend,       skc_suspend),
 295         DEVMETHOD(device_resume,        skc_resume),
 296         DEVMETHOD(device_shutdown,      skc_shutdown),
 297
 298         DEVMETHOD(bus_get_dma_tag,      skc_get_dma_tag),
 299
 300         DEVMETHOD_END
 301 };
 302
 303 static driver_t skc_driver = {
 304         "skc",
 305         skc_methods,
 306         sizeof(struct sk_softc)
 307 };
 308
 309 static devclass_t skc_devclass;
 310
 311 static device_method_t sk_methods[] = {
 312         /* Device interface */
 313         DEVMETHOD(device_probe,         sk_probe),
 314         DEVMETHOD(device_attach,        sk_attach),
 315         DEVMETHOD(device_detach,        sk_detach),
 316         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 317
 318         /* MII interface */
 319         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 320         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 321         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 322
 323         DEVMETHOD_END
 324 };
 325
 326 static driver_t sk_driver = {
 327         "sk",
 328         sk_methods,
 329         sizeof(struct sk_if_softc)
 330 };
 331
 332 static devclass_t sk_devclass;
 333
 334 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, NULL, NULL);
 335 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, NULL, NULL);
 336 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL);
 337
 338 static struct resource_spec sk_res_spec_io[] = {
 339         { SYS_RES_IOPORT,       PCIR_BAR(1),    RF_ACTIVE },
 340         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 341         { -1,                   0,              0 }
 342 };
 343
 344 static struct resource_spec sk_res_spec_mem[] = {
 345         { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 346         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 347         { -1,                   0,              0 }
 348 };
 349
 350 #define SK_SETBIT(sc, reg, x)           \
 351         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 352
 353 #define SK_CLRBIT(sc, reg, x)           \
 354         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 355
 356 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 357         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 358
 359 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 360         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 361
 362 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 363         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 364
 365 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 366         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 367
 368 static u_int32_t
 369 sk_win_read_4(sc, reg)
 370         struct sk_softc         *sc;
 371         int                     reg;
 372 {
 373 #ifdef SK_USEIOSPACE
 374         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 375         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 376 #else
 377         return(CSR_READ_4(sc, reg));
 378 #endif
 379 }
 380
 381 static u_int16_t
 382 sk_win_read_2(sc, reg)
 383         struct sk_softc         *sc;
 384         int                     reg;
 385 {
 386 #ifdef SK_USEIOSPACE
 387         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 388         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 389 #else
 390         return(CSR_READ_2(sc, reg));
 391 #endif
 392 }
 393
 394 static u_int8_t
 395 sk_win_read_1(sc, reg)
 396         struct sk_softc         *sc;
 397         int                     reg;
 398 {
 399 #ifdef SK_USEIOSPACE
 400         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 401         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 402 #else
 403         return(CSR_READ_1(sc, reg));
 404 #endif
 405 }
 406
 407 static void
 408 sk_win_write_4(sc, reg, val)
 409         struct sk_softc         *sc;
 410         int                     reg;
 411         u_int32_t               val;
 412 {
 413 #ifdef SK_USEIOSPACE
 414         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 415         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 416 #else
 417         CSR_WRITE_4(sc, reg, val);
 418 #endif
 419         return;
 420 }
 421
 422 static void
 423 sk_win_write_2(sc, reg, val)
 424         struct sk_softc         *sc;
 425         int                     reg;
 426         u_int32_t               val;
 427 {
 428 #ifdef SK_USEIOSPACE
 429         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 430         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 431 #else
 432         CSR_WRITE_2(sc, reg, val);
 433 #endif
 434         return;
 435 }
 436
 437 static void
 438 sk_win_write_1(sc, reg, val)
 439         struct sk_softc         *sc;
 440         int                     reg;
 441         u_int32_t               val;
 442 {
 443 #ifdef SK_USEIOSPACE
 444         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 445         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 446 #else
 447         CSR_WRITE_1(sc, reg, val);
 448 #endif
 449         return;
 450 }
 451
 452 static int
 453 sk_miibus_readreg(dev, phy, reg)
 454         device_t                dev;
 455         int                     phy, reg;
 456 {
 457         struct sk_if_softc      *sc_if;
 458         int                     v;
 459
 460         sc_if = device_get_softc(dev);
 461
 462         SK_IF_MII_LOCK(sc_if);
 463         switch(sc_if->sk_softc->sk_type) {
 464         case SK_GENESIS:
 465                 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
 466                 break;
 467         case SK_YUKON:
 468         case SK_YUKON_LITE:
 469         case SK_YUKON_LP:
 470                 v = sk_marv_miibus_readreg(sc_if, phy, reg);
 471                 break;
 472         default:
 473                 v = 0;
 474                 break;
 475         }
 476         SK_IF_MII_UNLOCK(sc_if);
 477
 478         return (v);
 479 }
 480
 481 static int
 482 sk_miibus_writereg(dev, phy, reg, val)
 483         device_t                dev;
 484         int                     phy, reg, val;
 485 {
 486         struct sk_if_softc      *sc_if;
 487         int                     v;
 488
 489         sc_if = device_get_softc(dev);
 490
 491         SK_IF_MII_LOCK(sc_if);
 492         switch(sc_if->sk_softc->sk_type) {
 493         case SK_GENESIS:
 494                 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
 495                 break;
 496         case SK_YUKON:
 497         case SK_YUKON_LITE:
 498         case SK_YUKON_LP:
 499                 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
 500                 break;
 501         default:
 502                 v = 0;
 503                 break;
 504         }
 505         SK_IF_MII_UNLOCK(sc_if);
 506
 507         return (v);
 508 }
 509
 510 static void
 511 sk_miibus_statchg(dev)
 512         device_t                dev;
 513 {
 514         struct sk_if_softc      *sc_if;
 515
 516         sc_if = device_get_softc(dev);
 517
 518         SK_IF_MII_LOCK(sc_if);
 519         switch(sc_if->sk_softc->sk_type) {
 520         case SK_GENESIS:
 521                 sk_xmac_miibus_statchg(sc_if);
 522                 break;
 523         case SK_YUKON:
 524         case SK_YUKON_LITE:
 525         case SK_YUKON_LP:
 526                 sk_marv_miibus_statchg(sc_if);
 527                 break;
 528         }
 529         SK_IF_MII_UNLOCK(sc_if);
 530
 531         return;
 532 }
 533
 534 static int
 535 sk_xmac_miibus_readreg(sc_if, phy, reg)
 536         struct sk_if_softc      *sc_if;
 537         int                     phy, reg;
 538 {
 539         int                     i;
 540
 541         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 542         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 543         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 544                 for (i = 0; i < SK_TIMEOUT; i++) {
 545                         DELAY(1);
 546                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 547                             XM_MMUCMD_PHYDATARDY)
 548                                 break;
 549                 }
 550
 551                 if (i == SK_TIMEOUT) {
 552                         if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 553                         return(0);
 554                 }
 555         }
 556         DELAY(1);
 557         i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
 558
 559         return(i);
 560 }
 561
 562 static int
 563 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 564         struct sk_if_softc      *sc_if;
 565         int                     phy, reg, val;
 566 {
 567         int                     i;
 568
 569         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 570         for (i = 0; i < SK_TIMEOUT; i++) {
 571                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 572                         break;
 573         }
 574
 575         if (i == SK_TIMEOUT) {
 576                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 577                 return (ETIMEDOUT);
 578         }
 579
 580         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 581         for (i = 0; i < SK_TIMEOUT; i++) {
 582                 DELAY(1);
 583                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 584                         break;
 585         }
 586         if (i == SK_TIMEOUT)
 587                 if_printf(sc_if->sk_ifp, "phy write timed out\n");
 588
 589         return(0);
 590 }
 591
 592 static void
 593 sk_xmac_miibus_statchg(sc_if)
 594         struct sk_if_softc      *sc_if;
 595 {
 596         struct mii_data         *mii;
 597
 598         mii = device_get_softc(sc_if->sk_miibus);
 599
 600         /*
 601          * If this is a GMII PHY, manually set the XMAC's
 602          * duplex mode accordingly.
 603          */
 604         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 605                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 606                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 607                 } else {
 608                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 609                 }
 610         }
 611 }
 612
 613 static int
 614 sk_marv_miibus_readreg(sc_if, phy, reg)
 615         struct sk_if_softc      *sc_if;
 616         int                     phy, reg;
 617 {
 618         u_int16_t               val;
 619         int                     i;
 620
 621         if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 622             sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
 623                 return(0);
 624         }
 625
 626         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 627                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 628
 629         for (i = 0; i < SK_TIMEOUT; i++) {
 630                 DELAY(1);
 631                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 632                 if (val & YU_SMICR_READ_VALID)
 633                         break;
 634         }
 635
 636         if (i == SK_TIMEOUT) {
 637                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 638                 return(0);
 639         }
 640
 641         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 642
 643         return(val);
 644 }
 645
 646 static int
 647 sk_marv_miibus_writereg(sc_if, phy, reg, val)
 648         struct sk_if_softc      *sc_if;
 649         int                     phy, reg, val;
 650 {
 651         int                     i;
 652
 653         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 654         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 655                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 656
 657         for (i = 0; i < SK_TIMEOUT; i++) {
 658                 DELAY(1);
 659                 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
 660                         break;
 661         }
 662         if (i == SK_TIMEOUT)
 663                 if_printf(sc_if->sk_ifp, "phy write timeout\n");
 664
 665         return(0);
 666 }
 667
 668 static void
 669 sk_marv_miibus_statchg(sc_if)
 670         struct sk_if_softc      *sc_if;
 671 {
 672         return;
 673 }
 674
 675 #define HASH_BITS               6
 676
 677 static u_int32_t
 678 sk_xmchash(addr)
 679         const uint8_t *addr;
 680 {
 681         uint32_t crc;
 682
 683         /* Compute CRC for the address value. */
 684         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 685
 686         return (~crc & ((1 << HASH_BITS) - 1));
 687 }
 688
 689 static void
 690 sk_setfilt(sc_if, addr, slot)
 691         struct sk_if_softc      *sc_if;
 692         u_int16_t               *addr;
 693         int                     slot;
 694 {
 695         int                     base;
 696
 697         base = XM_RXFILT_ENTRY(slot);
 698
 699         SK_XM_WRITE_2(sc_if, base, addr[0]);
 700         SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
 701         SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
 702
 703         return;
 704 }
 705
 706 static void
 707 sk_rxfilter(sc_if)
 708         struct sk_if_softc      *sc_if;
 709 {
 710         struct sk_softc         *sc;
 711
 712         SK_IF_LOCK_ASSERT(sc_if);
 713
 714         sc = sc_if->sk_softc;
 715         if (sc->sk_type == SK_GENESIS)
 716                 sk_rxfilter_genesis(sc_if);
 717         else
 718                 sk_rxfilter_yukon(sc_if);
 719 }
 720
 721 struct sk_add_maddr_genesis_ctx {
 722         struct sk_if_softc *sc_if;
 723         uint32_t hashes[2];
 724         uint32_t mode;
 725 };
 726
 727 static u_int
 728 sk_add_maddr_genesis(void *arg, struct sockaddr_dl *sdl, u_int cnt)
 729 {
 730         struct sk_add_maddr_genesis_ctx *ctx = arg;
 731         int h;
 732
 733         /*
 734          * Program the first XM_RXFILT_MAX multicast groups
 735          * into the perfect filter.
 736          */
 737         if (cnt + 1 < XM_RXFILT_MAX) {
 738                 sk_setfilt(ctx->sc_if, (uint16_t *)LLADDR(sdl), cnt + 1);
 739                 ctx->mode |= XM_MODE_RX_USE_PERFECT;
 740                 return (1);
 741         }
 742         h = sk_xmchash((const uint8_t *)LLADDR(sdl));
 743         if (h < 32)
 744                 ctx->hashes[0] |= (1 << h);
 745         else
 746                 ctx->hashes[1] |= (1 << (h - 32));
 747         ctx->mode |= XM_MODE_RX_USE_HASH;
 748
 749         return (1);
 750 }
 751
 752 static void
 753 sk_rxfilter_genesis(struct sk_if_softc *sc_if)
 754 {
 755         struct ifnet            *ifp = sc_if->sk_ifp;
 756         struct sk_add_maddr_genesis_ctx ctx = { sc_if, { 0, 0 } };
 757         int                     i;
 758         u_int16_t               dummy[] = { 0, 0, 0 };
 759
 760         SK_IF_LOCK_ASSERT(sc_if);
 761
 762         ctx.mode = SK_XM_READ_4(sc_if, XM_MODE);
 763         ctx.mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
 764             XM_MODE_RX_USE_PERFECT);
 765         /* First, zot all the existing perfect filters. */
 766         for (i = 1; i < XM_RXFILT_MAX; i++)
 767                 sk_setfilt(sc_if, dummy, i);
 768
 769         /* Now program new ones. */
 770         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 771                 if (ifp->if_flags & IFF_ALLMULTI)
 772                         ctx.mode |= XM_MODE_RX_USE_HASH;
 773                 if (ifp->if_flags & IFF_PROMISC)
 774                         ctx.mode |= XM_MODE_RX_PROMISC;
 775                 ctx.hashes[0] = 0xFFFFFFFF;
 776                 ctx.hashes[1] = 0xFFFFFFFF;
 777         } else
 778                 /* XXX want to maintain reverse semantics */
 779                 if_foreach_llmaddr(ifp, sk_add_maddr_genesis, &ctx);
 780
 781         SK_XM_WRITE_4(sc_if, XM_MODE, ctx.mode);
 782         SK_XM_WRITE_4(sc_if, XM_MAR0, ctx.hashes[0]);
 783         SK_XM_WRITE_4(sc_if, XM_MAR2, ctx.hashes[1]);
 784 }
 785
 786 static u_int
 787 sk_hash_maddr_yukon(void *arg, struct sockaddr_dl *sdl, u_int cnt)
 788 {
 789         uint32_t crc, *hashes = arg;
 790
 791         crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
 792         /* Just want the 6 least significant bits. */
 793         crc &= 0x3f;
 794         /* Set the corresponding bit in the hash table. */
 795         hashes[crc >> 5] |= 1 << (crc & 0x1f);
 796
 797         return (1);
 798 }
 799
 800 static void
 801 sk_rxfilter_yukon(struct sk_if_softc *sc_if)
 802 {
 803         struct ifnet            *ifp;
 804         uint32_t                hashes[2] = { 0, 0 }, mode;
 805
 806         SK_IF_LOCK_ASSERT(sc_if);
 807
 808         ifp = sc_if->sk_ifp;
 809         mode = SK_YU_READ_2(sc_if, YUKON_RCR);
 810         if (ifp->if_flags & IFF_PROMISC)
 811                 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
 812         else if (ifp->if_flags & IFF_ALLMULTI) {
 813                 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
 814                 hashes[0] = 0xFFFFFFFF;
 815                 hashes[1] = 0xFFFFFFFF;
 816         } else {
 817                 mode |= YU_RCR_UFLEN;
 818                 if_foreach_llmaddr(ifp, sk_hash_maddr_yukon, hashes);
 819                 if (hashes[0] != 0 || hashes[1] != 0)
 820                         mode |= YU_RCR_MUFLEN;
 821         }
 822
 823         SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 824         SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 825         SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 826         SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 827         SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
 828 }
 829
 830 static int
 831 sk_init_rx_ring(sc_if)
 832         struct sk_if_softc      *sc_if;
 833 {
 834         struct sk_ring_data     *rd;
 835         bus_addr_t              addr;
 836         u_int32_t               csum_start;
 837         int                     i;
 838
 839         sc_if->sk_cdata.sk_rx_cons = 0;
 840
 841         csum_start = (ETHER_HDR_LEN + sizeof(struct ip))  << 16 |
 842             ETHER_HDR_LEN;
 843         rd = &sc_if->sk_rdata;
 844         bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 845         for (i = 0; i < SK_RX_RING_CNT; i++) {
 846                 if (sk_newbuf(sc_if, i) != 0)
 847                         return (ENOBUFS);
 848                 if (i == (SK_RX_RING_CNT - 1))
 849                         addr = SK_RX_RING_ADDR(sc_if, 0);
 850                 else
 851                         addr = SK_RX_RING_ADDR(sc_if, i + 1);
 852                 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 853                 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
 854         }
 855
 856         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
 857             sc_if->sk_cdata.sk_rx_ring_map,
 858             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 859
 860         return(0);
 861 }
 862
 863 static int
 864 sk_init_jumbo_rx_ring(sc_if)
 865         struct sk_if_softc      *sc_if;
 866 {
 867         struct sk_ring_data     *rd;
 868         bus_addr_t              addr;
 869         u_int32_t               csum_start;
 870         int                     i;
 871
 872         sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
 873
 874         csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
 875             ETHER_HDR_LEN;
 876         rd = &sc_if->sk_rdata;
 877         bzero(rd->sk_jumbo_rx_ring,
 878             sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
 879         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
 880                 if (sk_jumbo_newbuf(sc_if, i) != 0)
 881                         return (ENOBUFS);
 882                 if (i == (SK_JUMBO_RX_RING_CNT - 1))
 883                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
 884                 else
 885                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
 886                 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 887                 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
 888         }
 889
 890         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
 891             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
 892             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 893
 894         return (0);
 895 }
 896
 897 static void
 898 sk_init_tx_ring(sc_if)
 899         struct sk_if_softc      *sc_if;
 900 {
 901         struct sk_ring_data     *rd;
 902         struct sk_txdesc        *txd;
 903         bus_addr_t              addr;
 904         int                     i;
 905
 906         STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
 907         STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
 908
 909         sc_if->sk_cdata.sk_tx_prod = 0;
 910         sc_if->sk_cdata.sk_tx_cons = 0;
 911         sc_if->sk_cdata.sk_tx_cnt = 0;
 912
 913         rd = &sc_if->sk_rdata;
 914         bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 915         for (i = 0; i < SK_TX_RING_CNT; i++) {
 916                 if (i == (SK_TX_RING_CNT - 1))
 917                         addr = SK_TX_RING_ADDR(sc_if, 0);
 918                 else
 919                         addr = SK_TX_RING_ADDR(sc_if, i + 1);
 920                 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 921                 txd = &sc_if->sk_cdata.sk_txdesc[i];
 922                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
 923         }
 924
 925         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
 926             sc_if->sk_cdata.sk_tx_ring_map,
 927             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 928 }
 929
 930 static __inline void
 931 sk_discard_rxbuf(sc_if, idx)
 932         struct sk_if_softc      *sc_if;
 933         int                     idx;
 934 {
 935         struct sk_rx_desc       *r;
 936         struct sk_rxdesc        *rxd;
 937         struct mbuf             *m;
 938
 939
 940         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 941         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 942         m = rxd->rx_m;
 943         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 944 }
 945
 946 static __inline void
 947 sk_discard_jumbo_rxbuf(sc_if, idx)
 948         struct sk_if_softc      *sc_if;
 949         int                     idx;
 950 {
 951         struct sk_rx_desc       *r;
 952         struct sk_rxdesc        *rxd;
 953         struct mbuf             *m;
 954
 955         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
 956         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
 957         m = rxd->rx_m;
 958         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 959 }
 960
 961 static int
 962 sk_newbuf(sc_if, idx)
 963         struct sk_if_softc      *sc_if;
 964         int                     idx;
 965 {
 966         struct sk_rx_desc       *r;
 967         struct sk_rxdesc        *rxd;
 968         struct mbuf             *m;
 969         bus_dma_segment_t       segs[1];
 970         bus_dmamap_t            map;
 971         int                     nsegs;
 972
 973         m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
 974         if (m == NULL)
 975                 return (ENOBUFS);
 976         m->m_len = m->m_pkthdr.len = MCLBYTES;
 977         m_adj(m, ETHER_ALIGN);
 978
 979         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
 980             sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
 981                 m_freem(m);
 982                 return (ENOBUFS);
 983         }
 984         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 985
 986         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 987         if (rxd->rx_m != NULL) {
 988                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 989                     BUS_DMASYNC_POSTREAD);
 990                 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
 991         }
 992         map = rxd->rx_dmamap;
 993         rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
 994         sc_if->sk_cdata.sk_rx_sparemap = map;
 995         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 996             BUS_DMASYNC_PREREAD);
 997         rxd->rx_m = m;
 998         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 999         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1000         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1001         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1002
1003         return (0);
1004 }
1005
1006 static int
1007 sk_jumbo_newbuf(sc_if, idx)
1008         struct sk_if_softc      *sc_if;
1009         int                     idx;
1010 {
1011         struct sk_rx_desc       *r;
1012         struct sk_rxdesc        *rxd;
1013         struct mbuf             *m;
1014         bus_dma_segment_t       segs[1];
1015         bus_dmamap_t            map;
1016         int                     nsegs;
1017
1018         m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1019         if (m == NULL)
1020                 return (ENOBUFS);
1021         m->m_pkthdr.len = m->m_len = MJUM9BYTES;
1022         /*
1023          * Adjust alignment so packet payload begins on a
1024          * longword boundary. Mandatory for Alpha, useful on
1025          * x86 too.
1026          */
1027         m_adj(m, ETHER_ALIGN);
1028
1029         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1030             sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1031                 m_freem(m);
1032                 return (ENOBUFS);
1033         }
1034         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1035
1036         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1037         if (rxd->rx_m != NULL) {
1038                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1039                     BUS_DMASYNC_POSTREAD);
1040                 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1041                     rxd->rx_dmamap);
1042         }
1043         map = rxd->rx_dmamap;
1044         rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1045         sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1046         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1047             BUS_DMASYNC_PREREAD);
1048         rxd->rx_m = m;
1049         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1050         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1051         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1052         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1053
1054         return (0);
1055 }
1056
1057 /*
1058  * Set media options.
1059  */
1060 static int
1061 sk_ifmedia_upd(ifp)
1062         struct ifnet            *ifp;
1063 {
1064         struct sk_if_softc      *sc_if = ifp->if_softc;
1065         struct mii_data         *mii;
1066
1067         mii = device_get_softc(sc_if->sk_miibus);
1068         sk_init(sc_if);
1069         mii_mediachg(mii);
1070
1071         return(0);
1072 }
1073
1074 /*
1075  * Report current media status.
1076  */
1077 static void
1078 sk_ifmedia_sts(ifp, ifmr)
1079         struct ifnet            *ifp;
1080         struct ifmediareq       *ifmr;
1081 {
1082         struct sk_if_softc      *sc_if;
1083         struct mii_data         *mii;
1084
1085         sc_if = ifp->if_softc;
1086         mii = device_get_softc(sc_if->sk_miibus);
1087
1088         mii_pollstat(mii);
1089         ifmr->ifm_active = mii->mii_media_active;
1090         ifmr->ifm_status = mii->mii_media_status;
1091
1092         return;
1093 }
1094
1095 static int
1096 sk_ioctl(ifp, command, data)
1097         struct ifnet            *ifp;
1098         u_long                  command;
1099         caddr_t                 data;
1100 {
1101         struct sk_if_softc      *sc_if = ifp->if_softc;
1102         struct ifreq            *ifr = (struct ifreq *) data;
1103         int                     error, mask;
1104         struct mii_data         *mii;
1105
1106         error = 0;
1107         switch(command) {
1108         case SIOCSIFMTU:
1109                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1110                         error = EINVAL;
1111                 else if (ifp->if_mtu != ifr->ifr_mtu) {
1112                         if (sc_if->sk_jumbo_disable != 0 &&
1113                             ifr->ifr_mtu > SK_MAX_FRAMELEN)
1114                                 error = EINVAL;
1115                         else {
1116                                 SK_IF_LOCK(sc_if);
1117                                 ifp->if_mtu = ifr->ifr_mtu;
1118                                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1119                                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1120                                         sk_init_locked(sc_if);
1121                                 }
1122                                 SK_IF_UNLOCK(sc_if);
1123                         }
1124                 }
1125                 break;
1126         case SIOCSIFFLAGS:
1127                 SK_IF_LOCK(sc_if);
1128                 if (ifp->if_flags & IFF_UP) {
1129                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1130                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1131                                     & (IFF_PROMISC | IFF_ALLMULTI))
1132                                         sk_rxfilter(sc_if);
1133                         } else
1134                                 sk_init_locked(sc_if);
1135                 } else {
1136                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1137                                 sk_stop(sc_if);
1138                 }
1139                 sc_if->sk_if_flags = ifp->if_flags;
1140                 SK_IF_UNLOCK(sc_if);
1141                 break;
1142         case SIOCADDMULTI:
1143         case SIOCDELMULTI:
1144                 SK_IF_LOCK(sc_if);
1145                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1146                         sk_rxfilter(sc_if);
1147                 SK_IF_UNLOCK(sc_if);
1148                 break;
1149         case SIOCGIFMEDIA:
1150         case SIOCSIFMEDIA:
1151                 mii = device_get_softc(sc_if->sk_miibus);
1152                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1153                 break;
1154         case SIOCSIFCAP:
1155                 SK_IF_LOCK(sc_if);
1156                 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1157                         SK_IF_UNLOCK(sc_if);
1158                         break;
1159                 }
1160                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1161                 if ((mask & IFCAP_TXCSUM) != 0 &&
1162                     (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1163                         ifp->if_capenable ^= IFCAP_TXCSUM;
1164                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1165                                 ifp->if_hwassist |= SK_CSUM_FEATURES;
1166                         else
1167                                 ifp->if_hwassist &= ~SK_CSUM_FEATURES;
1168                 }
1169                 if ((mask & IFCAP_RXCSUM) != 0 &&
1170                     (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
1171                         ifp->if_capenable ^= IFCAP_RXCSUM;
1172                 SK_IF_UNLOCK(sc_if);
1173                 break;
1174         default:
1175                 error = ether_ioctl(ifp, command, data);
1176                 break;
1177         }
1178
1179         return (error);
1180 }
1181
1182 /*
1183  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1184  * IDs against our list and return a device name if we find a match.
1185  */
1186 static int
1187 skc_probe(dev)
1188         device_t                dev;
1189 {
1190         const struct sk_type    *t = sk_devs;
1191
1192         while(t->sk_name != NULL) {
1193                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1194                     (pci_get_device(dev) == t->sk_did)) {
1195                         /*
1196                          * Only attach to rev. 2 of the Linksys EG1032 adapter.
1197                          * Rev. 3 is supported by re(4).
1198                          */
1199                         if ((t->sk_vid == VENDORID_LINKSYS) &&
1200                                 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1201                                 (pci_get_subdevice(dev) !=
1202                                  SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1203                                 t++;
1204                                 continue;
1205                         }
1206                         device_set_desc(dev, t->sk_name);
1207                         return (BUS_PROBE_DEFAULT);
1208                 }
1209                 t++;
1210         }
1211
1212         return(ENXIO);
1213 }
1214
1215 /*
1216  * Force the GEnesis into reset, then bring it out of reset.
1217  */
1218 static void
1219 sk_reset(sc)
1220         struct sk_softc         *sc;
1221 {
1222
1223         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1224         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1225         if (SK_YUKON_FAMILY(sc->sk_type))
1226                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1227
1228         DELAY(1000);
1229         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1230         DELAY(2);
1231         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1232         if (SK_YUKON_FAMILY(sc->sk_type))
1233                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1234
1235         if (sc->sk_type == SK_GENESIS) {
1236                 /* Configure packet arbiter */
1237                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1238                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1239                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1240                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1241                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1242         }
1243
1244         /* Enable RAM interface */
1245         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1246
1247         /*
1248          * Configure interrupt moderation. The moderation timer
1249          * defers interrupts specified in the interrupt moderation
1250          * timer mask based on the timeout specified in the interrupt
1251          * moderation timer init register. Each bit in the timer
1252          * register represents one tick, so to specify a timeout in
1253          * microseconds, we have to multiply by the correct number of
1254          * ticks-per-microsecond.
1255          */
1256         switch (sc->sk_type) {
1257         case SK_GENESIS:
1258                 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1259                 break;
1260         default:
1261                 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1262                 break;
1263         }
1264         if (bootverbose)
1265                 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1266                     sc->sk_int_mod);
1267         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1268             sc->sk_int_ticks));
1269         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1270             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1271         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1272
1273         return;
1274 }
1275
1276 static int
1277 sk_probe(dev)
1278         device_t                dev;
1279 {
1280         struct sk_softc         *sc;
1281
1282         sc = device_get_softc(device_get_parent(dev));
1283
1284         /*
1285          * Not much to do here. We always know there will be
1286          * at least one XMAC present, and if there are two,
1287          * skc_attach() will create a second device instance
1288          * for us.
1289          */
1290         switch (sc->sk_type) {
1291         case SK_GENESIS:
1292                 device_set_desc(dev, "XaQti Corp. XMAC II");
1293                 break;
1294         case SK_YUKON:
1295         case SK_YUKON_LITE:
1296         case SK_YUKON_LP:
1297                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1298                 break;
1299         }
1300
1301         return (BUS_PROBE_DEFAULT);
1302 }
1303
1304 /*
1305  * Each XMAC chip is attached as a separate logical IP interface.
1306  * Single port cards will have only one logical interface of course.
1307  */
1308 static int
1309 sk_attach(dev)
1310         device_t                dev;
1311 {
1312         struct sk_softc         *sc;
1313         struct sk_if_softc      *sc_if;
1314         struct ifnet            *ifp;
1315         u_int32_t               r;
1316         int                     error, i, phy, port;
1317         u_char                  eaddr[6];
1318         u_char                  inv_mac[] = {0, 0, 0, 0, 0, 0};
1319
1320         if (dev == NULL)
1321                 return(EINVAL);
1322
1323         error = 0;
1324         sc_if = device_get_softc(dev);
1325         sc = device_get_softc(device_get_parent(dev));
1326         port = *(int *)device_get_ivars(dev);
1327
1328         sc_if->sk_if_dev = dev;
1329         sc_if->sk_port = port;
1330         sc_if->sk_softc = sc;
1331         sc->sk_if[port] = sc_if;
1332         if (port == SK_PORT_A)
1333                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1334         if (port == SK_PORT_B)
1335                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1336
1337         callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1338         callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1339
1340         if (sk_dma_alloc(sc_if) != 0) {
1341                 error = ENOMEM;
1342                 goto fail;
1343         }
1344         sk_dma_jumbo_alloc(sc_if);
1345
1346         ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1347         if (ifp == NULL) {
1348                 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1349                 error = ENOSPC;
1350                 goto fail;
1351         }
1352         ifp->if_softc = sc_if;
1353         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1354         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1355         /*
1356          * SK_GENESIS has a bug in checksum offload - From linux.
1357          */
1358         if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1359                 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
1360                 ifp->if_hwassist = 0;
1361         } else {
1362                 ifp->if_capabilities = 0;
1363                 ifp->if_hwassist = 0;
1364         }
1365         ifp->if_capenable = ifp->if_capabilities;
1366         /*
1367          * Some revision of Yukon controller generates corrupted
1368          * frame when TX checksum offloading is enabled.  The
1369          * frame has a valid checksum value so payload might be
1370          * modified during TX checksum calculation. Disable TX
1371          * checksum offloading but give users chance to enable it
1372          * when they know their controller works without problems
1373          * with TX checksum offloading.
1374          */
1375         ifp->if_capenable &= ~IFCAP_TXCSUM;
1376         ifp->if_ioctl = sk_ioctl;
1377         ifp->if_start = sk_start;
1378         ifp->if_init = sk_init;
1379         IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1380         ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1381         IFQ_SET_READY(&ifp->if_snd);
1382
1383         /*
1384          * Get station address for this interface. Note that
1385          * dual port cards actually come with three station
1386          * addresses: one for each port, plus an extra. The
1387          * extra one is used by the SysKonnect driver software
1388          * as a 'virtual' station address for when both ports
1389          * are operating in failover mode. Currently we don't
1390          * use this extra address.
1391          */
1392         SK_IF_LOCK(sc_if);
1393         for (i = 0; i < ETHER_ADDR_LEN; i++)
1394                 eaddr[i] =
1395                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1396
1397         /* Verify whether the station address is invalid or not. */
1398         if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1399                 device_printf(sc_if->sk_if_dev,
1400                     "Generating random ethernet address\n");
1401                 r = arc4random();
1402                 /*
1403                  * Set OUI to convenient locally assigned address.  'b'
1404                  * is 0x62, which has the locally assigned bit set, and
1405                  * the broadcast/multicast bit clear.
1406                  */
1407                 eaddr[0] = 'b';
1408                 eaddr[1] = 's';
1409                 eaddr[2] = 'd';
1410                 eaddr[3] = (r >> 16) & 0xff;
1411                 eaddr[4] = (r >>  8) & 0xff;
1412                 eaddr[5] = (r >>  0) & 0xff;
1413         }
1414         /*
1415          * Set up RAM buffer addresses. The NIC will have a certain
1416          * amount of SRAM on it, somewhere between 512K and 2MB. We
1417          * need to divide this up a) between the transmitter and
1418          * receiver and b) between the two XMACs, if this is a
1419          * dual port NIC. Our algotithm is to divide up the memory
1420          * evenly so that everyone gets a fair share.
1421          *
1422          * Just to be contrary, Yukon2 appears to have separate memory
1423          * for each MAC.
1424          */
1425         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1426                 u_int32_t               chunk, val;
1427
1428                 chunk = sc->sk_ramsize / 2;
1429                 val = sc->sk_rboff / sizeof(u_int64_t);
1430                 sc_if->sk_rx_ramstart = val;
1431                 val += (chunk / sizeof(u_int64_t));
1432                 sc_if->sk_rx_ramend = val - 1;
1433                 sc_if->sk_tx_ramstart = val;
1434                 val += (chunk / sizeof(u_int64_t));
1435                 sc_if->sk_tx_ramend = val - 1;
1436         } else {
1437                 u_int32_t               chunk, val;
1438
1439                 chunk = sc->sk_ramsize / 4;
1440                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1441                     sizeof(u_int64_t);
1442                 sc_if->sk_rx_ramstart = val;
1443                 val += (chunk / sizeof(u_int64_t));
1444                 sc_if->sk_rx_ramend = val - 1;
1445                 sc_if->sk_tx_ramstart = val;
1446                 val += (chunk / sizeof(u_int64_t));
1447                 sc_if->sk_tx_ramend = val - 1;
1448         }
1449
1450         /* Read and save PHY type and set PHY address */
1451         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1452         if (!SK_YUKON_FAMILY(sc->sk_type)) {
1453                 switch(sc_if->sk_phytype) {
1454                 case SK_PHYTYPE_XMAC:
1455                         sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1456                         break;
1457                 case SK_PHYTYPE_BCOM:
1458                         sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1459                         break;
1460                 default:
1461                         device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1462                             sc_if->sk_phytype);
1463                         error = ENODEV;
1464                         SK_IF_UNLOCK(sc_if);
1465                         goto fail;
1466                 }
1467         } else {
1468                 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1469                     sc->sk_pmd != 'S') {
1470                         /* not initialized, punt */
1471                         sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1472                         sc->sk_coppertype = 1;
1473                 }
1474
1475                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1476
1477                 if (!(sc->sk_coppertype))
1478                         sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1479         }
1480
1481         /*
1482          * Call MI attach routine.  Can't hold locks when calling into ether_*.
1483          */
1484         SK_IF_UNLOCK(sc_if);
1485         ether_ifattach(ifp, eaddr);
1486         SK_IF_LOCK(sc_if);
1487
1488         /*
1489          * The hardware should be ready for VLAN_MTU by default:
1490          * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1491          * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1492          *
1493          */
1494         ifp->if_capabilities |= IFCAP_VLAN_MTU;
1495         ifp->if_capenable |= IFCAP_VLAN_MTU;
1496         /*
1497          * Tell the upper layer(s) we support long frames.
1498          * Must appear after the call to ether_ifattach() because
1499          * ether_ifattach() sets ifi_hdrlen to the default value.
1500          */
1501         ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1502
1503         /*
1504          * Do miibus setup.
1505          */
1506         phy = MII_PHY_ANY;
1507         switch (sc->sk_type) {
1508         case SK_GENESIS:
1509                 sk_init_xmac(sc_if);
1510                 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1511                         phy = 0;
1512                 break;
1513         case SK_YUKON:
1514         case SK_YUKON_LITE:
1515         case SK_YUKON_LP:
1516                 sk_init_yukon(sc_if);
1517                 phy = 0;
1518                 break;
1519         }
1520
1521         SK_IF_UNLOCK(sc_if);
1522         error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1523             sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1524         if (error != 0) {
1525                 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1526                 ether_ifdetach(ifp);
1527                 goto fail;
1528         }
1529
1530 fail:
1531         if (error) {
1532                 /* Access should be ok even though lock has been dropped */
1533                 sc->sk_if[port] = NULL;
1534                 sk_detach(dev);
1535         }
1536
1537         return(error);
1538 }
1539
1540 /*
1541  * Attach the interface. Allocate softc structures, do ifmedia
1542  * setup and ethernet/BPF attach.
1543  */
1544 static int
1545 skc_attach(dev)
1546         device_t                dev;
1547 {
1548         struct sk_softc         *sc;
1549         int                     error = 0, *port;
1550         uint8_t                 skrs;
1551         const char              *pname = NULL;
1552         char                    *revstr;
1553
1554         sc = device_get_softc(dev);
1555         sc->sk_dev = dev;
1556
1557         mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1558             MTX_DEF);
1559         mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1560         /*
1561          * Map control/status registers.
1562          */
1563         pci_enable_busmaster(dev);
1564
1565         /* Allocate resources */
1566 #ifdef SK_USEIOSPACE
1567         sc->sk_res_spec = sk_res_spec_io;
1568 #else
1569         sc->sk_res_spec = sk_res_spec_mem;
1570 #endif
1571         error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1572         if (error) {
1573                 if (sc->sk_res_spec == sk_res_spec_mem)
1574                         sc->sk_res_spec = sk_res_spec_io;
1575                 else
1576                         sc->sk_res_spec = sk_res_spec_mem;
1577                 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1578                 if (error) {
1579                         device_printf(dev, "couldn't allocate %s resources\n",
1580                             sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1581                             "I/O");
1582                         goto fail;
1583                 }
1584         }
1585
1586         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1587         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1588
1589         /* Bail out if chip is not recognized. */
1590         if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1591                 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1592                     sc->sk_type, sc->sk_rev);
1593                 error = ENXIO;
1594                 goto fail;
1595         }
1596
1597         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1598                 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1599                 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1600                 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1601                 "SK interrupt moderation");
1602
1603         /* Pull in device tunables. */
1604         sc->sk_int_mod = SK_IM_DEFAULT;
1605         error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1606                 "int_mod", &sc->sk_int_mod);
1607         if (error == 0) {
1608                 if (sc->sk_int_mod < SK_IM_MIN ||
1609                     sc->sk_int_mod > SK_IM_MAX) {
1610                         device_printf(dev, "int_mod value out of range; "
1611                             "using default: %d\n", SK_IM_DEFAULT);
1612                         sc->sk_int_mod = SK_IM_DEFAULT;
1613                 }
1614         }
1615
1616         /* Reset the adapter. */
1617         sk_reset(sc);
1618
1619         skrs = sk_win_read_1(sc, SK_EPROM0);
1620         if (sc->sk_type == SK_GENESIS) {
1621                 /* Read and save RAM size and RAMbuffer offset */
1622                 switch(skrs) {
1623                 case SK_RAMSIZE_512K_64:
1624                         sc->sk_ramsize = 0x80000;
1625                         sc->sk_rboff = SK_RBOFF_0;
1626                         break;
1627                 case SK_RAMSIZE_1024K_64:
1628                         sc->sk_ramsize = 0x100000;
1629                         sc->sk_rboff = SK_RBOFF_80000;
1630                         break;
1631                 case SK_RAMSIZE_1024K_128:
1632                         sc->sk_ramsize = 0x100000;
1633                         sc->sk_rboff = SK_RBOFF_0;
1634                         break;
1635                 case SK_RAMSIZE_2048K_128:
1636                         sc->sk_ramsize = 0x200000;
1637                         sc->sk_rboff = SK_RBOFF_0;
1638                         break;
1639                 default:
1640                         device_printf(dev, "unknown ram size: %d\n", skrs);
1641                         error = ENXIO;
1642                         goto fail;
1643                 }
1644         } else { /* SK_YUKON_FAMILY */
1645                 if (skrs == 0x00)
1646                         sc->sk_ramsize = 0x20000;
1647                 else
1648                         sc->sk_ramsize = skrs * (1<<12);
1649                 sc->sk_rboff = SK_RBOFF_0;
1650         }
1651
1652         /* Read and save physical media type */
1653          sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1654
1655          if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1656                  sc->sk_coppertype = 1;
1657          else
1658                  sc->sk_coppertype = 0;
1659
1660         /* Determine whether to name it with VPD PN or just make it up.
1661          * Marvell Yukon VPD PN seems to freqently be bogus. */
1662         switch (pci_get_device(dev)) {
1663         case DEVICEID_SK_V1:
1664         case DEVICEID_BELKIN_5005:
1665         case DEVICEID_3COM_3C940:
1666         case DEVICEID_LINKSYS_EG1032:
1667         case DEVICEID_DLINK_DGE530T_A1:
1668         case DEVICEID_DLINK_DGE530T_B1:
1669                 /* Stay with VPD PN. */
1670                 (void) pci_get_vpd_ident(dev, &pname);
1671                 break;
1672         case DEVICEID_SK_V2:
1673                 /* YUKON VPD PN might bear no resemblance to reality. */
1674                 switch (sc->sk_type) {
1675                 case SK_GENESIS:
1676                         /* Stay with VPD PN. */
1677                         (void) pci_get_vpd_ident(dev, &pname);
1678                         break;
1679                 case SK_YUKON:
1680                         pname = "Marvell Yukon Gigabit Ethernet";
1681                         break;
1682                 case SK_YUKON_LITE:
1683                         pname = "Marvell Yukon Lite Gigabit Ethernet";
1684                         break;
1685                 case SK_YUKON_LP:
1686                         pname = "Marvell Yukon LP Gigabit Ethernet";
1687                         break;
1688                 default:
1689                         pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1690                         break;
1691                 }
1692
1693                 /* Yukon Lite Rev. A0 needs special test. */
1694                 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1695                         u_int32_t far;
1696                         u_int8_t testbyte;
1697
1698                         /* Save flash address register before testing. */
1699                         far = sk_win_read_4(sc, SK_EP_ADDR);
1700
1701                         sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1702                         testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1703
1704                         if (testbyte != 0x00) {
1705                                 /* Yukon Lite Rev. A0 detected. */
1706                                 sc->sk_type = SK_YUKON_LITE;
1707                                 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1708                                 /* Restore flash address register. */
1709                                 sk_win_write_4(sc, SK_EP_ADDR, far);
1710                         }
1711                 }
1712                 break;
1713         default:
1714                 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1715                         "chipver=%02x, rev=%x\n",
1716                         pci_get_vendor(dev), pci_get_device(dev),
1717                         sc->sk_type, sc->sk_rev);
1718                 error = ENXIO;
1719                 goto fail;
1720         }
1721
1722         if (sc->sk_type == SK_YUKON_LITE) {
1723                 switch (sc->sk_rev) {
1724                 case SK_YUKON_LITE_REV_A0:
1725                         revstr = "A0";
1726                         break;
1727                 case SK_YUKON_LITE_REV_A1:
1728                         revstr = "A1";
1729                         break;
1730                 case SK_YUKON_LITE_REV_A3:
1731                         revstr = "A3";
1732                         break;
1733                 default:
1734                         revstr = "";
1735                         break;
1736                 }
1737         } else {
1738                 revstr = "";
1739         }
1740
1741         /* Announce the product name and more VPD data if there. */
1742         if (pname != NULL)
1743                 device_printf(dev, "%s rev. %s(0x%x)\n",
1744                         pname, revstr, sc->sk_rev);
1745
1746         if (bootverbose) {
1747                 device_printf(dev, "chip ver  = 0x%02x\n", sc->sk_type);
1748                 device_printf(dev, "chip rev  = 0x%02x\n", sc->sk_rev);
1749                 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1750                 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1751         }
1752
1753         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1754         if (sc->sk_devs[SK_PORT_A] == NULL) {
1755                 device_printf(dev, "failed to add child for PORT_A\n");
1756                 error = ENXIO;
1757                 goto fail;
1758         }
1759         port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1760         if (port == NULL) {
1761                 device_printf(dev, "failed to allocate memory for "
1762                     "ivars of PORT_A\n");
1763                 error = ENXIO;
1764                 goto fail;
1765         }
1766         *port = SK_PORT_A;
1767         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1768
1769         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1770                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1771                 if (sc->sk_devs[SK_PORT_B] == NULL) {
1772                         device_printf(dev, "failed to add child for PORT_B\n");
1773                         error = ENXIO;
1774                         goto fail;
1775                 }
1776                 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1777                 if (port == NULL) {
1778                         device_printf(dev, "failed to allocate memory for "
1779                             "ivars of PORT_B\n");
1780                         error = ENXIO;
1781                         goto fail;
1782                 }
1783                 *port = SK_PORT_B;
1784                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1785         }
1786
1787         /* Turn on the 'driver is loaded' LED. */
1788         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1789
1790         error = bus_generic_attach(dev);
1791         if (error) {
1792                 device_printf(dev, "failed to attach port(s)\n");
1793                 goto fail;
1794         }
1795
1796         /* Hook interrupt last to avoid having to lock softc */
1797         error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1798             NULL, sk_intr, sc, &sc->sk_intrhand);
1799
1800         if (error) {
1801                 device_printf(dev, "couldn't set up irq\n");
1802                 goto fail;
1803         }
1804
1805 fail:
1806         if (error)
1807                 skc_detach(dev);
1808
1809         return(error);
1810 }
1811
1812 /*
1813  * Shutdown hardware and free up resources. This can be called any
1814  * time after the mutex has been initialized. It is called in both
1815  * the error case in attach and the normal detach case so it needs
1816  * to be careful about only freeing resources that have actually been
1817  * allocated.
1818  */
1819 static int
1820 sk_detach(dev)
1821         device_t                dev;
1822 {
1823         struct sk_if_softc      *sc_if;
1824         struct ifnet            *ifp;
1825
1826         sc_if = device_get_softc(dev);
1827         KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1828             ("sk mutex not initialized in sk_detach"));
1829         SK_IF_LOCK(sc_if);
1830
1831         ifp = sc_if->sk_ifp;
1832         /* These should only be active if attach_xmac succeeded */
1833         if (device_is_attached(dev)) {
1834                 sk_stop(sc_if);
1835                 /* Can't hold locks while calling detach */
1836                 SK_IF_UNLOCK(sc_if);
1837                 callout_drain(&sc_if->sk_tick_ch);
1838                 callout_drain(&sc_if->sk_watchdog_ch);
1839                 ether_ifdetach(ifp);
1840                 SK_IF_LOCK(sc_if);
1841         }
1842         /*
1843          * We're generally called from skc_detach() which is using
1844          * device_delete_child() to get to here. It's already trashed
1845          * miibus for us, so don't do it here or we'll panic.
1846          */
1847         /*
1848         if (sc_if->sk_miibus != NULL)
1849                 device_delete_child(dev, sc_if->sk_miibus);
1850         */
1851         bus_generic_detach(dev);
1852         sk_dma_jumbo_free(sc_if);
1853         sk_dma_free(sc_if);
1854         SK_IF_UNLOCK(sc_if);
1855         if (ifp)
1856                 if_free(ifp);
1857
1858         return(0);
1859 }
1860
1861 static int
1862 skc_detach(dev)
1863         device_t                dev;
1864 {
1865         struct sk_softc         *sc;
1866
1867         sc = device_get_softc(dev);
1868         KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1869
1870         if (device_is_alive(dev)) {
1871                 if (sc->sk_devs[SK_PORT_A] != NULL) {
1872                         free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1873                         device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1874                 }
1875                 if (sc->sk_devs[SK_PORT_B] != NULL) {
1876                         free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1877                         device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1878                 }
1879                 bus_generic_detach(dev);
1880         }
1881
1882         if (sc->sk_intrhand)
1883                 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1884         bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1885
1886         mtx_destroy(&sc->sk_mii_mtx);
1887         mtx_destroy(&sc->sk_mtx);
1888
1889         return(0);
1890 }
1891
1892 static bus_dma_tag_t
1893 skc_get_dma_tag(device_t bus, device_t child __unused)
1894 {
1895
1896         return (bus_get_dma_tag(bus));
1897 }
1898
1899 struct sk_dmamap_arg {
1900         bus_addr_t      sk_busaddr;
1901 };
1902
1903 static void
1904 sk_dmamap_cb(arg, segs, nseg, error)
1905         void                    *arg;
1906         bus_dma_segment_t       *segs;
1907         int                     nseg;
1908         int                     error;
1909 {
1910         struct sk_dmamap_arg    *ctx;
1911
1912         if (error != 0)
1913                 return;
1914
1915         ctx = arg;
1916         ctx->sk_busaddr = segs[0].ds_addr;
1917 }
1918
1919 /*
1920  * Allocate jumbo buffer storage. The SysKonnect adapters support
1921  * "jumbograms" (9K frames), although SysKonnect doesn't currently
1922  * use them in their drivers. In order for us to use them, we need
1923  * large 9K receive buffers, however standard mbuf clusters are only
1924  * 2048 bytes in size. Consequently, we need to allocate and manage
1925  * our own jumbo buffer pool. Fortunately, this does not require an
1926  * excessive amount of additional code.
1927  */
1928 static int
1929 sk_dma_alloc(sc_if)
1930         struct sk_if_softc      *sc_if;
1931 {
1932         struct sk_dmamap_arg    ctx;
1933         struct sk_txdesc        *txd;
1934         struct sk_rxdesc        *rxd;
1935         int                     error, i;
1936
1937         /* create parent tag */
1938         /*
1939          * XXX
1940          * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1941          * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1942          * However bz@ reported that it does not work on amd64 with > 4GB
1943          * RAM. Until we have more clues of the breakage, disable DAC mode
1944          * by limiting DMA address to be in 32bit address space.
1945          */
1946         error = bus_dma_tag_create(
1947                     bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1948                     1, 0,                       /* algnmnt, boundary */
1949                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1950                     BUS_SPACE_MAXADDR,          /* highaddr */
1951                     NULL, NULL,                 /* filter, filterarg */
1952                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1953                     0,                          /* nsegments */
1954                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1955                     0,                          /* flags */
1956                     NULL, NULL,                 /* lockfunc, lockarg */
1957                     &sc_if->sk_cdata.sk_parent_tag);
1958         if (error != 0) {
1959                 device_printf(sc_if->sk_if_dev,
1960                     "failed to create parent DMA tag\n");
1961                 goto fail;
1962         }
1963
1964         /* create tag for Tx ring */
1965         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1966                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1967                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1968                     BUS_SPACE_MAXADDR,          /* highaddr */
1969                     NULL, NULL,                 /* filter, filterarg */
1970                     SK_TX_RING_SZ,              /* maxsize */
1971                     1,                          /* nsegments */
1972                     SK_TX_RING_SZ,              /* maxsegsize */
1973                     0,                          /* flags */
1974                     NULL, NULL,                 /* lockfunc, lockarg */
1975                     &sc_if->sk_cdata.sk_tx_ring_tag);
1976         if (error != 0) {
1977                 device_printf(sc_if->sk_if_dev,
1978                     "failed to allocate Tx ring DMA tag\n");
1979                 goto fail;
1980         }
1981
1982         /* create tag for Rx ring */
1983         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1984                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1985                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1986                     BUS_SPACE_MAXADDR,          /* highaddr */
1987                     NULL, NULL,                 /* filter, filterarg */
1988                     SK_RX_RING_SZ,              /* maxsize */
1989                     1,                          /* nsegments */
1990                     SK_RX_RING_SZ,              /* maxsegsize */
1991                     0,                          /* flags */
1992                     NULL, NULL,                 /* lockfunc, lockarg */
1993                     &sc_if->sk_cdata.sk_rx_ring_tag);
1994         if (error != 0) {
1995                 device_printf(sc_if->sk_if_dev,
1996                     "failed to allocate Rx ring DMA tag\n");
1997                 goto fail;
1998         }
1999
2000         /* create tag for Tx buffers */
2001         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2002                     1, 0,                       /* algnmnt, boundary */
2003                     BUS_SPACE_MAXADDR,          /* lowaddr */
2004                     BUS_SPACE_MAXADDR,          /* highaddr */
2005                     NULL, NULL,                 /* filter, filterarg */
2006                     MCLBYTES * SK_MAXTXSEGS,    /* maxsize */
2007                     SK_MAXTXSEGS,               /* nsegments */
2008                     MCLBYTES,                   /* maxsegsize */
2009                     0,                          /* flags */
2010                     NULL, NULL,                 /* lockfunc, lockarg */
2011                     &sc_if->sk_cdata.sk_tx_tag);
2012         if (error != 0) {
2013                 device_printf(sc_if->sk_if_dev,
2014                     "failed to allocate Tx DMA tag\n");
2015                 goto fail;
2016         }
2017
2018         /* create tag for Rx buffers */
2019         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2020                     1, 0,                       /* algnmnt, boundary */
2021                     BUS_SPACE_MAXADDR,          /* lowaddr */
2022                     BUS_SPACE_MAXADDR,          /* highaddr */
2023                     NULL, NULL,                 /* filter, filterarg */
2024                     MCLBYTES,                   /* maxsize */
2025                     1,                          /* nsegments */
2026                     MCLBYTES,                   /* maxsegsize */
2027                     0,                          /* flags */
2028                     NULL, NULL,                 /* lockfunc, lockarg */
2029                     &sc_if->sk_cdata.sk_rx_tag);
2030         if (error != 0) {
2031                 device_printf(sc_if->sk_if_dev,
2032                     "failed to allocate Rx DMA tag\n");
2033                 goto fail;
2034         }
2035
2036         /* allocate DMA'able memory and load the DMA map for Tx ring */
2037         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2038             (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
2039             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
2040         if (error != 0) {
2041                 device_printf(sc_if->sk_if_dev,
2042                     "failed to allocate DMA'able memory for Tx ring\n");
2043                 goto fail;
2044         }
2045
2046         ctx.sk_busaddr = 0;
2047         error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2048             sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2049             SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2050         if (error != 0) {
2051                 device_printf(sc_if->sk_if_dev,
2052                     "failed to load DMA'able memory for Tx ring\n");
2053                 goto fail;
2054         }
2055         sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2056
2057         /* allocate DMA'able memory and load the DMA map for Rx ring */
2058         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2059             (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
2060             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
2061         if (error != 0) {
2062                 device_printf(sc_if->sk_if_dev,
2063                     "failed to allocate DMA'able memory for Rx ring\n");
2064                 goto fail;
2065         }
2066
2067         ctx.sk_busaddr = 0;
2068         error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2069             sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2070             SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2071         if (error != 0) {
2072                 device_printf(sc_if->sk_if_dev,
2073                     "failed to load DMA'able memory for Rx ring\n");
2074                 goto fail;
2075         }
2076         sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2077
2078         /* create DMA maps for Tx buffers */
2079         for (i = 0; i < SK_TX_RING_CNT; i++) {
2080                 txd = &sc_if->sk_cdata.sk_txdesc[i];
2081                 txd->tx_m = NULL;
2082                 txd->tx_dmamap = NULL;
2083                 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2084                     &txd->tx_dmamap);
2085                 if (error != 0) {
2086                         device_printf(sc_if->sk_if_dev,
2087                             "failed to create Tx dmamap\n");
2088                         goto fail;
2089                 }
2090         }
2091
2092         /* create DMA maps for Rx buffers */
2093         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2094             &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2095                 device_printf(sc_if->sk_if_dev,
2096                     "failed to create spare Rx dmamap\n");
2097                 goto fail;
2098         }
2099         for (i = 0; i < SK_RX_RING_CNT; i++) {
2100                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2101                 rxd->rx_m = NULL;
2102                 rxd->rx_dmamap = NULL;
2103                 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2104                     &rxd->rx_dmamap);
2105                 if (error != 0) {
2106                         device_printf(sc_if->sk_if_dev,
2107                             "failed to create Rx dmamap\n");
2108                         goto fail;
2109                 }
2110         }
2111
2112 fail:
2113         return (error);
2114 }
2115
2116 static int
2117 sk_dma_jumbo_alloc(sc_if)
2118         struct sk_if_softc      *sc_if;
2119 {
2120         struct sk_dmamap_arg    ctx;
2121         struct sk_rxdesc        *jrxd;
2122         int                     error, i;
2123
2124         if (jumbo_disable != 0) {
2125                 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2126                 sc_if->sk_jumbo_disable = 1;
2127                 return (0);
2128         }
2129         /* create tag for jumbo Rx ring */
2130         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2131                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
2132                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
2133                     BUS_SPACE_MAXADDR,          /* highaddr */
2134                     NULL, NULL,                 /* filter, filterarg */
2135                     SK_JUMBO_RX_RING_SZ,        /* maxsize */
2136                     1,                          /* nsegments */
2137                     SK_JUMBO_RX_RING_SZ,        /* maxsegsize */
2138                     0,                          /* flags */
2139                     NULL, NULL,                 /* lockfunc, lockarg */
2140                     &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2141         if (error != 0) {
2142                 device_printf(sc_if->sk_if_dev,
2143                     "failed to allocate jumbo Rx ring DMA tag\n");
2144                 goto jumbo_fail;
2145         }
2146
2147         /* create tag for jumbo Rx buffers */
2148         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2149                     1, 0,                       /* algnmnt, boundary */
2150                     BUS_SPACE_MAXADDR,          /* lowaddr */
2151                     BUS_SPACE_MAXADDR,          /* highaddr */
2152                     NULL, NULL,                 /* filter, filterarg */
2153                     MJUM9BYTES,                 /* maxsize */
2154                     1,                          /* nsegments */
2155                     MJUM9BYTES,                 /* maxsegsize */
2156                     0,                          /* flags */
2157                     NULL, NULL,                 /* lockfunc, lockarg */
2158                     &sc_if->sk_cdata.sk_jumbo_rx_tag);
2159         if (error != 0) {
2160                 device_printf(sc_if->sk_if_dev,
2161                     "failed to allocate jumbo Rx DMA tag\n");
2162                 goto jumbo_fail;
2163         }
2164
2165         /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2166         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2167             (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2168             BUS_DMA_COHERENT | BUS_DMA_ZERO,
2169             &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2170         if (error != 0) {
2171                 device_printf(sc_if->sk_if_dev,
2172                     "failed to allocate DMA'able memory for jumbo Rx ring\n");
2173                 goto jumbo_fail;
2174         }
2175
2176         ctx.sk_busaddr = 0;
2177         error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2178             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2179             sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2180             &ctx, BUS_DMA_NOWAIT);
2181         if (error != 0) {
2182                 device_printf(sc_if->sk_if_dev,
2183                     "failed to load DMA'able memory for jumbo Rx ring\n");
2184                 goto jumbo_fail;
2185         }
2186         sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2187
2188         /* create DMA maps for jumbo Rx buffers */
2189         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2190             &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2191                 device_printf(sc_if->sk_if_dev,
2192                     "failed to create spare jumbo Rx dmamap\n");
2193                 goto jumbo_fail;
2194         }
2195         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2196                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2197                 jrxd->rx_m = NULL;
2198                 jrxd->rx_dmamap = NULL;
2199                 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2200                     &jrxd->rx_dmamap);
2201                 if (error != 0) {
2202                         device_printf(sc_if->sk_if_dev,
2203                             "failed to create jumbo Rx dmamap\n");
2204                         goto jumbo_fail;
2205                 }
2206         }
2207
2208         return (0);
2209
2210 jumbo_fail:
2211         sk_dma_jumbo_free(sc_if);
2212         device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2213             "resource shortage\n");
2214         sc_if->sk_jumbo_disable = 1;
2215         return (0);
2216 }
2217
2218 static void
2219 sk_dma_free(sc_if)
2220         struct sk_if_softc      *sc_if;
2221 {
2222         struct sk_txdesc        *txd;
2223         struct sk_rxdesc        *rxd;
2224         int                     i;
2225
2226         /* Tx ring */
2227         if (sc_if->sk_cdata.sk_tx_ring_tag) {
2228                 if (sc_if->sk_rdata.sk_tx_ring_paddr)
2229                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2230                             sc_if->sk_cdata.sk_tx_ring_map);
2231                 if (sc_if->sk_rdata.sk_tx_ring)
2232                         bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2233                             sc_if->sk_rdata.sk_tx_ring,
2234                             sc_if->sk_cdata.sk_tx_ring_map);
2235                 sc_if->sk_rdata.sk_tx_ring = NULL;
2236                 sc_if->sk_rdata.sk_tx_ring_paddr = 0;
2237                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2238                 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2239         }
2240         /* Rx ring */
2241         if (sc_if->sk_cdata.sk_rx_ring_tag) {
2242                 if (sc_if->sk_rdata.sk_rx_ring_paddr)
2243                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2244                             sc_if->sk_cdata.sk_rx_ring_map);
2245                 if (sc_if->sk_rdata.sk_rx_ring)
2246                         bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2247                             sc_if->sk_rdata.sk_rx_ring,
2248                             sc_if->sk_cdata.sk_rx_ring_map);
2249                 sc_if->sk_rdata.sk_rx_ring = NULL;
2250                 sc_if->sk_rdata.sk_rx_ring_paddr = 0;
2251                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2252                 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2253         }
2254         /* Tx buffers */
2255         if (sc_if->sk_cdata.sk_tx_tag) {
2256                 for (i = 0; i < SK_TX_RING_CNT; i++) {
2257                         txd = &sc_if->sk_cdata.sk_txdesc[i];
2258                         if (txd->tx_dmamap) {
2259                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2260                                     txd->tx_dmamap);
2261                                 txd->tx_dmamap = NULL;
2262                         }
2263                 }
2264                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2265                 sc_if->sk_cdata.sk_tx_tag = NULL;
2266         }
2267         /* Rx buffers */
2268         if (sc_if->sk_cdata.sk_rx_tag) {
2269                 for (i = 0; i < SK_RX_RING_CNT; i++) {
2270                         rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2271                         if (rxd->rx_dmamap) {
2272                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2273                                     rxd->rx_dmamap);
2274                                 rxd->rx_dmamap = NULL;
2275                         }
2276                 }
2277                 if (sc_if->sk_cdata.sk_rx_sparemap) {
2278                         bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2279                             sc_if->sk_cdata.sk_rx_sparemap);
2280                         sc_if->sk_cdata.sk_rx_sparemap = NULL;
2281                 }
2282                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2283                 sc_if->sk_cdata.sk_rx_tag = NULL;
2284         }
2285
2286         if (sc_if->sk_cdata.sk_parent_tag) {
2287                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2288                 sc_if->sk_cdata.sk_parent_tag = NULL;
2289         }
2290 }
2291
2292 static void
2293 sk_dma_jumbo_free(sc_if)
2294         struct sk_if_softc      *sc_if;
2295 {
2296         struct sk_rxdesc        *jrxd;
2297         int                     i;
2298
2299         /* jumbo Rx ring */
2300         if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2301                 if (sc_if->sk_rdata.sk_jumbo_rx_ring_paddr)
2302                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2303                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2304                 if (sc_if->sk_rdata.sk_jumbo_rx_ring)
2305                         bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2306                             sc_if->sk_rdata.sk_jumbo_rx_ring,
2307                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2308                 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2309                 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = 0;
2310                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2311                 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2312         }
2313
2314         /* jumbo Rx buffers */
2315         if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2316                 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2317                         jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2318                         if (jrxd->rx_dmamap) {
2319                                 bus_dmamap_destroy(
2320                                     sc_if->sk_cdata.sk_jumbo_rx_tag,
2321                                     jrxd->rx_dmamap);
2322                                 jrxd->rx_dmamap = NULL;
2323                         }
2324                 }
2325                 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2326                         bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2327                             sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2328                         sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2329                 }
2330                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2331                 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2332         }
2333 }
2334
2335 static void
2336 sk_txcksum(ifp, m, f)
2337         struct ifnet            *ifp;
2338         struct mbuf             *m;
2339         struct sk_tx_desc       *f;
2340 {
2341         struct ip               *ip;
2342         u_int16_t               offset;
2343         u_int8_t                *p;
2344
2345         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2346         for(; m && m->m_len == 0; m = m->m_next)
2347                 ;
2348         if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2349                 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2350                 /* checksum may be corrupted */
2351                 goto sendit;
2352         }
2353         if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2354                 if (m->m_len != ETHER_HDR_LEN) {
2355                         if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2356                             __func__);
2357                         /* checksum may be corrupted */
2358                         goto sendit;
2359                 }
2360                 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2361                         ;
2362                 if (m == NULL) {
2363                         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2364                         /* checksum may be corrupted */
2365                         goto sendit;
2366                 }
2367                 ip = mtod(m, struct ip *);
2368         } else {
2369                 p = mtod(m, u_int8_t *);
2370                 p += ETHER_HDR_LEN;
2371                 ip = (struct ip *)p;
2372         }
2373         offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2374
2375 sendit:
2376         f->sk_csum_startval = 0;
2377         f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2378             (offset << 16));
2379 }
2380
2381 static int
2382 sk_encap(sc_if, m_head)
2383         struct sk_if_softc      *sc_if;
2384         struct mbuf             **m_head;
2385 {
2386         struct sk_txdesc        *txd;
2387         struct sk_tx_desc       *f = NULL;
2388         struct mbuf             *m;
2389         bus_dma_segment_t       txsegs[SK_MAXTXSEGS];
2390         u_int32_t               cflags, frag, si, sk_ctl;
2391         int                     error, i, nseg;
2392
2393         SK_IF_LOCK_ASSERT(sc_if);
2394
2395         if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2396                 return (ENOBUFS);
2397
2398         error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2399             txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2400         if (error == EFBIG) {
2401                 m = m_defrag(*m_head, M_NOWAIT);
2402                 if (m == NULL) {
2403                         m_freem(*m_head);
2404                         *m_head = NULL;
2405                         return (ENOMEM);
2406                 }
2407                 *m_head = m;
2408                 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2409                     txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2410                 if (error != 0) {
2411                         m_freem(*m_head);
2412                         *m_head = NULL;
2413                         return (error);
2414                 }
2415         } else if (error != 0)
2416                 return (error);
2417         if (nseg == 0) {
2418                 m_freem(*m_head);
2419                 *m_head = NULL;
2420                 return (EIO);
2421         }
2422         if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2423                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2424                 return (ENOBUFS);
2425         }
2426
2427         m = *m_head;
2428         if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2429                 cflags = SK_OPCODE_CSUM;
2430         else
2431                 cflags = SK_OPCODE_DEFAULT;
2432         si = frag = sc_if->sk_cdata.sk_tx_prod;
2433         for (i = 0; i < nseg; i++) {
2434                 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2435                 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2436                 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2437                 sk_ctl = txsegs[i].ds_len | cflags;
2438                 if (i == 0) {
2439                         if (cflags == SK_OPCODE_CSUM)
2440                                 sk_txcksum(sc_if->sk_ifp, m, f);
2441                         sk_ctl |= SK_TXCTL_FIRSTFRAG;
2442                 } else
2443                         sk_ctl |= SK_TXCTL_OWN;
2444                 f->sk_ctl = htole32(sk_ctl);
2445                 sc_if->sk_cdata.sk_tx_cnt++;
2446                 SK_INC(frag, SK_TX_RING_CNT);
2447         }
2448         sc_if->sk_cdata.sk_tx_prod = frag;
2449
2450         /* set EOF on the last desciptor */
2451         frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2452         f = &sc_if->sk_rdata.sk_tx_ring[frag];
2453         f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2454
2455         /* turn the first descriptor ownership to NIC */
2456         f = &sc_if->sk_rdata.sk_tx_ring[si];
2457         f->sk_ctl |= htole32(SK_TXCTL_OWN);
2458
2459         STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2460         STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2461         txd->tx_m = m;
2462
2463         /* sync descriptors */
2464         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2465             BUS_DMASYNC_PREWRITE);
2466         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2467             sc_if->sk_cdata.sk_tx_ring_map,
2468             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2469
2470         return (0);
2471 }
2472
2473 static void
2474 sk_start(ifp)
2475         struct ifnet            *ifp;
2476 {
2477         struct sk_if_softc *sc_if;
2478
2479         sc_if = ifp->if_softc;
2480
2481         SK_IF_LOCK(sc_if);
2482         sk_start_locked(ifp);
2483         SK_IF_UNLOCK(sc_if);
2484
2485         return;
2486 }
2487
2488 static void
2489 sk_start_locked(ifp)
2490         struct ifnet            *ifp;
2491 {
2492         struct sk_softc         *sc;
2493         struct sk_if_softc      *sc_if;
2494         struct mbuf             *m_head;
2495         int                     enq;
2496
2497         sc_if = ifp->if_softc;
2498         sc = sc_if->sk_softc;
2499
2500         SK_IF_LOCK_ASSERT(sc_if);
2501
2502         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2503             sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2504                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2505                 if (m_head == NULL)
2506                         break;
2507
2508                 /*
2509                  * Pack the data into the transmit ring. If we
2510                  * don't have room, set the OACTIVE flag and wait
2511                  * for the NIC to drain the ring.
2512                  */
2513                 if (sk_encap(sc_if, &m_head)) {
2514                         if (m_head == NULL)
2515                                 break;
2516                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2517                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2518                         break;
2519                 }
2520
2521                 enq++;
2522                 /*
2523                  * If there's a BPF listener, bounce a copy of this frame
2524                  * to him.
2525                  */
2526                 BPF_MTAP(ifp, m_head);
2527         }
2528
2529         if (enq > 0) {
2530                 /* Transmit */
2531                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2532
2533                 /* Set a timeout in case the chip goes out to lunch. */
2534                 sc_if->sk_watchdog_timer = 5;
2535         }
2536 }
2537
2538
2539 static void
2540 sk_watchdog(arg)
2541         void                    *arg;
2542 {
2543         struct sk_if_softc      *sc_if;
2544         struct ifnet            *ifp;
2545
2546         ifp = arg;
2547         sc_if = ifp->if_softc;
2548
2549         SK_IF_LOCK_ASSERT(sc_if);
2550
2551         if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2552                 goto done;
2553
2554         /*
2555          * Reclaim first as there is a possibility of losing Tx completion
2556          * interrupts.
2557          */
2558         sk_txeof(sc_if);
2559         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2560                 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2561                 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2562                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2563                 sk_init_locked(sc_if);
2564         }
2565
2566 done:
2567         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2568
2569         return;
2570 }
2571
2572 static int
2573 skc_shutdown(dev)
2574         device_t                dev;
2575 {
2576         struct sk_softc         *sc;
2577
2578         sc = device_get_softc(dev);
2579         SK_LOCK(sc);
2580
2581         /* Turn off the 'driver is loaded' LED. */
2582         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2583
2584         /*
2585          * Reset the GEnesis controller. Doing this should also
2586          * assert the resets on the attached XMAC(s).
2587          */
2588         sk_reset(sc);
2589         SK_UNLOCK(sc);
2590
2591         return (0);
2592 }
2593
2594 static int
2595 skc_suspend(dev)
2596         device_t                dev;
2597 {
2598         struct sk_softc         *sc;
2599         struct sk_if_softc      *sc_if0, *sc_if1;
2600         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2601
2602         sc = device_get_softc(dev);
2603
2604         SK_LOCK(sc);
2605
2606         sc_if0 = sc->sk_if[SK_PORT_A];
2607         sc_if1 = sc->sk_if[SK_PORT_B];
2608         if (sc_if0 != NULL)
2609                 ifp0 = sc_if0->sk_ifp;
2610         if (sc_if1 != NULL)
2611                 ifp1 = sc_if1->sk_ifp;
2612         if (ifp0 != NULL)
2613                 sk_stop(sc_if0);
2614         if (ifp1 != NULL)
2615                 sk_stop(sc_if1);
2616         sc->sk_suspended = 1;
2617
2618         SK_UNLOCK(sc);
2619
2620         return (0);
2621 }
2622
2623 static int
2624 skc_resume(dev)
2625         device_t                dev;
2626 {
2627         struct sk_softc         *sc;
2628         struct sk_if_softc      *sc_if0, *sc_if1;
2629         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2630
2631         sc = device_get_softc(dev);
2632
2633         SK_LOCK(sc);
2634
2635         sc_if0 = sc->sk_if[SK_PORT_A];
2636         sc_if1 = sc->sk_if[SK_PORT_B];
2637         if (sc_if0 != NULL)
2638                 ifp0 = sc_if0->sk_ifp;
2639         if (sc_if1 != NULL)
2640                 ifp1 = sc_if1->sk_ifp;
2641         if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2642                 sk_init_locked(sc_if0);
2643         if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2644                 sk_init_locked(sc_if1);
2645         sc->sk_suspended = 0;
2646
2647         SK_UNLOCK(sc);
2648
2649         return (0);
2650 }
2651
2652 /*
2653  * According to the data sheet from SK-NET GENESIS the hardware can compute
2654  * two Rx checksums at the same time(Each checksum start position is
2655  * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2656  * does not work at least on my Yukon hardware. I tried every possible ways
2657  * to get correct checksum value but couldn't get correct one. So TCP/UDP
2658  * checksum offload was disabled at the moment and only IP checksum offload
2659  * was enabled.
2660  * As nomral IP header size is 20 bytes I can't expect it would give an
2661  * increase in throughput. However it seems it doesn't hurt performance in
2662  * my testing. If there is a more detailed information for checksum secret
2663  * of the hardware in question please contact yongari@FreeBSD.org to add
2664  * TCP/UDP checksum offload support.
2665  */
2666 static __inline void
2667 sk_rxcksum(ifp, m, csum)
2668         struct ifnet            *ifp;
2669         struct mbuf             *m;
2670         u_int32_t               csum;
2671 {
2672         struct ether_header     *eh;
2673         struct ip               *ip;
2674         int32_t                 hlen, len, pktlen;
2675         u_int16_t               csum1, csum2, ipcsum;
2676
2677         pktlen = m->m_pkthdr.len;
2678         if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2679                 return;
2680         eh = mtod(m, struct ether_header *);
2681         if (eh->ether_type != htons(ETHERTYPE_IP))
2682                 return;
2683         ip = (struct ip *)(eh + 1);
2684         if (ip->ip_v != IPVERSION)
2685                 return;
2686         hlen = ip->ip_hl << 2;
2687         pktlen -= sizeof(struct ether_header);
2688         if (hlen < sizeof(struct ip))
2689                 return;
2690         if (ntohs(ip->ip_len) < hlen)
2691                 return;
2692         if (ntohs(ip->ip_len) != pktlen)
2693                 return;
2694
2695         csum1 = htons(csum & 0xffff);
2696         csum2 = htons((csum >> 16) & 0xffff);
2697         ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2698         /* checksum fixup for IP options */
2699         len = hlen - sizeof(struct ip);
2700         if (len > 0) {
2701                 /*
2702                  * If the second checksum value is correct we can compute IP
2703                  * checksum with simple math. Unfortunately the second checksum
2704                  * value is wrong so we can't verify the checksum from the
2705                  * value(It seems there is some magic here to get correct
2706                  * value). If the second checksum value is correct it also
2707                  * means we can get TCP/UDP checksum) here. However, it still
2708                  * needs pseudo header checksum calculation due to hardware
2709                  * limitations.
2710                  */
2711                 return;
2712         }
2713         m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2714         if (ipcsum == 0xffff)
2715                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2716 }
2717
2718 static __inline int
2719 sk_rxvalid(sc, stat, len)
2720         struct sk_softc         *sc;
2721         u_int32_t               stat, len;
2722 {
2723
2724         if (sc->sk_type == SK_GENESIS) {
2725                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2726                     XM_RXSTAT_BYTES(stat) != len)
2727                         return (0);
2728         } else {
2729                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2730                     YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2731                     YU_RXSTAT_JABBER)) != 0 ||
2732                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2733                     YU_RXSTAT_BYTES(stat) != len)
2734                         return (0);
2735         }
2736
2737         return (1);
2738 }
2739
2740 static void
2741 sk_rxeof(sc_if)
2742         struct sk_if_softc      *sc_if;
2743 {
2744         struct sk_softc         *sc;
2745         struct mbuf             *m;
2746         struct ifnet            *ifp;
2747         struct sk_rx_desc       *cur_rx;
2748         struct sk_rxdesc        *rxd;
2749         int                     cons, prog;
2750         u_int32_t               csum, rxstat, sk_ctl;
2751
2752         sc = sc_if->sk_softc;
2753         ifp = sc_if->sk_ifp;
2754
2755         SK_IF_LOCK_ASSERT(sc_if);
2756
2757         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2758             sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2759
2760         prog = 0;
2761         for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2762             prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2763                 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2764                 sk_ctl = le32toh(cur_rx->sk_ctl);
2765                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2766                         break;
2767                 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2768                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2769
2770                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2771                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2772                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2773                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2774                     SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2775                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2776                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2777                         sk_discard_rxbuf(sc_if, cons);
2778                         continue;
2779                 }
2780
2781                 m = rxd->rx_m;
2782                 csum = le32toh(cur_rx->sk_csum);
2783                 if (sk_newbuf(sc_if, cons) != 0) {
2784                         if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2785                         /* reuse old buffer */
2786                         sk_discard_rxbuf(sc_if, cons);
2787                         continue;
2788                 }
2789                 m->m_pkthdr.rcvif = ifp;
2790                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2791                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2792                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2793                         sk_rxcksum(ifp, m, csum);
2794                 SK_IF_UNLOCK(sc_if);
2795                 (*ifp->if_input)(ifp, m);
2796                 SK_IF_LOCK(sc_if);
2797         }
2798
2799         if (prog > 0) {
2800                 sc_if->sk_cdata.sk_rx_cons = cons;
2801                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2802                     sc_if->sk_cdata.sk_rx_ring_map,
2803                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2804         }
2805 }
2806
2807 static void
2808 sk_jumbo_rxeof(sc_if)
2809         struct sk_if_softc      *sc_if;
2810 {
2811         struct sk_softc         *sc;
2812         struct mbuf             *m;
2813         struct ifnet            *ifp;
2814         struct sk_rx_desc       *cur_rx;
2815         struct sk_rxdesc        *jrxd;
2816         int                     cons, prog;
2817         u_int32_t               csum, rxstat, sk_ctl;
2818
2819         sc = sc_if->sk_softc;
2820         ifp = sc_if->sk_ifp;
2821
2822         SK_IF_LOCK_ASSERT(sc_if);
2823
2824         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2825             sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2826
2827         prog = 0;
2828         for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2829             prog < SK_JUMBO_RX_RING_CNT;
2830             prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2831                 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2832                 sk_ctl = le32toh(cur_rx->sk_ctl);
2833                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2834                         break;
2835                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2836                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2837
2838                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2839                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2840                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2841                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2842                     SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2843                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2844                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2845                         sk_discard_jumbo_rxbuf(sc_if, cons);
2846                         continue;
2847                 }
2848
2849                 m = jrxd->rx_m;
2850                 csum = le32toh(cur_rx->sk_csum);
2851                 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2852                         if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2853                         /* reuse old buffer */
2854                         sk_discard_jumbo_rxbuf(sc_if, cons);
2855                         continue;
2856                 }
2857                 m->m_pkthdr.rcvif = ifp;
2858                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2859                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2860                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2861                         sk_rxcksum(ifp, m, csum);
2862                 SK_IF_UNLOCK(sc_if);
2863                 (*ifp->if_input)(ifp, m);
2864                 SK_IF_LOCK(sc_if);
2865         }
2866
2867         if (prog > 0) {
2868                 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2869                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2870                     sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2871                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2872         }
2873 }
2874
2875 static void
2876 sk_txeof(sc_if)
2877         struct sk_if_softc      *sc_if;
2878 {
2879         struct sk_txdesc        *txd;
2880         struct sk_tx_desc       *cur_tx;
2881         struct ifnet            *ifp;
2882         u_int32_t               idx, sk_ctl;
2883
2884         ifp = sc_if->sk_ifp;
2885
2886         txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2887         if (txd == NULL)
2888                 return;
2889         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2890             sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2891         /*
2892          * Go through our tx ring and free mbufs for those
2893          * frames that have been sent.
2894          */
2895         for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2896                 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2897                         break;
2898                 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2899                 sk_ctl = le32toh(cur_tx->sk_ctl);
2900                 if (sk_ctl & SK_TXCTL_OWN)
2901                         break;
2902                 sc_if->sk_cdata.sk_tx_cnt--;
2903                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2904                 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2905                         continue;
2906                 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2907                     BUS_DMASYNC_POSTWRITE);
2908                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2909
2910                 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2911                 m_freem(txd->tx_m);
2912                 txd->tx_m = NULL;
2913                 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2914                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2915                 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2916         }
2917         sc_if->sk_cdata.sk_tx_cons = idx;
2918         sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2919
2920         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2921             sc_if->sk_cdata.sk_tx_ring_map,
2922             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2923 }
2924
2925 static void
2926 sk_tick(xsc_if)
2927         void                    *xsc_if;
2928 {
2929         struct sk_if_softc      *sc_if;
2930         struct mii_data         *mii;
2931         struct ifnet            *ifp;
2932         int                     i;
2933
2934         sc_if = xsc_if;
2935         ifp = sc_if->sk_ifp;
2936         mii = device_get_softc(sc_if->sk_miibus);
2937
2938         if (!(ifp->if_flags & IFF_UP))
2939                 return;
2940
2941         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2942                 sk_intr_bcom(sc_if);
2943                 return;
2944         }
2945
2946         /*
2947          * According to SysKonnect, the correct way to verify that
2948          * the link has come back up is to poll bit 0 of the GPIO
2949          * register three times. This pin has the signal from the
2950          * link_sync pin connected to it; if we read the same link
2951          * state 3 times in a row, we know the link is up.
2952          */
2953         for (i = 0; i < 3; i++) {
2954                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2955                         break;
2956         }
2957
2958         if (i != 3) {
2959                 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2960                 return;
2961         }
2962
2963         /* Turn the GP0 interrupt back on. */
2964         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2965         SK_XM_READ_2(sc_if, XM_ISR);
2966         mii_tick(mii);
2967         callout_stop(&sc_if->sk_tick_ch);
2968 }
2969
2970 static void
2971 sk_yukon_tick(xsc_if)
2972         void                    *xsc_if;
2973 {
2974         struct sk_if_softc      *sc_if;
2975         struct mii_data         *mii;
2976
2977         sc_if = xsc_if;
2978         mii = device_get_softc(sc_if->sk_miibus);
2979
2980         mii_tick(mii);
2981         callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2982 }
2983
2984 static void
2985 sk_intr_bcom(sc_if)
2986         struct sk_if_softc      *sc_if;
2987 {
2988         struct mii_data         *mii;
2989         struct ifnet            *ifp;
2990         int                     status;
2991         mii = device_get_softc(sc_if->sk_miibus);
2992         ifp = sc_if->sk_ifp;
2993
2994         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2995
2996         /*
2997          * Read the PHY interrupt register to make sure
2998          * we clear any pending interrupts.
2999          */
3000         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
3001
3002         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3003                 sk_init_xmac(sc_if);
3004                 return;
3005         }
3006
3007         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
3008                 int                     lstat;
3009                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
3010                     BRGPHY_MII_AUXSTS);
3011
3012                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
3013                         mii_mediachg(mii);
3014                         /* Turn off the link LED. */
3015                         SK_IF_WRITE_1(sc_if, 0,
3016                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
3017                         sc_if->sk_link = 0;
3018                 } else if (status & BRGPHY_ISR_LNK_CHG) {
3019                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3020                             BRGPHY_MII_IMR, 0xFF00);
3021                         mii_tick(mii);
3022                         sc_if->sk_link = 1;
3023                         /* Turn on the link LED. */
3024                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3025                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
3026                             SK_LINKLED_BLINK_OFF);
3027                 } else {
3028                         mii_tick(mii);
3029                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3030                 }
3031         }
3032
3033         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3034
3035         return;
3036 }
3037
3038 static void
3039 sk_intr_xmac(sc_if)
3040         struct sk_if_softc      *sc_if;
3041 {
3042         struct sk_softc         *sc;
3043         u_int16_t               status;
3044
3045         sc = sc_if->sk_softc;
3046         status = SK_XM_READ_2(sc_if, XM_ISR);
3047
3048         /*
3049          * Link has gone down. Start MII tick timeout to
3050          * watch for link resync.
3051          */
3052         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3053                 if (status & XM_ISR_GP0_SET) {
3054                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3055                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3056                 }
3057
3058                 if (status & XM_ISR_AUTONEG_DONE) {
3059                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3060                 }
3061         }
3062
3063         if (status & XM_IMR_TX_UNDERRUN)
3064                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3065
3066         if (status & XM_IMR_RX_OVERRUN)
3067                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3068
3069         status = SK_XM_READ_2(sc_if, XM_ISR);
3070
3071         return;
3072 }
3073
3074 static void
3075 sk_intr_yukon(sc_if)
3076         struct sk_if_softc      *sc_if;
3077 {
3078         u_int8_t status;
3079
3080         status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3081         /* RX overrun */
3082         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3083                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3084                     SK_RFCTL_RX_FIFO_OVER);
3085         }
3086         /* TX underrun */
3087         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3088                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3089                     SK_TFCTL_TX_FIFO_UNDER);
3090         }
3091 }
3092
3093 static void
3094 sk_intr(xsc)
3095         void                    *xsc;
3096 {
3097         struct sk_softc         *sc = xsc;
3098         struct sk_if_softc      *sc_if0, *sc_if1;
3099         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
3100         u_int32_t               status;
3101
3102         SK_LOCK(sc);
3103
3104         status = CSR_READ_4(sc, SK_ISSR);
3105         if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3106                 goto done_locked;
3107
3108         sc_if0 = sc->sk_if[SK_PORT_A];
3109         sc_if1 = sc->sk_if[SK_PORT_B];
3110
3111         if (sc_if0 != NULL)
3112                 ifp0 = sc_if0->sk_ifp;
3113         if (sc_if1 != NULL)
3114                 ifp1 = sc_if1->sk_ifp;
3115
3116         for (; (status &= sc->sk_intrmask) != 0;) {
3117                 /* Handle receive interrupts first. */
3118                 if (status & SK_ISR_RX1_EOF) {
3119                         if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3120                                 sk_jumbo_rxeof(sc_if0);
3121                         else
3122                                 sk_rxeof(sc_if0);
3123                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3124                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3125                 }
3126                 if (status & SK_ISR_RX2_EOF) {
3127                         if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3128                                 sk_jumbo_rxeof(sc_if1);
3129                         else
3130                                 sk_rxeof(sc_if1);
3131                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3132                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3133                 }
3134
3135                 /* Then transmit interrupts. */
3136                 if (status & SK_ISR_TX1_S_EOF) {
3137                         sk_txeof(sc_if0);
3138                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3139                 }
3140                 if (status & SK_ISR_TX2_S_EOF) {
3141                         sk_txeof(sc_if1);
3142                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3143                 }
3144
3145                 /* Then MAC interrupts. */
3146                 if (status & SK_ISR_MAC1 &&
3147                     ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3148                         if (sc->sk_type == SK_GENESIS)
3149                                 sk_intr_xmac(sc_if0);
3150                         else
3151                                 sk_intr_yukon(sc_if0);
3152                 }
3153
3154                 if (status & SK_ISR_MAC2 &&
3155                     ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3156                         if (sc->sk_type == SK_GENESIS)
3157                                 sk_intr_xmac(sc_if1);
3158                         else
3159                                 sk_intr_yukon(sc_if1);
3160                 }
3161
3162                 if (status & SK_ISR_EXTERNAL_REG) {
3163                         if (ifp0 != NULL &&
3164                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3165                                 sk_intr_bcom(sc_if0);
3166                         if (ifp1 != NULL &&
3167                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3168                                 sk_intr_bcom(sc_if1);
3169                 }
3170                 status = CSR_READ_4(sc, SK_ISSR);
3171         }
3172
3173         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3174
3175         if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3176                 sk_start_locked(ifp0);
3177         if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3178                 sk_start_locked(ifp1);
3179
3180 done_locked:
3181         SK_UNLOCK(sc);
3182 }
3183
3184 static void
3185 sk_init_xmac(sc_if)
3186         struct sk_if_softc      *sc_if;
3187 {
3188         struct sk_softc         *sc;
3189         struct ifnet            *ifp;
3190         u_int16_t               eaddr[(ETHER_ADDR_LEN+1)/2];
3191         static const struct sk_bcom_hack bhack[] = {
3192         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3193         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3194         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3195         { 0, 0 } };
3196
3197         SK_IF_LOCK_ASSERT(sc_if);
3198
3199         sc = sc_if->sk_softc;
3200         ifp = sc_if->sk_ifp;
3201
3202         /* Unreset the XMAC. */
3203         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3204         DELAY(1000);
3205
3206         /* Reset the XMAC's internal state. */
3207         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3208
3209         /* Save the XMAC II revision */
3210         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3211
3212         /*
3213          * Perform additional initialization for external PHYs,
3214          * namely for the 1000baseTX cards that use the XMAC's
3215          * GMII mode.
3216          */
3217         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3218                 int                     i = 0;
3219                 u_int32_t               val;
3220
3221                 /* Take PHY out of reset. */
3222                 val = sk_win_read_4(sc, SK_GPIO);
3223                 if (sc_if->sk_port == SK_PORT_A)
3224                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3225                 else
3226                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3227                 sk_win_write_4(sc, SK_GPIO, val);
3228
3229                 /* Enable GMII mode on the XMAC. */
3230                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3231
3232                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3233                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3234                 DELAY(10000);
3235                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3236                     BRGPHY_MII_IMR, 0xFFF0);
3237
3238                 /*
3239                  * Early versions of the BCM5400 apparently have
3240                  * a bug that requires them to have their reserved
3241                  * registers initialized to some magic values. I don't
3242                  * know what the numbers do, I'm just the messenger.
3243                  */
3244                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3245                     == 0x6041) {
3246                         while(bhack[i].reg) {
3247                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3248                                     bhack[i].reg, bhack[i].val);
3249                                 i++;
3250                         }
3251                 }
3252         }
3253
3254         /* Set station address */
3255         bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3256         SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3257         SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3258         SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3259         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3260
3261         if (ifp->if_flags & IFF_BROADCAST) {
3262                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3263         } else {
3264                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3265         }
3266
3267         /* We don't need the FCS appended to the packet. */
3268         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3269
3270         /* We want short frames padded to 60 bytes. */
3271         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3272
3273         /*
3274          * Enable the reception of all error frames. This is is
3275          * a necessary evil due to the design of the XMAC. The
3276          * XMAC's receive FIFO is only 8K in size, however jumbo
3277          * frames can be up to 9000 bytes in length. When bad
3278          * frame filtering is enabled, the XMAC's RX FIFO operates
3279          * in 'store and forward' mode. For this to work, the
3280          * entire frame has to fit into the FIFO, but that means
3281          * that jumbo frames larger than 8192 bytes will be
3282          * truncated. Disabling all bad frame filtering causes
3283          * the RX FIFO to operate in streaming mode, in which
3284          * case the XMAC will start transferring frames out of the
3285          * RX FIFO as soon as the FIFO threshold is reached.
3286          */
3287         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3288                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3289                     XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3290                     XM_MODE_RX_INRANGELEN);
3291                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3292         } else
3293                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3294
3295         /*
3296          * Bump up the transmit threshold. This helps hold off transmit
3297          * underruns when we're blasting traffic from both ports at once.
3298          */
3299         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3300
3301         /* Set Rx filter */
3302         sk_rxfilter_genesis(sc_if);
3303
3304         /* Clear and enable interrupts */
3305         SK_XM_READ_2(sc_if, XM_ISR);
3306         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3307                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3308         else
3309                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3310
3311         /* Configure MAC arbiter */
3312         switch(sc_if->sk_xmac_rev) {
3313         case XM_XMAC_REV_B2:
3314                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3315                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3316                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3317                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3318                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3319                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3320                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3321                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3322                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3323                 break;
3324         case XM_XMAC_REV_C1:
3325                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3326                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3327                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3328                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3329                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3330                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3331                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3332                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3333                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3334                 break;
3335         default:
3336                 break;
3337         }
3338         sk_win_write_2(sc, SK_MACARB_CTL,
3339             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3340
3341         sc_if->sk_link = 1;
3342
3343         return;
3344 }
3345
3346 static void
3347 sk_init_yukon(sc_if)
3348         struct sk_if_softc      *sc_if;
3349 {
3350         u_int32_t               phy, v;
3351         u_int16_t               reg;
3352         struct sk_softc         *sc;
3353         struct ifnet            *ifp;
3354         u_int8_t                *eaddr;
3355         int                     i;
3356
3357         SK_IF_LOCK_ASSERT(sc_if);
3358
3359         sc = sc_if->sk_softc;
3360         ifp = sc_if->sk_ifp;
3361
3362         if (sc->sk_type == SK_YUKON_LITE &&
3363             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3364                 /*
3365                  * Workaround code for COMA mode, set PHY reset.
3366                  * Otherwise it will not correctly take chip out of
3367                  * powerdown (coma)
3368                  */
3369                 v = sk_win_read_4(sc, SK_GPIO);
3370                 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3371                 sk_win_write_4(sc, SK_GPIO, v);
3372         }
3373
3374         /* GMAC and GPHY Reset */
3375         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3376         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3377         DELAY(1000);
3378
3379         if (sc->sk_type == SK_YUKON_LITE &&
3380             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3381                 /*
3382                  * Workaround code for COMA mode, clear PHY reset
3383                  */
3384                 v = sk_win_read_4(sc, SK_GPIO);
3385                 v |= SK_GPIO_DIR9;
3386                 v &= ~SK_GPIO_DAT9;
3387                 sk_win_write_4(sc, SK_GPIO, v);
3388         }
3389
3390         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3391                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3392
3393         if (sc->sk_coppertype)
3394                 phy |= SK_GPHY_COPPER;
3395         else
3396                 phy |= SK_GPHY_FIBER;
3397
3398         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3399         DELAY(1000);
3400         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3401         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3402                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3403
3404         /* unused read of the interrupt source register */
3405         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3406
3407         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3408
3409         /* MIB Counter Clear Mode set */
3410         reg |= YU_PAR_MIB_CLR;
3411         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3412
3413         /* MIB Counter Clear Mode clear */
3414         reg &= ~YU_PAR_MIB_CLR;
3415         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3416
3417         /* receive control reg */
3418         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3419
3420         /* transmit parameter register */
3421         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3422                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3423
3424         /* serial mode register */
3425         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3426         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3427                 reg |= YU_SMR_MFL_JUMBO;
3428         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3429
3430         /* Setup Yukon's station address */
3431         eaddr = IF_LLADDR(sc_if->sk_ifp);
3432         for (i = 0; i < 3; i++)
3433                 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3434                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3435         /* Set GMAC source address of flow control. */
3436         for (i = 0; i < 3; i++)
3437                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3438                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3439         /* Set GMAC virtual address. */
3440         for (i = 0; i < 3; i++)
3441                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3442                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3443
3444         /* Set Rx filter */
3445         sk_rxfilter_yukon(sc_if);
3446
3447         /* enable interrupt mask for counter overflows */
3448         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3449         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3450         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3451
3452         /* Configure RX MAC FIFO Flush Mask */
3453         v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3454             YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3455             YU_RXSTAT_JABBER;
3456         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3457
3458         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3459         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3460                 v = SK_TFCTL_OPERATION_ON;
3461         else
3462                 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3463         /* Configure RX MAC FIFO */
3464         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3465         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3466
3467         /* Increase flush threshould to 64 bytes */
3468         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3469             SK_RFCTL_FIFO_THRESHOLD + 1);
3470
3471         /* Configure TX MAC FIFO */
3472         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3473         SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3474 }
3475
3476 /*
3477  * Note that to properly initialize any part of the GEnesis chip,
3478  * you first have to take it out of reset mode.
3479  */
3480 static void
3481 sk_init(xsc)
3482         void                    *xsc;
3483 {
3484         struct sk_if_softc      *sc_if = xsc;
3485
3486         SK_IF_LOCK(sc_if);
3487         sk_init_locked(sc_if);
3488         SK_IF_UNLOCK(sc_if);
3489
3490         return;
3491 }
3492
3493 static void
3494 sk_init_locked(sc_if)
3495         struct sk_if_softc      *sc_if;
3496 {
3497         struct sk_softc         *sc;
3498         struct ifnet            *ifp;
3499         struct mii_data         *mii;
3500         u_int16_t               reg;
3501         u_int32_t               imr;
3502         int                     error;
3503
3504         SK_IF_LOCK_ASSERT(sc_if);
3505
3506         ifp = sc_if->sk_ifp;
3507         sc = sc_if->sk_softc;
3508         mii = device_get_softc(sc_if->sk_miibus);
3509
3510         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3511                 return;
3512
3513         /* Cancel pending I/O and free all RX/TX buffers. */
3514         sk_stop(sc_if);
3515
3516         if (sc->sk_type == SK_GENESIS) {
3517                 /* Configure LINK_SYNC LED */
3518                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3519                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3520                         SK_LINKLED_LINKSYNC_ON);
3521
3522                 /* Configure RX LED */
3523                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3524                         SK_RXLEDCTL_COUNTER_START);
3525
3526                 /* Configure TX LED */
3527                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3528                         SK_TXLEDCTL_COUNTER_START);
3529         }
3530
3531         /*
3532          * Configure descriptor poll timer
3533          *
3534          * SK-NET GENESIS data sheet says that possibility of losing Start
3535          * transmit command due to CPU/cache related interim storage problems
3536          * under certain conditions. The document recommends a polling
3537          * mechanism to send a Start transmit command to initiate transfer
3538          * of ready descriptors regulary. To cope with this issue sk(4) now
3539          * enables descriptor poll timer to initiate descriptor processing
3540          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3541          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3542          * command instead of waiting for next descriptor polling time.
3543          * The same rule may apply to Rx side too but it seems that is not
3544          * needed at the moment.
3545          * Since sk(4) uses descriptor polling as a last resort there is no
3546          * need to set smaller polling time than maximum allowable one.
3547          */
3548         SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3549
3550         /* Configure I2C registers */
3551
3552         /* Configure XMAC(s) */
3553         switch (sc->sk_type) {
3554         case SK_GENESIS:
3555                 sk_init_xmac(sc_if);
3556                 break;
3557         case SK_YUKON:
3558         case SK_YUKON_LITE:
3559         case SK_YUKON_LP:
3560                 sk_init_yukon(sc_if);
3561                 break;
3562         }
3563         mii_mediachg(mii);
3564
3565         if (sc->sk_type == SK_GENESIS) {
3566                 /* Configure MAC FIFOs */
3567                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3568                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3569                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3570
3571                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3572                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3573                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3574         }
3575
3576         /* Configure transmit arbiter(s) */
3577         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3578             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3579
3580         /* Configure RAMbuffers */
3581         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3582         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3583         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3584         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3585         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3586         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3587
3588         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3589         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3590         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3591         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3592         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3593         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3594         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3595
3596         /* Configure BMUs */
3597         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3598         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3599                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3600                     SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3601                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3602                     SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3603         } else {
3604                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3605                     SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3606                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3607                     SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3608         }
3609
3610         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3611         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3612             SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3613         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3614             SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3615
3616         /* Init descriptors */
3617         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3618                 error = sk_init_jumbo_rx_ring(sc_if);
3619         else
3620                 error = sk_init_rx_ring(sc_if);
3621         if (error != 0) {
3622                 device_printf(sc_if->sk_if_dev,
3623                     "initialization failed: no memory for rx buffers\n");
3624                 sk_stop(sc_if);
3625                 return;
3626         }
3627         sk_init_tx_ring(sc_if);
3628
3629         /* Set interrupt moderation if changed via sysctl. */
3630         imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3631         if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3632                 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3633                     sc->sk_int_ticks));
3634                 if (bootverbose)
3635                         device_printf(sc_if->sk_if_dev,
3636                             "interrupt moderation is %d us.\n",
3637                             sc->sk_int_mod);
3638         }
3639
3640         /* Configure interrupt handling */
3641         CSR_READ_4(sc, SK_ISSR);
3642         if (sc_if->sk_port == SK_PORT_A)
3643                 sc->sk_intrmask |= SK_INTRS1;
3644         else
3645                 sc->sk_intrmask |= SK_INTRS2;
3646
3647         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3648
3649         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3650
3651         /* Start BMUs. */
3652         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3653
3654         switch(sc->sk_type) {
3655         case SK_GENESIS:
3656                 /* Enable XMACs TX and RX state machines */
3657                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3658                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3659                 break;
3660         case SK_YUKON:
3661         case SK_YUKON_LITE:
3662         case SK_YUKON_LP:
3663                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3664                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3665 #if 0
3666                 /* XXX disable 100Mbps and full duplex mode? */
3667                 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3668 #endif
3669                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3670         }
3671
3672         /* Activate descriptor polling timer */
3673         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3674         /* start transfer of Tx descriptors */
3675         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3676
3677         ifp->if_drv_flags |= IFF_DRV_RUNNING;
3678         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3679
3680         switch (sc->sk_type) {
3681         case SK_YUKON:
3682         case SK_YUKON_LITE:
3683         case SK_YUKON_LP:
3684                 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3685                 break;
3686         }
3687
3688         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3689
3690         return;
3691 }
3692
3693 static void
3694 sk_stop(sc_if)
3695         struct sk_if_softc      *sc_if;
3696 {
3697         int                     i;
3698         struct sk_softc         *sc;
3699         struct sk_txdesc        *txd;
3700         struct sk_rxdesc        *rxd;
3701         struct sk_rxdesc        *jrxd;
3702         struct ifnet            *ifp;
3703         u_int32_t               val;
3704
3705         SK_IF_LOCK_ASSERT(sc_if);
3706         sc = sc_if->sk_softc;
3707         ifp = sc_if->sk_ifp;
3708
3709         callout_stop(&sc_if->sk_tick_ch);
3710         callout_stop(&sc_if->sk_watchdog_ch);
3711
3712         /* stop Tx descriptor polling timer */
3713         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3714         /* stop transfer of Tx descriptors */
3715         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3716         for (i = 0; i < SK_TIMEOUT; i++) {
3717                 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3718                 if ((val & SK_TXBMU_TX_STOP) == 0)
3719                         break;
3720                 DELAY(1);
3721         }
3722         if (i == SK_TIMEOUT)
3723                 device_printf(sc_if->sk_if_dev,
3724                     "can not stop transfer of Tx descriptor\n");
3725         /* stop transfer of Rx descriptors */
3726         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3727         for (i = 0; i < SK_TIMEOUT; i++) {
3728                 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3729                 if ((val & SK_RXBMU_RX_STOP) == 0)
3730                         break;
3731                 DELAY(1);
3732         }
3733         if (i == SK_TIMEOUT)
3734                 device_printf(sc_if->sk_if_dev,
3735                     "can not stop transfer of Rx descriptor\n");
3736
3737         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3738                 /* Put PHY back into reset. */
3739                 val = sk_win_read_4(sc, SK_GPIO);
3740                 if (sc_if->sk_port == SK_PORT_A) {
3741                         val |= SK_GPIO_DIR0;
3742                         val &= ~SK_GPIO_DAT0;
3743                 } else {
3744                         val |= SK_GPIO_DIR2;
3745                         val &= ~SK_GPIO_DAT2;
3746                 }
3747                 sk_win_write_4(sc, SK_GPIO, val);
3748         }
3749
3750         /* Turn off various components of this interface. */
3751         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3752         switch (sc->sk_type) {
3753         case SK_GENESIS:
3754                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3755                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3756                 break;
3757         case SK_YUKON:
3758         case SK_YUKON_LITE:
3759         case SK_YUKON_LP:
3760                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3761                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3762                 break;
3763         }
3764         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3765         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3766         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3767         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3768         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3769         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3770         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3771         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3772         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3773
3774         /* Disable interrupts */
3775         if (sc_if->sk_port == SK_PORT_A)
3776                 sc->sk_intrmask &= ~SK_INTRS1;
3777         else
3778                 sc->sk_intrmask &= ~SK_INTRS2;
3779         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3780
3781         SK_XM_READ_2(sc_if, XM_ISR);
3782         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3783
3784         /* Free RX and TX mbufs still in the queues. */
3785         for (i = 0; i < SK_RX_RING_CNT; i++) {
3786                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3787                 if (rxd->rx_m != NULL) {
3788                         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3789                             rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3790                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3791                             rxd->rx_dmamap);
3792                         m_freem(rxd->rx_m);
3793                         rxd->rx_m = NULL;
3794                 }
3795         }
3796         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3797                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3798                 if (jrxd->rx_m != NULL) {
3799                         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3800                             jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3801                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3802                             jrxd->rx_dmamap);
3803                         m_freem(jrxd->rx_m);
3804                         jrxd->rx_m = NULL;
3805                 }
3806         }
3807         for (i = 0; i < SK_TX_RING_CNT; i++) {
3808                 txd = &sc_if->sk_cdata.sk_txdesc[i];
3809                 if (txd->tx_m != NULL) {
3810                         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3811                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3812                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3813                             txd->tx_dmamap);
3814                         m_freem(txd->tx_m);
3815                         txd->tx_m = NULL;
3816                 }
3817         }
3818
3819         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
3820
3821         return;
3822 }
3823
3824 static int
3825 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3826 {
3827         int error, value;
3828
3829         if (!arg1)
3830                 return (EINVAL);
3831         value = *(int *)arg1;
3832         error = sysctl_handle_int(oidp, &value, 0, req);
3833         if (error || !req->newptr)
3834                 return (error);
3835         if (value < low || value > high)
3836                 return (EINVAL);
3837         *(int *)arg1 = value;
3838         return (0);
3839 }
3840
3841 static int
3842 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3843 {
3844         return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
3845 }