sys/dev/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1997, 1998, 1999, 2000
   5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34 /*-
  35  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  36  *
  37  * Permission to use, copy, modify, and distribute this software for any
  38  * purpose with or without fee is hereby granted, provided that the above
  39  * copyright notice and this permission notice appear in all copies.
  40  *
  41  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  42  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  43  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  44  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  45  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  46  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  47  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  48  */
  49
  50 #include <sys/cdefs.h>
  51 __FBSDID("$FreeBSD$");
  52
  53 /*
  54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  55  * the SK-984x series adapters, both single port and dual port.
  56  * References:
  57  *      The XaQti XMAC II datasheet,
  58  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  60  *
  61  * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
  62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  63  * convenience to others until Vitesse corrects this problem:
  64  *
  65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  66  *
  67  * Written by Bill Paul <wpaul@ee.columbia.edu>
  68  * Department of Electrical Engineering
  69  * Columbia University, New York City
  70  */
  71 /*
  72  * The SysKonnect gigabit ethernet adapters consist of two main
  73  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  74  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  75  * components and a PHY while the GEnesis controller provides a PCI
  76  * interface with DMA support. Each card may have between 512K and
  77  * 2MB of SRAM on board depending on the configuration.
  78  *
  79  * The SysKonnect GEnesis controller can have either one or two XMAC
  80  * chips connected to it, allowing single or dual port NIC configurations.
  81  * SysKonnect has the distinction of being the only vendor on the market
  82  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  83  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  84  * XMAC registers. This driver takes advantage of these features to allow
  85  * both XMACs to operate as independent interfaces.
  86  */
  87
  88 #include <sys/param.h>
  89 #include <sys/systm.h>
  90 #include <sys/bus.h>
  91 #include <sys/endian.h>
  92 #include <sys/mbuf.h>
  93 #include <sys/malloc.h>
  94 #include <sys/kernel.h>
  95 #include <sys/module.h>
  96 #include <sys/socket.h>
  97 #include <sys/sockio.h>
  98 #include <sys/queue.h>
  99 #include <sys/sysctl.h>
 100
 101 #include <net/bpf.h>
 102 #include <net/ethernet.h>
 103 #include <net/if.h>
 104 #include <net/if_arp.h>
 105 #include <net/if_dl.h>
 106 #include <net/if_media.h>
 107 #include <net/if_types.h>
 108 #include <net/if_vlan_var.h>
 109
 110 #include <netinet/in.h>
 111 #include <netinet/in_systm.h>
 112 #include <netinet/ip.h>
 113
 114 #include <machine/bus.h>
 115 #include <machine/in_cksum.h>
 116 #include <machine/resource.h>
 117 #include <sys/rman.h>
 118
 119 #include <dev/mii/mii.h>
 120 #include <dev/mii/miivar.h>
 121 #include <dev/mii/brgphyreg.h>
 122
 123 #include <dev/pci/pcireg.h>
 124 #include <dev/pci/pcivar.h>
 125
 126 #if 0
 127 #define SK_USEIOSPACE
 128 #endif
 129
 130 #include <dev/sk/if_skreg.h>
 131 #include <dev/sk/xmaciireg.h>
 132 #include <dev/sk/yukonreg.h>
 133
 134 MODULE_DEPEND(sk, pci, 1, 1, 1);
 135 MODULE_DEPEND(sk, ether, 1, 1, 1);
 136 MODULE_DEPEND(sk, miibus, 1, 1, 1);
 137
 138 /* "device miibus" required.  See GENERIC if you get errors here. */
 139 #include "miibus_if.h"
 140
 141 #ifndef lint
 142 static const char rcsid[] =
 143   "$FreeBSD$";
 144 #endif
 145
 146 static struct sk_type sk_devs[] = {
 147         {
 148                 VENDORID_SK,
 149                 DEVICEID_SK_V1,
 150                 "SysKonnect Gigabit Ethernet (V1.0)"
 151         },
 152         {
 153                 VENDORID_SK,
 154                 DEVICEID_SK_V2,
 155                 "SysKonnect Gigabit Ethernet (V2.0)"
 156         },
 157         {
 158                 VENDORID_MARVELL,
 159                 DEVICEID_SK_V2,
 160                 "Marvell Gigabit Ethernet"
 161         },
 162         {
 163                 VENDORID_MARVELL,
 164                 DEVICEID_BELKIN_5005,
 165                 "Belkin F5D5005 Gigabit Ethernet"
 166         },
 167         {
 168                 VENDORID_3COM,
 169                 DEVICEID_3COM_3C940,
 170                 "3Com 3C940 Gigabit Ethernet"
 171         },
 172         {
 173                 VENDORID_LINKSYS,
 174                 DEVICEID_LINKSYS_EG1032,
 175                 "Linksys EG1032 Gigabit Ethernet"
 176         },
 177         {
 178                 VENDORID_DLINK,
 179                 DEVICEID_DLINK_DGE530T_A1,
 180                 "D-Link DGE-530T Gigabit Ethernet"
 181         },
 182         {
 183                 VENDORID_DLINK,
 184                 DEVICEID_DLINK_DGE530T_B1,
 185                 "D-Link DGE-530T Gigabit Ethernet"
 186         },
 187         { 0, 0, NULL }
 188 };
 189
 190 static int skc_probe(device_t);
 191 static int skc_attach(device_t);
 192 static int skc_detach(device_t);
 193 static void skc_shutdown(device_t);
 194 static int skc_suspend(device_t);
 195 static int skc_resume(device_t);
 196 static int sk_detach(device_t);
 197 static int sk_probe(device_t);
 198 static int sk_attach(device_t);
 199 static void sk_tick(void *);
 200 static void sk_yukon_tick(void *);
 201 static void sk_intr(void *);
 202 static void sk_intr_xmac(struct sk_if_softc *);
 203 static void sk_intr_bcom(struct sk_if_softc *);
 204 static void sk_intr_yukon(struct sk_if_softc *);
 205 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
 206 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
 207 static void sk_rxeof(struct sk_if_softc *);
 208 static void sk_jumbo_rxeof(struct sk_if_softc *);
 209 static void sk_txeof(struct sk_if_softc *);
 210 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
 211 static int sk_encap(struct sk_if_softc *, struct mbuf **);
 212 static void sk_start(struct ifnet *);
 213 static void sk_start_locked(struct ifnet *);
 214 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
 215 static void sk_init(void *);
 216 static void sk_init_locked(struct sk_if_softc *);
 217 static void sk_init_xmac(struct sk_if_softc *);
 218 static void sk_init_yukon(struct sk_if_softc *);
 219 static void sk_stop(struct sk_if_softc *);
 220 static void sk_watchdog(void *);
 221 static int sk_ifmedia_upd(struct ifnet *);
 222 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 223 static void sk_reset(struct sk_softc *);
 224 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
 225 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
 226 static int sk_newbuf(struct sk_if_softc *, int);
 227 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
 228 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 229 static int sk_dma_alloc(struct sk_if_softc *);
 230 static void sk_dma_free(struct sk_if_softc *);
 231 static void *sk_jalloc(struct sk_if_softc *);
 232 static void sk_jfree(void *, void *);
 233 static int sk_init_rx_ring(struct sk_if_softc *);
 234 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
 235 static void sk_init_tx_ring(struct sk_if_softc *);
 236 static u_int32_t sk_win_read_4(struct sk_softc *, int);
 237 static u_int16_t sk_win_read_2(struct sk_softc *, int);
 238 static u_int8_t sk_win_read_1(struct sk_softc *, int);
 239 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
 240 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
 241 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
 242 static u_int8_t sk_vpd_readbyte(struct sk_softc *, int);
 243 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int);
 244 static void sk_vpd_read(struct sk_softc *);
 245
 246 static int sk_miibus_readreg(device_t, int, int);
 247 static int sk_miibus_writereg(device_t, int, int, int);
 248 static void sk_miibus_statchg(device_t);
 249
 250 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
 251 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
 252                                                 int);
 253 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
 254
 255 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
 256 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
 257                                                 int);
 258 static void sk_marv_miibus_statchg(struct sk_if_softc *);
 259
 260 static uint32_t sk_xmchash(const uint8_t *);
 261 static uint32_t sk_gmchash(const uint8_t *);
 262 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
 263 static void sk_setmulti(struct sk_if_softc *);
 264 static void sk_setpromisc(struct sk_if_softc *);
 265
 266 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
 267 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
 268
 269 #ifdef SK_USEIOSPACE
 270 #define SK_RES          SYS_RES_IOPORT
 271 #define SK_RID          SK_PCI_LOIO
 272 #else
 273 #define SK_RES          SYS_RES_MEMORY
 274 #define SK_RID          SK_PCI_LOMEM
 275 #endif
 276
 277 /*
 278  * It seems that SK-NET GENESIS supports very simple checksum offload
 279  * capability for Tx and I believe it can generate 0 checksum value for
 280  * UDP packets in Tx as the hardware can't differenciate UDP packets from
 281  * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
 282  * means sender didn't perforam checksum computation. For the safety I
 283  * disabled UDP checksum offload capability at the moment. Alternatively
 284  * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
 285  * offload routine.
 286  */
 287 #define SK_CSUM_FEATURES        (CSUM_TCP)
 288
 289 /*
 290  * Note that we have newbus methods for both the GEnesis controller
 291  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 292  * the miibus code is a child of the XMACs. We need to do it this way
 293  * so that the miibus drivers can access the PHY registers on the
 294  * right PHY. It's not quite what I had in mind, but it's the only
 295  * design that achieves the desired effect.
 296  */
 297 static device_method_t skc_methods[] = {
 298         /* Device interface */
 299         DEVMETHOD(device_probe,         skc_probe),
 300         DEVMETHOD(device_attach,        skc_attach),
 301         DEVMETHOD(device_detach,        skc_detach),
 302         DEVMETHOD(device_suspend,       skc_suspend),
 303         DEVMETHOD(device_resume,        skc_resume),
 304         DEVMETHOD(device_shutdown,      skc_shutdown),
 305
 306         /* bus interface */
 307         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 308         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 309
 310         { 0, 0 }
 311 };
 312
 313 static driver_t skc_driver = {
 314         "skc",
 315         skc_methods,
 316         sizeof(struct sk_softc)
 317 };
 318
 319 static devclass_t skc_devclass;
 320
 321 static device_method_t sk_methods[] = {
 322         /* Device interface */
 323         DEVMETHOD(device_probe,         sk_probe),
 324         DEVMETHOD(device_attach,        sk_attach),
 325         DEVMETHOD(device_detach,        sk_detach),
 326         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 327
 328         /* bus interface */
 329         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 330         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 331
 332         /* MII interface */
 333         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 334         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 335         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 336
 337         { 0, 0 }
 338 };
 339
 340 static driver_t sk_driver = {
 341         "sk",
 342         sk_methods,
 343         sizeof(struct sk_if_softc)
 344 };
 345
 346 static devclass_t sk_devclass;
 347
 348 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, 0, 0);
 349 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0);
 350 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
 351
 352 #define SK_SETBIT(sc, reg, x)           \
 353         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 354
 355 #define SK_CLRBIT(sc, reg, x)           \
 356         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 357
 358 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 359         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 360
 361 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 362         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 363
 364 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 365         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 366
 367 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 368         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 369
 370 static u_int32_t
 371 sk_win_read_4(sc, reg)
 372         struct sk_softc         *sc;
 373         int                     reg;
 374 {
 375 #ifdef SK_USEIOSPACE
 376         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 377         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 378 #else
 379         return(CSR_READ_4(sc, reg));
 380 #endif
 381 }
 382
 383 static u_int16_t
 384 sk_win_read_2(sc, reg)
 385         struct sk_softc         *sc;
 386         int                     reg;
 387 {
 388 #ifdef SK_USEIOSPACE
 389         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 390         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 391 #else
 392         return(CSR_READ_2(sc, reg));
 393 #endif
 394 }
 395
 396 static u_int8_t
 397 sk_win_read_1(sc, reg)
 398         struct sk_softc         *sc;
 399         int                     reg;
 400 {
 401 #ifdef SK_USEIOSPACE
 402         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 403         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 404 #else
 405         return(CSR_READ_1(sc, reg));
 406 #endif
 407 }
 408
 409 static void
 410 sk_win_write_4(sc, reg, val)
 411         struct sk_softc         *sc;
 412         int                     reg;
 413         u_int32_t               val;
 414 {
 415 #ifdef SK_USEIOSPACE
 416         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 417         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 418 #else
 419         CSR_WRITE_4(sc, reg, val);
 420 #endif
 421         return;
 422 }
 423
 424 static void
 425 sk_win_write_2(sc, reg, val)
 426         struct sk_softc         *sc;
 427         int                     reg;
 428         u_int32_t               val;
 429 {
 430 #ifdef SK_USEIOSPACE
 431         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 432         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 433 #else
 434         CSR_WRITE_2(sc, reg, val);
 435 #endif
 436         return;
 437 }
 438
 439 static void
 440 sk_win_write_1(sc, reg, val)
 441         struct sk_softc         *sc;
 442         int                     reg;
 443         u_int32_t               val;
 444 {
 445 #ifdef SK_USEIOSPACE
 446         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 447         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 448 #else
 449         CSR_WRITE_1(sc, reg, val);
 450 #endif
 451         return;
 452 }
 453
 454 /*
 455  * The VPD EEPROM contains Vital Product Data, as suggested in
 456  * the PCI 2.1 specification. The VPD data is separared into areas
 457  * denoted by resource IDs. The SysKonnect VPD contains an ID string
 458  * resource (the name of the adapter), a read-only area resource
 459  * containing various key/data fields and a read/write area which
 460  * can be used to store asset management information or log messages.
 461  * We read the ID string and read-only into buffers attached to
 462  * the controller softc structure for later use. At the moment,
 463  * we only use the ID string during skc_attach().
 464  */
 465 static u_int8_t
 466 sk_vpd_readbyte(sc, addr)
 467         struct sk_softc         *sc;
 468         int                     addr;
 469 {
 470         int                     i;
 471
 472         sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
 473         for (i = 0; i < SK_TIMEOUT; i++) {
 474                 /* ASUS LOM takes a very long time to read VPD. */
 475                 DELAY(100);
 476                 if (sk_win_read_2(sc,
 477                     SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
 478                         break;
 479         }
 480
 481         if (i == SK_TIMEOUT)
 482                 return(0);
 483
 484         return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
 485 }
 486
 487 static void
 488 sk_vpd_read_res(sc, res, addr)
 489         struct sk_softc         *sc;
 490         struct vpd_res          *res;
 491         int                     addr;
 492 {
 493         int                     i;
 494         u_int8_t                *ptr;
 495
 496         ptr = (u_int8_t *)res;
 497         for (i = 0; i < sizeof(struct vpd_res); i++)
 498                 ptr[i] = sk_vpd_readbyte(sc, i + addr);
 499
 500         return;
 501 }
 502
 503 static void
 504 sk_vpd_read(sc)
 505         struct sk_softc         *sc;
 506 {
 507         int                     pos = 0, i;
 508         struct vpd_res          res;
 509
 510         /* Check VPD capability */
 511         if (sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_CAPID)) != PCIY_VPD)
 512                 return;
 513         if (sc->sk_vpd_prodname != NULL)
 514                 free(sc->sk_vpd_prodname, M_DEVBUF);
 515         if (sc->sk_vpd_readonly != NULL)
 516                 free(sc->sk_vpd_readonly, M_DEVBUF);
 517         sc->sk_vpd_prodname = NULL;
 518         sc->sk_vpd_readonly = NULL;
 519         sc->sk_vpd_readonly_len = 0;
 520
 521         sk_vpd_read_res(sc, &res, pos);
 522
 523         /*
 524          * Bail out quietly if the eeprom appears to be missing or empty.
 525          */
 526         if (res.vr_id == 0xff && res.vr_len == 0xff && res.vr_pad == 0xff)
 527                 return;
 528
 529         if (res.vr_id != VPD_RES_ID) {
 530                 device_printf(sc->sk_dev, "bad VPD resource id: expected %x "
 531                     "got %x\n", VPD_RES_ID, res.vr_id);
 532                 return;
 533         }
 534
 535         pos += sizeof(res);
 536         sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
 537         if (sc->sk_vpd_prodname != NULL) {
 538                 for (i = 0; i < res.vr_len; i++)
 539                         sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
 540                 sc->sk_vpd_prodname[i] = '\0';
 541         }
 542         pos += res.vr_len;
 543
 544         sk_vpd_read_res(sc, &res, pos);
 545
 546         if (res.vr_id != VPD_RES_READ) {
 547                 device_printf(sc->sk_dev, "bad VPD resource id: expected %x "
 548                     "got %x\n", VPD_RES_READ, res.vr_id);
 549                 return;
 550         }
 551
 552         pos += sizeof(res);
 553         sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
 554         for (i = 0; i < res.vr_len; i++)
 555                 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
 556         sc->sk_vpd_readonly_len = res.vr_len;
 557
 558         return;
 559 }
 560
 561 static int
 562 sk_miibus_readreg(dev, phy, reg)
 563         device_t                dev;
 564         int                     phy, reg;
 565 {
 566         struct sk_if_softc      *sc_if;
 567         int                     v;
 568
 569         sc_if = device_get_softc(dev);
 570
 571         SK_IF_MII_LOCK(sc_if);
 572         switch(sc_if->sk_softc->sk_type) {
 573         case SK_GENESIS:
 574                 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
 575                 break;
 576         case SK_YUKON:
 577         case SK_YUKON_LITE:
 578         case SK_YUKON_LP:
 579                 v = sk_marv_miibus_readreg(sc_if, phy, reg);
 580                 break;
 581         default:
 582                 v = 0;
 583                 break;
 584         }
 585         SK_IF_MII_UNLOCK(sc_if);
 586
 587         return (v);
 588 }
 589
 590 static int
 591 sk_miibus_writereg(dev, phy, reg, val)
 592         device_t                dev;
 593         int                     phy, reg, val;
 594 {
 595         struct sk_if_softc      *sc_if;
 596         int                     v;
 597
 598         sc_if = device_get_softc(dev);
 599
 600         SK_IF_MII_LOCK(sc_if);
 601         switch(sc_if->sk_softc->sk_type) {
 602         case SK_GENESIS:
 603                 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
 604                 break;
 605         case SK_YUKON:
 606         case SK_YUKON_LITE:
 607         case SK_YUKON_LP:
 608                 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
 609                 break;
 610         default:
 611                 v = 0;
 612                 break;
 613         }
 614         SK_IF_MII_UNLOCK(sc_if);
 615
 616         return (v);
 617 }
 618
 619 static void
 620 sk_miibus_statchg(dev)
 621         device_t                dev;
 622 {
 623         struct sk_if_softc      *sc_if;
 624
 625         sc_if = device_get_softc(dev);
 626
 627         SK_IF_MII_LOCK(sc_if);
 628         switch(sc_if->sk_softc->sk_type) {
 629         case SK_GENESIS:
 630                 sk_xmac_miibus_statchg(sc_if);
 631                 break;
 632         case SK_YUKON:
 633         case SK_YUKON_LITE:
 634         case SK_YUKON_LP:
 635                 sk_marv_miibus_statchg(sc_if);
 636                 break;
 637         }
 638         SK_IF_MII_UNLOCK(sc_if);
 639
 640         return;
 641 }
 642
 643 static int
 644 sk_xmac_miibus_readreg(sc_if, phy, reg)
 645         struct sk_if_softc      *sc_if;
 646         int                     phy, reg;
 647 {
 648         int                     i;
 649
 650         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
 651                 return(0);
 652
 653         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 654         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 655         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 656                 for (i = 0; i < SK_TIMEOUT; i++) {
 657                         DELAY(1);
 658                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 659                             XM_MMUCMD_PHYDATARDY)
 660                                 break;
 661                 }
 662
 663                 if (i == SK_TIMEOUT) {
 664                         if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 665                         return(0);
 666                 }
 667         }
 668         DELAY(1);
 669         i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
 670
 671         return(i);
 672 }
 673
 674 static int
 675 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 676         struct sk_if_softc      *sc_if;
 677         int                     phy, reg, val;
 678 {
 679         int                     i;
 680
 681         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 682         for (i = 0; i < SK_TIMEOUT; i++) {
 683                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 684                         break;
 685         }
 686
 687         if (i == SK_TIMEOUT) {
 688                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 689                 return (ETIMEDOUT);
 690         }
 691
 692         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 693         for (i = 0; i < SK_TIMEOUT; i++) {
 694                 DELAY(1);
 695                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 696                         break;
 697         }
 698         if (i == SK_TIMEOUT)
 699                 if_printf(sc_if->sk_ifp, "phy write timed out\n");
 700
 701         return(0);
 702 }
 703
 704 static void
 705 sk_xmac_miibus_statchg(sc_if)
 706         struct sk_if_softc      *sc_if;
 707 {
 708         struct mii_data         *mii;
 709
 710         mii = device_get_softc(sc_if->sk_miibus);
 711
 712         /*
 713          * If this is a GMII PHY, manually set the XMAC's
 714          * duplex mode accordingly.
 715          */
 716         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 717                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 718                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 719                 } else {
 720                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 721                 }
 722         }
 723 }
 724
 725 static int
 726 sk_marv_miibus_readreg(sc_if, phy, reg)
 727         struct sk_if_softc      *sc_if;
 728         int                     phy, reg;
 729 {
 730         u_int16_t               val;
 731         int                     i;
 732
 733         if (phy != 0 ||
 734             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 735              sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
 736                 return(0);
 737         }
 738
 739         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 740                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 741
 742         for (i = 0; i < SK_TIMEOUT; i++) {
 743                 DELAY(1);
 744                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 745                 if (val & YU_SMICR_READ_VALID)
 746                         break;
 747         }
 748
 749         if (i == SK_TIMEOUT) {
 750                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 751                 return(0);
 752         }
 753
 754         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 755
 756         return(val);
 757 }
 758
 759 static int
 760 sk_marv_miibus_writereg(sc_if, phy, reg, val)
 761         struct sk_if_softc      *sc_if;
 762         int                     phy, reg, val;
 763 {
 764         int                     i;
 765
 766         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 767         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 768                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 769
 770         for (i = 0; i < SK_TIMEOUT; i++) {
 771                 DELAY(1);
 772                 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
 773                         break;
 774         }
 775         if (i == SK_TIMEOUT)
 776                 if_printf(sc_if->sk_ifp, "phy write timeout\n");
 777
 778         return(0);
 779 }
 780
 781 static void
 782 sk_marv_miibus_statchg(sc_if)
 783         struct sk_if_softc      *sc_if;
 784 {
 785         return;
 786 }
 787
 788 #define HASH_BITS               6
 789
 790 static u_int32_t
 791 sk_xmchash(addr)
 792         const uint8_t *addr;
 793 {
 794         uint32_t crc;
 795
 796         /* Compute CRC for the address value. */
 797         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 798
 799         return (~crc & ((1 << HASH_BITS) - 1));
 800 }
 801
 802 /* gmchash is just a big endian crc */
 803 static u_int32_t
 804 sk_gmchash(addr)
 805         const uint8_t *addr;
 806 {
 807         uint32_t crc;
 808
 809         /* Compute CRC for the address value. */
 810         crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
 811
 812         return (crc & ((1 << HASH_BITS) - 1));
 813 }
 814
 815 static void
 816 sk_setfilt(sc_if, addr, slot)
 817         struct sk_if_softc      *sc_if;
 818         u_int16_t               *addr;
 819         int                     slot;
 820 {
 821         int                     base;
 822
 823         base = XM_RXFILT_ENTRY(slot);
 824
 825         SK_XM_WRITE_2(sc_if, base, addr[0]);
 826         SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
 827         SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
 828
 829         return;
 830 }
 831
 832 static void
 833 sk_setmulti(sc_if)
 834         struct sk_if_softc      *sc_if;
 835 {
 836         struct sk_softc         *sc = sc_if->sk_softc;
 837         struct ifnet            *ifp = sc_if->sk_ifp;
 838         u_int32_t               hashes[2] = { 0, 0 };
 839         int                     h = 0, i;
 840         struct ifmultiaddr      *ifma;
 841         u_int16_t               dummy[] = { 0, 0, 0 };
 842         u_int16_t               maddr[(ETHER_ADDR_LEN+1)/2];
 843
 844         SK_IF_LOCK_ASSERT(sc_if);
 845
 846         /* First, zot all the existing filters. */
 847         switch(sc->sk_type) {
 848         case SK_GENESIS:
 849                 for (i = 1; i < XM_RXFILT_MAX; i++)
 850                         sk_setfilt(sc_if, dummy, i);
 851
 852                 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
 853                 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
 854                 break;
 855         case SK_YUKON:
 856         case SK_YUKON_LITE:
 857         case SK_YUKON_LP:
 858                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
 859                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
 860                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
 861                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
 862                 break;
 863         }
 864
 865         /* Now program new ones. */
 866         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 867                 hashes[0] = 0xFFFFFFFF;
 868                 hashes[1] = 0xFFFFFFFF;
 869         } else {
 870                 i = 1;
 871                 IF_ADDR_LOCK(ifp);
 872                 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
 873                         if (ifma->ifma_addr->sa_family != AF_LINK)
 874                                 continue;
 875                         /*
 876                          * Program the first XM_RXFILT_MAX multicast groups
 877                          * into the perfect filter. For all others,
 878                          * use the hash table.
 879                          */
 880                         if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
 881                                 bcopy(LLADDR(
 882                                     (struct sockaddr_dl *)ifma->ifma_addr),
 883                                     maddr, ETHER_ADDR_LEN);
 884                                 sk_setfilt(sc_if, maddr, i);
 885                                 i++;
 886                                 continue;
 887                         }
 888
 889                         switch(sc->sk_type) {
 890                         case SK_GENESIS:
 891                                 bcopy(LLADDR(
 892                                     (struct sockaddr_dl *)ifma->ifma_addr),
 893                                     maddr, ETHER_ADDR_LEN);
 894                                 h = sk_xmchash((const uint8_t *)maddr);
 895                                 break;
 896                         case SK_YUKON:
 897                         case SK_YUKON_LITE:
 898                         case SK_YUKON_LP:
 899                                 bcopy(LLADDR(
 900                                     (struct sockaddr_dl *)ifma->ifma_addr),
 901                                     maddr, ETHER_ADDR_LEN);
 902                                 h = sk_gmchash((const uint8_t *)maddr);
 903                                 break;
 904                         }
 905                         if (h < 32)
 906                                 hashes[0] |= (1 << h);
 907                         else
 908                                 hashes[1] |= (1 << (h - 32));
 909                 }
 910                 IF_ADDR_UNLOCK(ifp);
 911         }
 912
 913         switch(sc->sk_type) {
 914         case SK_GENESIS:
 915                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
 916                                XM_MODE_RX_USE_PERFECT);
 917                 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 918                 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 919                 break;
 920         case SK_YUKON:
 921         case SK_YUKON_LITE:
 922         case SK_YUKON_LP:
 923                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 924                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 925                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 926                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 927                 break;
 928         }
 929
 930         return;
 931 }
 932
 933 static void
 934 sk_setpromisc(sc_if)
 935         struct sk_if_softc      *sc_if;
 936 {
 937         struct sk_softc         *sc = sc_if->sk_softc;
 938         struct ifnet            *ifp = sc_if->sk_ifp;
 939
 940         SK_IF_LOCK_ASSERT(sc_if);
 941
 942         switch(sc->sk_type) {
 943         case SK_GENESIS:
 944                 if (ifp->if_flags & IFF_PROMISC) {
 945                         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 946                 } else {
 947                         SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 948                 }
 949                 break;
 950         case SK_YUKON:
 951         case SK_YUKON_LITE:
 952         case SK_YUKON_LP:
 953                 if (ifp->if_flags & IFF_PROMISC) {
 954                         SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
 955                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 956                 } else {
 957                         SK_YU_SETBIT_2(sc_if, YUKON_RCR,
 958                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 959                 }
 960                 break;
 961         }
 962
 963         return;
 964 }
 965
 966 static int
 967 sk_init_rx_ring(sc_if)
 968         struct sk_if_softc      *sc_if;
 969 {
 970         struct sk_ring_data     *rd;
 971         bus_addr_t              addr;
 972         u_int32_t               csum_start;
 973         int                     i;
 974
 975         sc_if->sk_cdata.sk_rx_cons = 0;
 976
 977         csum_start = (ETHER_HDR_LEN + sizeof(struct ip))  << 16 |
 978             ETHER_HDR_LEN;
 979         rd = &sc_if->sk_rdata;
 980         bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 981         for (i = 0; i < SK_RX_RING_CNT; i++) {
 982                 if (sk_newbuf(sc_if, i) != 0)
 983                         return (ENOBUFS);
 984                 if (i == (SK_RX_RING_CNT - 1))
 985                         addr = SK_RX_RING_ADDR(sc_if, 0);
 986                 else
 987                         addr = SK_RX_RING_ADDR(sc_if, i + 1);
 988                 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 989                 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
 990         }
 991
 992         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
 993             sc_if->sk_cdata.sk_rx_ring_map,
 994             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 995
 996         return(0);
 997 }
 998
 999 static int
1000 sk_init_jumbo_rx_ring(sc_if)
1001         struct sk_if_softc      *sc_if;
1002 {
1003         struct sk_ring_data     *rd;
1004         bus_addr_t              addr;
1005         u_int32_t               csum_start;
1006         int                     i;
1007
1008         sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
1009
1010         csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
1011             ETHER_HDR_LEN;
1012         rd = &sc_if->sk_rdata;
1013         bzero(rd->sk_jumbo_rx_ring,
1014             sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
1015         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
1016                 if (sk_jumbo_newbuf(sc_if, i) != 0)
1017                         return (ENOBUFS);
1018                 if (i == (SK_JUMBO_RX_RING_CNT - 1))
1019                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
1020                 else
1021                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
1022                 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
1023                 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
1024         }
1025
1026         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
1027             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
1028             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1029
1030         return (0);
1031 }
1032
1033 static void
1034 sk_init_tx_ring(sc_if)
1035         struct sk_if_softc      *sc_if;
1036 {
1037         struct sk_ring_data     *rd;
1038         struct sk_txdesc        *txd;
1039         bus_addr_t              addr;
1040         int                     i;
1041
1042         STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
1043         STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
1044
1045         sc_if->sk_cdata.sk_tx_prod = 0;
1046         sc_if->sk_cdata.sk_tx_cons = 0;
1047         sc_if->sk_cdata.sk_tx_cnt = 0;
1048
1049         rd = &sc_if->sk_rdata;
1050         bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
1051         for (i = 0; i < SK_TX_RING_CNT; i++) {
1052                 if (i == (SK_TX_RING_CNT - 1))
1053                         addr = SK_TX_RING_ADDR(sc_if, 0);
1054                 else
1055                         addr = SK_TX_RING_ADDR(sc_if, i + 1);
1056                 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
1057                 txd = &sc_if->sk_cdata.sk_txdesc[i];
1058                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
1059         }
1060
1061         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
1062             sc_if->sk_cdata.sk_tx_ring_map,
1063             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1064 }
1065
1066 static __inline void
1067 sk_discard_rxbuf(sc_if, idx)
1068         struct sk_if_softc      *sc_if;
1069         int                     idx;
1070 {
1071         struct sk_rx_desc       *r;
1072         struct sk_rxdesc        *rxd;
1073         struct mbuf             *m;
1074
1075
1076         r = &sc_if->sk_rdata.sk_rx_ring[idx];
1077         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
1078         m = rxd->rx_m;
1079         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
1080 }
1081
1082 static __inline void
1083 sk_discard_jumbo_rxbuf(sc_if, idx)
1084         struct sk_if_softc      *sc_if;
1085         int                     idx;
1086 {
1087         struct sk_rx_desc       *r;
1088         struct sk_rxdesc        *rxd;
1089         struct mbuf             *m;
1090
1091         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1092         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1093         m = rxd->rx_m;
1094         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
1095 }
1096
1097 static int
1098 sk_newbuf(sc_if, idx)
1099         struct sk_if_softc      *sc_if;
1100         int                     idx;
1101 {
1102         struct sk_rx_desc       *r;
1103         struct sk_rxdesc        *rxd;
1104         struct mbuf             *m;
1105         bus_dma_segment_t       segs[1];
1106         bus_dmamap_t            map;
1107         int                     nsegs;
1108
1109         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1110         if (m == NULL)
1111                 return (ENOBUFS);
1112         m->m_len = m->m_pkthdr.len = MCLBYTES;
1113         m_adj(m, ETHER_ALIGN);
1114
1115         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
1116             sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1117                 m_freem(m);
1118                 return (ENOBUFS);
1119         }
1120         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1121
1122         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
1123         if (rxd->rx_m != NULL) {
1124                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
1125                     BUS_DMASYNC_POSTREAD);
1126                 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
1127         }
1128         map = rxd->rx_dmamap;
1129         rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
1130         sc_if->sk_cdata.sk_rx_sparemap = map;
1131         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
1132             BUS_DMASYNC_PREREAD);
1133         rxd->rx_m = m;
1134         r = &sc_if->sk_rdata.sk_rx_ring[idx];
1135         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1136         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1137         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1138
1139         return (0);
1140 }
1141
1142 static int
1143 sk_jumbo_newbuf(sc_if, idx)
1144         struct sk_if_softc      *sc_if;
1145         int                     idx;
1146 {
1147         struct sk_rx_desc       *r;
1148         struct sk_rxdesc        *rxd;
1149         struct mbuf             *m;
1150         bus_dma_segment_t       segs[1];
1151         bus_dmamap_t            map;
1152         int                     nsegs;
1153         void                    *buf;
1154
1155         MGETHDR(m, M_DONTWAIT, MT_DATA);
1156         if (m == NULL)
1157                 return (ENOBUFS);
1158         buf = sk_jalloc(sc_if);
1159         if (buf == NULL) {
1160                 m_freem(m);
1161                 return (ENOBUFS);
1162         }
1163         /* Attach the buffer to the mbuf */
1164         MEXTADD(m, buf, SK_JLEN, sk_jfree, (struct sk_if_softc *)sc_if, 0,
1165             EXT_NET_DRV);
1166         if ((m->m_flags & M_EXT) == 0) {
1167                 m_freem(m);
1168                 return (ENOBUFS);
1169         }
1170         m->m_pkthdr.len = m->m_len = SK_JLEN;
1171         /*
1172          * Adjust alignment so packet payload begins on a
1173          * longword boundary. Mandatory for Alpha, useful on
1174          * x86 too.
1175          */
1176         m_adj(m, ETHER_ALIGN);
1177
1178         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1179             sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1180                 m_freem(m);
1181                 return (ENOBUFS);
1182         }
1183         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1184
1185         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1186         if (rxd->rx_m != NULL) {
1187                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1188                     BUS_DMASYNC_POSTREAD);
1189                 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1190                     rxd->rx_dmamap);
1191         }
1192         map = rxd->rx_dmamap;
1193         rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1194         sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1195         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1196             BUS_DMASYNC_PREREAD);
1197         rxd->rx_m = m;
1198         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1199         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1200         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1201         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1202
1203         return (0);
1204 }
1205
1206 /*
1207  * Set media options.
1208  */
1209 static int
1210 sk_ifmedia_upd(ifp)
1211         struct ifnet            *ifp;
1212 {
1213         struct sk_if_softc      *sc_if = ifp->if_softc;
1214         struct mii_data         *mii;
1215
1216         mii = device_get_softc(sc_if->sk_miibus);
1217         sk_init(sc_if);
1218         mii_mediachg(mii);
1219
1220         return(0);
1221 }
1222
1223 /*
1224  * Report current media status.
1225  */
1226 static void
1227 sk_ifmedia_sts(ifp, ifmr)
1228         struct ifnet            *ifp;
1229         struct ifmediareq       *ifmr;
1230 {
1231         struct sk_if_softc      *sc_if;
1232         struct mii_data         *mii;
1233
1234         sc_if = ifp->if_softc;
1235         mii = device_get_softc(sc_if->sk_miibus);
1236
1237         mii_pollstat(mii);
1238         ifmr->ifm_active = mii->mii_media_active;
1239         ifmr->ifm_status = mii->mii_media_status;
1240
1241         return;
1242 }
1243
1244 static int
1245 sk_ioctl(ifp, command, data)
1246         struct ifnet            *ifp;
1247         u_long                  command;
1248         caddr_t                 data;
1249 {
1250         struct sk_if_softc      *sc_if = ifp->if_softc;
1251         struct ifreq            *ifr = (struct ifreq *) data;
1252         int                     error, mask;
1253         struct mii_data         *mii;
1254
1255         error = 0;
1256         switch(command) {
1257         case SIOCSIFMTU:
1258                 SK_IF_LOCK(sc_if);
1259                 if (ifr->ifr_mtu > SK_JUMBO_MTU)
1260                         error = EINVAL;
1261                 else {
1262                         ifp->if_mtu = ifr->ifr_mtu;
1263                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1264                         sk_init_locked(sc_if);
1265                 }
1266                 SK_IF_UNLOCK(sc_if);
1267                 break;
1268         case SIOCSIFFLAGS:
1269                 SK_IF_LOCK(sc_if);
1270                 if (ifp->if_flags & IFF_UP) {
1271                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1272                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1273                                     & IFF_PROMISC) {
1274                                         sk_setpromisc(sc_if);
1275                                         sk_setmulti(sc_if);
1276                                 }
1277                         } else
1278                                 sk_init_locked(sc_if);
1279                 } else {
1280                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1281                                 sk_stop(sc_if);
1282                 }
1283                 sc_if->sk_if_flags = ifp->if_flags;
1284                 SK_IF_UNLOCK(sc_if);
1285                 break;
1286         case SIOCADDMULTI:
1287         case SIOCDELMULTI:
1288                 SK_IF_LOCK(sc_if);
1289                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1290                         sk_setmulti(sc_if);
1291                 SK_IF_UNLOCK(sc_if);
1292                 break;
1293         case SIOCGIFMEDIA:
1294         case SIOCSIFMEDIA:
1295                 mii = device_get_softc(sc_if->sk_miibus);
1296                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1297                 break;
1298         case SIOCSIFCAP:
1299                 SK_IF_LOCK(sc_if);
1300                 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1301                         SK_IF_UNLOCK(sc_if);
1302                         break;
1303                 }
1304                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1305                 if (mask & IFCAP_HWCSUM) {
1306                         ifp->if_capenable ^= IFCAP_HWCSUM;
1307                         if (IFCAP_HWCSUM & ifp->if_capenable &&
1308                             IFCAP_HWCSUM & ifp->if_capabilities)
1309                                 ifp->if_hwassist = SK_CSUM_FEATURES;
1310                         else
1311                                 ifp->if_hwassist = 0;
1312                 }
1313                 SK_IF_UNLOCK(sc_if);
1314                 break;
1315         default:
1316                 error = ether_ioctl(ifp, command, data);
1317                 break;
1318         }
1319
1320         return (error);
1321 }
1322
1323 /*
1324  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1325  * IDs against our list and return a device name if we find a match.
1326  */
1327 static int
1328 skc_probe(dev)
1329         device_t                dev;
1330 {
1331         struct sk_type          *t = sk_devs;
1332
1333         while(t->sk_name != NULL) {
1334                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1335                     (pci_get_device(dev) == t->sk_did)) {
1336                         /*
1337                          * Only attach to rev. 2 of the Linksys EG1032 adapter.
1338                          * Rev. 3 is supported by re(4).
1339                          */
1340                         if ((t->sk_vid == VENDORID_LINKSYS) &&
1341                                 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1342                                 (pci_get_subdevice(dev) !=
1343                                  SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1344                                 t++;
1345                                 continue;
1346                         }
1347                         device_set_desc(dev, t->sk_name);
1348                         return (BUS_PROBE_DEFAULT);
1349                 }
1350                 t++;
1351         }
1352
1353         return(ENXIO);
1354 }
1355
1356 /*
1357  * Force the GEnesis into reset, then bring it out of reset.
1358  */
1359 static void
1360 sk_reset(sc)
1361         struct sk_softc         *sc;
1362 {
1363
1364         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1365         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1366         if (SK_YUKON_FAMILY(sc->sk_type))
1367                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1368
1369         DELAY(1000);
1370         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1371         DELAY(2);
1372         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1373         if (SK_YUKON_FAMILY(sc->sk_type))
1374                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1375
1376         if (sc->sk_type == SK_GENESIS) {
1377                 /* Configure packet arbiter */
1378                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1379                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1380                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1381                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1382                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1383         }
1384
1385         /* Enable RAM interface */
1386         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1387
1388         /*
1389          * Configure interrupt moderation. The moderation timer
1390          * defers interrupts specified in the interrupt moderation
1391          * timer mask based on the timeout specified in the interrupt
1392          * moderation timer init register. Each bit in the timer
1393          * register represents one tick, so to specify a timeout in
1394          * microseconds, we have to multiply by the correct number of
1395          * ticks-per-microsecond.
1396          */
1397         switch (sc->sk_type) {
1398         case SK_GENESIS:
1399                 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1400                 break;
1401         default:
1402                 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1403                 break;
1404         }
1405         if (bootverbose)
1406                 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1407                     sc->sk_int_mod);
1408         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1409             sc->sk_int_ticks));
1410         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1411             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1412         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1413
1414         return;
1415 }
1416
1417 static int
1418 sk_probe(dev)
1419         device_t                dev;
1420 {
1421         struct sk_softc         *sc;
1422
1423         sc = device_get_softc(device_get_parent(dev));
1424
1425         /*
1426          * Not much to do here. We always know there will be
1427          * at least one XMAC present, and if there are two,
1428          * skc_attach() will create a second device instance
1429          * for us.
1430          */
1431         switch (sc->sk_type) {
1432         case SK_GENESIS:
1433                 device_set_desc(dev, "XaQti Corp. XMAC II");
1434                 break;
1435         case SK_YUKON:
1436         case SK_YUKON_LITE:
1437         case SK_YUKON_LP:
1438                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1439                 break;
1440         }
1441
1442         return (BUS_PROBE_DEFAULT);
1443 }
1444
1445 /*
1446  * Each XMAC chip is attached as a separate logical IP interface.
1447  * Single port cards will have only one logical interface of course.
1448  */
1449 static int
1450 sk_attach(dev)
1451         device_t                dev;
1452 {
1453         struct sk_softc         *sc;
1454         struct sk_if_softc      *sc_if;
1455         struct ifnet            *ifp;
1456         int                     i, port, error;
1457         u_char                  eaddr[6];
1458
1459         if (dev == NULL)
1460                 return(EINVAL);
1461
1462         error = 0;
1463         sc_if = device_get_softc(dev);
1464         sc = device_get_softc(device_get_parent(dev));
1465         port = *(int *)device_get_ivars(dev);
1466
1467         sc_if->sk_if_dev = dev;
1468         sc_if->sk_port = port;
1469         sc_if->sk_softc = sc;
1470         sc->sk_if[port] = sc_if;
1471         if (port == SK_PORT_A)
1472                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1473         if (port == SK_PORT_B)
1474                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1475
1476         callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1477         callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1478
1479         if (sk_dma_alloc(sc_if) != 0) {
1480                 error = ENOMEM;
1481                 goto fail;
1482         }
1483
1484         ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1485         if (ifp == NULL) {
1486                 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1487                 error = ENOSPC;
1488                 goto fail;
1489         }
1490         ifp->if_softc = sc_if;
1491         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1492         ifp->if_mtu = ETHERMTU;
1493         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1494         /*
1495          * SK_GENESIS has a bug in checksum offload - From linux.
1496          */
1497         if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1498                 ifp->if_capabilities = IFCAP_HWCSUM;
1499                 ifp->if_hwassist = SK_CSUM_FEATURES;
1500         } else {
1501                 ifp->if_capabilities = 0;
1502                 ifp->if_hwassist = 0;
1503         }
1504         ifp->if_capenable = ifp->if_capabilities;
1505         ifp->if_ioctl = sk_ioctl;
1506         ifp->if_start = sk_start;
1507         ifp->if_timer = 0;
1508         ifp->if_watchdog = NULL;
1509         ifp->if_init = sk_init;
1510         IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1511         ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1512         IFQ_SET_READY(&ifp->if_snd);
1513
1514         /*
1515          * Get station address for this interface. Note that
1516          * dual port cards actually come with three station
1517          * addresses: one for each port, plus an extra. The
1518          * extra one is used by the SysKonnect driver software
1519          * as a 'virtual' station address for when both ports
1520          * are operating in failover mode. Currently we don't
1521          * use this extra address.
1522          */
1523         SK_IF_LOCK(sc_if);
1524         for (i = 0; i < ETHER_ADDR_LEN; i++)
1525                 eaddr[i] =
1526                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1527
1528         /*
1529          * Set up RAM buffer addresses. The NIC will have a certain
1530          * amount of SRAM on it, somewhere between 512K and 2MB. We
1531          * need to divide this up a) between the transmitter and
1532          * receiver and b) between the two XMACs, if this is a
1533          * dual port NIC. Our algotithm is to divide up the memory
1534          * evenly so that everyone gets a fair share.
1535          *
1536          * Just to be contrary, Yukon2 appears to have separate memory
1537          * for each MAC.
1538          */
1539         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1540                 u_int32_t               chunk, val;
1541
1542                 chunk = sc->sk_ramsize / 2;
1543                 val = sc->sk_rboff / sizeof(u_int64_t);
1544                 sc_if->sk_rx_ramstart = val;
1545                 val += (chunk / sizeof(u_int64_t));
1546                 sc_if->sk_rx_ramend = val - 1;
1547                 sc_if->sk_tx_ramstart = val;
1548                 val += (chunk / sizeof(u_int64_t));
1549                 sc_if->sk_tx_ramend = val - 1;
1550         } else {
1551                 u_int32_t               chunk, val;
1552
1553                 chunk = sc->sk_ramsize / 4;
1554                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1555                     sizeof(u_int64_t);
1556                 sc_if->sk_rx_ramstart = val;
1557                 val += (chunk / sizeof(u_int64_t));
1558                 sc_if->sk_rx_ramend = val - 1;
1559                 sc_if->sk_tx_ramstart = val;
1560                 val += (chunk / sizeof(u_int64_t));
1561                 sc_if->sk_tx_ramend = val - 1;
1562         }
1563
1564         /* Read and save PHY type and set PHY address */
1565         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1566         if (!SK_YUKON_FAMILY(sc->sk_type)) {
1567                 switch(sc_if->sk_phytype) {
1568                 case SK_PHYTYPE_XMAC:
1569                         sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1570                         break;
1571                 case SK_PHYTYPE_BCOM:
1572                         sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1573                         break;
1574                 default:
1575                         device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1576                             sc_if->sk_phytype);
1577                         error = ENODEV;
1578                         SK_IF_UNLOCK(sc_if);
1579                         goto fail;
1580                 }
1581         } else {
1582                 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1583                     sc->sk_pmd != 'S') {
1584                         /* not initialized, punt */
1585                         sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1586                         sc->sk_coppertype = 1;
1587                 }
1588
1589                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1590
1591                 if (!(sc->sk_coppertype))
1592                         sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1593         }
1594
1595         /*
1596          * Call MI attach routine.  Can't hold locks when calling into ether_*.
1597          */
1598         SK_IF_UNLOCK(sc_if);
1599         ether_ifattach(ifp, eaddr);
1600         SK_IF_LOCK(sc_if);
1601
1602         /*
1603          * The hardware should be ready for VLAN_MTU by default:
1604          * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1605          * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1606          *
1607          */
1608         ifp->if_capabilities |= IFCAP_VLAN_MTU;
1609         ifp->if_capenable |= IFCAP_VLAN_MTU;
1610         /*
1611          * Tell the upper layer(s) we support long frames.
1612          * Must appear after the call to ether_ifattach() because
1613          * ether_ifattach() sets ifi_hdrlen to the default value.
1614          */
1615         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1616
1617         /*
1618          * Do miibus setup.
1619          */
1620         switch (sc->sk_type) {
1621         case SK_GENESIS:
1622                 sk_init_xmac(sc_if);
1623                 break;
1624         case SK_YUKON:
1625         case SK_YUKON_LITE:
1626         case SK_YUKON_LP:
1627                 sk_init_yukon(sc_if);
1628                 break;
1629         }
1630
1631         SK_IF_UNLOCK(sc_if);
1632         if (mii_phy_probe(dev, &sc_if->sk_miibus,
1633             sk_ifmedia_upd, sk_ifmedia_sts)) {
1634                 device_printf(sc_if->sk_if_dev, "no PHY found!\n");
1635                 ether_ifdetach(ifp);
1636                 error = ENXIO;
1637                 goto fail;
1638         }
1639
1640 fail:
1641         if (error) {
1642                 /* Access should be ok even though lock has been dropped */
1643                 sc->sk_if[port] = NULL;
1644                 sk_detach(dev);
1645         }
1646
1647         return(error);
1648 }
1649
1650 /*
1651  * Attach the interface. Allocate softc structures, do ifmedia
1652  * setup and ethernet/BPF attach.
1653  */
1654 static int
1655 skc_attach(dev)
1656         device_t                dev;
1657 {
1658         struct sk_softc         *sc;
1659         int                     error = 0, *port, rid;
1660         uint8_t                 skrs;
1661         char                    *pname, *revstr;
1662
1663         sc = device_get_softc(dev);
1664         sc->sk_dev = dev;
1665
1666         mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1667             MTX_DEF);
1668         mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1669         /*
1670          * Map control/status registers.
1671          */
1672         pci_enable_busmaster(dev);
1673
1674         rid = SK_RID;
1675         sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE);
1676
1677         if (sc->sk_res == NULL) {
1678                 device_printf(dev, "couldn't map ports/memory\n");
1679                 error = ENXIO;
1680                 goto fail;
1681         }
1682
1683         sc->sk_btag = rman_get_bustag(sc->sk_res);
1684         sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1685
1686         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1687         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1688
1689         /* Bail out if chip is not recognized. */
1690         if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1691                 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1692                     sc->sk_type, sc->sk_rev);
1693                 error = ENXIO;
1694                 goto fail;
1695         }
1696
1697         /* Allocate interrupt */
1698         rid = 0;
1699         sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1700             RF_SHAREABLE | RF_ACTIVE);
1701
1702         if (sc->sk_irq == NULL) {
1703                 device_printf(dev, "couldn't map interrupt\n");
1704                 error = ENXIO;
1705                 goto fail;
1706         }
1707
1708         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1709                 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1710                 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1711                 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1712                 "SK interrupt moderation");
1713
1714         /* Pull in device tunables. */
1715         sc->sk_int_mod = SK_IM_DEFAULT;
1716         error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1717                 "int_mod", &sc->sk_int_mod);
1718         if (error == 0) {
1719                 if (sc->sk_int_mod < SK_IM_MIN ||
1720                     sc->sk_int_mod > SK_IM_MAX) {
1721                         device_printf(dev, "int_mod value out of range; "
1722                             "using default: %d\n", SK_IM_DEFAULT);
1723                         sc->sk_int_mod = SK_IM_DEFAULT;
1724                 }
1725         }
1726
1727         /* Reset the adapter. */
1728         sk_reset(sc);
1729
1730         /* Read and save vital product data from EEPROM. */
1731         sk_vpd_read(sc);
1732
1733         skrs = sk_win_read_1(sc, SK_EPROM0);
1734         if (sc->sk_type == SK_GENESIS) {
1735                 /* Read and save RAM size and RAMbuffer offset */
1736                 switch(skrs) {
1737                 case SK_RAMSIZE_512K_64:
1738                         sc->sk_ramsize = 0x80000;
1739                         sc->sk_rboff = SK_RBOFF_0;
1740                         break;
1741                 case SK_RAMSIZE_1024K_64:
1742                         sc->sk_ramsize = 0x100000;
1743                         sc->sk_rboff = SK_RBOFF_80000;
1744                         break;
1745                 case SK_RAMSIZE_1024K_128:
1746                         sc->sk_ramsize = 0x100000;
1747                         sc->sk_rboff = SK_RBOFF_0;
1748                         break;
1749                 case SK_RAMSIZE_2048K_128:
1750                         sc->sk_ramsize = 0x200000;
1751                         sc->sk_rboff = SK_RBOFF_0;
1752                         break;
1753                 default:
1754                         device_printf(dev, "unknown ram size: %d\n", skrs);
1755                         error = ENXIO;
1756                         goto fail;
1757                 }
1758         } else { /* SK_YUKON_FAMILY */
1759                 if (skrs == 0x00)
1760                         sc->sk_ramsize = 0x20000;
1761                 else
1762                         sc->sk_ramsize = skrs * (1<<12);
1763                 sc->sk_rboff = SK_RBOFF_0;
1764         }
1765
1766         /* Read and save physical media type */
1767          sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1768
1769          if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1770                  sc->sk_coppertype = 1;
1771          else
1772                  sc->sk_coppertype = 0;
1773
1774         /* Determine whether to name it with VPD PN or just make it up.
1775          * Marvell Yukon VPD PN seems to freqently be bogus. */
1776         switch (pci_get_device(dev)) {
1777         case DEVICEID_SK_V1:
1778         case DEVICEID_BELKIN_5005:
1779         case DEVICEID_3COM_3C940:
1780         case DEVICEID_LINKSYS_EG1032:
1781         case DEVICEID_DLINK_DGE530T_A1:
1782         case DEVICEID_DLINK_DGE530T_B1:
1783                 /* Stay with VPD PN. */
1784                 pname = sc->sk_vpd_prodname;
1785                 break;
1786         case DEVICEID_SK_V2:
1787                 /* YUKON VPD PN might bear no resemblance to reality. */
1788                 switch (sc->sk_type) {
1789                 case SK_GENESIS:
1790                         /* Stay with VPD PN. */
1791                         pname = sc->sk_vpd_prodname;
1792                         break;
1793                 case SK_YUKON:
1794                         pname = "Marvell Yukon Gigabit Ethernet";
1795                         break;
1796                 case SK_YUKON_LITE:
1797                         pname = "Marvell Yukon Lite Gigabit Ethernet";
1798                         break;
1799                 case SK_YUKON_LP:
1800                         pname = "Marvell Yukon LP Gigabit Ethernet";
1801                         break;
1802                 default:
1803                         pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1804                         break;
1805                 }
1806
1807                 /* Yukon Lite Rev. A0 needs special test. */
1808                 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1809                         u_int32_t far;
1810                         u_int8_t testbyte;
1811
1812                         /* Save flash address register before testing. */
1813                         far = sk_win_read_4(sc, SK_EP_ADDR);
1814
1815                         sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1816                         testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1817
1818                         if (testbyte != 0x00) {
1819                                 /* Yukon Lite Rev. A0 detected. */
1820                                 sc->sk_type = SK_YUKON_LITE;
1821                                 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1822                                 /* Restore flash address register. */
1823                                 sk_win_write_4(sc, SK_EP_ADDR, far);
1824                         }
1825                 }
1826                 break;
1827         default:
1828                 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1829                         "chipver=%02x, rev=%x\n",
1830                         pci_get_vendor(dev), pci_get_device(dev),
1831                         sc->sk_type, sc->sk_rev);
1832                 error = ENXIO;
1833                 goto fail;
1834         }
1835
1836         if (sc->sk_type == SK_YUKON_LITE) {
1837                 switch (sc->sk_rev) {
1838                 case SK_YUKON_LITE_REV_A0:
1839                         revstr = "A0";
1840                         break;
1841                 case SK_YUKON_LITE_REV_A1:
1842                         revstr = "A1";
1843                         break;
1844                 case SK_YUKON_LITE_REV_A3:
1845                         revstr = "A3";
1846                         break;
1847                 default:
1848                         revstr = "";
1849                         break;
1850                 }
1851         } else {
1852                 revstr = "";
1853         }
1854
1855         /* Announce the product name and more VPD data if there. */
1856         device_printf(dev, "%s rev. %s(0x%x)\n",
1857                 pname != NULL ? pname : "<unknown>", revstr, sc->sk_rev);
1858
1859         if (bootverbose) {
1860                 if (sc->sk_vpd_readonly != NULL &&
1861                     sc->sk_vpd_readonly_len != 0) {
1862                         char buf[256];
1863                         char *dp = sc->sk_vpd_readonly;
1864                         uint16_t l, len = sc->sk_vpd_readonly_len;
1865
1866                         while (len >= 3) {
1867                                 if ((*dp == 'P' && *(dp+1) == 'N') ||
1868                                     (*dp == 'E' && *(dp+1) == 'C') ||
1869                                     (*dp == 'M' && *(dp+1) == 'N') ||
1870                                     (*dp == 'S' && *(dp+1) == 'N')) {
1871                                         l = 0;
1872                                         while (l < *(dp+2)) {
1873                                                 buf[l] = *(dp+3+l);
1874                                                 ++l;
1875                                         }
1876                                         buf[l] = '\0';
1877                                         device_printf(dev, "%c%c: %s\n",
1878                                             *dp, *(dp+1), buf);
1879                                         len -= (3 + l);
1880                                         dp += (3 + l);
1881                                 } else {
1882                                         len -= (3 + *(dp+2));
1883                                         dp += (3 + *(dp+2));
1884                                 }
1885                         }
1886                 }
1887                 device_printf(dev, "chip ver  = 0x%02x\n", sc->sk_type);
1888                 device_printf(dev, "chip rev  = 0x%02x\n", sc->sk_rev);
1889                 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1890                 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1891         }
1892
1893         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1894         if (sc->sk_devs[SK_PORT_A] == NULL) {
1895                 device_printf(dev, "failed to add child for PORT_A\n");
1896                 error = ENXIO;
1897                 goto fail;
1898         }
1899         port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1900         if (port == NULL) {
1901                 device_printf(dev, "failed to allocate memory for "
1902                     "ivars of PORT_A\n");
1903                 error = ENXIO;
1904                 goto fail;
1905         }
1906         *port = SK_PORT_A;
1907         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1908
1909         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1910                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1911                 if (sc->sk_devs[SK_PORT_B] == NULL) {
1912                         device_printf(dev, "failed to add child for PORT_B\n");
1913                         error = ENXIO;
1914                         goto fail;
1915                 }
1916                 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1917                 if (port == NULL) {
1918                         device_printf(dev, "failed to allocate memory for "
1919                             "ivars of PORT_B\n");
1920                         error = ENXIO;
1921                         goto fail;
1922                 }
1923                 *port = SK_PORT_B;
1924                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1925         }
1926
1927         /* Turn on the 'driver is loaded' LED. */
1928         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1929
1930         error = bus_generic_attach(dev);
1931         if (error) {
1932                 device_printf(dev, "failed to attach port(s)\n");
1933                 goto fail;
1934         }
1935
1936         /* Hook interrupt last to avoid having to lock softc */
1937         error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET|INTR_MPSAFE,
1938             sk_intr, sc, &sc->sk_intrhand);
1939
1940         if (error) {
1941                 device_printf(dev, "couldn't set up irq\n");
1942                 goto fail;
1943         }
1944
1945 fail:
1946         if (error)
1947                 skc_detach(dev);
1948
1949         return(error);
1950 }
1951
1952 /*
1953  * Shutdown hardware and free up resources. This can be called any
1954  * time after the mutex has been initialized. It is called in both
1955  * the error case in attach and the normal detach case so it needs
1956  * to be careful about only freeing resources that have actually been
1957  * allocated.
1958  */
1959 static int
1960 sk_detach(dev)
1961         device_t                dev;
1962 {
1963         struct sk_if_softc      *sc_if;
1964         struct ifnet            *ifp;
1965
1966         sc_if = device_get_softc(dev);
1967         KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1968             ("sk mutex not initialized in sk_detach"));
1969         SK_IF_LOCK(sc_if);
1970
1971         ifp = sc_if->sk_ifp;
1972         /* These should only be active if attach_xmac succeeded */
1973         if (device_is_attached(dev)) {
1974                 sk_stop(sc_if);
1975                 /* Can't hold locks while calling detach */
1976                 SK_IF_UNLOCK(sc_if);
1977                 callout_drain(&sc_if->sk_tick_ch);
1978                 callout_drain(&sc_if->sk_watchdog_ch);
1979                 ether_ifdetach(ifp);
1980                 SK_IF_LOCK(sc_if);
1981         }
1982         if (ifp)
1983                 if_free(ifp);
1984         /*
1985          * We're generally called from skc_detach() which is using
1986          * device_delete_child() to get to here. It's already trashed
1987          * miibus for us, so don't do it here or we'll panic.
1988          */
1989         /*
1990         if (sc_if->sk_miibus != NULL)
1991                 device_delete_child(dev, sc_if->sk_miibus);
1992         */
1993         bus_generic_detach(dev);
1994         sk_dma_free(sc_if);
1995         SK_IF_UNLOCK(sc_if);
1996
1997         return(0);
1998 }
1999
2000 static int
2001 skc_detach(dev)
2002         device_t                dev;
2003 {
2004         struct sk_softc         *sc;
2005
2006         sc = device_get_softc(dev);
2007         KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
2008
2009         if (device_is_alive(dev)) {
2010                 if (sc->sk_devs[SK_PORT_A] != NULL) {
2011                         free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
2012                         device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
2013                 }
2014                 if (sc->sk_devs[SK_PORT_B] != NULL) {
2015                         free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
2016                         device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
2017                 }
2018                 bus_generic_detach(dev);
2019         }
2020
2021         if (sc->sk_vpd_prodname != NULL)
2022                 free(sc->sk_vpd_prodname, M_DEVBUF);
2023         if (sc->sk_vpd_readonly != NULL)
2024                 free(sc->sk_vpd_readonly, M_DEVBUF);
2025
2026         if (sc->sk_intrhand)
2027                 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
2028         if (sc->sk_irq)
2029                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
2030         if (sc->sk_res)
2031                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
2032
2033         mtx_destroy(&sc->sk_mii_mtx);
2034         mtx_destroy(&sc->sk_mtx);
2035
2036         return(0);
2037 }
2038
2039 struct sk_dmamap_arg {
2040         bus_addr_t      sk_busaddr;
2041 };
2042
2043 static void
2044 sk_dmamap_cb(arg, segs, nseg, error)
2045         void                    *arg;
2046         bus_dma_segment_t       *segs;
2047         int                     nseg;
2048         int                     error;
2049 {
2050         struct sk_dmamap_arg    *ctx;
2051
2052         if (error != 0)
2053                 return;
2054
2055         ctx = arg;
2056         ctx->sk_busaddr = segs[0].ds_addr;
2057 }
2058
2059 /*
2060  * Allocate jumbo buffer storage. The SysKonnect adapters support
2061  * "jumbograms" (9K frames), although SysKonnect doesn't currently
2062  * use them in their drivers. In order for us to use them, we need
2063  * large 9K receive buffers, however standard mbuf clusters are only
2064  * 2048 bytes in size. Consequently, we need to allocate and manage
2065  * our own jumbo buffer pool. Fortunately, this does not require an
2066  * excessive amount of additional code.
2067  */
2068 static int
2069 sk_dma_alloc(sc_if)
2070         struct sk_if_softc      *sc_if;
2071 {
2072         struct sk_dmamap_arg    ctx;
2073         struct sk_txdesc        *txd;
2074         struct sk_rxdesc        *rxd;
2075         struct sk_rxdesc        *jrxd;
2076         u_int8_t                *ptr;
2077         struct sk_jpool_entry   *entry;
2078         int                     error, i;
2079
2080         mtx_init(&sc_if->sk_jlist_mtx, "sk_jlist_mtx", NULL, MTX_DEF);
2081         SLIST_INIT(&sc_if->sk_jfree_listhead);
2082         SLIST_INIT(&sc_if->sk_jinuse_listhead);
2083
2084         /* create parent tag */
2085         /*
2086          * XXX
2087          * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
2088          * in bus_dma_tag_create(9) as the NIC would support DAC mode.
2089          * However bz@ reported that it does not work on amd64 with > 4GB
2090          * RAM. Until we have more clues of the breakage, disable DAC mode
2091          * by limiting DMA address to be in 32bit address space.
2092          */
2093         error = bus_dma_tag_create(NULL,        /* parent */
2094                     1, 0,                       /* algnmnt, boundary */
2095                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
2096                     BUS_SPACE_MAXADDR,          /* highaddr */
2097                     NULL, NULL,                 /* filter, filterarg */
2098                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
2099                     0,                          /* nsegments */
2100                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
2101                     0,                          /* flags */
2102                     NULL, NULL,                 /* lockfunc, lockarg */
2103                     &sc_if->sk_cdata.sk_parent_tag);
2104         if (error != 0) {
2105                 device_printf(sc_if->sk_if_dev,
2106                     "failed to create parent DMA tag\n");
2107                 goto fail;
2108         }
2109         /* create tag for Tx ring */
2110         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2111                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
2112                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
2113                     BUS_SPACE_MAXADDR,          /* highaddr */
2114                     NULL, NULL,                 /* filter, filterarg */
2115                     SK_TX_RING_SZ,              /* maxsize */
2116                     1,                          /* nsegments */
2117                     SK_TX_RING_SZ,              /* maxsegsize */
2118                     0,                          /* flags */
2119                     NULL, NULL,                 /* lockfunc, lockarg */
2120                     &sc_if->sk_cdata.sk_tx_ring_tag);
2121         if (error != 0) {
2122                 device_printf(sc_if->sk_if_dev,
2123                     "failed to allocate Tx ring DMA tag\n");
2124                 goto fail;
2125         }
2126
2127         /* create tag for Rx ring */
2128         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2129                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
2130                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
2131                     BUS_SPACE_MAXADDR,          /* highaddr */
2132                     NULL, NULL,                 /* filter, filterarg */
2133                     SK_RX_RING_SZ,              /* maxsize */
2134                     1,                          /* nsegments */
2135                     SK_RX_RING_SZ,              /* maxsegsize */
2136                     0,                          /* flags */
2137                     NULL, NULL,                 /* lockfunc, lockarg */
2138                     &sc_if->sk_cdata.sk_rx_ring_tag);
2139         if (error != 0) {
2140                 device_printf(sc_if->sk_if_dev,
2141                     "failed to allocate Rx ring DMA tag\n");
2142                 goto fail;
2143         }
2144
2145         /* create tag for jumbo Rx ring */
2146         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2147                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
2148                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
2149                     BUS_SPACE_MAXADDR,          /* highaddr */
2150                     NULL, NULL,                 /* filter, filterarg */
2151                     SK_JUMBO_RX_RING_SZ,        /* maxsize */
2152                     1,                          /* nsegments */
2153                     SK_JUMBO_RX_RING_SZ,        /* maxsegsize */
2154                     0,                          /* flags */
2155                     NULL, NULL,                 /* lockfunc, lockarg */
2156                     &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2157         if (error != 0) {
2158                 device_printf(sc_if->sk_if_dev,
2159                     "failed to allocate jumbo Rx ring DMA tag\n");
2160                 goto fail;
2161         }
2162
2163         /* create tag for jumbo buffer blocks */
2164         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2165                     PAGE_SIZE, 0,               /* algnmnt, boundary */
2166                     BUS_SPACE_MAXADDR,          /* lowaddr */
2167                     BUS_SPACE_MAXADDR,          /* highaddr */
2168                     NULL, NULL,                 /* filter, filterarg */
2169                     SK_JMEM,                    /* maxsize */
2170                     1,                          /* nsegments */
2171                     SK_JMEM,                    /* maxsegsize */
2172                     0,                          /* flags */
2173                     NULL, NULL,                 /* lockfunc, lockarg */
2174                     &sc_if->sk_cdata.sk_jumbo_tag);
2175         if (error != 0) {
2176                 device_printf(sc_if->sk_if_dev,
2177                     "failed to allocate jumbo Rx buffer block DMA tag\n");
2178                 goto fail;
2179         }
2180
2181         /* create tag for Tx buffers */
2182         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2183                     1, 0,                       /* algnmnt, boundary */
2184                     BUS_SPACE_MAXADDR,          /* lowaddr */
2185                     BUS_SPACE_MAXADDR,          /* highaddr */
2186                     NULL, NULL,                 /* filter, filterarg */
2187                     MCLBYTES * SK_MAXTXSEGS,    /* maxsize */
2188                     SK_MAXTXSEGS,               /* nsegments */
2189                     MCLBYTES,                   /* maxsegsize */
2190                     0,                          /* flags */
2191                     NULL, NULL,                 /* lockfunc, lockarg */
2192                     &sc_if->sk_cdata.sk_tx_tag);
2193         if (error != 0) {
2194                 device_printf(sc_if->sk_if_dev,
2195                     "failed to allocate Tx DMA tag\n");
2196                 goto fail;
2197         }
2198
2199         /* create tag for Rx buffers */
2200         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2201                     1, 0,                       /* algnmnt, boundary */
2202                     BUS_SPACE_MAXADDR,          /* lowaddr */
2203                     BUS_SPACE_MAXADDR,          /* highaddr */
2204                     NULL, NULL,                 /* filter, filterarg */
2205                     MCLBYTES,                   /* maxsize */
2206                     1,                          /* nsegments */
2207                     MCLBYTES,                   /* maxsegsize */
2208                     0,                          /* flags */
2209                     NULL, NULL,                 /* lockfunc, lockarg */
2210                     &sc_if->sk_cdata.sk_rx_tag);
2211         if (error != 0) {
2212                 device_printf(sc_if->sk_if_dev,
2213                     "failed to allocate Rx DMA tag\n");
2214                 goto fail;
2215         }
2216
2217         /* create tag for jumbo Rx buffers */
2218         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2219                     PAGE_SIZE, 0,               /* algnmnt, boundary */
2220                     BUS_SPACE_MAXADDR,          /* lowaddr */
2221                     BUS_SPACE_MAXADDR,          /* highaddr */
2222                     NULL, NULL,                 /* filter, filterarg */
2223                     MCLBYTES * SK_MAXRXSEGS,    /* maxsize */
2224                     SK_MAXRXSEGS,               /* nsegments */
2225                     SK_JLEN,                    /* maxsegsize */
2226                     0,                          /* flags */
2227                     NULL, NULL,                 /* lockfunc, lockarg */
2228                     &sc_if->sk_cdata.sk_jumbo_rx_tag);
2229         if (error != 0) {
2230                 device_printf(sc_if->sk_if_dev,
2231                     "failed to allocate jumbo Rx DMA tag\n");
2232                 goto fail;
2233         }
2234
2235         /* allocate DMA'able memory and load the DMA map for Tx ring */
2236         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2237             (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2238             &sc_if->sk_cdata.sk_tx_ring_map);
2239         if (error != 0) {
2240                 device_printf(sc_if->sk_if_dev,
2241                     "failed to allocate DMA'able memory for Tx ring\n");
2242                 goto fail;
2243         }
2244
2245         ctx.sk_busaddr = 0;
2246         error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2247             sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2248             SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2249         if (error != 0) {
2250                 device_printf(sc_if->sk_if_dev,
2251                     "failed to load DMA'able memory for Tx ring\n");
2252                 goto fail;
2253         }
2254         sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2255
2256         /* allocate DMA'able memory and load the DMA map for Rx ring */
2257         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2258             (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2259             &sc_if->sk_cdata.sk_rx_ring_map);
2260         if (error != 0) {
2261                 device_printf(sc_if->sk_if_dev,
2262                     "failed to allocate DMA'able memory for Rx ring\n");
2263                 goto fail;
2264         }
2265
2266         ctx.sk_busaddr = 0;
2267         error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2268             sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2269             SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2270         if (error != 0) {
2271                 device_printf(sc_if->sk_if_dev,
2272                     "failed to load DMA'able memory for Rx ring\n");
2273                 goto fail;
2274         }
2275         sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2276
2277         /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2278         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2279             (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring,
2280             BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2281         if (error != 0) {
2282                 device_printf(sc_if->sk_if_dev,
2283                     "failed to allocate DMA'able memory for jumbo Rx ring\n");
2284                 goto fail;
2285         }
2286
2287         ctx.sk_busaddr = 0;
2288         error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2289             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2290             sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2291             &ctx, BUS_DMA_NOWAIT);
2292         if (error != 0) {
2293                 device_printf(sc_if->sk_if_dev,
2294                     "failed to load DMA'able memory for jumbo Rx ring\n");
2295                 goto fail;
2296         }
2297         sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2298
2299         /* create DMA maps for Tx buffers */
2300         for (i = 0; i < SK_TX_RING_CNT; i++) {
2301                 txd = &sc_if->sk_cdata.sk_txdesc[i];
2302                 txd->tx_m = NULL;
2303                 txd->tx_dmamap = 0;
2304                 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2305                     &txd->tx_dmamap);
2306                 if (error != 0) {
2307                         device_printf(sc_if->sk_if_dev,
2308                             "failed to create Tx dmamap\n");
2309                         goto fail;
2310                 }
2311         }
2312         /* create DMA maps for Rx buffers */
2313         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2314             &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2315                 device_printf(sc_if->sk_if_dev,
2316                     "failed to create spare Rx dmamap\n");
2317                 goto fail;
2318         }
2319         for (i = 0; i < SK_RX_RING_CNT; i++) {
2320                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2321                 rxd->rx_m = NULL;
2322                 rxd->rx_dmamap = 0;
2323                 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2324                     &rxd->rx_dmamap);
2325                 if (error != 0) {
2326                         device_printf(sc_if->sk_if_dev,
2327                             "failed to create Rx dmamap\n");
2328                         goto fail;
2329                 }
2330         }
2331         /* create DMA maps for jumbo Rx buffers */
2332         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2333             &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2334                 device_printf(sc_if->sk_if_dev,
2335                     "failed to create spare jumbo Rx dmamap\n");
2336                 goto fail;
2337         }
2338         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2339                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2340                 jrxd->rx_m = NULL;
2341                 jrxd->rx_dmamap = 0;
2342                 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2343                     &jrxd->rx_dmamap);
2344                 if (error != 0) {
2345                         device_printf(sc_if->sk_if_dev,
2346                             "failed to create jumbo Rx dmamap\n");
2347                         goto fail;
2348                 }
2349         }
2350
2351         /* allocate DMA'able memory and load the DMA map for jumbo buf */
2352         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_tag,
2353             (void **)&sc_if->sk_rdata.sk_jumbo_buf,
2354             BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_map);
2355         if (error != 0) {
2356                 device_printf(sc_if->sk_if_dev,
2357                     "failed to allocate DMA'able memory for jumbo buf\n");
2358                 goto fail;
2359         }
2360
2361         ctx.sk_busaddr = 0;
2362         error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_tag,
2363             sc_if->sk_cdata.sk_jumbo_map,
2364             sc_if->sk_rdata.sk_jumbo_buf, SK_JMEM, sk_dmamap_cb,
2365             &ctx, BUS_DMA_NOWAIT);
2366         if (error != 0) {
2367                 device_printf(sc_if->sk_if_dev,
2368                     "failed to load DMA'able memory for jumbobuf\n");
2369                 goto fail;
2370         }
2371         sc_if->sk_rdata.sk_jumbo_buf_paddr = ctx.sk_busaddr;
2372
2373         /*
2374          * Now divide it up into 9K pieces and save the addresses
2375          * in an array.
2376          */
2377         ptr = sc_if->sk_rdata.sk_jumbo_buf;
2378         for (i = 0; i < SK_JSLOTS; i++) {
2379                 sc_if->sk_cdata.sk_jslots[i] = ptr;
2380                 ptr += SK_JLEN;
2381                 entry = malloc(sizeof(struct sk_jpool_entry),
2382                     M_DEVBUF, M_NOWAIT);
2383                 if (entry == NULL) {
2384                         device_printf(sc_if->sk_if_dev,
2385                             "no memory for jumbo buffers!\n");
2386                         error = ENOMEM;
2387                         goto fail;
2388                 }
2389                 entry->slot = i;
2390                 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry,
2391                     jpool_entries);
2392         }
2393
2394 fail:
2395         return (error);
2396 }
2397
2398 static void
2399 sk_dma_free(sc_if)
2400         struct sk_if_softc      *sc_if;
2401 {
2402         struct sk_txdesc        *txd;
2403         struct sk_rxdesc        *rxd;
2404         struct sk_rxdesc        *jrxd;
2405         struct sk_jpool_entry   *entry;
2406         int                     i;
2407
2408         SK_JLIST_LOCK(sc_if);
2409         while ((entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead))) {
2410                 device_printf(sc_if->sk_if_dev,
2411                     "asked to free buffer that is in use!\n");
2412                 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries);
2413                 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry,
2414                     jpool_entries);
2415         }
2416
2417         while (!SLIST_EMPTY(&sc_if->sk_jfree_listhead)) {
2418                 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
2419                 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
2420                 free(entry, M_DEVBUF);
2421         }
2422         SK_JLIST_UNLOCK(sc_if);
2423
2424         /* destroy jumbo buffer block */
2425         if (sc_if->sk_cdata.sk_jumbo_map)
2426                 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_tag,
2427                     sc_if->sk_cdata.sk_jumbo_map);
2428
2429         if (sc_if->sk_rdata.sk_jumbo_buf) {
2430                 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_tag,
2431                     sc_if->sk_rdata.sk_jumbo_buf,
2432                     sc_if->sk_cdata.sk_jumbo_map);
2433                 sc_if->sk_rdata.sk_jumbo_buf = NULL;
2434                 sc_if->sk_cdata.sk_jumbo_map = 0;
2435         }
2436
2437         /* Tx ring */
2438         if (sc_if->sk_cdata.sk_tx_ring_tag) {
2439                 if (sc_if->sk_cdata.sk_tx_ring_map)
2440                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2441                             sc_if->sk_cdata.sk_tx_ring_map);
2442                 if (sc_if->sk_cdata.sk_tx_ring_map &&
2443                     sc_if->sk_rdata.sk_tx_ring)
2444                         bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2445                             sc_if->sk_rdata.sk_tx_ring,
2446                             sc_if->sk_cdata.sk_tx_ring_map);
2447                 sc_if->sk_rdata.sk_tx_ring = NULL;
2448                 sc_if->sk_cdata.sk_tx_ring_map = 0;
2449                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2450                 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2451         }
2452         /* Rx ring */
2453         if (sc_if->sk_cdata.sk_rx_ring_tag) {
2454                 if (sc_if->sk_cdata.sk_rx_ring_map)
2455                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2456                             sc_if->sk_cdata.sk_rx_ring_map);
2457                 if (sc_if->sk_cdata.sk_rx_ring_map &&
2458                     sc_if->sk_rdata.sk_rx_ring)
2459                         bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2460                             sc_if->sk_rdata.sk_rx_ring,
2461                             sc_if->sk_cdata.sk_rx_ring_map);
2462                 sc_if->sk_rdata.sk_rx_ring = NULL;
2463                 sc_if->sk_cdata.sk_rx_ring_map = 0;
2464                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2465                 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2466         }
2467         /* jumbo Rx ring */
2468         if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2469                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map)
2470                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2471                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2472                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map &&
2473                     sc_if->sk_rdata.sk_jumbo_rx_ring)
2474                         bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2475                             sc_if->sk_rdata.sk_jumbo_rx_ring,
2476                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2477                 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2478                 sc_if->sk_cdata.sk_jumbo_rx_ring_map = 0;
2479                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2480                 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2481         }
2482         /* Tx buffers */
2483         if (sc_if->sk_cdata.sk_tx_tag) {
2484                 for (i = 0; i < SK_TX_RING_CNT; i++) {
2485                         txd = &sc_if->sk_cdata.sk_txdesc[i];
2486                         if (txd->tx_dmamap) {
2487                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2488                                     txd->tx_dmamap);
2489                                 txd->tx_dmamap = 0;
2490                         }
2491                 }
2492                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2493                 sc_if->sk_cdata.sk_tx_tag = NULL;
2494         }
2495         /* Rx buffers */
2496         if (sc_if->sk_cdata.sk_rx_tag) {
2497                 for (i = 0; i < SK_RX_RING_CNT; i++) {
2498                         rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2499                         if (rxd->rx_dmamap) {
2500                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2501                                     rxd->rx_dmamap);
2502                                 rxd->rx_dmamap = 0;
2503                         }
2504                 }
2505                 if (sc_if->sk_cdata.sk_rx_sparemap) {
2506                         bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2507                             sc_if->sk_cdata.sk_rx_sparemap);
2508                         sc_if->sk_cdata.sk_rx_sparemap = 0;
2509                 }
2510                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2511                 sc_if->sk_cdata.sk_rx_tag = NULL;
2512         }
2513         /* jumbo Rx buffers */
2514         if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2515                 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2516                         jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2517                         if (jrxd->rx_dmamap) {
2518                                 bus_dmamap_destroy(
2519                                     sc_if->sk_cdata.sk_jumbo_rx_tag,
2520                                     jrxd->rx_dmamap);
2521                                 jrxd->rx_dmamap = 0;
2522                         }
2523                 }
2524                 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2525                         bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2526                             sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2527                         sc_if->sk_cdata.sk_jumbo_rx_sparemap = 0;
2528                 }
2529                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2530                 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2531         }
2532
2533         if (sc_if->sk_cdata.sk_parent_tag) {
2534                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2535                 sc_if->sk_cdata.sk_parent_tag = NULL;
2536         }
2537         mtx_destroy(&sc_if->sk_jlist_mtx);
2538 }
2539
2540 /*
2541  * Allocate a jumbo buffer.
2542  */
2543 static void *
2544 sk_jalloc(sc_if)
2545         struct sk_if_softc              *sc_if;
2546 {
2547         struct sk_jpool_entry   *entry;
2548
2549         SK_JLIST_LOCK(sc_if);
2550
2551         entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
2552
2553         if (entry == NULL) {
2554                 SK_JLIST_UNLOCK(sc_if);
2555                 return (NULL);
2556         }
2557
2558         SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
2559         SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
2560
2561         SK_JLIST_UNLOCK(sc_if);
2562
2563         return (sc_if->sk_cdata.sk_jslots[entry->slot]);
2564 }
2565
2566 /*
2567  * Release a jumbo buffer.
2568  */
2569 static void
2570 sk_jfree(buf, args)
2571         void                    *buf;
2572         void                    *args;
2573 {
2574         struct sk_if_softc      *sc_if;
2575         struct sk_jpool_entry   *entry;
2576         int                     i;
2577
2578         /* Extract the softc struct pointer. */
2579         sc_if = (struct sk_if_softc *)args;
2580         KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__));
2581
2582         SK_JLIST_LOCK(sc_if);
2583         /* calculate the slot this buffer belongs to */
2584         i = ((vm_offset_t)buf
2585              - (vm_offset_t)sc_if->sk_rdata.sk_jumbo_buf) / SK_JLEN;
2586         KASSERT(i >= 0 && i < SK_JSLOTS,
2587             ("%s: asked to free buffer that we don't manage!", __func__));
2588
2589         entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
2590         KASSERT(entry != NULL, ("%s: buffer not in use!", __func__));
2591         entry->slot = i;
2592         SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries);
2593         SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries);
2594         if (SLIST_EMPTY(&sc_if->sk_jinuse_listhead))
2595                 wakeup(sc_if);
2596
2597         SK_JLIST_UNLOCK(sc_if);
2598 }
2599
2600 static void
2601 sk_txcksum(ifp, m, f)
2602         struct ifnet            *ifp;
2603         struct mbuf             *m;
2604         struct sk_tx_desc       *f;
2605 {
2606         struct ip               *ip;
2607         u_int16_t               offset;
2608         u_int8_t                *p;
2609
2610         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2611         for(; m && m->m_len == 0; m = m->m_next)
2612                 ;
2613         if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2614                 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2615                 /* checksum may be corrupted */
2616                 goto sendit;
2617         }
2618         if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2619                 if (m->m_len != ETHER_HDR_LEN) {
2620                         if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2621                             __func__);
2622                         /* checksum may be corrupted */
2623                         goto sendit;
2624                 }
2625                 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2626                         ;
2627                 if (m == NULL) {
2628                         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2629                         /* checksum may be corrupted */
2630                         goto sendit;
2631                 }
2632                 ip = mtod(m, struct ip *);
2633         } else {
2634                 p = mtod(m, u_int8_t *);
2635                 p += ETHER_HDR_LEN;
2636                 ip = (struct ip *)p;
2637         }
2638         offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2639
2640 sendit:
2641         f->sk_csum_startval = 0;
2642         f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2643             (offset << 16));
2644 }
2645
2646 static int
2647 sk_encap(sc_if, m_head)
2648         struct sk_if_softc      *sc_if;
2649         struct mbuf             **m_head;
2650 {
2651         struct sk_txdesc        *txd;
2652         struct sk_tx_desc       *f = NULL;
2653         struct mbuf             *m;
2654         bus_dma_segment_t       txsegs[SK_MAXTXSEGS];
2655         u_int32_t               cflags, frag, si, sk_ctl;
2656         int                     error, i, nseg;
2657
2658         SK_IF_LOCK_ASSERT(sc_if);
2659
2660         if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2661                 return (ENOBUFS);
2662
2663         error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2664             txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2665         if (error == EFBIG) {
2666                 m = m_defrag(*m_head, M_DONTWAIT);
2667                 if (m == NULL) {
2668                         m_freem(*m_head);
2669                         *m_head = NULL;
2670                         return (ENOMEM);
2671                 }
2672                 *m_head = m;
2673                 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2674                     txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2675                 if (error != 0) {
2676                         m_freem(*m_head);
2677                         *m_head = NULL;
2678                         return (error);
2679                 }
2680         } else if (error != 0)
2681                 return (error);
2682         if (nseg == 0) {
2683                 m_freem(*m_head);
2684                 *m_head = NULL;
2685                 return (EIO);
2686         }
2687         if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2688                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2689                 return (ENOBUFS);
2690         }
2691
2692         m = *m_head;
2693         if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2694                 cflags = SK_OPCODE_CSUM;
2695         else
2696                 cflags = SK_OPCODE_DEFAULT;
2697         si = frag = sc_if->sk_cdata.sk_tx_prod;
2698         for (i = 0; i < nseg; i++) {
2699                 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2700                 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2701                 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2702                 sk_ctl = txsegs[i].ds_len | cflags;
2703                 if (i == 0) {
2704                         if (cflags == SK_OPCODE_CSUM)
2705                                 sk_txcksum(sc_if->sk_ifp, m, f);
2706                         sk_ctl |= SK_TXCTL_FIRSTFRAG;
2707                 } else
2708                         sk_ctl |= SK_TXCTL_OWN;
2709                 f->sk_ctl = htole32(sk_ctl);
2710                 sc_if->sk_cdata.sk_tx_cnt++;
2711                 SK_INC(frag, SK_TX_RING_CNT);
2712         }
2713         sc_if->sk_cdata.sk_tx_prod = frag;
2714
2715         /* set EOF on the last desciptor */
2716         frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2717         f = &sc_if->sk_rdata.sk_tx_ring[frag];
2718         f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2719
2720         /* turn the first descriptor ownership to NIC */
2721         f = &sc_if->sk_rdata.sk_tx_ring[si];
2722         f->sk_ctl |= htole32(SK_TXCTL_OWN);
2723
2724         STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2725         STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2726         txd->tx_m = m;
2727
2728         /* sync descriptors */
2729         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2730             BUS_DMASYNC_PREWRITE);
2731         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2732             sc_if->sk_cdata.sk_tx_ring_map,
2733             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2734
2735         return (0);
2736 }
2737
2738 static void
2739 sk_start(ifp)
2740         struct ifnet            *ifp;
2741 {
2742         struct sk_if_softc *sc_if;
2743
2744         sc_if = ifp->if_softc;
2745
2746         SK_IF_LOCK(sc_if);
2747         sk_start_locked(ifp);
2748         SK_IF_UNLOCK(sc_if);
2749
2750         return;
2751 }
2752
2753 static void
2754 sk_start_locked(ifp)
2755         struct ifnet            *ifp;
2756 {
2757         struct sk_softc         *sc;
2758         struct sk_if_softc      *sc_if;
2759         struct mbuf             *m_head;
2760         int                     enq;
2761
2762         sc_if = ifp->if_softc;
2763         sc = sc_if->sk_softc;
2764
2765         SK_IF_LOCK_ASSERT(sc_if);
2766
2767         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2768             sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2769                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2770                 if (m_head == NULL)
2771                         break;
2772
2773                 /*
2774                  * Pack the data into the transmit ring. If we
2775                  * don't have room, set the OACTIVE flag and wait
2776                  * for the NIC to drain the ring.
2777                  */
2778                 if (sk_encap(sc_if, &m_head)) {
2779                         if (m_head == NULL)
2780                                 break;
2781                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2782                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2783                         break;
2784                 }
2785
2786                 enq++;
2787                 /*
2788                  * If there's a BPF listener, bounce a copy of this frame
2789                  * to him.
2790                  */
2791                 BPF_MTAP(ifp, m_head);
2792         }
2793
2794         if (enq > 0) {
2795                 /* Transmit */
2796                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2797
2798                 /* Set a timeout in case the chip goes out to lunch. */
2799                 sc_if->sk_watchdog_timer = 5;
2800         }
2801 }
2802
2803
2804 static void
2805 sk_watchdog(arg)
2806         void                    *arg;
2807 {
2808         struct sk_if_softc      *sc_if;
2809         struct ifnet            *ifp;
2810
2811         ifp = arg;
2812         sc_if = ifp->if_softc;
2813
2814         SK_IF_LOCK_ASSERT(sc_if);
2815
2816         if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2817                 goto done;
2818
2819         /*
2820          * Reclaim first as there is a possibility of losing Tx completion
2821          * interrupts.
2822          */
2823         sk_txeof(sc_if);
2824         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2825                 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2826                 ifp->if_oerrors++;
2827                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2828                 sk_init_locked(sc_if);
2829         }
2830
2831 done:
2832         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2833
2834         return;
2835 }
2836
2837 static void
2838 skc_shutdown(dev)
2839         device_t                dev;
2840 {
2841         struct sk_softc         *sc;
2842
2843         sc = device_get_softc(dev);
2844         SK_LOCK(sc);
2845
2846         /* Turn off the 'driver is loaded' LED. */
2847         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2848
2849         /*
2850          * Reset the GEnesis controller. Doing this should also
2851          * assert the resets on the attached XMAC(s).
2852          */
2853         sk_reset(sc);
2854         SK_UNLOCK(sc);
2855
2856         return;
2857 }
2858
2859 static int
2860 skc_suspend(dev)
2861         device_t                dev;
2862 {
2863         struct sk_softc         *sc;
2864         struct sk_if_softc      *sc_if0, *sc_if1;
2865         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2866
2867         sc = device_get_softc(dev);
2868
2869         SK_LOCK(sc);
2870
2871         sc_if0 = sc->sk_if[SK_PORT_A];
2872         sc_if1 = sc->sk_if[SK_PORT_B];
2873         if (sc_if0 != NULL)
2874                 ifp0 = sc_if0->sk_ifp;
2875         if (sc_if1 != NULL)
2876                 ifp1 = sc_if1->sk_ifp;
2877         if (ifp0 != NULL)
2878                 sk_stop(sc_if0);
2879         if (ifp1 != NULL)
2880                 sk_stop(sc_if1);
2881         sc->sk_suspended = 1;
2882
2883         SK_UNLOCK(sc);
2884
2885         return (0);
2886 }
2887
2888 static int
2889 skc_resume(dev)
2890         device_t                dev;
2891 {
2892         struct sk_softc         *sc;
2893         struct sk_if_softc      *sc_if0, *sc_if1;
2894         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2895
2896         sc = device_get_softc(dev);
2897
2898         SK_LOCK(sc);
2899
2900         sc_if0 = sc->sk_if[SK_PORT_A];
2901         sc_if1 = sc->sk_if[SK_PORT_B];
2902         if (sc_if0 != NULL)
2903                 ifp0 = sc_if0->sk_ifp;
2904         if (sc_if1 != NULL)
2905                 ifp1 = sc_if1->sk_ifp;
2906         if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2907                 sk_init_locked(sc_if0);
2908         if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2909                 sk_init_locked(sc_if1);
2910         sc->sk_suspended = 0;
2911
2912         SK_UNLOCK(sc);
2913
2914         return (0);
2915 }
2916
2917 /*
2918  * According to the data sheet from SK-NET GENESIS the hardware can compute
2919  * two Rx checksums at the same time(Each checksum start position is
2920  * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2921  * does not work at least on my Yukon hardware. I tried every possible ways
2922  * to get correct checksum value but couldn't get correct one. So TCP/UDP
2923  * checksum offload was disabled at the moment and only IP checksum offload
2924  * was enabled.
2925  * As nomral IP header size is 20 bytes I can't expect it would give an
2926  * increase in throughput. However it seems it doesn't hurt performance in
2927  * my testing. If there is a more detailed information for checksum secret
2928  * of the hardware in question please contact yongari@FreeBSD.org to add
2929  * TCP/UDP checksum offload support.
2930  */
2931 static __inline void
2932 sk_rxcksum(ifp, m, csum)
2933         struct ifnet            *ifp;
2934         struct mbuf             *m;
2935         u_int32_t               csum;
2936 {
2937         struct ether_header     *eh;
2938         struct ip               *ip;
2939         int32_t                 hlen, len, pktlen;
2940         u_int16_t               csum1, csum2, ipcsum;
2941
2942         pktlen = m->m_pkthdr.len;
2943         if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2944                 return;
2945         eh = mtod(m, struct ether_header *);
2946         if (eh->ether_type != htons(ETHERTYPE_IP))
2947                 return;
2948         ip = (struct ip *)(eh + 1);
2949         if (ip->ip_v != IPVERSION)
2950                 return;
2951         hlen = ip->ip_hl << 2;
2952         pktlen -= sizeof(struct ether_header);
2953         if (hlen < sizeof(struct ip))
2954                 return;
2955         if (ntohs(ip->ip_len) < hlen)
2956                 return;
2957         if (ntohs(ip->ip_len) != pktlen)
2958                 return;
2959
2960         csum1 = htons(csum & 0xffff);
2961         csum2 = htons((csum >> 16) & 0xffff);
2962         ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2963         /* checksum fixup for IP options */
2964         len = hlen - sizeof(struct ip);
2965         if (len > 0) {
2966                 /*
2967                  * If the second checksum value is correct we can compute IP
2968                  * checksum with simple math. Unfortunately the second checksum
2969                  * value is wrong so we can't verify the checksum from the
2970                  * value(It seems there is some magic here to get correct
2971                  * value). If the second checksum value is correct it also
2972                  * means we can get TCP/UDP checksum) here. However, it still
2973                  * needs pseudo header checksum calculation due to hardware
2974                  * limitations.
2975                  */
2976                 return;
2977         }
2978         m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2979         if (ipcsum == 0xffff)
2980                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2981 }
2982
2983 static __inline int
2984 sk_rxvalid(sc, stat, len)
2985         struct sk_softc         *sc;
2986         u_int32_t               stat, len;
2987 {
2988
2989         if (sc->sk_type == SK_GENESIS) {
2990                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2991                     XM_RXSTAT_BYTES(stat) != len)
2992                         return (0);
2993         } else {
2994                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2995                     YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2996                     YU_RXSTAT_JABBER)) != 0 ||
2997                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2998                     YU_RXSTAT_BYTES(stat) != len)
2999                         return (0);
3000         }
3001
3002         return (1);
3003 }
3004
3005 static void
3006 sk_rxeof(sc_if)
3007         struct sk_if_softc      *sc_if;
3008 {
3009         struct sk_softc         *sc;
3010         struct mbuf             *m;
3011         struct ifnet            *ifp;
3012         struct sk_rx_desc       *cur_rx;
3013         struct sk_rxdesc        *rxd;
3014         int                     cons, prog;
3015         u_int32_t               csum, rxstat, sk_ctl;
3016
3017         sc = sc_if->sk_softc;
3018         ifp = sc_if->sk_ifp;
3019
3020         SK_IF_LOCK_ASSERT(sc_if);
3021
3022         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
3023             sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
3024
3025         prog = 0;
3026         for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
3027             prog++, SK_INC(cons, SK_RX_RING_CNT)) {
3028                 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
3029                 sk_ctl = le32toh(cur_rx->sk_ctl);
3030                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
3031                         break;
3032                 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
3033                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
3034
3035                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
3036                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
3037                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
3038                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
3039                     SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
3040                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
3041                         ifp->if_ierrors++;
3042                         sk_discard_rxbuf(sc_if, cons);
3043                         continue;
3044                 }
3045
3046                 m = rxd->rx_m;
3047                 csum = le32toh(cur_rx->sk_csum);
3048                 if (sk_newbuf(sc_if, cons) != 0) {
3049                         ifp->if_iqdrops++;
3050                         /* reuse old buffer */
3051                         sk_discard_rxbuf(sc_if, cons);
3052                         continue;
3053                 }
3054                 m->m_pkthdr.rcvif = ifp;
3055                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
3056                 ifp->if_ipackets++;
3057                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3058                         sk_rxcksum(ifp, m, csum);
3059                 SK_IF_UNLOCK(sc_if);
3060                 (*ifp->if_input)(ifp, m);
3061                 SK_IF_LOCK(sc_if);
3062         }
3063
3064         if (prog > 0) {
3065                 sc_if->sk_cdata.sk_rx_cons = cons;
3066                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
3067                     sc_if->sk_cdata.sk_rx_ring_map,
3068                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3069         }
3070 }
3071
3072 static void
3073 sk_jumbo_rxeof(sc_if)
3074         struct sk_if_softc      *sc_if;
3075 {
3076         struct sk_softc         *sc;
3077         struct mbuf             *m;
3078         struct ifnet            *ifp;
3079         struct sk_rx_desc       *cur_rx;
3080         struct sk_rxdesc        *jrxd;
3081         int                     cons, prog;
3082         u_int32_t               csum, rxstat, sk_ctl;
3083
3084         sc = sc_if->sk_softc;
3085         ifp = sc_if->sk_ifp;
3086
3087         SK_IF_LOCK_ASSERT(sc_if);
3088
3089         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
3090             sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
3091
3092         prog = 0;
3093         for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
3094             prog < SK_JUMBO_RX_RING_CNT;
3095             prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
3096                 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
3097                 sk_ctl = le32toh(cur_rx->sk_ctl);
3098                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
3099                         break;
3100                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
3101                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
3102
3103                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
3104                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
3105                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
3106                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
3107                     SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
3108                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
3109                         ifp->if_ierrors++;
3110                         sk_discard_jumbo_rxbuf(sc_if, cons);
3111                         continue;
3112                 }
3113
3114                 m = jrxd->rx_m;
3115                 csum = le32toh(cur_rx->sk_csum);
3116                 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
3117                         ifp->if_iqdrops++;
3118                         /* reuse old buffer */
3119                         sk_discard_jumbo_rxbuf(sc_if, cons);
3120                         continue;
3121                 }
3122                 m->m_pkthdr.rcvif = ifp;
3123                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
3124                 ifp->if_ipackets++;
3125                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3126                         sk_rxcksum(ifp, m, csum);
3127                 SK_IF_UNLOCK(sc_if);
3128                 (*ifp->if_input)(ifp, m);
3129                 SK_IF_LOCK(sc_if);
3130         }
3131
3132         if (prog > 0) {
3133                 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
3134                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
3135                     sc_if->sk_cdata.sk_jumbo_rx_ring_map,
3136                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3137         }
3138 }
3139
3140 static void
3141 sk_txeof(sc_if)
3142         struct sk_if_softc      *sc_if;
3143 {
3144         struct sk_softc         *sc;
3145         struct sk_txdesc        *txd;
3146         struct sk_tx_desc       *cur_tx;
3147         struct ifnet            *ifp;
3148         u_int32_t               idx, sk_ctl;
3149
3150         sc = sc_if->sk_softc;
3151         ifp = sc_if->sk_ifp;
3152
3153         txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
3154         if (txd == NULL)
3155                 return;
3156         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
3157             sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
3158         /*
3159          * Go through our tx ring and free mbufs for those
3160          * frames that have been sent.
3161          */
3162         for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
3163                 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
3164                         break;
3165                 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
3166                 sk_ctl = le32toh(cur_tx->sk_ctl);
3167                 if (sk_ctl & SK_TXCTL_OWN)
3168                         break;
3169                 sc_if->sk_cdata.sk_tx_cnt--;
3170                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3171                 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
3172                         continue;
3173                 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
3174                     BUS_DMASYNC_POSTWRITE);
3175                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
3176
3177                 ifp->if_opackets++;
3178                 m_freem(txd->tx_m);
3179                 txd->tx_m = NULL;
3180                 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
3181                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
3182                 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
3183         }
3184         sc_if->sk_cdata.sk_tx_cons = idx;
3185         sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
3186
3187         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
3188             sc_if->sk_cdata.sk_tx_ring_map,
3189             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3190 }
3191
3192 static void
3193 sk_tick(xsc_if)
3194         void                    *xsc_if;
3195 {
3196         struct sk_if_softc      *sc_if;
3197         struct mii_data         *mii;
3198         struct ifnet            *ifp;
3199         int                     i;
3200
3201         sc_if = xsc_if;
3202         ifp = sc_if->sk_ifp;
3203         mii = device_get_softc(sc_if->sk_miibus);
3204
3205         if (!(ifp->if_flags & IFF_UP))
3206                 return;
3207
3208         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3209                 sk_intr_bcom(sc_if);
3210                 return;
3211         }
3212
3213         /*
3214          * According to SysKonnect, the correct way to verify that
3215          * the link has come back up is to poll bit 0 of the GPIO
3216          * register three times. This pin has the signal from the
3217          * link_sync pin connected to it; if we read the same link
3218          * state 3 times in a row, we know the link is up.
3219          */
3220         for (i = 0; i < 3; i++) {
3221                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
3222                         break;
3223         }
3224
3225         if (i != 3) {
3226                 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3227                 return;
3228         }
3229
3230         /* Turn the GP0 interrupt back on. */
3231         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3232         SK_XM_READ_2(sc_if, XM_ISR);
3233         mii_tick(mii);
3234         callout_stop(&sc_if->sk_tick_ch);
3235 }
3236
3237 static void
3238 sk_yukon_tick(xsc_if)
3239         void                    *xsc_if;
3240 {
3241         struct sk_if_softc      *sc_if;
3242         struct mii_data         *mii;
3243
3244         sc_if = xsc_if;
3245         mii = device_get_softc(sc_if->sk_miibus);
3246
3247         mii_tick(mii);
3248         callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3249 }
3250
3251 static void
3252 sk_intr_bcom(sc_if)
3253         struct sk_if_softc      *sc_if;
3254 {
3255         struct mii_data         *mii;
3256         struct ifnet            *ifp;
3257         int                     status;
3258         mii = device_get_softc(sc_if->sk_miibus);
3259         ifp = sc_if->sk_ifp;
3260
3261         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3262
3263         /*
3264          * Read the PHY interrupt register to make sure
3265          * we clear any pending interrupts.
3266          */
3267         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
3268
3269         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3270                 sk_init_xmac(sc_if);
3271                 return;
3272         }
3273
3274         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
3275                 int                     lstat;
3276                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
3277                     BRGPHY_MII_AUXSTS);
3278
3279                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
3280                         mii_mediachg(mii);
3281                         /* Turn off the link LED. */
3282                         SK_IF_WRITE_1(sc_if, 0,
3283                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
3284                         sc_if->sk_link = 0;
3285                 } else if (status & BRGPHY_ISR_LNK_CHG) {
3286                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3287                             BRGPHY_MII_IMR, 0xFF00);
3288                         mii_tick(mii);
3289                         sc_if->sk_link = 1;
3290                         /* Turn on the link LED. */
3291                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3292                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
3293                             SK_LINKLED_BLINK_OFF);
3294                 } else {
3295                         mii_tick(mii);
3296                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3297                 }
3298         }
3299
3300         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3301
3302         return;
3303 }
3304
3305 static void
3306 sk_intr_xmac(sc_if)
3307         struct sk_if_softc      *sc_if;
3308 {
3309         struct sk_softc         *sc;
3310         u_int16_t               status;
3311
3312         sc = sc_if->sk_softc;
3313         status = SK_XM_READ_2(sc_if, XM_ISR);
3314
3315         /*
3316          * Link has gone down. Start MII tick timeout to
3317          * watch for link resync.
3318          */
3319         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3320                 if (status & XM_ISR_GP0_SET) {
3321                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3322                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3323                 }
3324
3325                 if (status & XM_ISR_AUTONEG_DONE) {
3326                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3327                 }
3328         }
3329
3330         if (status & XM_IMR_TX_UNDERRUN)
3331                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3332
3333         if (status & XM_IMR_RX_OVERRUN)
3334                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3335
3336         status = SK_XM_READ_2(sc_if, XM_ISR);
3337
3338         return;
3339 }
3340
3341 static void
3342 sk_intr_yukon(sc_if)
3343         struct sk_if_softc      *sc_if;
3344 {
3345         u_int8_t status;
3346
3347         status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3348         /* RX overrun */
3349         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3350                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3351                     SK_RFCTL_RX_FIFO_OVER);
3352         }
3353         /* TX underrun */
3354         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3355                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3356                     SK_TFCTL_TX_FIFO_UNDER);
3357         }
3358 }
3359
3360 static void
3361 sk_intr(xsc)
3362         void                    *xsc;
3363 {
3364         struct sk_softc         *sc = xsc;
3365         struct sk_if_softc      *sc_if0, *sc_if1;
3366         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
3367         u_int32_t               status;
3368
3369         SK_LOCK(sc);
3370
3371         status = CSR_READ_4(sc, SK_ISSR);
3372         if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3373                 goto done_locked;
3374
3375         sc_if0 = sc->sk_if[SK_PORT_A];
3376         sc_if1 = sc->sk_if[SK_PORT_B];
3377
3378         if (sc_if0 != NULL)
3379                 ifp0 = sc_if0->sk_ifp;
3380         if (sc_if1 != NULL)
3381                 ifp1 = sc_if1->sk_ifp;
3382
3383         for (; (status &= sc->sk_intrmask) != 0;) {
3384                 /* Handle receive interrupts first. */
3385                 if (status & SK_ISR_RX1_EOF) {
3386                         if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3387                                 sk_jumbo_rxeof(sc_if0);
3388                         else
3389                                 sk_rxeof(sc_if0);
3390                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3391                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3392                 }
3393                 if (status & SK_ISR_RX2_EOF) {
3394                         if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3395                                 sk_jumbo_rxeof(sc_if1);
3396                         else
3397                                 sk_rxeof(sc_if1);
3398                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3399                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3400                 }
3401
3402                 /* Then transmit interrupts. */
3403                 if (status & SK_ISR_TX1_S_EOF) {
3404                         sk_txeof(sc_if0);
3405                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3406                 }
3407                 if (status & SK_ISR_TX2_S_EOF) {
3408                         sk_txeof(sc_if1);
3409                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3410                 }
3411
3412                 /* Then MAC interrupts. */
3413                 if (status & SK_ISR_MAC1 &&
3414                     ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3415                         if (sc->sk_type == SK_GENESIS)
3416                                 sk_intr_xmac(sc_if0);
3417                         else
3418                                 sk_intr_yukon(sc_if0);
3419                 }
3420
3421                 if (status & SK_ISR_MAC2 &&
3422                     ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3423                         if (sc->sk_type == SK_GENESIS)
3424                                 sk_intr_xmac(sc_if1);
3425                         else
3426                                 sk_intr_yukon(sc_if1);
3427                 }
3428
3429                 if (status & SK_ISR_EXTERNAL_REG) {
3430                         if (ifp0 != NULL &&
3431                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3432                                 sk_intr_bcom(sc_if0);
3433                         if (ifp1 != NULL &&
3434                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3435                                 sk_intr_bcom(sc_if1);
3436                 }
3437                 status = CSR_READ_4(sc, SK_ISSR);
3438         }
3439
3440         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3441
3442         if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3443                 sk_start_locked(ifp0);
3444         if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3445                 sk_start_locked(ifp1);
3446
3447 done_locked:
3448         SK_UNLOCK(sc);
3449 }
3450
3451 static void
3452 sk_init_xmac(sc_if)
3453         struct sk_if_softc      *sc_if;
3454 {
3455         struct sk_softc         *sc;
3456         struct ifnet            *ifp;
3457         u_int16_t               eaddr[(ETHER_ADDR_LEN+1)/2];
3458         struct sk_bcom_hack     bhack[] = {
3459         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3460         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3461         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3462         { 0, 0 } };
3463
3464         SK_IF_LOCK_ASSERT(sc_if);
3465
3466         sc = sc_if->sk_softc;
3467         ifp = sc_if->sk_ifp;
3468
3469         /* Unreset the XMAC. */
3470         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3471         DELAY(1000);
3472
3473         /* Reset the XMAC's internal state. */
3474         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3475
3476         /* Save the XMAC II revision */
3477         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3478
3479         /*
3480          * Perform additional initialization for external PHYs,
3481          * namely for the 1000baseTX cards that use the XMAC's
3482          * GMII mode.
3483          */
3484         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3485                 int                     i = 0;
3486                 u_int32_t               val;
3487
3488                 /* Take PHY out of reset. */
3489                 val = sk_win_read_4(sc, SK_GPIO);
3490                 if (sc_if->sk_port == SK_PORT_A)
3491                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3492                 else
3493                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3494                 sk_win_write_4(sc, SK_GPIO, val);
3495
3496                 /* Enable GMII mode on the XMAC. */
3497                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3498
3499                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3500                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3501                 DELAY(10000);
3502                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3503                     BRGPHY_MII_IMR, 0xFFF0);
3504
3505                 /*
3506                  * Early versions of the BCM5400 apparently have
3507                  * a bug that requires them to have their reserved
3508                  * registers initialized to some magic values. I don't
3509                  * know what the numbers do, I'm just the messenger.
3510                  */
3511                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3512                     == 0x6041) {
3513                         while(bhack[i].reg) {
3514                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3515                                     bhack[i].reg, bhack[i].val);
3516                                 i++;
3517                         }
3518                 }
3519         }
3520
3521         /* Set station address */
3522         bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3523         SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3524         SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3525         SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3526         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3527
3528         if (ifp->if_flags & IFF_BROADCAST) {
3529                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3530         } else {
3531                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3532         }
3533
3534         /* We don't need the FCS appended to the packet. */
3535         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3536
3537         /* We want short frames padded to 60 bytes. */
3538         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3539
3540         /*
3541          * Enable the reception of all error frames. This is is
3542          * a necessary evil due to the design of the XMAC. The
3543          * XMAC's receive FIFO is only 8K in size, however jumbo
3544          * frames can be up to 9000 bytes in length. When bad
3545          * frame filtering is enabled, the XMAC's RX FIFO operates
3546          * in 'store and forward' mode. For this to work, the
3547          * entire frame has to fit into the FIFO, but that means
3548          * that jumbo frames larger than 8192 bytes will be
3549          * truncated. Disabling all bad frame filtering causes
3550          * the RX FIFO to operate in streaming mode, in which
3551          * case the XMAC will start transfering frames out of the
3552          * RX FIFO as soon as the FIFO threshold is reached.
3553          */
3554         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3555                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3556                     XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3557                     XM_MODE_RX_INRANGELEN);
3558                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3559         } else
3560                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3561
3562         /*
3563          * Bump up the transmit threshold. This helps hold off transmit
3564          * underruns when we're blasting traffic from both ports at once.
3565          */
3566         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3567
3568         /* Set promiscuous mode */
3569         sk_setpromisc(sc_if);
3570
3571         /* Set multicast filter */
3572         sk_setmulti(sc_if);
3573
3574         /* Clear and enable interrupts */
3575         SK_XM_READ_2(sc_if, XM_ISR);
3576         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3577                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3578         else
3579                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3580
3581         /* Configure MAC arbiter */
3582         switch(sc_if->sk_xmac_rev) {
3583         case XM_XMAC_REV_B2:
3584                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3585                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3586                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3587                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3588                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3589                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3590                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3591                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3592                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3593                 break;
3594         case XM_XMAC_REV_C1:
3595                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3596                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3597                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3598                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3599                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3600                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3601                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3602                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3603                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3604                 break;
3605         default:
3606                 break;
3607         }
3608         sk_win_write_2(sc, SK_MACARB_CTL,
3609             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3610
3611         sc_if->sk_link = 1;
3612
3613         return;
3614 }
3615
3616 static void
3617 sk_init_yukon(sc_if)
3618         struct sk_if_softc      *sc_if;
3619 {
3620         u_int32_t               phy, v;
3621         u_int16_t               reg;
3622         struct sk_softc         *sc;
3623         struct ifnet            *ifp;
3624         int                     i;
3625
3626         SK_IF_LOCK_ASSERT(sc_if);
3627
3628         sc = sc_if->sk_softc;
3629         ifp = sc_if->sk_ifp;
3630
3631         if (sc->sk_type == SK_YUKON_LITE &&
3632             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3633                 /*
3634                  * Workaround code for COMA mode, set PHY reset.
3635                  * Otherwise it will not correctly take chip out of
3636                  * powerdown (coma)
3637                  */
3638                 v = sk_win_read_4(sc, SK_GPIO);
3639                 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3640                 sk_win_write_4(sc, SK_GPIO, v);
3641         }
3642
3643         /* GMAC and GPHY Reset */
3644         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3645         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3646         DELAY(1000);
3647
3648         if (sc->sk_type == SK_YUKON_LITE &&
3649             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3650                 /*
3651                  * Workaround code for COMA mode, clear PHY reset
3652                  */
3653                 v = sk_win_read_4(sc, SK_GPIO);
3654                 v |= SK_GPIO_DIR9;
3655                 v &= ~SK_GPIO_DAT9;
3656                 sk_win_write_4(sc, SK_GPIO, v);
3657         }
3658
3659         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3660                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3661
3662         if (sc->sk_coppertype)
3663                 phy |= SK_GPHY_COPPER;
3664         else
3665                 phy |= SK_GPHY_FIBER;
3666
3667         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3668         DELAY(1000);
3669         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3670         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3671                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3672
3673         /* unused read of the interrupt source register */
3674         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3675
3676         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3677
3678         /* MIB Counter Clear Mode set */
3679         reg |= YU_PAR_MIB_CLR;
3680         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3681
3682         /* MIB Counter Clear Mode clear */
3683         reg &= ~YU_PAR_MIB_CLR;
3684         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3685
3686         /* receive control reg */
3687         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3688
3689         /* transmit parameter register */
3690         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3691                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3692
3693         /* serial mode register */
3694         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3695         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3696                 reg |= YU_SMR_MFL_JUMBO;
3697         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3698
3699         /* Setup Yukon's address */
3700         for (i = 0; i < 3; i++) {
3701                 /* Write Source Address 1 (unicast filter) */
3702                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3703                               IF_LLADDR(sc_if->sk_ifp)[i * 2] |
3704                               IF_LLADDR(sc_if->sk_ifp)[i * 2 + 1] << 8);
3705         }
3706
3707         for (i = 0; i < 3; i++) {
3708                 reg = sk_win_read_2(sc_if->sk_softc,
3709                                     SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
3710                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
3711         }
3712
3713         /* Set promiscuous mode */
3714         sk_setpromisc(sc_if);
3715
3716         /* Set multicast filter */
3717         sk_setmulti(sc_if);
3718
3719         /* enable interrupt mask for counter overflows */
3720         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3721         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3722         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3723
3724         /* Configure RX MAC FIFO Flush Mask */
3725         v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3726             YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3727             YU_RXSTAT_JABBER;
3728         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3729
3730         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3731         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3732                 v = SK_TFCTL_OPERATION_ON;
3733         else
3734                 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3735         /* Configure RX MAC FIFO */
3736         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3737         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3738
3739         /* Increase flush threshould to 64 bytes */
3740         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3741             SK_RFCTL_FIFO_THRESHOLD + 1);
3742
3743         /* Configure TX MAC FIFO */
3744         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3745         SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3746 }
3747
3748 /*
3749  * Note that to properly initialize any part of the GEnesis chip,
3750  * you first have to take it out of reset mode.
3751  */
3752 static void
3753 sk_init(xsc)
3754         void                    *xsc;
3755 {
3756         struct sk_if_softc      *sc_if = xsc;
3757
3758         SK_IF_LOCK(sc_if);
3759         sk_init_locked(sc_if);
3760         SK_IF_UNLOCK(sc_if);
3761
3762         return;
3763 }
3764
3765 static void
3766 sk_init_locked(sc_if)
3767         struct sk_if_softc      *sc_if;
3768 {
3769         struct sk_softc         *sc;
3770         struct ifnet            *ifp;
3771         struct mii_data         *mii;
3772         u_int16_t               reg;
3773         u_int32_t               imr;
3774         int                     error;
3775
3776         SK_IF_LOCK_ASSERT(sc_if);
3777
3778         ifp = sc_if->sk_ifp;
3779         sc = sc_if->sk_softc;
3780         mii = device_get_softc(sc_if->sk_miibus);
3781
3782         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3783                 return;
3784
3785         /* Cancel pending I/O and free all RX/TX buffers. */
3786         sk_stop(sc_if);
3787
3788         if (sc->sk_type == SK_GENESIS) {
3789                 /* Configure LINK_SYNC LED */
3790                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3791                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3792                         SK_LINKLED_LINKSYNC_ON);
3793
3794                 /* Configure RX LED */
3795                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3796                         SK_RXLEDCTL_COUNTER_START);
3797
3798                 /* Configure TX LED */
3799                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3800                         SK_TXLEDCTL_COUNTER_START);
3801         }
3802
3803         /*
3804          * Configure descriptor poll timer
3805          *
3806          * SK-NET GENESIS data sheet says that possibility of losing Start
3807          * transmit command due to CPU/cache related interim storage problems
3808          * under certain conditions. The document recommends a polling
3809          * mechanism to send a Start transmit command to initiate transfer
3810          * of ready descriptors regulary. To cope with this issue sk(4) now
3811          * enables descriptor poll timer to initiate descriptor processing
3812          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3813          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3814          * command instead of waiting for next descriptor polling time.
3815          * The same rule may apply to Rx side too but it seems that is not
3816          * needed at the moment.
3817          * Since sk(4) uses descriptor polling as a last resort there is no
3818          * need to set smaller polling time than maximum allowable one.
3819          */
3820         SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3821
3822         /* Configure I2C registers */
3823
3824         /* Configure XMAC(s) */
3825         switch (sc->sk_type) {
3826         case SK_GENESIS:
3827                 sk_init_xmac(sc_if);
3828                 break;
3829         case SK_YUKON:
3830         case SK_YUKON_LITE:
3831         case SK_YUKON_LP:
3832                 sk_init_yukon(sc_if);
3833                 break;
3834         }
3835         mii_mediachg(mii);
3836
3837         if (sc->sk_type == SK_GENESIS) {
3838                 /* Configure MAC FIFOs */
3839                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3840                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3841                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3842
3843                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3844                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3845                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3846         }
3847
3848         /* Configure transmit arbiter(s) */
3849         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3850             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3851
3852         /* Configure RAMbuffers */
3853         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3854         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3855         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3856         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3857         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3858         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3859
3860         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3861         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3862         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3863         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3864         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3865         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3866         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3867
3868         /* Configure BMUs */
3869         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3870         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3871                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3872                     SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3873                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3874                     SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3875         } else {
3876                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3877                     SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3878                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3879                     SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3880         }
3881
3882         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3883         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3884             SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3885         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3886             SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3887
3888         /* Init descriptors */
3889         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3890                 error = sk_init_jumbo_rx_ring(sc_if);
3891         else
3892                 error = sk_init_rx_ring(sc_if);
3893         if (error != 0) {
3894                 device_printf(sc_if->sk_if_dev,
3895                     "initialization failed: no memory for rx buffers\n");
3896                 sk_stop(sc_if);
3897                 return;
3898         }
3899         sk_init_tx_ring(sc_if);
3900
3901         /* Set interrupt moderation if changed via sysctl. */
3902         imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3903         if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3904                 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3905                     sc->sk_int_ticks));
3906                 if (bootverbose)
3907                         device_printf(sc_if->sk_if_dev,
3908                             "interrupt moderation is %d us.\n",
3909                             sc->sk_int_mod);
3910         }
3911
3912         /* Configure interrupt handling */
3913         CSR_READ_4(sc, SK_ISSR);
3914         if (sc_if->sk_port == SK_PORT_A)
3915                 sc->sk_intrmask |= SK_INTRS1;
3916         else
3917                 sc->sk_intrmask |= SK_INTRS2;
3918
3919         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3920
3921         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3922
3923         /* Start BMUs. */
3924         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3925
3926         switch(sc->sk_type) {
3927         case SK_GENESIS:
3928                 /* Enable XMACs TX and RX state machines */
3929                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3930                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3931                 break;
3932         case SK_YUKON:
3933         case SK_YUKON_LITE:
3934         case SK_YUKON_LP:
3935                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3936                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3937 #if 0
3938                 /* XXX disable 100Mbps and full duplex mode? */
3939                 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3940 #endif
3941                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3942         }
3943
3944         /* Activate descriptor polling timer */
3945         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3946         /* start transfer of Tx descriptors */
3947         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3948
3949         ifp->if_drv_flags |= IFF_DRV_RUNNING;
3950         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3951
3952         switch (sc->sk_type) {
3953         case SK_YUKON:
3954         case SK_YUKON_LITE:
3955         case SK_YUKON_LP:
3956                 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3957                 break;
3958         }
3959
3960         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3961
3962         return;
3963 }
3964
3965 static void
3966 sk_stop(sc_if)
3967         struct sk_if_softc      *sc_if;
3968 {
3969         int                     i;
3970         struct sk_softc         *sc;
3971         struct sk_txdesc        *txd;
3972         struct sk_rxdesc        *rxd;
3973         struct sk_rxdesc        *jrxd;
3974         struct ifnet            *ifp;
3975         u_int32_t               val;
3976
3977         SK_IF_LOCK_ASSERT(sc_if);
3978         sc = sc_if->sk_softc;
3979         ifp = sc_if->sk_ifp;
3980
3981         callout_stop(&sc_if->sk_tick_ch);
3982         callout_stop(&sc_if->sk_watchdog_ch);
3983
3984         /* stop Tx descriptor polling timer */
3985         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3986         /* stop transfer of Tx descriptors */
3987         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3988         for (i = 0; i < SK_TIMEOUT; i++) {
3989                 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3990                 if ((val & SK_TXBMU_TX_STOP) == 0)
3991                         break;
3992                 DELAY(1);
3993         }
3994         if (i == SK_TIMEOUT)
3995                 device_printf(sc_if->sk_if_dev,
3996                     "can not stop transfer of Tx descriptor\n");
3997         /* stop transfer of Rx descriptors */
3998         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3999         for (i = 0; i < SK_TIMEOUT; i++) {
4000                 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
4001                 if ((val & SK_RXBMU_RX_STOP) == 0)
4002                         break;
4003                 DELAY(1);
4004         }
4005         if (i == SK_TIMEOUT)
4006                 device_printf(sc_if->sk_if_dev,
4007                     "can not stop transfer of Rx descriptor\n");
4008
4009         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
4010                 /* Put PHY back into reset. */
4011                 val = sk_win_read_4(sc, SK_GPIO);
4012                 if (sc_if->sk_port == SK_PORT_A) {
4013                         val |= SK_GPIO_DIR0;
4014                         val &= ~SK_GPIO_DAT0;
4015                 } else {
4016                         val |= SK_GPIO_DIR2;
4017                         val &= ~SK_GPIO_DAT2;
4018                 }
4019                 sk_win_write_4(sc, SK_GPIO, val);
4020         }
4021
4022         /* Turn off various components of this interface. */
4023         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
4024         switch (sc->sk_type) {
4025         case SK_GENESIS:
4026                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
4027                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
4028                 break;
4029         case SK_YUKON:
4030         case SK_YUKON_LITE:
4031         case SK_YUKON_LP:
4032                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
4033                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
4034                 break;
4035         }
4036         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
4037         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
4038         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
4039         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
4040         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
4041         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
4042         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
4043         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
4044         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
4045
4046         /* Disable interrupts */
4047         if (sc_if->sk_port == SK_PORT_A)
4048                 sc->sk_intrmask &= ~SK_INTRS1;
4049         else
4050                 sc->sk_intrmask &= ~SK_INTRS2;
4051         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
4052
4053         SK_XM_READ_2(sc_if, XM_ISR);
4054         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
4055
4056         /* Free RX and TX mbufs still in the queues. */
4057         for (i = 0; i < SK_RX_RING_CNT; i++) {
4058                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
4059                 if (rxd->rx_m != NULL) {
4060                         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
4061                             rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4062                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
4063                             rxd->rx_dmamap);
4064                         m_freem(rxd->rx_m);
4065                         rxd->rx_m = NULL;
4066                 }
4067         }
4068         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
4069                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
4070                 if (jrxd->rx_m != NULL) {
4071                         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
4072                             jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4073                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
4074                             jrxd->rx_dmamap);
4075                         m_freem(jrxd->rx_m);
4076                         jrxd->rx_m = NULL;
4077                 }
4078         }
4079         for (i = 0; i < SK_TX_RING_CNT; i++) {
4080                 txd = &sc_if->sk_cdata.sk_txdesc[i];
4081                 if (txd->tx_m != NULL) {
4082                         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
4083                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4084                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
4085                             txd->tx_dmamap);
4086                         m_freem(txd->tx_m);
4087                         txd->tx_m = NULL;
4088                 }
4089         }
4090
4091         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
4092
4093         return;
4094 }
4095
4096 static int
4097 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4098 {
4099         int error, value;
4100
4101         if (!arg1)
4102                 return (EINVAL);
4103         value = *(int *)arg1;
4104         error = sysctl_handle_int(oidp, &value, 0, req);
4105         if (error || !req->newptr)
4106                 return (error);
4107         if (value < low || value > high)
4108                 return (EINVAL);
4109         *(int *)arg1 = value;
4110         return (0);
4111 }
4112
4113 static int
4114 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
4115 {
4116         return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
4117 }