1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
4 * Copyright (c) 1997, 1998, 1999, 2000
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
37 * Permission to use, copy, modify, and distribute this software for any
38 * purpose with or without fee is hereby granted, provided that the above
39 * copyright notice and this permission notice appear in all copies.
41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
57 * The XaQti XMAC II datasheet,
58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
59 * The SysKonnect GEnesis manual, http://www.syskonnect.com
61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63 * convenience to others until Vitesse corrects this problem:
65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
67 * Written by Bill Paul <wpaul@ee.columbia.edu>
68 * Department of Electrical Engineering
69 * Columbia University, New York City
72 * The SysKonnect gigabit ethernet adapters consist of two main
73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
75 * components and a PHY while the GEnesis controller provides a PCI
76 * interface with DMA support. Each card may have between 512K and
77 * 2MB of SRAM on board depending on the configuration.
79 * The SysKonnect GEnesis controller can have either one or two XMAC
80 * chips connected to it, allowing single or dual port NIC configurations.
81 * SysKonnect has the distinction of being the only vendor on the market
82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
84 * XMAC registers. This driver takes advantage of these features to allow
85 * both XMACs to operate as independent interfaces.
88 #include <sys/param.h>
89 #include <sys/systm.h>
91 #include <sys/endian.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/sockio.h>
98 #include <sys/queue.h>
99 #include <sys/sysctl.h>
102 #include <net/ethernet.h>
104 #include <net/if_arp.h>
105 #include <net/if_dl.h>
106 #include <net/if_media.h>
107 #include <net/if_types.h>
108 #include <net/if_vlan_var.h>
110 #include <netinet/in.h>
111 #include <netinet/in_systm.h>
112 #include <netinet/ip.h>
114 #include <machine/bus.h>
115 #include <machine/in_cksum.h>
116 #include <machine/resource.h>
117 #include <sys/rman.h>
119 #include <dev/mii/mii.h>
120 #include <dev/mii/miivar.h>
121 #include <dev/mii/brgphyreg.h>
123 #include <dev/pci/pcireg.h>
124 #include <dev/pci/pcivar.h>
127 #define SK_USEIOSPACE
130 #include <dev/sk/if_skreg.h>
131 #include <dev/sk/xmaciireg.h>
132 #include <dev/sk/yukonreg.h>
134 MODULE_DEPEND(sk, pci, 1, 1, 1);
135 MODULE_DEPEND(sk, ether, 1, 1, 1);
136 MODULE_DEPEND(sk, miibus, 1, 1, 1);
138 /* "device miibus" required. See GENERIC if you get errors here. */
139 #include "miibus_if.h"
142 static const char rcsid[] =
146 static struct sk_type sk_devs[] = {
150 "SysKonnect Gigabit Ethernet (V1.0)"
155 "SysKonnect Gigabit Ethernet (V2.0)"
160 "Marvell Gigabit Ethernet"
164 DEVICEID_BELKIN_5005,
165 "Belkin F5D5005 Gigabit Ethernet"
170 "3Com 3C940 Gigabit Ethernet"
174 DEVICEID_LINKSYS_EG1032,
175 "Linksys EG1032 Gigabit Ethernet"
179 DEVICEID_DLINK_DGE530T_A1,
180 "D-Link DGE-530T Gigabit Ethernet"
184 DEVICEID_DLINK_DGE530T_B1,
185 "D-Link DGE-530T Gigabit Ethernet"
190 static int skc_probe(device_t);
191 static int skc_attach(device_t);
192 static int skc_detach(device_t);
193 static int skc_shutdown(device_t);
194 static int skc_suspend(device_t);
195 static int skc_resume(device_t);
196 static int sk_detach(device_t);
197 static int sk_probe(device_t);
198 static int sk_attach(device_t);
199 static void sk_tick(void *);
200 static void sk_yukon_tick(void *);
201 static void sk_intr(void *);
202 static void sk_intr_xmac(struct sk_if_softc *);
203 static void sk_intr_bcom(struct sk_if_softc *);
204 static void sk_intr_yukon(struct sk_if_softc *);
205 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
206 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
207 static void sk_rxeof(struct sk_if_softc *);
208 static void sk_jumbo_rxeof(struct sk_if_softc *);
209 static void sk_txeof(struct sk_if_softc *);
210 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
211 static int sk_encap(struct sk_if_softc *, struct mbuf **);
212 static void sk_start(struct ifnet *);
213 static void sk_start_locked(struct ifnet *);
214 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
215 static void sk_init(void *);
216 static void sk_init_locked(struct sk_if_softc *);
217 static void sk_init_xmac(struct sk_if_softc *);
218 static void sk_init_yukon(struct sk_if_softc *);
219 static void sk_stop(struct sk_if_softc *);
220 static void sk_watchdog(void *);
221 static int sk_ifmedia_upd(struct ifnet *);
222 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
223 static void sk_reset(struct sk_softc *);
224 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
225 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
226 static int sk_newbuf(struct sk_if_softc *, int);
227 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
228 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
229 static int sk_dma_alloc(struct sk_if_softc *);
230 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
231 static void sk_dma_free(struct sk_if_softc *);
232 static void sk_dma_jumbo_free(struct sk_if_softc *);
233 static int sk_init_rx_ring(struct sk_if_softc *);
234 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
235 static void sk_init_tx_ring(struct sk_if_softc *);
236 static u_int32_t sk_win_read_4(struct sk_softc *, int);
237 static u_int16_t sk_win_read_2(struct sk_softc *, int);
238 static u_int8_t sk_win_read_1(struct sk_softc *, int);
239 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
240 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
241 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
243 static int sk_miibus_readreg(device_t, int, int);
244 static int sk_miibus_writereg(device_t, int, int, int);
245 static void sk_miibus_statchg(device_t);
247 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
248 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
250 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
252 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
253 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
255 static void sk_marv_miibus_statchg(struct sk_if_softc *);
257 static uint32_t sk_xmchash(const uint8_t *);
258 static uint32_t sk_gmchash(const uint8_t *);
259 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
260 static void sk_setmulti(struct sk_if_softc *);
261 static void sk_setpromisc(struct sk_if_softc *);
263 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
264 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
267 static int jumbo_disable = 0;
268 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
271 * It seems that SK-NET GENESIS supports very simple checksum offload
272 * capability for Tx and I believe it can generate 0 checksum value for
273 * UDP packets in Tx as the hardware can't differenciate UDP packets from
274 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
275 * means sender didn't perforam checksum computation. For the safety I
276 * disabled UDP checksum offload capability at the moment. Alternatively
277 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
280 #define SK_CSUM_FEATURES (CSUM_TCP)
283 * Note that we have newbus methods for both the GEnesis controller
284 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
285 * the miibus code is a child of the XMACs. We need to do it this way
286 * so that the miibus drivers can access the PHY registers on the
287 * right PHY. It's not quite what I had in mind, but it's the only
288 * design that achieves the desired effect.
290 static device_method_t skc_methods[] = {
291 /* Device interface */
292 DEVMETHOD(device_probe, skc_probe),
293 DEVMETHOD(device_attach, skc_attach),
294 DEVMETHOD(device_detach, skc_detach),
295 DEVMETHOD(device_suspend, skc_suspend),
296 DEVMETHOD(device_resume, skc_resume),
297 DEVMETHOD(device_shutdown, skc_shutdown),
300 DEVMETHOD(bus_print_child, bus_generic_print_child),
301 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
306 static driver_t skc_driver = {
309 sizeof(struct sk_softc)
312 static devclass_t skc_devclass;
314 static device_method_t sk_methods[] = {
315 /* Device interface */
316 DEVMETHOD(device_probe, sk_probe),
317 DEVMETHOD(device_attach, sk_attach),
318 DEVMETHOD(device_detach, sk_detach),
319 DEVMETHOD(device_shutdown, bus_generic_shutdown),
322 DEVMETHOD(bus_print_child, bus_generic_print_child),
323 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
326 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
327 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
328 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
333 static driver_t sk_driver = {
336 sizeof(struct sk_if_softc)
339 static devclass_t sk_devclass;
341 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, 0, 0);
342 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0);
343 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
345 static struct resource_spec sk_res_spec_io[] = {
346 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
347 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
351 static struct resource_spec sk_res_spec_mem[] = {
352 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
353 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
357 #define SK_SETBIT(sc, reg, x) \
358 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
360 #define SK_CLRBIT(sc, reg, x) \
361 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
363 #define SK_WIN_SETBIT_4(sc, reg, x) \
364 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
366 #define SK_WIN_CLRBIT_4(sc, reg, x) \
367 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
369 #define SK_WIN_SETBIT_2(sc, reg, x) \
370 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
372 #define SK_WIN_CLRBIT_2(sc, reg, x) \
373 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
376 sk_win_read_4(sc, reg)
381 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
382 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
384 return(CSR_READ_4(sc, reg));
389 sk_win_read_2(sc, reg)
394 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
395 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
397 return(CSR_READ_2(sc, reg));
402 sk_win_read_1(sc, reg)
407 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
408 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
410 return(CSR_READ_1(sc, reg));
415 sk_win_write_4(sc, reg, val)
421 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
422 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
424 CSR_WRITE_4(sc, reg, val);
430 sk_win_write_2(sc, reg, val)
436 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
437 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
439 CSR_WRITE_2(sc, reg, val);
445 sk_win_write_1(sc, reg, val)
451 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
452 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
454 CSR_WRITE_1(sc, reg, val);
460 sk_miibus_readreg(dev, phy, reg)
464 struct sk_if_softc *sc_if;
467 sc_if = device_get_softc(dev);
469 SK_IF_MII_LOCK(sc_if);
470 switch(sc_if->sk_softc->sk_type) {
472 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
477 v = sk_marv_miibus_readreg(sc_if, phy, reg);
483 SK_IF_MII_UNLOCK(sc_if);
489 sk_miibus_writereg(dev, phy, reg, val)
493 struct sk_if_softc *sc_if;
496 sc_if = device_get_softc(dev);
498 SK_IF_MII_LOCK(sc_if);
499 switch(sc_if->sk_softc->sk_type) {
501 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
506 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
512 SK_IF_MII_UNLOCK(sc_if);
518 sk_miibus_statchg(dev)
521 struct sk_if_softc *sc_if;
523 sc_if = device_get_softc(dev);
525 SK_IF_MII_LOCK(sc_if);
526 switch(sc_if->sk_softc->sk_type) {
528 sk_xmac_miibus_statchg(sc_if);
533 sk_marv_miibus_statchg(sc_if);
536 SK_IF_MII_UNLOCK(sc_if);
542 sk_xmac_miibus_readreg(sc_if, phy, reg)
543 struct sk_if_softc *sc_if;
548 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
551 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
552 SK_XM_READ_2(sc_if, XM_PHY_DATA);
553 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
554 for (i = 0; i < SK_TIMEOUT; i++) {
556 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
557 XM_MMUCMD_PHYDATARDY)
561 if (i == SK_TIMEOUT) {
562 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
567 i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
573 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
574 struct sk_if_softc *sc_if;
579 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
580 for (i = 0; i < SK_TIMEOUT; i++) {
581 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
585 if (i == SK_TIMEOUT) {
586 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
590 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
591 for (i = 0; i < SK_TIMEOUT; i++) {
593 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
597 if_printf(sc_if->sk_ifp, "phy write timed out\n");
603 sk_xmac_miibus_statchg(sc_if)
604 struct sk_if_softc *sc_if;
606 struct mii_data *mii;
608 mii = device_get_softc(sc_if->sk_miibus);
611 * If this is a GMII PHY, manually set the XMAC's
612 * duplex mode accordingly.
614 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
615 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
616 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
618 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
624 sk_marv_miibus_readreg(sc_if, phy, reg)
625 struct sk_if_softc *sc_if;
632 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
633 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
637 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
638 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
640 for (i = 0; i < SK_TIMEOUT; i++) {
642 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
643 if (val & YU_SMICR_READ_VALID)
647 if (i == SK_TIMEOUT) {
648 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
652 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
658 sk_marv_miibus_writereg(sc_if, phy, reg, val)
659 struct sk_if_softc *sc_if;
664 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
665 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
666 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
668 for (i = 0; i < SK_TIMEOUT; i++) {
670 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
674 if_printf(sc_if->sk_ifp, "phy write timeout\n");
680 sk_marv_miibus_statchg(sc_if)
681 struct sk_if_softc *sc_if;
694 /* Compute CRC for the address value. */
695 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
697 return (~crc & ((1 << HASH_BITS) - 1));
700 /* gmchash is just a big endian crc */
707 /* Compute CRC for the address value. */
708 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
710 return (crc & ((1 << HASH_BITS) - 1));
714 sk_setfilt(sc_if, addr, slot)
715 struct sk_if_softc *sc_if;
721 base = XM_RXFILT_ENTRY(slot);
723 SK_XM_WRITE_2(sc_if, base, addr[0]);
724 SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
725 SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
732 struct sk_if_softc *sc_if;
734 struct sk_softc *sc = sc_if->sk_softc;
735 struct ifnet *ifp = sc_if->sk_ifp;
736 u_int32_t hashes[2] = { 0, 0 };
738 struct ifmultiaddr *ifma;
739 u_int16_t dummy[] = { 0, 0, 0 };
740 u_int16_t maddr[(ETHER_ADDR_LEN+1)/2];
742 SK_IF_LOCK_ASSERT(sc_if);
744 /* First, zot all the existing filters. */
745 switch(sc->sk_type) {
747 for (i = 1; i < XM_RXFILT_MAX; i++)
748 sk_setfilt(sc_if, dummy, i);
750 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
751 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
756 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
757 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
758 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
759 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
763 /* Now program new ones. */
764 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
765 hashes[0] = 0xFFFFFFFF;
766 hashes[1] = 0xFFFFFFFF;
770 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
771 if (ifma->ifma_addr->sa_family != AF_LINK)
774 * Program the first XM_RXFILT_MAX multicast groups
775 * into the perfect filter. For all others,
776 * use the hash table.
778 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
780 (struct sockaddr_dl *)ifma->ifma_addr),
781 maddr, ETHER_ADDR_LEN);
782 sk_setfilt(sc_if, maddr, i);
787 switch(sc->sk_type) {
790 (struct sockaddr_dl *)ifma->ifma_addr),
791 maddr, ETHER_ADDR_LEN);
792 h = sk_xmchash((const uint8_t *)maddr);
798 (struct sockaddr_dl *)ifma->ifma_addr),
799 maddr, ETHER_ADDR_LEN);
800 h = sk_gmchash((const uint8_t *)maddr);
804 hashes[0] |= (1 << h);
806 hashes[1] |= (1 << (h - 32));
811 switch(sc->sk_type) {
813 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
814 XM_MODE_RX_USE_PERFECT);
815 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
816 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
821 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
822 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
823 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
824 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
833 struct sk_if_softc *sc_if;
835 struct sk_softc *sc = sc_if->sk_softc;
836 struct ifnet *ifp = sc_if->sk_ifp;
838 SK_IF_LOCK_ASSERT(sc_if);
840 switch(sc->sk_type) {
842 if (ifp->if_flags & IFF_PROMISC) {
843 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
845 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
851 if (ifp->if_flags & IFF_PROMISC) {
852 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
853 YU_RCR_UFLEN | YU_RCR_MUFLEN);
855 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
856 YU_RCR_UFLEN | YU_RCR_MUFLEN);
865 sk_init_rx_ring(sc_if)
866 struct sk_if_softc *sc_if;
868 struct sk_ring_data *rd;
870 u_int32_t csum_start;
873 sc_if->sk_cdata.sk_rx_cons = 0;
875 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 |
877 rd = &sc_if->sk_rdata;
878 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
879 for (i = 0; i < SK_RX_RING_CNT; i++) {
880 if (sk_newbuf(sc_if, i) != 0)
882 if (i == (SK_RX_RING_CNT - 1))
883 addr = SK_RX_RING_ADDR(sc_if, 0);
885 addr = SK_RX_RING_ADDR(sc_if, i + 1);
886 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
887 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
890 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
891 sc_if->sk_cdata.sk_rx_ring_map,
892 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
898 sk_init_jumbo_rx_ring(sc_if)
899 struct sk_if_softc *sc_if;
901 struct sk_ring_data *rd;
903 u_int32_t csum_start;
906 sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
908 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
910 rd = &sc_if->sk_rdata;
911 bzero(rd->sk_jumbo_rx_ring,
912 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
913 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
914 if (sk_jumbo_newbuf(sc_if, i) != 0)
916 if (i == (SK_JUMBO_RX_RING_CNT - 1))
917 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
919 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
920 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
921 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
924 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
925 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
926 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
932 sk_init_tx_ring(sc_if)
933 struct sk_if_softc *sc_if;
935 struct sk_ring_data *rd;
936 struct sk_txdesc *txd;
940 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
941 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
943 sc_if->sk_cdata.sk_tx_prod = 0;
944 sc_if->sk_cdata.sk_tx_cons = 0;
945 sc_if->sk_cdata.sk_tx_cnt = 0;
947 rd = &sc_if->sk_rdata;
948 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
949 for (i = 0; i < SK_TX_RING_CNT; i++) {
950 if (i == (SK_TX_RING_CNT - 1))
951 addr = SK_TX_RING_ADDR(sc_if, 0);
953 addr = SK_TX_RING_ADDR(sc_if, i + 1);
954 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
955 txd = &sc_if->sk_cdata.sk_txdesc[i];
956 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
959 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
960 sc_if->sk_cdata.sk_tx_ring_map,
961 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
965 sk_discard_rxbuf(sc_if, idx)
966 struct sk_if_softc *sc_if;
969 struct sk_rx_desc *r;
970 struct sk_rxdesc *rxd;
974 r = &sc_if->sk_rdata.sk_rx_ring[idx];
975 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
977 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
981 sk_discard_jumbo_rxbuf(sc_if, idx)
982 struct sk_if_softc *sc_if;
985 struct sk_rx_desc *r;
986 struct sk_rxdesc *rxd;
989 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
990 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
992 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
996 sk_newbuf(sc_if, idx)
997 struct sk_if_softc *sc_if;
1000 struct sk_rx_desc *r;
1001 struct sk_rxdesc *rxd;
1003 bus_dma_segment_t segs[1];
1007 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1010 m->m_len = m->m_pkthdr.len = MCLBYTES;
1011 m_adj(m, ETHER_ALIGN);
1013 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
1014 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1018 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1020 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
1021 if (rxd->rx_m != NULL) {
1022 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
1023 BUS_DMASYNC_POSTREAD);
1024 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
1026 map = rxd->rx_dmamap;
1027 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
1028 sc_if->sk_cdata.sk_rx_sparemap = map;
1029 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
1030 BUS_DMASYNC_PREREAD);
1032 r = &sc_if->sk_rdata.sk_rx_ring[idx];
1033 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1034 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1035 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1041 sk_jumbo_newbuf(sc_if, idx)
1042 struct sk_if_softc *sc_if;
1045 struct sk_rx_desc *r;
1046 struct sk_rxdesc *rxd;
1048 bus_dma_segment_t segs[1];
1052 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1055 if ((m->m_flags & M_EXT) == 0) {
1059 m->m_pkthdr.len = m->m_len = MJUM9BYTES;
1061 * Adjust alignment so packet payload begins on a
1062 * longword boundary. Mandatory for Alpha, useful on
1065 m_adj(m, ETHER_ALIGN);
1067 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1068 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1072 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1074 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1075 if (rxd->rx_m != NULL) {
1076 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1077 BUS_DMASYNC_POSTREAD);
1078 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1081 map = rxd->rx_dmamap;
1082 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1083 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1084 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1085 BUS_DMASYNC_PREREAD);
1087 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1088 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1089 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1090 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1096 * Set media options.
1102 struct sk_if_softc *sc_if = ifp->if_softc;
1103 struct mii_data *mii;
1105 mii = device_get_softc(sc_if->sk_miibus);
1113 * Report current media status.
1116 sk_ifmedia_sts(ifp, ifmr)
1118 struct ifmediareq *ifmr;
1120 struct sk_if_softc *sc_if;
1121 struct mii_data *mii;
1123 sc_if = ifp->if_softc;
1124 mii = device_get_softc(sc_if->sk_miibus);
1127 ifmr->ifm_active = mii->mii_media_active;
1128 ifmr->ifm_status = mii->mii_media_status;
1134 sk_ioctl(ifp, command, data)
1139 struct sk_if_softc *sc_if = ifp->if_softc;
1140 struct ifreq *ifr = (struct ifreq *) data;
1142 struct mii_data *mii;
1147 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1149 else if (ifp->if_mtu != ifr->ifr_mtu) {
1150 if (sc_if->sk_jumbo_disable != 0 &&
1151 ifr->ifr_mtu > SK_MAX_FRAMELEN)
1155 ifp->if_mtu = ifr->ifr_mtu;
1156 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1157 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1158 sk_init_locked(sc_if);
1160 SK_IF_UNLOCK(sc_if);
1166 if (ifp->if_flags & IFF_UP) {
1167 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1168 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1170 sk_setpromisc(sc_if);
1174 sk_init_locked(sc_if);
1176 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1179 sc_if->sk_if_flags = ifp->if_flags;
1180 SK_IF_UNLOCK(sc_if);
1185 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1187 SK_IF_UNLOCK(sc_if);
1191 mii = device_get_softc(sc_if->sk_miibus);
1192 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1196 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1197 SK_IF_UNLOCK(sc_if);
1200 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1201 if (mask & IFCAP_HWCSUM) {
1202 ifp->if_capenable ^= IFCAP_HWCSUM;
1203 if (IFCAP_HWCSUM & ifp->if_capenable &&
1204 IFCAP_HWCSUM & ifp->if_capabilities)
1205 ifp->if_hwassist = SK_CSUM_FEATURES;
1207 ifp->if_hwassist = 0;
1209 SK_IF_UNLOCK(sc_if);
1212 error = ether_ioctl(ifp, command, data);
1220 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1221 * IDs against our list and return a device name if we find a match.
1227 struct sk_type *t = sk_devs;
1229 while(t->sk_name != NULL) {
1230 if ((pci_get_vendor(dev) == t->sk_vid) &&
1231 (pci_get_device(dev) == t->sk_did)) {
1233 * Only attach to rev. 2 of the Linksys EG1032 adapter.
1234 * Rev. 3 is supported by re(4).
1236 if ((t->sk_vid == VENDORID_LINKSYS) &&
1237 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1238 (pci_get_subdevice(dev) !=
1239 SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1243 device_set_desc(dev, t->sk_name);
1244 return (BUS_PROBE_DEFAULT);
1253 * Force the GEnesis into reset, then bring it out of reset.
1257 struct sk_softc *sc;
1260 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1261 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1262 if (SK_YUKON_FAMILY(sc->sk_type))
1263 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1266 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1268 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1269 if (SK_YUKON_FAMILY(sc->sk_type))
1270 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1272 if (sc->sk_type == SK_GENESIS) {
1273 /* Configure packet arbiter */
1274 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1275 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1276 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1277 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1278 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1281 /* Enable RAM interface */
1282 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1285 * Configure interrupt moderation. The moderation timer
1286 * defers interrupts specified in the interrupt moderation
1287 * timer mask based on the timeout specified in the interrupt
1288 * moderation timer init register. Each bit in the timer
1289 * register represents one tick, so to specify a timeout in
1290 * microseconds, we have to multiply by the correct number of
1291 * ticks-per-microsecond.
1293 switch (sc->sk_type) {
1295 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1298 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1302 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1304 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1306 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1307 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1308 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1317 struct sk_softc *sc;
1319 sc = device_get_softc(device_get_parent(dev));
1322 * Not much to do here. We always know there will be
1323 * at least one XMAC present, and if there are two,
1324 * skc_attach() will create a second device instance
1327 switch (sc->sk_type) {
1329 device_set_desc(dev, "XaQti Corp. XMAC II");
1334 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1338 return (BUS_PROBE_DEFAULT);
1342 * Each XMAC chip is attached as a separate logical IP interface.
1343 * Single port cards will have only one logical interface of course.
1349 struct sk_softc *sc;
1350 struct sk_if_softc *sc_if;
1359 sc_if = device_get_softc(dev);
1360 sc = device_get_softc(device_get_parent(dev));
1361 port = *(int *)device_get_ivars(dev);
1363 sc_if->sk_if_dev = dev;
1364 sc_if->sk_port = port;
1365 sc_if->sk_softc = sc;
1366 sc->sk_if[port] = sc_if;
1367 if (port == SK_PORT_A)
1368 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1369 if (port == SK_PORT_B)
1370 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1372 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1373 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1375 if (sk_dma_alloc(sc_if) != 0) {
1379 sk_dma_jumbo_alloc(sc_if);
1381 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1383 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1387 ifp->if_softc = sc_if;
1388 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1389 ifp->if_mtu = ETHERMTU;
1390 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1392 * SK_GENESIS has a bug in checksum offload - From linux.
1394 if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1395 ifp->if_capabilities = IFCAP_HWCSUM;
1396 ifp->if_hwassist = SK_CSUM_FEATURES;
1398 ifp->if_capabilities = 0;
1399 ifp->if_hwassist = 0;
1401 ifp->if_capenable = ifp->if_capabilities;
1402 ifp->if_ioctl = sk_ioctl;
1403 ifp->if_start = sk_start;
1405 ifp->if_watchdog = NULL;
1406 ifp->if_init = sk_init;
1407 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1408 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1409 IFQ_SET_READY(&ifp->if_snd);
1412 * Get station address for this interface. Note that
1413 * dual port cards actually come with three station
1414 * addresses: one for each port, plus an extra. The
1415 * extra one is used by the SysKonnect driver software
1416 * as a 'virtual' station address for when both ports
1417 * are operating in failover mode. Currently we don't
1418 * use this extra address.
1421 for (i = 0; i < ETHER_ADDR_LEN; i++)
1423 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1426 * Set up RAM buffer addresses. The NIC will have a certain
1427 * amount of SRAM on it, somewhere between 512K and 2MB. We
1428 * need to divide this up a) between the transmitter and
1429 * receiver and b) between the two XMACs, if this is a
1430 * dual port NIC. Our algotithm is to divide up the memory
1431 * evenly so that everyone gets a fair share.
1433 * Just to be contrary, Yukon2 appears to have separate memory
1436 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1437 u_int32_t chunk, val;
1439 chunk = sc->sk_ramsize / 2;
1440 val = sc->sk_rboff / sizeof(u_int64_t);
1441 sc_if->sk_rx_ramstart = val;
1442 val += (chunk / sizeof(u_int64_t));
1443 sc_if->sk_rx_ramend = val - 1;
1444 sc_if->sk_tx_ramstart = val;
1445 val += (chunk / sizeof(u_int64_t));
1446 sc_if->sk_tx_ramend = val - 1;
1448 u_int32_t chunk, val;
1450 chunk = sc->sk_ramsize / 4;
1451 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1453 sc_if->sk_rx_ramstart = val;
1454 val += (chunk / sizeof(u_int64_t));
1455 sc_if->sk_rx_ramend = val - 1;
1456 sc_if->sk_tx_ramstart = val;
1457 val += (chunk / sizeof(u_int64_t));
1458 sc_if->sk_tx_ramend = val - 1;
1461 /* Read and save PHY type and set PHY address */
1462 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1463 if (!SK_YUKON_FAMILY(sc->sk_type)) {
1464 switch(sc_if->sk_phytype) {
1465 case SK_PHYTYPE_XMAC:
1466 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1468 case SK_PHYTYPE_BCOM:
1469 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1472 device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1475 SK_IF_UNLOCK(sc_if);
1479 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1480 sc->sk_pmd != 'S') {
1481 /* not initialized, punt */
1482 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1483 sc->sk_coppertype = 1;
1486 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1488 if (!(sc->sk_coppertype))
1489 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1493 * Call MI attach routine. Can't hold locks when calling into ether_*.
1495 SK_IF_UNLOCK(sc_if);
1496 ether_ifattach(ifp, eaddr);
1500 * The hardware should be ready for VLAN_MTU by default:
1501 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1502 * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1505 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1506 ifp->if_capenable |= IFCAP_VLAN_MTU;
1508 * Tell the upper layer(s) we support long frames.
1509 * Must appear after the call to ether_ifattach() because
1510 * ether_ifattach() sets ifi_hdrlen to the default value.
1512 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1517 switch (sc->sk_type) {
1519 sk_init_xmac(sc_if);
1524 sk_init_yukon(sc_if);
1528 SK_IF_UNLOCK(sc_if);
1529 if (mii_phy_probe(dev, &sc_if->sk_miibus,
1530 sk_ifmedia_upd, sk_ifmedia_sts)) {
1531 device_printf(sc_if->sk_if_dev, "no PHY found!\n");
1532 ether_ifdetach(ifp);
1539 /* Access should be ok even though lock has been dropped */
1540 sc->sk_if[port] = NULL;
1548 * Attach the interface. Allocate softc structures, do ifmedia
1549 * setup and ethernet/BPF attach.
1555 struct sk_softc *sc;
1556 int error = 0, *port;
1558 const char *pname = NULL;
1561 sc = device_get_softc(dev);
1564 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1566 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1568 * Map control/status registers.
1570 pci_enable_busmaster(dev);
1572 /* Allocate resources */
1573 #ifdef SK_USEIOSPACE
1574 sc->sk_res_spec = sk_res_spec_io;
1576 sc->sk_res_spec = sk_res_spec_mem;
1578 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1580 if (sc->sk_res_spec == sk_res_spec_mem)
1581 sc->sk_res_spec = sk_res_spec_io;
1583 sc->sk_res_spec = sk_res_spec_mem;
1584 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1586 device_printf(dev, "couldn't allocate %s resources\n",
1587 sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1593 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1594 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1596 /* Bail out if chip is not recognized. */
1597 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1598 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1599 sc->sk_type, sc->sk_rev);
1604 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1605 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1606 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1607 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1608 "SK interrupt moderation");
1610 /* Pull in device tunables. */
1611 sc->sk_int_mod = SK_IM_DEFAULT;
1612 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1613 "int_mod", &sc->sk_int_mod);
1615 if (sc->sk_int_mod < SK_IM_MIN ||
1616 sc->sk_int_mod > SK_IM_MAX) {
1617 device_printf(dev, "int_mod value out of range; "
1618 "using default: %d\n", SK_IM_DEFAULT);
1619 sc->sk_int_mod = SK_IM_DEFAULT;
1623 /* Reset the adapter. */
1626 skrs = sk_win_read_1(sc, SK_EPROM0);
1627 if (sc->sk_type == SK_GENESIS) {
1628 /* Read and save RAM size and RAMbuffer offset */
1630 case SK_RAMSIZE_512K_64:
1631 sc->sk_ramsize = 0x80000;
1632 sc->sk_rboff = SK_RBOFF_0;
1634 case SK_RAMSIZE_1024K_64:
1635 sc->sk_ramsize = 0x100000;
1636 sc->sk_rboff = SK_RBOFF_80000;
1638 case SK_RAMSIZE_1024K_128:
1639 sc->sk_ramsize = 0x100000;
1640 sc->sk_rboff = SK_RBOFF_0;
1642 case SK_RAMSIZE_2048K_128:
1643 sc->sk_ramsize = 0x200000;
1644 sc->sk_rboff = SK_RBOFF_0;
1647 device_printf(dev, "unknown ram size: %d\n", skrs);
1651 } else { /* SK_YUKON_FAMILY */
1653 sc->sk_ramsize = 0x20000;
1655 sc->sk_ramsize = skrs * (1<<12);
1656 sc->sk_rboff = SK_RBOFF_0;
1659 /* Read and save physical media type */
1660 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1662 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1663 sc->sk_coppertype = 1;
1665 sc->sk_coppertype = 0;
1667 /* Determine whether to name it with VPD PN or just make it up.
1668 * Marvell Yukon VPD PN seems to freqently be bogus. */
1669 switch (pci_get_device(dev)) {
1670 case DEVICEID_SK_V1:
1671 case DEVICEID_BELKIN_5005:
1672 case DEVICEID_3COM_3C940:
1673 case DEVICEID_LINKSYS_EG1032:
1674 case DEVICEID_DLINK_DGE530T_A1:
1675 case DEVICEID_DLINK_DGE530T_B1:
1676 /* Stay with VPD PN. */
1677 (void) pci_get_vpd_ident(dev, &pname);
1679 case DEVICEID_SK_V2:
1680 /* YUKON VPD PN might bear no resemblance to reality. */
1681 switch (sc->sk_type) {
1683 /* Stay with VPD PN. */
1684 (void) pci_get_vpd_ident(dev, &pname);
1687 pname = "Marvell Yukon Gigabit Ethernet";
1690 pname = "Marvell Yukon Lite Gigabit Ethernet";
1693 pname = "Marvell Yukon LP Gigabit Ethernet";
1696 pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1700 /* Yukon Lite Rev. A0 needs special test. */
1701 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1705 /* Save flash address register before testing. */
1706 far = sk_win_read_4(sc, SK_EP_ADDR);
1708 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1709 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1711 if (testbyte != 0x00) {
1712 /* Yukon Lite Rev. A0 detected. */
1713 sc->sk_type = SK_YUKON_LITE;
1714 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1715 /* Restore flash address register. */
1716 sk_win_write_4(sc, SK_EP_ADDR, far);
1721 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1722 "chipver=%02x, rev=%x\n",
1723 pci_get_vendor(dev), pci_get_device(dev),
1724 sc->sk_type, sc->sk_rev);
1729 if (sc->sk_type == SK_YUKON_LITE) {
1730 switch (sc->sk_rev) {
1731 case SK_YUKON_LITE_REV_A0:
1734 case SK_YUKON_LITE_REV_A1:
1737 case SK_YUKON_LITE_REV_A3:
1748 /* Announce the product name and more VPD data if there. */
1750 device_printf(dev, "%s rev. %s(0x%x)\n",
1751 pname, revstr, sc->sk_rev);
1754 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type);
1755 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev);
1756 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1757 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1760 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1761 if (sc->sk_devs[SK_PORT_A] == NULL) {
1762 device_printf(dev, "failed to add child for PORT_A\n");
1766 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1768 device_printf(dev, "failed to allocate memory for "
1769 "ivars of PORT_A\n");
1774 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1776 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1777 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1778 if (sc->sk_devs[SK_PORT_B] == NULL) {
1779 device_printf(dev, "failed to add child for PORT_B\n");
1783 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1785 device_printf(dev, "failed to allocate memory for "
1786 "ivars of PORT_B\n");
1791 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1794 /* Turn on the 'driver is loaded' LED. */
1795 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1797 error = bus_generic_attach(dev);
1799 device_printf(dev, "failed to attach port(s)\n");
1803 /* Hook interrupt last to avoid having to lock softc */
1804 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1805 NULL, sk_intr, sc, &sc->sk_intrhand);
1808 device_printf(dev, "couldn't set up irq\n");
1820 * Shutdown hardware and free up resources. This can be called any
1821 * time after the mutex has been initialized. It is called in both
1822 * the error case in attach and the normal detach case so it needs
1823 * to be careful about only freeing resources that have actually been
1830 struct sk_if_softc *sc_if;
1833 sc_if = device_get_softc(dev);
1834 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1835 ("sk mutex not initialized in sk_detach"));
1838 ifp = sc_if->sk_ifp;
1839 /* These should only be active if attach_xmac succeeded */
1840 if (device_is_attached(dev)) {
1842 /* Can't hold locks while calling detach */
1843 SK_IF_UNLOCK(sc_if);
1844 callout_drain(&sc_if->sk_tick_ch);
1845 callout_drain(&sc_if->sk_watchdog_ch);
1846 ether_ifdetach(ifp);
1852 * We're generally called from skc_detach() which is using
1853 * device_delete_child() to get to here. It's already trashed
1854 * miibus for us, so don't do it here or we'll panic.
1857 if (sc_if->sk_miibus != NULL)
1858 device_delete_child(dev, sc_if->sk_miibus);
1860 bus_generic_detach(dev);
1861 sk_dma_jumbo_free(sc_if);
1863 SK_IF_UNLOCK(sc_if);
1872 struct sk_softc *sc;
1874 sc = device_get_softc(dev);
1875 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1877 if (device_is_alive(dev)) {
1878 if (sc->sk_devs[SK_PORT_A] != NULL) {
1879 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1880 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1882 if (sc->sk_devs[SK_PORT_B] != NULL) {
1883 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1884 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1886 bus_generic_detach(dev);
1889 if (sc->sk_intrhand)
1890 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1891 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1893 mtx_destroy(&sc->sk_mii_mtx);
1894 mtx_destroy(&sc->sk_mtx);
1899 struct sk_dmamap_arg {
1900 bus_addr_t sk_busaddr;
1904 sk_dmamap_cb(arg, segs, nseg, error)
1906 bus_dma_segment_t *segs;
1910 struct sk_dmamap_arg *ctx;
1916 ctx->sk_busaddr = segs[0].ds_addr;
1920 * Allocate jumbo buffer storage. The SysKonnect adapters support
1921 * "jumbograms" (9K frames), although SysKonnect doesn't currently
1922 * use them in their drivers. In order for us to use them, we need
1923 * large 9K receive buffers, however standard mbuf clusters are only
1924 * 2048 bytes in size. Consequently, we need to allocate and manage
1925 * our own jumbo buffer pool. Fortunately, this does not require an
1926 * excessive amount of additional code.
1930 struct sk_if_softc *sc_if;
1932 struct sk_dmamap_arg ctx;
1933 struct sk_txdesc *txd;
1934 struct sk_rxdesc *rxd;
1937 /* create parent tag */
1940 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1941 * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1942 * However bz@ reported that it does not work on amd64 with > 4GB
1943 * RAM. Until we have more clues of the breakage, disable DAC mode
1944 * by limiting DMA address to be in 32bit address space.
1946 error = bus_dma_tag_create(
1947 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1948 1, 0, /* algnmnt, boundary */
1949 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1950 BUS_SPACE_MAXADDR, /* highaddr */
1951 NULL, NULL, /* filter, filterarg */
1952 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1954 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1956 NULL, NULL, /* lockfunc, lockarg */
1957 &sc_if->sk_cdata.sk_parent_tag);
1959 device_printf(sc_if->sk_if_dev,
1960 "failed to create parent DMA tag\n");
1964 /* create tag for Tx ring */
1965 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1966 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1967 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1968 BUS_SPACE_MAXADDR, /* highaddr */
1969 NULL, NULL, /* filter, filterarg */
1970 SK_TX_RING_SZ, /* maxsize */
1972 SK_TX_RING_SZ, /* maxsegsize */
1974 NULL, NULL, /* lockfunc, lockarg */
1975 &sc_if->sk_cdata.sk_tx_ring_tag);
1977 device_printf(sc_if->sk_if_dev,
1978 "failed to allocate Tx ring DMA tag\n");
1982 /* create tag for Rx ring */
1983 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1984 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1985 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1986 BUS_SPACE_MAXADDR, /* highaddr */
1987 NULL, NULL, /* filter, filterarg */
1988 SK_RX_RING_SZ, /* maxsize */
1990 SK_RX_RING_SZ, /* maxsegsize */
1992 NULL, NULL, /* lockfunc, lockarg */
1993 &sc_if->sk_cdata.sk_rx_ring_tag);
1995 device_printf(sc_if->sk_if_dev,
1996 "failed to allocate Rx ring DMA tag\n");
2000 /* create tag for Tx buffers */
2001 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2002 1, 0, /* algnmnt, boundary */
2003 BUS_SPACE_MAXADDR, /* lowaddr */
2004 BUS_SPACE_MAXADDR, /* highaddr */
2005 NULL, NULL, /* filter, filterarg */
2006 MCLBYTES * SK_MAXTXSEGS, /* maxsize */
2007 SK_MAXTXSEGS, /* nsegments */
2008 MCLBYTES, /* maxsegsize */
2010 NULL, NULL, /* lockfunc, lockarg */
2011 &sc_if->sk_cdata.sk_tx_tag);
2013 device_printf(sc_if->sk_if_dev,
2014 "failed to allocate Tx DMA tag\n");
2018 /* create tag for Rx buffers */
2019 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2020 1, 0, /* algnmnt, boundary */
2021 BUS_SPACE_MAXADDR, /* lowaddr */
2022 BUS_SPACE_MAXADDR, /* highaddr */
2023 NULL, NULL, /* filter, filterarg */
2024 MCLBYTES, /* maxsize */
2026 MCLBYTES, /* maxsegsize */
2028 NULL, NULL, /* lockfunc, lockarg */
2029 &sc_if->sk_cdata.sk_rx_tag);
2031 device_printf(sc_if->sk_if_dev,
2032 "failed to allocate Rx DMA tag\n");
2036 /* allocate DMA'able memory and load the DMA map for Tx ring */
2037 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2038 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2039 &sc_if->sk_cdata.sk_tx_ring_map);
2041 device_printf(sc_if->sk_if_dev,
2042 "failed to allocate DMA'able memory for Tx ring\n");
2047 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2048 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2049 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2051 device_printf(sc_if->sk_if_dev,
2052 "failed to load DMA'able memory for Tx ring\n");
2055 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2057 /* allocate DMA'able memory and load the DMA map for Rx ring */
2058 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2059 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2060 &sc_if->sk_cdata.sk_rx_ring_map);
2062 device_printf(sc_if->sk_if_dev,
2063 "failed to allocate DMA'able memory for Rx ring\n");
2068 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2069 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2070 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2072 device_printf(sc_if->sk_if_dev,
2073 "failed to load DMA'able memory for Rx ring\n");
2076 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2078 /* create DMA maps for Tx buffers */
2079 for (i = 0; i < SK_TX_RING_CNT; i++) {
2080 txd = &sc_if->sk_cdata.sk_txdesc[i];
2082 txd->tx_dmamap = NULL;
2083 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2086 device_printf(sc_if->sk_if_dev,
2087 "failed to create Tx dmamap\n");
2092 /* create DMA maps for Rx buffers */
2093 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2094 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2095 device_printf(sc_if->sk_if_dev,
2096 "failed to create spare Rx dmamap\n");
2099 for (i = 0; i < SK_RX_RING_CNT; i++) {
2100 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2102 rxd->rx_dmamap = NULL;
2103 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2106 device_printf(sc_if->sk_if_dev,
2107 "failed to create Rx dmamap\n");
2117 sk_dma_jumbo_alloc(sc_if)
2118 struct sk_if_softc *sc_if;
2120 struct sk_dmamap_arg ctx;
2121 struct sk_rxdesc *jrxd;
2124 if (jumbo_disable != 0) {
2125 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2126 sc_if->sk_jumbo_disable = 1;
2129 /* create tag for jumbo Rx ring */
2130 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2131 SK_RING_ALIGN, 0, /* algnmnt, boundary */
2132 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2133 BUS_SPACE_MAXADDR, /* highaddr */
2134 NULL, NULL, /* filter, filterarg */
2135 SK_JUMBO_RX_RING_SZ, /* maxsize */
2137 SK_JUMBO_RX_RING_SZ, /* maxsegsize */
2139 NULL, NULL, /* lockfunc, lockarg */
2140 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2142 device_printf(sc_if->sk_if_dev,
2143 "failed to allocate jumbo Rx ring DMA tag\n");
2147 /* create tag for jumbo Rx buffers */
2148 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2149 1, 0, /* algnmnt, boundary */
2150 BUS_SPACE_MAXADDR, /* lowaddr */
2151 BUS_SPACE_MAXADDR, /* highaddr */
2152 NULL, NULL, /* filter, filterarg */
2153 MJUM9BYTES, /* maxsize */
2155 MJUM9BYTES, /* maxsegsize */
2157 NULL, NULL, /* lockfunc, lockarg */
2158 &sc_if->sk_cdata.sk_jumbo_rx_tag);
2160 device_printf(sc_if->sk_if_dev,
2161 "failed to allocate jumbo Rx DMA tag\n");
2165 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2166 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2167 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring,
2168 BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2170 device_printf(sc_if->sk_if_dev,
2171 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2176 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2177 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2178 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2179 &ctx, BUS_DMA_NOWAIT);
2181 device_printf(sc_if->sk_if_dev,
2182 "failed to load DMA'able memory for jumbo Rx ring\n");
2185 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2187 /* create DMA maps for jumbo Rx buffers */
2188 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2189 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2190 device_printf(sc_if->sk_if_dev,
2191 "failed to create spare jumbo Rx dmamap\n");
2194 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2195 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2197 jrxd->rx_dmamap = NULL;
2198 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2201 device_printf(sc_if->sk_if_dev,
2202 "failed to create jumbo Rx dmamap\n");
2210 sk_dma_jumbo_free(sc_if);
2211 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2212 "resource shortage\n");
2213 sc_if->sk_jumbo_disable = 1;
2219 struct sk_if_softc *sc_if;
2221 struct sk_txdesc *txd;
2222 struct sk_rxdesc *rxd;
2226 if (sc_if->sk_cdata.sk_tx_ring_tag) {
2227 if (sc_if->sk_cdata.sk_tx_ring_map)
2228 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2229 sc_if->sk_cdata.sk_tx_ring_map);
2230 if (sc_if->sk_cdata.sk_tx_ring_map &&
2231 sc_if->sk_rdata.sk_tx_ring)
2232 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2233 sc_if->sk_rdata.sk_tx_ring,
2234 sc_if->sk_cdata.sk_tx_ring_map);
2235 sc_if->sk_rdata.sk_tx_ring = NULL;
2236 sc_if->sk_cdata.sk_tx_ring_map = NULL;
2237 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2238 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2241 if (sc_if->sk_cdata.sk_rx_ring_tag) {
2242 if (sc_if->sk_cdata.sk_rx_ring_map)
2243 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2244 sc_if->sk_cdata.sk_rx_ring_map);
2245 if (sc_if->sk_cdata.sk_rx_ring_map &&
2246 sc_if->sk_rdata.sk_rx_ring)
2247 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2248 sc_if->sk_rdata.sk_rx_ring,
2249 sc_if->sk_cdata.sk_rx_ring_map);
2250 sc_if->sk_rdata.sk_rx_ring = NULL;
2251 sc_if->sk_cdata.sk_rx_ring_map = NULL;
2252 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2253 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2256 if (sc_if->sk_cdata.sk_tx_tag) {
2257 for (i = 0; i < SK_TX_RING_CNT; i++) {
2258 txd = &sc_if->sk_cdata.sk_txdesc[i];
2259 if (txd->tx_dmamap) {
2260 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2262 txd->tx_dmamap = NULL;
2265 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2266 sc_if->sk_cdata.sk_tx_tag = NULL;
2269 if (sc_if->sk_cdata.sk_rx_tag) {
2270 for (i = 0; i < SK_RX_RING_CNT; i++) {
2271 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2272 if (rxd->rx_dmamap) {
2273 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2275 rxd->rx_dmamap = NULL;
2278 if (sc_if->sk_cdata.sk_rx_sparemap) {
2279 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2280 sc_if->sk_cdata.sk_rx_sparemap);
2281 sc_if->sk_cdata.sk_rx_sparemap = NULL;
2283 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2284 sc_if->sk_cdata.sk_rx_tag = NULL;
2287 if (sc_if->sk_cdata.sk_parent_tag) {
2288 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2289 sc_if->sk_cdata.sk_parent_tag = NULL;
2294 sk_dma_jumbo_free(sc_if)
2295 struct sk_if_softc *sc_if;
2297 struct sk_rxdesc *jrxd;
2301 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2302 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map)
2303 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2304 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2305 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map &&
2306 sc_if->sk_rdata.sk_jumbo_rx_ring)
2307 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2308 sc_if->sk_rdata.sk_jumbo_rx_ring,
2309 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2310 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2311 sc_if->sk_cdata.sk_jumbo_rx_ring_map = NULL;
2312 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2313 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2316 /* jumbo Rx buffers */
2317 if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2318 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2319 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2320 if (jrxd->rx_dmamap) {
2322 sc_if->sk_cdata.sk_jumbo_rx_tag,
2324 jrxd->rx_dmamap = NULL;
2327 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2328 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2329 sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2330 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2332 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2333 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2338 sk_txcksum(ifp, m, f)
2341 struct sk_tx_desc *f;
2347 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2348 for(; m && m->m_len == 0; m = m->m_next)
2350 if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2351 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2352 /* checksum may be corrupted */
2355 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2356 if (m->m_len != ETHER_HDR_LEN) {
2357 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2359 /* checksum may be corrupted */
2362 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2365 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2366 /* checksum may be corrupted */
2369 ip = mtod(m, struct ip *);
2371 p = mtod(m, u_int8_t *);
2373 ip = (struct ip *)p;
2375 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2378 f->sk_csum_startval = 0;
2379 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2384 sk_encap(sc_if, m_head)
2385 struct sk_if_softc *sc_if;
2386 struct mbuf **m_head;
2388 struct sk_txdesc *txd;
2389 struct sk_tx_desc *f = NULL;
2391 bus_dma_segment_t txsegs[SK_MAXTXSEGS];
2392 u_int32_t cflags, frag, si, sk_ctl;
2395 SK_IF_LOCK_ASSERT(sc_if);
2397 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2400 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2401 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2402 if (error == EFBIG) {
2403 m = m_defrag(*m_head, M_DONTWAIT);
2410 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2411 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2417 } else if (error != 0)
2424 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2425 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2430 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2431 cflags = SK_OPCODE_CSUM;
2433 cflags = SK_OPCODE_DEFAULT;
2434 si = frag = sc_if->sk_cdata.sk_tx_prod;
2435 for (i = 0; i < nseg; i++) {
2436 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2437 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2438 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2439 sk_ctl = txsegs[i].ds_len | cflags;
2441 if (cflags == SK_OPCODE_CSUM)
2442 sk_txcksum(sc_if->sk_ifp, m, f);
2443 sk_ctl |= SK_TXCTL_FIRSTFRAG;
2445 sk_ctl |= SK_TXCTL_OWN;
2446 f->sk_ctl = htole32(sk_ctl);
2447 sc_if->sk_cdata.sk_tx_cnt++;
2448 SK_INC(frag, SK_TX_RING_CNT);
2450 sc_if->sk_cdata.sk_tx_prod = frag;
2452 /* set EOF on the last desciptor */
2453 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2454 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2455 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2457 /* turn the first descriptor ownership to NIC */
2458 f = &sc_if->sk_rdata.sk_tx_ring[si];
2459 f->sk_ctl |= htole32(SK_TXCTL_OWN);
2461 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2462 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2465 /* sync descriptors */
2466 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2467 BUS_DMASYNC_PREWRITE);
2468 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2469 sc_if->sk_cdata.sk_tx_ring_map,
2470 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2479 struct sk_if_softc *sc_if;
2481 sc_if = ifp->if_softc;
2484 sk_start_locked(ifp);
2485 SK_IF_UNLOCK(sc_if);
2491 sk_start_locked(ifp)
2494 struct sk_softc *sc;
2495 struct sk_if_softc *sc_if;
2496 struct mbuf *m_head;
2499 sc_if = ifp->if_softc;
2500 sc = sc_if->sk_softc;
2502 SK_IF_LOCK_ASSERT(sc_if);
2504 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2505 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2506 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2511 * Pack the data into the transmit ring. If we
2512 * don't have room, set the OACTIVE flag and wait
2513 * for the NIC to drain the ring.
2515 if (sk_encap(sc_if, &m_head)) {
2518 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2519 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2525 * If there's a BPF listener, bounce a copy of this frame
2528 BPF_MTAP(ifp, m_head);
2533 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2535 /* Set a timeout in case the chip goes out to lunch. */
2536 sc_if->sk_watchdog_timer = 5;
2545 struct sk_if_softc *sc_if;
2549 sc_if = ifp->if_softc;
2551 SK_IF_LOCK_ASSERT(sc_if);
2553 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2557 * Reclaim first as there is a possibility of losing Tx completion
2561 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2562 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2564 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2565 sk_init_locked(sc_if);
2569 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2578 struct sk_softc *sc;
2580 sc = device_get_softc(dev);
2583 /* Turn off the 'driver is loaded' LED. */
2584 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2587 * Reset the GEnesis controller. Doing this should also
2588 * assert the resets on the attached XMAC(s).
2600 struct sk_softc *sc;
2601 struct sk_if_softc *sc_if0, *sc_if1;
2602 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2604 sc = device_get_softc(dev);
2608 sc_if0 = sc->sk_if[SK_PORT_A];
2609 sc_if1 = sc->sk_if[SK_PORT_B];
2611 ifp0 = sc_if0->sk_ifp;
2613 ifp1 = sc_if1->sk_ifp;
2618 sc->sk_suspended = 1;
2629 struct sk_softc *sc;
2630 struct sk_if_softc *sc_if0, *sc_if1;
2631 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2633 sc = device_get_softc(dev);
2637 sc_if0 = sc->sk_if[SK_PORT_A];
2638 sc_if1 = sc->sk_if[SK_PORT_B];
2640 ifp0 = sc_if0->sk_ifp;
2642 ifp1 = sc_if1->sk_ifp;
2643 if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2644 sk_init_locked(sc_if0);
2645 if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2646 sk_init_locked(sc_if1);
2647 sc->sk_suspended = 0;
2655 * According to the data sheet from SK-NET GENESIS the hardware can compute
2656 * two Rx checksums at the same time(Each checksum start position is
2657 * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2658 * does not work at least on my Yukon hardware. I tried every possible ways
2659 * to get correct checksum value but couldn't get correct one. So TCP/UDP
2660 * checksum offload was disabled at the moment and only IP checksum offload
2662 * As nomral IP header size is 20 bytes I can't expect it would give an
2663 * increase in throughput. However it seems it doesn't hurt performance in
2664 * my testing. If there is a more detailed information for checksum secret
2665 * of the hardware in question please contact yongari@FreeBSD.org to add
2666 * TCP/UDP checksum offload support.
2668 static __inline void
2669 sk_rxcksum(ifp, m, csum)
2674 struct ether_header *eh;
2676 int32_t hlen, len, pktlen;
2677 u_int16_t csum1, csum2, ipcsum;
2679 pktlen = m->m_pkthdr.len;
2680 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2682 eh = mtod(m, struct ether_header *);
2683 if (eh->ether_type != htons(ETHERTYPE_IP))
2685 ip = (struct ip *)(eh + 1);
2686 if (ip->ip_v != IPVERSION)
2688 hlen = ip->ip_hl << 2;
2689 pktlen -= sizeof(struct ether_header);
2690 if (hlen < sizeof(struct ip))
2692 if (ntohs(ip->ip_len) < hlen)
2694 if (ntohs(ip->ip_len) != pktlen)
2697 csum1 = htons(csum & 0xffff);
2698 csum2 = htons((csum >> 16) & 0xffff);
2699 ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2700 /* checksum fixup for IP options */
2701 len = hlen - sizeof(struct ip);
2704 * If the second checksum value is correct we can compute IP
2705 * checksum with simple math. Unfortunately the second checksum
2706 * value is wrong so we can't verify the checksum from the
2707 * value(It seems there is some magic here to get correct
2708 * value). If the second checksum value is correct it also
2709 * means we can get TCP/UDP checksum) here. However, it still
2710 * needs pseudo header checksum calculation due to hardware
2715 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2716 if (ipcsum == 0xffff)
2717 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2721 sk_rxvalid(sc, stat, len)
2722 struct sk_softc *sc;
2723 u_int32_t stat, len;
2726 if (sc->sk_type == SK_GENESIS) {
2727 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2728 XM_RXSTAT_BYTES(stat) != len)
2731 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2732 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2733 YU_RXSTAT_JABBER)) != 0 ||
2734 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2735 YU_RXSTAT_BYTES(stat) != len)
2744 struct sk_if_softc *sc_if;
2746 struct sk_softc *sc;
2749 struct sk_rx_desc *cur_rx;
2750 struct sk_rxdesc *rxd;
2752 u_int32_t csum, rxstat, sk_ctl;
2754 sc = sc_if->sk_softc;
2755 ifp = sc_if->sk_ifp;
2757 SK_IF_LOCK_ASSERT(sc_if);
2759 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2760 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2763 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2764 prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2765 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2766 sk_ctl = le32toh(cur_rx->sk_ctl);
2767 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2769 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2770 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2772 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2773 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2774 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2775 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2776 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2777 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2779 sk_discard_rxbuf(sc_if, cons);
2784 csum = le32toh(cur_rx->sk_csum);
2785 if (sk_newbuf(sc_if, cons) != 0) {
2787 /* reuse old buffer */
2788 sk_discard_rxbuf(sc_if, cons);
2791 m->m_pkthdr.rcvif = ifp;
2792 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2794 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2795 sk_rxcksum(ifp, m, csum);
2796 SK_IF_UNLOCK(sc_if);
2797 (*ifp->if_input)(ifp, m);
2802 sc_if->sk_cdata.sk_rx_cons = cons;
2803 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2804 sc_if->sk_cdata.sk_rx_ring_map,
2805 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2810 sk_jumbo_rxeof(sc_if)
2811 struct sk_if_softc *sc_if;
2813 struct sk_softc *sc;
2816 struct sk_rx_desc *cur_rx;
2817 struct sk_rxdesc *jrxd;
2819 u_int32_t csum, rxstat, sk_ctl;
2821 sc = sc_if->sk_softc;
2822 ifp = sc_if->sk_ifp;
2824 SK_IF_LOCK_ASSERT(sc_if);
2826 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2827 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2830 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2831 prog < SK_JUMBO_RX_RING_CNT;
2832 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2833 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2834 sk_ctl = le32toh(cur_rx->sk_ctl);
2835 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2837 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2838 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2840 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2841 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2842 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2843 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2844 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2845 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2847 sk_discard_jumbo_rxbuf(sc_if, cons);
2852 csum = le32toh(cur_rx->sk_csum);
2853 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2855 /* reuse old buffer */
2856 sk_discard_jumbo_rxbuf(sc_if, cons);
2859 m->m_pkthdr.rcvif = ifp;
2860 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2862 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2863 sk_rxcksum(ifp, m, csum);
2864 SK_IF_UNLOCK(sc_if);
2865 (*ifp->if_input)(ifp, m);
2870 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2871 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2872 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2873 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2879 struct sk_if_softc *sc_if;
2881 struct sk_softc *sc;
2882 struct sk_txdesc *txd;
2883 struct sk_tx_desc *cur_tx;
2885 u_int32_t idx, sk_ctl;
2887 sc = sc_if->sk_softc;
2888 ifp = sc_if->sk_ifp;
2890 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2893 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2894 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2896 * Go through our tx ring and free mbufs for those
2897 * frames that have been sent.
2899 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2900 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2902 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2903 sk_ctl = le32toh(cur_tx->sk_ctl);
2904 if (sk_ctl & SK_TXCTL_OWN)
2906 sc_if->sk_cdata.sk_tx_cnt--;
2907 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2908 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2910 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2911 BUS_DMASYNC_POSTWRITE);
2912 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2917 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2918 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2919 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2921 sc_if->sk_cdata.sk_tx_cons = idx;
2922 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2924 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2925 sc_if->sk_cdata.sk_tx_ring_map,
2926 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2933 struct sk_if_softc *sc_if;
2934 struct mii_data *mii;
2939 ifp = sc_if->sk_ifp;
2940 mii = device_get_softc(sc_if->sk_miibus);
2942 if (!(ifp->if_flags & IFF_UP))
2945 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2946 sk_intr_bcom(sc_if);
2951 * According to SysKonnect, the correct way to verify that
2952 * the link has come back up is to poll bit 0 of the GPIO
2953 * register three times. This pin has the signal from the
2954 * link_sync pin connected to it; if we read the same link
2955 * state 3 times in a row, we know the link is up.
2957 for (i = 0; i < 3; i++) {
2958 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2963 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2967 /* Turn the GP0 interrupt back on. */
2968 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2969 SK_XM_READ_2(sc_if, XM_ISR);
2971 callout_stop(&sc_if->sk_tick_ch);
2975 sk_yukon_tick(xsc_if)
2978 struct sk_if_softc *sc_if;
2979 struct mii_data *mii;
2982 mii = device_get_softc(sc_if->sk_miibus);
2985 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2990 struct sk_if_softc *sc_if;
2992 struct mii_data *mii;
2995 mii = device_get_softc(sc_if->sk_miibus);
2996 ifp = sc_if->sk_ifp;
2998 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3001 * Read the PHY interrupt register to make sure
3002 * we clear any pending interrupts.
3004 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
3006 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3007 sk_init_xmac(sc_if);
3011 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
3013 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
3016 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
3018 /* Turn off the link LED. */
3019 SK_IF_WRITE_1(sc_if, 0,
3020 SK_LINKLED1_CTL, SK_LINKLED_OFF);
3022 } else if (status & BRGPHY_ISR_LNK_CHG) {
3023 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3024 BRGPHY_MII_IMR, 0xFF00);
3027 /* Turn on the link LED. */
3028 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3029 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
3030 SK_LINKLED_BLINK_OFF);
3033 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3037 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3044 struct sk_if_softc *sc_if;
3046 struct sk_softc *sc;
3049 sc = sc_if->sk_softc;
3050 status = SK_XM_READ_2(sc_if, XM_ISR);
3053 * Link has gone down. Start MII tick timeout to
3054 * watch for link resync.
3056 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3057 if (status & XM_ISR_GP0_SET) {
3058 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3059 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3062 if (status & XM_ISR_AUTONEG_DONE) {
3063 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3067 if (status & XM_IMR_TX_UNDERRUN)
3068 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3070 if (status & XM_IMR_RX_OVERRUN)
3071 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3073 status = SK_XM_READ_2(sc_if, XM_ISR);
3079 sk_intr_yukon(sc_if)
3080 struct sk_if_softc *sc_if;
3084 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3086 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3087 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3088 SK_RFCTL_RX_FIFO_OVER);
3091 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3092 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3093 SK_TFCTL_TX_FIFO_UNDER);
3101 struct sk_softc *sc = xsc;
3102 struct sk_if_softc *sc_if0, *sc_if1;
3103 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
3108 status = CSR_READ_4(sc, SK_ISSR);
3109 if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3112 sc_if0 = sc->sk_if[SK_PORT_A];
3113 sc_if1 = sc->sk_if[SK_PORT_B];
3116 ifp0 = sc_if0->sk_ifp;
3118 ifp1 = sc_if1->sk_ifp;
3120 for (; (status &= sc->sk_intrmask) != 0;) {
3121 /* Handle receive interrupts first. */
3122 if (status & SK_ISR_RX1_EOF) {
3123 if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3124 sk_jumbo_rxeof(sc_if0);
3127 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3128 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3130 if (status & SK_ISR_RX2_EOF) {
3131 if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3132 sk_jumbo_rxeof(sc_if1);
3135 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3136 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3139 /* Then transmit interrupts. */
3140 if (status & SK_ISR_TX1_S_EOF) {
3142 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3144 if (status & SK_ISR_TX2_S_EOF) {
3146 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3149 /* Then MAC interrupts. */
3150 if (status & SK_ISR_MAC1 &&
3151 ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3152 if (sc->sk_type == SK_GENESIS)
3153 sk_intr_xmac(sc_if0);
3155 sk_intr_yukon(sc_if0);
3158 if (status & SK_ISR_MAC2 &&
3159 ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3160 if (sc->sk_type == SK_GENESIS)
3161 sk_intr_xmac(sc_if1);
3163 sk_intr_yukon(sc_if1);
3166 if (status & SK_ISR_EXTERNAL_REG) {
3168 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3169 sk_intr_bcom(sc_if0);
3171 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3172 sk_intr_bcom(sc_if1);
3174 status = CSR_READ_4(sc, SK_ISSR);
3177 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3179 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3180 sk_start_locked(ifp0);
3181 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3182 sk_start_locked(ifp1);
3190 struct sk_if_softc *sc_if;
3192 struct sk_softc *sc;
3194 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2];
3195 struct sk_bcom_hack bhack[] = {
3196 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3197 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3198 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3201 SK_IF_LOCK_ASSERT(sc_if);
3203 sc = sc_if->sk_softc;
3204 ifp = sc_if->sk_ifp;
3206 /* Unreset the XMAC. */
3207 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3210 /* Reset the XMAC's internal state. */
3211 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3213 /* Save the XMAC II revision */
3214 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3217 * Perform additional initialization for external PHYs,
3218 * namely for the 1000baseTX cards that use the XMAC's
3221 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3225 /* Take PHY out of reset. */
3226 val = sk_win_read_4(sc, SK_GPIO);
3227 if (sc_if->sk_port == SK_PORT_A)
3228 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3230 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3231 sk_win_write_4(sc, SK_GPIO, val);
3233 /* Enable GMII mode on the XMAC. */
3234 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3236 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3237 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3239 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3240 BRGPHY_MII_IMR, 0xFFF0);
3243 * Early versions of the BCM5400 apparently have
3244 * a bug that requires them to have their reserved
3245 * registers initialized to some magic values. I don't
3246 * know what the numbers do, I'm just the messenger.
3248 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3250 while(bhack[i].reg) {
3251 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3252 bhack[i].reg, bhack[i].val);
3258 /* Set station address */
3259 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3260 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3261 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3262 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3263 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3265 if (ifp->if_flags & IFF_BROADCAST) {
3266 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3268 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3271 /* We don't need the FCS appended to the packet. */
3272 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3274 /* We want short frames padded to 60 bytes. */
3275 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3278 * Enable the reception of all error frames. This is is
3279 * a necessary evil due to the design of the XMAC. The
3280 * XMAC's receive FIFO is only 8K in size, however jumbo
3281 * frames can be up to 9000 bytes in length. When bad
3282 * frame filtering is enabled, the XMAC's RX FIFO operates
3283 * in 'store and forward' mode. For this to work, the
3284 * entire frame has to fit into the FIFO, but that means
3285 * that jumbo frames larger than 8192 bytes will be
3286 * truncated. Disabling all bad frame filtering causes
3287 * the RX FIFO to operate in streaming mode, in which
3288 * case the XMAC will start transfering frames out of the
3289 * RX FIFO as soon as the FIFO threshold is reached.
3291 if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3292 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3293 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3294 XM_MODE_RX_INRANGELEN);
3295 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3297 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3300 * Bump up the transmit threshold. This helps hold off transmit
3301 * underruns when we're blasting traffic from both ports at once.
3303 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3305 /* Set promiscuous mode */
3306 sk_setpromisc(sc_if);
3308 /* Set multicast filter */
3311 /* Clear and enable interrupts */
3312 SK_XM_READ_2(sc_if, XM_ISR);
3313 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3314 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3316 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3318 /* Configure MAC arbiter */
3319 switch(sc_if->sk_xmac_rev) {
3320 case XM_XMAC_REV_B2:
3321 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3322 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3323 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3324 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3325 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3326 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3327 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3328 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3329 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3331 case XM_XMAC_REV_C1:
3332 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3333 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3334 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3335 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3336 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3337 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3338 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3339 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3340 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3345 sk_win_write_2(sc, SK_MACARB_CTL,
3346 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3354 sk_init_yukon(sc_if)
3355 struct sk_if_softc *sc_if;
3359 struct sk_softc *sc;
3363 SK_IF_LOCK_ASSERT(sc_if);
3365 sc = sc_if->sk_softc;
3366 ifp = sc_if->sk_ifp;
3368 if (sc->sk_type == SK_YUKON_LITE &&
3369 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3371 * Workaround code for COMA mode, set PHY reset.
3372 * Otherwise it will not correctly take chip out of
3375 v = sk_win_read_4(sc, SK_GPIO);
3376 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3377 sk_win_write_4(sc, SK_GPIO, v);
3380 /* GMAC and GPHY Reset */
3381 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3382 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3385 if (sc->sk_type == SK_YUKON_LITE &&
3386 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3388 * Workaround code for COMA mode, clear PHY reset
3390 v = sk_win_read_4(sc, SK_GPIO);
3393 sk_win_write_4(sc, SK_GPIO, v);
3396 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3397 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3399 if (sc->sk_coppertype)
3400 phy |= SK_GPHY_COPPER;
3402 phy |= SK_GPHY_FIBER;
3404 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3406 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3407 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3408 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3410 /* unused read of the interrupt source register */
3411 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3413 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3415 /* MIB Counter Clear Mode set */
3416 reg |= YU_PAR_MIB_CLR;
3417 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3419 /* MIB Counter Clear Mode clear */
3420 reg &= ~YU_PAR_MIB_CLR;
3421 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3423 /* receive control reg */
3424 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3426 /* transmit parameter register */
3427 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3428 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3430 /* serial mode register */
3431 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3432 if (ifp->if_mtu > SK_MAX_FRAMELEN)
3433 reg |= YU_SMR_MFL_JUMBO;
3434 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3436 /* Setup Yukon's address */
3437 for (i = 0; i < 3; i++) {
3438 /* Write Source Address 1 (unicast filter) */
3439 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3440 IF_LLADDR(sc_if->sk_ifp)[i * 2] |
3441 IF_LLADDR(sc_if->sk_ifp)[i * 2 + 1] << 8);
3444 for (i = 0; i < 3; i++) {
3445 reg = sk_win_read_2(sc_if->sk_softc,
3446 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
3447 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
3450 /* Set promiscuous mode */
3451 sk_setpromisc(sc_if);
3453 /* Set multicast filter */
3456 /* enable interrupt mask for counter overflows */
3457 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3458 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3459 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3461 /* Configure RX MAC FIFO Flush Mask */
3462 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3463 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3465 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3467 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3468 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3469 v = SK_TFCTL_OPERATION_ON;
3471 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3472 /* Configure RX MAC FIFO */
3473 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3474 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3476 /* Increase flush threshould to 64 bytes */
3477 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3478 SK_RFCTL_FIFO_THRESHOLD + 1);
3480 /* Configure TX MAC FIFO */
3481 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3482 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3486 * Note that to properly initialize any part of the GEnesis chip,
3487 * you first have to take it out of reset mode.
3493 struct sk_if_softc *sc_if = xsc;
3496 sk_init_locked(sc_if);
3497 SK_IF_UNLOCK(sc_if);
3503 sk_init_locked(sc_if)
3504 struct sk_if_softc *sc_if;
3506 struct sk_softc *sc;
3508 struct mii_data *mii;
3513 SK_IF_LOCK_ASSERT(sc_if);
3515 ifp = sc_if->sk_ifp;
3516 sc = sc_if->sk_softc;
3517 mii = device_get_softc(sc_if->sk_miibus);
3519 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3522 /* Cancel pending I/O and free all RX/TX buffers. */
3525 if (sc->sk_type == SK_GENESIS) {
3526 /* Configure LINK_SYNC LED */
3527 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3528 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3529 SK_LINKLED_LINKSYNC_ON);
3531 /* Configure RX LED */
3532 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3533 SK_RXLEDCTL_COUNTER_START);
3535 /* Configure TX LED */
3536 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3537 SK_TXLEDCTL_COUNTER_START);
3541 * Configure descriptor poll timer
3543 * SK-NET GENESIS data sheet says that possibility of losing Start
3544 * transmit command due to CPU/cache related interim storage problems
3545 * under certain conditions. The document recommends a polling
3546 * mechanism to send a Start transmit command to initiate transfer
3547 * of ready descriptors regulary. To cope with this issue sk(4) now
3548 * enables descriptor poll timer to initiate descriptor processing
3549 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3550 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3551 * command instead of waiting for next descriptor polling time.
3552 * The same rule may apply to Rx side too but it seems that is not
3553 * needed at the moment.
3554 * Since sk(4) uses descriptor polling as a last resort there is no
3555 * need to set smaller polling time than maximum allowable one.
3557 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3559 /* Configure I2C registers */
3561 /* Configure XMAC(s) */
3562 switch (sc->sk_type) {
3564 sk_init_xmac(sc_if);
3569 sk_init_yukon(sc_if);
3574 if (sc->sk_type == SK_GENESIS) {
3575 /* Configure MAC FIFOs */
3576 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3577 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3578 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3580 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3581 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3582 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3585 /* Configure transmit arbiter(s) */
3586 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3587 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3589 /* Configure RAMbuffers */
3590 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3591 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3592 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3593 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3594 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3595 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3597 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3598 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3599 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3600 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3601 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3602 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3603 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3605 /* Configure BMUs */
3606 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3607 if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3608 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3609 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3610 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3611 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3613 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3614 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3615 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3616 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3619 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3620 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3621 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3622 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3623 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3625 /* Init descriptors */
3626 if (ifp->if_mtu > SK_MAX_FRAMELEN)
3627 error = sk_init_jumbo_rx_ring(sc_if);
3629 error = sk_init_rx_ring(sc_if);
3631 device_printf(sc_if->sk_if_dev,
3632 "initialization failed: no memory for rx buffers\n");
3636 sk_init_tx_ring(sc_if);
3638 /* Set interrupt moderation if changed via sysctl. */
3639 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3640 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3641 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3644 device_printf(sc_if->sk_if_dev,
3645 "interrupt moderation is %d us.\n",
3649 /* Configure interrupt handling */
3650 CSR_READ_4(sc, SK_ISSR);
3651 if (sc_if->sk_port == SK_PORT_A)
3652 sc->sk_intrmask |= SK_INTRS1;
3654 sc->sk_intrmask |= SK_INTRS2;
3656 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3658 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3661 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3663 switch(sc->sk_type) {
3665 /* Enable XMACs TX and RX state machines */
3666 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3667 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3672 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3673 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3675 /* XXX disable 100Mbps and full duplex mode? */
3676 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3678 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3681 /* Activate descriptor polling timer */
3682 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3683 /* start transfer of Tx descriptors */
3684 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3686 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3687 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3689 switch (sc->sk_type) {
3693 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3697 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3704 struct sk_if_softc *sc_if;
3707 struct sk_softc *sc;
3708 struct sk_txdesc *txd;
3709 struct sk_rxdesc *rxd;
3710 struct sk_rxdesc *jrxd;
3714 SK_IF_LOCK_ASSERT(sc_if);
3715 sc = sc_if->sk_softc;
3716 ifp = sc_if->sk_ifp;
3718 callout_stop(&sc_if->sk_tick_ch);
3719 callout_stop(&sc_if->sk_watchdog_ch);
3721 /* stop Tx descriptor polling timer */
3722 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3723 /* stop transfer of Tx descriptors */
3724 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3725 for (i = 0; i < SK_TIMEOUT; i++) {
3726 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3727 if ((val & SK_TXBMU_TX_STOP) == 0)
3731 if (i == SK_TIMEOUT)
3732 device_printf(sc_if->sk_if_dev,
3733 "can not stop transfer of Tx descriptor\n");
3734 /* stop transfer of Rx descriptors */
3735 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3736 for (i = 0; i < SK_TIMEOUT; i++) {
3737 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3738 if ((val & SK_RXBMU_RX_STOP) == 0)
3742 if (i == SK_TIMEOUT)
3743 device_printf(sc_if->sk_if_dev,
3744 "can not stop transfer of Rx descriptor\n");
3746 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3747 /* Put PHY back into reset. */
3748 val = sk_win_read_4(sc, SK_GPIO);
3749 if (sc_if->sk_port == SK_PORT_A) {
3750 val |= SK_GPIO_DIR0;
3751 val &= ~SK_GPIO_DAT0;
3753 val |= SK_GPIO_DIR2;
3754 val &= ~SK_GPIO_DAT2;
3756 sk_win_write_4(sc, SK_GPIO, val);
3759 /* Turn off various components of this interface. */
3760 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3761 switch (sc->sk_type) {
3763 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3764 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3769 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3770 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3773 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3774 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3775 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3776 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3777 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3778 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3779 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3780 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3781 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3783 /* Disable interrupts */
3784 if (sc_if->sk_port == SK_PORT_A)
3785 sc->sk_intrmask &= ~SK_INTRS1;
3787 sc->sk_intrmask &= ~SK_INTRS2;
3788 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3790 SK_XM_READ_2(sc_if, XM_ISR);
3791 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3793 /* Free RX and TX mbufs still in the queues. */
3794 for (i = 0; i < SK_RX_RING_CNT; i++) {
3795 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3796 if (rxd->rx_m != NULL) {
3797 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3798 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3799 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3805 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3806 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3807 if (jrxd->rx_m != NULL) {
3808 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3809 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3810 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3812 m_freem(jrxd->rx_m);
3816 for (i = 0; i < SK_TX_RING_CNT; i++) {
3817 txd = &sc_if->sk_cdata.sk_txdesc[i];
3818 if (txd->tx_m != NULL) {
3819 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3820 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3821 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3828 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
3834 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3840 value = *(int *)arg1;
3841 error = sysctl_handle_int(oidp, &value, 0, req);
3842 if (error || !req->newptr)
3844 if (value < low || value > high)
3846 *(int *)arg1 = value;
3851 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3853 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));