sys/dev/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1997, 1998, 1999, 2000
   5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34 /*-
  35  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  36  *
  37  * Permission to use, copy, modify, and distribute this software for any
  38  * purpose with or without fee is hereby granted, provided that the above
  39  * copyright notice and this permission notice appear in all copies.
  40  *
  41  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  42  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  43  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  44  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  45  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  46  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  47  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  48  */
  49
  50 #include <sys/cdefs.h>
  51 __FBSDID("$FreeBSD$");
  52
  53 /*
  54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  55  * the SK-984x series adapters, both single port and dual port.
  56  * References:
  57  *      The XaQti XMAC II datasheet,
  58  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  60  *
  61  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
  62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  63  * convenience to others until Vitesse corrects this problem:
  64  *
  65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  66  *
  67  * Written by Bill Paul <wpaul@ee.columbia.edu>
  68  * Department of Electrical Engineering
  69  * Columbia University, New York City
  70  */
  71 /*
  72  * The SysKonnect gigabit ethernet adapters consist of two main
  73  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  74  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  75  * components and a PHY while the GEnesis controller provides a PCI
  76  * interface with DMA support. Each card may have between 512K and
  77  * 2MB of SRAM on board depending on the configuration.
  78  *
  79  * The SysKonnect GEnesis controller can have either one or two XMAC
  80  * chips connected to it, allowing single or dual port NIC configurations.
  81  * SysKonnect has the distinction of being the only vendor on the market
  82  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  83  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  84  * XMAC registers. This driver takes advantage of these features to allow
  85  * both XMACs to operate as independent interfaces.
  86  */
  87
  88 #include <sys/param.h>
  89 #include <sys/systm.h>
  90 #include <sys/bus.h>
  91 #include <sys/endian.h>
  92 #include <sys/mbuf.h>
  93 #include <sys/malloc.h>
  94 #include <sys/kernel.h>
  95 #include <sys/module.h>
  96 #include <sys/socket.h>
  97 #include <sys/sockio.h>
  98 #include <sys/queue.h>
  99 #include <sys/sysctl.h>
 100
 101 #include <net/bpf.h>
 102 #include <net/ethernet.h>
 103 #include <net/if.h>
 104 #include <net/if_arp.h>
 105 #include <net/if_dl.h>
 106 #include <net/if_media.h>
 107 #include <net/if_types.h>
 108 #include <net/if_vlan_var.h>
 109
 110 #include <netinet/in.h>
 111 #include <netinet/in_systm.h>
 112 #include <netinet/ip.h>
 113
 114 #include <machine/bus.h>
 115 #include <machine/in_cksum.h>
 116 #include <machine/resource.h>
 117 #include <sys/rman.h>
 118
 119 #include <dev/mii/mii.h>
 120 #include <dev/mii/miivar.h>
 121 #include <dev/mii/brgphyreg.h>
 122
 123 #include <dev/pci/pcireg.h>
 124 #include <dev/pci/pcivar.h>
 125
 126 #if 0
 127 #define SK_USEIOSPACE
 128 #endif
 129
 130 #include <dev/sk/if_skreg.h>
 131 #include <dev/sk/xmaciireg.h>
 132 #include <dev/sk/yukonreg.h>
 133
 134 MODULE_DEPEND(sk, pci, 1, 1, 1);
 135 MODULE_DEPEND(sk, ether, 1, 1, 1);
 136 MODULE_DEPEND(sk, miibus, 1, 1, 1);
 137
 138 /* "device miibus" required.  See GENERIC if you get errors here. */
 139 #include "miibus_if.h"
 140
 141 #ifndef lint
 142 static const char rcsid[] =
 143   "$FreeBSD$";
 144 #endif
 145
 146 static struct sk_type sk_devs[] = {
 147         {
 148                 VENDORID_SK,
 149                 DEVICEID_SK_V1,
 150                 "SysKonnect Gigabit Ethernet (V1.0)"
 151         },
 152         {
 153                 VENDORID_SK,
 154                 DEVICEID_SK_V2,
 155                 "SysKonnect Gigabit Ethernet (V2.0)"
 156         },
 157         {
 158                 VENDORID_MARVELL,
 159                 DEVICEID_SK_V2,
 160                 "Marvell Gigabit Ethernet"
 161         },
 162         {
 163                 VENDORID_MARVELL,
 164                 DEVICEID_BELKIN_5005,
 165                 "Belkin F5D5005 Gigabit Ethernet"
 166         },
 167         {
 168                 VENDORID_3COM,
 169                 DEVICEID_3COM_3C940,
 170                 "3Com 3C940 Gigabit Ethernet"
 171         },
 172         {
 173                 VENDORID_LINKSYS,
 174                 DEVICEID_LINKSYS_EG1032,
 175                 "Linksys EG1032 Gigabit Ethernet"
 176         },
 177         {
 178                 VENDORID_DLINK,
 179                 DEVICEID_DLINK_DGE530T_A1,
 180                 "D-Link DGE-530T Gigabit Ethernet"
 181         },
 182         {
 183                 VENDORID_DLINK,
 184                 DEVICEID_DLINK_DGE530T_B1,
 185                 "D-Link DGE-530T Gigabit Ethernet"
 186         },
 187         { 0, 0, NULL }
 188 };
 189
 190 static int skc_probe(device_t);
 191 static int skc_attach(device_t);
 192 static int skc_detach(device_t);
 193 static int skc_shutdown(device_t);
 194 static int skc_suspend(device_t);
 195 static int skc_resume(device_t);
 196 static int sk_detach(device_t);
 197 static int sk_probe(device_t);
 198 static int sk_attach(device_t);
 199 static void sk_tick(void *);
 200 static void sk_yukon_tick(void *);
 201 static void sk_intr(void *);
 202 static void sk_intr_xmac(struct sk_if_softc *);
 203 static void sk_intr_bcom(struct sk_if_softc *);
 204 static void sk_intr_yukon(struct sk_if_softc *);
 205 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
 206 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
 207 static void sk_rxeof(struct sk_if_softc *);
 208 static void sk_jumbo_rxeof(struct sk_if_softc *);
 209 static void sk_txeof(struct sk_if_softc *);
 210 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
 211 static int sk_encap(struct sk_if_softc *, struct mbuf **);
 212 static void sk_start(struct ifnet *);
 213 static void sk_start_locked(struct ifnet *);
 214 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
 215 static void sk_init(void *);
 216 static void sk_init_locked(struct sk_if_softc *);
 217 static void sk_init_xmac(struct sk_if_softc *);
 218 static void sk_init_yukon(struct sk_if_softc *);
 219 static void sk_stop(struct sk_if_softc *);
 220 static void sk_watchdog(void *);
 221 static int sk_ifmedia_upd(struct ifnet *);
 222 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 223 static void sk_reset(struct sk_softc *);
 224 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
 225 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
 226 static int sk_newbuf(struct sk_if_softc *, int);
 227 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
 228 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 229 static int sk_dma_alloc(struct sk_if_softc *);
 230 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
 231 static void sk_dma_free(struct sk_if_softc *);
 232 static void sk_dma_jumbo_free(struct sk_if_softc *);
 233 static int sk_init_rx_ring(struct sk_if_softc *);
 234 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
 235 static void sk_init_tx_ring(struct sk_if_softc *);
 236 static u_int32_t sk_win_read_4(struct sk_softc *, int);
 237 static u_int16_t sk_win_read_2(struct sk_softc *, int);
 238 static u_int8_t sk_win_read_1(struct sk_softc *, int);
 239 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
 240 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
 241 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
 242
 243 static int sk_miibus_readreg(device_t, int, int);
 244 static int sk_miibus_writereg(device_t, int, int, int);
 245 static void sk_miibus_statchg(device_t);
 246
 247 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
 248 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
 249                                                 int);
 250 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
 251
 252 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
 253 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
 254                                                 int);
 255 static void sk_marv_miibus_statchg(struct sk_if_softc *);
 256
 257 static uint32_t sk_xmchash(const uint8_t *);
 258 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
 259 static void sk_rxfilter(struct sk_if_softc *);
 260 static void sk_rxfilter_genesis(struct sk_if_softc *);
 261 static void sk_rxfilter_yukon(struct sk_if_softc *);
 262
 263 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
 264 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
 265
 266 /* Tunables. */
 267 static int jumbo_disable = 0;
 268 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
 269
 270 /*
 271  * It seems that SK-NET GENESIS supports very simple checksum offload
 272  * capability for Tx and I believe it can generate 0 checksum value for
 273  * UDP packets in Tx as the hardware can't differenciate UDP packets from
 274  * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
 275  * means sender didn't perforam checksum computation. For the safety I
 276  * disabled UDP checksum offload capability at the moment. Alternatively
 277  * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
 278  * offload routine.
 279  */
 280 #define SK_CSUM_FEATURES        (CSUM_TCP)
 281
 282 /*
 283  * Note that we have newbus methods for both the GEnesis controller
 284  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 285  * the miibus code is a child of the XMACs. We need to do it this way
 286  * so that the miibus drivers can access the PHY registers on the
 287  * right PHY. It's not quite what I had in mind, but it's the only
 288  * design that achieves the desired effect.
 289  */
 290 static device_method_t skc_methods[] = {
 291         /* Device interface */
 292         DEVMETHOD(device_probe,         skc_probe),
 293         DEVMETHOD(device_attach,        skc_attach),
 294         DEVMETHOD(device_detach,        skc_detach),
 295         DEVMETHOD(device_suspend,       skc_suspend),
 296         DEVMETHOD(device_resume,        skc_resume),
 297         DEVMETHOD(device_shutdown,      skc_shutdown),
 298
 299         DEVMETHOD_END
 300 };
 301
 302 static driver_t skc_driver = {
 303         "skc",
 304         skc_methods,
 305         sizeof(struct sk_softc)
 306 };
 307
 308 static devclass_t skc_devclass;
 309
 310 static device_method_t sk_methods[] = {
 311         /* Device interface */
 312         DEVMETHOD(device_probe,         sk_probe),
 313         DEVMETHOD(device_attach,        sk_attach),
 314         DEVMETHOD(device_detach,        sk_detach),
 315         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 316
 317         /* MII interface */
 318         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 319         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 320         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 321
 322         DEVMETHOD_END
 323 };
 324
 325 static driver_t sk_driver = {
 326         "sk",
 327         sk_methods,
 328         sizeof(struct sk_if_softc)
 329 };
 330
 331 static devclass_t sk_devclass;
 332
 333 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, 0, 0);
 334 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0);
 335 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
 336
 337 static struct resource_spec sk_res_spec_io[] = {
 338         { SYS_RES_IOPORT,       PCIR_BAR(1),    RF_ACTIVE },
 339         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 340         { -1,                   0,              0 }
 341 };
 342
 343 static struct resource_spec sk_res_spec_mem[] = {
 344         { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 345         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 346         { -1,                   0,              0 }
 347 };
 348
 349 #define SK_SETBIT(sc, reg, x)           \
 350         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 351
 352 #define SK_CLRBIT(sc, reg, x)           \
 353         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 354
 355 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 356         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 357
 358 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 359         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 360
 361 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 362         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 363
 364 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 365         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 366
 367 static u_int32_t
 368 sk_win_read_4(sc, reg)
 369         struct sk_softc         *sc;
 370         int                     reg;
 371 {
 372 #ifdef SK_USEIOSPACE
 373         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 374         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 375 #else
 376         return(CSR_READ_4(sc, reg));
 377 #endif
 378 }
 379
 380 static u_int16_t
 381 sk_win_read_2(sc, reg)
 382         struct sk_softc         *sc;
 383         int                     reg;
 384 {
 385 #ifdef SK_USEIOSPACE
 386         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 387         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 388 #else
 389         return(CSR_READ_2(sc, reg));
 390 #endif
 391 }
 392
 393 static u_int8_t
 394 sk_win_read_1(sc, reg)
 395         struct sk_softc         *sc;
 396         int                     reg;
 397 {
 398 #ifdef SK_USEIOSPACE
 399         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 400         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 401 #else
 402         return(CSR_READ_1(sc, reg));
 403 #endif
 404 }
 405
 406 static void
 407 sk_win_write_4(sc, reg, val)
 408         struct sk_softc         *sc;
 409         int                     reg;
 410         u_int32_t               val;
 411 {
 412 #ifdef SK_USEIOSPACE
 413         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 414         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 415 #else
 416         CSR_WRITE_4(sc, reg, val);
 417 #endif
 418         return;
 419 }
 420
 421 static void
 422 sk_win_write_2(sc, reg, val)
 423         struct sk_softc         *sc;
 424         int                     reg;
 425         u_int32_t               val;
 426 {
 427 #ifdef SK_USEIOSPACE
 428         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 429         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 430 #else
 431         CSR_WRITE_2(sc, reg, val);
 432 #endif
 433         return;
 434 }
 435
 436 static void
 437 sk_win_write_1(sc, reg, val)
 438         struct sk_softc         *sc;
 439         int                     reg;
 440         u_int32_t               val;
 441 {
 442 #ifdef SK_USEIOSPACE
 443         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 444         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 445 #else
 446         CSR_WRITE_1(sc, reg, val);
 447 #endif
 448         return;
 449 }
 450
 451 static int
 452 sk_miibus_readreg(dev, phy, reg)
 453         device_t                dev;
 454         int                     phy, reg;
 455 {
 456         struct sk_if_softc      *sc_if;
 457         int                     v;
 458
 459         sc_if = device_get_softc(dev);
 460
 461         SK_IF_MII_LOCK(sc_if);
 462         switch(sc_if->sk_softc->sk_type) {
 463         case SK_GENESIS:
 464                 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
 465                 break;
 466         case SK_YUKON:
 467         case SK_YUKON_LITE:
 468         case SK_YUKON_LP:
 469                 v = sk_marv_miibus_readreg(sc_if, phy, reg);
 470                 break;
 471         default:
 472                 v = 0;
 473                 break;
 474         }
 475         SK_IF_MII_UNLOCK(sc_if);
 476
 477         return (v);
 478 }
 479
 480 static int
 481 sk_miibus_writereg(dev, phy, reg, val)
 482         device_t                dev;
 483         int                     phy, reg, val;
 484 {
 485         struct sk_if_softc      *sc_if;
 486         int                     v;
 487
 488         sc_if = device_get_softc(dev);
 489
 490         SK_IF_MII_LOCK(sc_if);
 491         switch(sc_if->sk_softc->sk_type) {
 492         case SK_GENESIS:
 493                 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
 494                 break;
 495         case SK_YUKON:
 496         case SK_YUKON_LITE:
 497         case SK_YUKON_LP:
 498                 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
 499                 break;
 500         default:
 501                 v = 0;
 502                 break;
 503         }
 504         SK_IF_MII_UNLOCK(sc_if);
 505
 506         return (v);
 507 }
 508
 509 static void
 510 sk_miibus_statchg(dev)
 511         device_t                dev;
 512 {
 513         struct sk_if_softc      *sc_if;
 514
 515         sc_if = device_get_softc(dev);
 516
 517         SK_IF_MII_LOCK(sc_if);
 518         switch(sc_if->sk_softc->sk_type) {
 519         case SK_GENESIS:
 520                 sk_xmac_miibus_statchg(sc_if);
 521                 break;
 522         case SK_YUKON:
 523         case SK_YUKON_LITE:
 524         case SK_YUKON_LP:
 525                 sk_marv_miibus_statchg(sc_if);
 526                 break;
 527         }
 528         SK_IF_MII_UNLOCK(sc_if);
 529
 530         return;
 531 }
 532
 533 static int
 534 sk_xmac_miibus_readreg(sc_if, phy, reg)
 535         struct sk_if_softc      *sc_if;
 536         int                     phy, reg;
 537 {
 538         int                     i;
 539
 540         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 541         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 542         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 543                 for (i = 0; i < SK_TIMEOUT; i++) {
 544                         DELAY(1);
 545                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 546                             XM_MMUCMD_PHYDATARDY)
 547                                 break;
 548                 }
 549
 550                 if (i == SK_TIMEOUT) {
 551                         if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 552                         return(0);
 553                 }
 554         }
 555         DELAY(1);
 556         i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
 557
 558         return(i);
 559 }
 560
 561 static int
 562 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 563         struct sk_if_softc      *sc_if;
 564         int                     phy, reg, val;
 565 {
 566         int                     i;
 567
 568         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 569         for (i = 0; i < SK_TIMEOUT; i++) {
 570                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 571                         break;
 572         }
 573
 574         if (i == SK_TIMEOUT) {
 575                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 576                 return (ETIMEDOUT);
 577         }
 578
 579         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 580         for (i = 0; i < SK_TIMEOUT; i++) {
 581                 DELAY(1);
 582                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 583                         break;
 584         }
 585         if (i == SK_TIMEOUT)
 586                 if_printf(sc_if->sk_ifp, "phy write timed out\n");
 587
 588         return(0);
 589 }
 590
 591 static void
 592 sk_xmac_miibus_statchg(sc_if)
 593         struct sk_if_softc      *sc_if;
 594 {
 595         struct mii_data         *mii;
 596
 597         mii = device_get_softc(sc_if->sk_miibus);
 598
 599         /*
 600          * If this is a GMII PHY, manually set the XMAC's
 601          * duplex mode accordingly.
 602          */
 603         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 604                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 605                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 606                 } else {
 607                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 608                 }
 609         }
 610 }
 611
 612 static int
 613 sk_marv_miibus_readreg(sc_if, phy, reg)
 614         struct sk_if_softc      *sc_if;
 615         int                     phy, reg;
 616 {
 617         u_int16_t               val;
 618         int                     i;
 619
 620         if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 621             sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
 622                 return(0);
 623         }
 624
 625         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 626                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 627
 628         for (i = 0; i < SK_TIMEOUT; i++) {
 629                 DELAY(1);
 630                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 631                 if (val & YU_SMICR_READ_VALID)
 632                         break;
 633         }
 634
 635         if (i == SK_TIMEOUT) {
 636                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 637                 return(0);
 638         }
 639
 640         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 641
 642         return(val);
 643 }
 644
 645 static int
 646 sk_marv_miibus_writereg(sc_if, phy, reg, val)
 647         struct sk_if_softc      *sc_if;
 648         int                     phy, reg, val;
 649 {
 650         int                     i;
 651
 652         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 653         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 654                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 655
 656         for (i = 0; i < SK_TIMEOUT; i++) {
 657                 DELAY(1);
 658                 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
 659                         break;
 660         }
 661         if (i == SK_TIMEOUT)
 662                 if_printf(sc_if->sk_ifp, "phy write timeout\n");
 663
 664         return(0);
 665 }
 666
 667 static void
 668 sk_marv_miibus_statchg(sc_if)
 669         struct sk_if_softc      *sc_if;
 670 {
 671         return;
 672 }
 673
 674 #define HASH_BITS               6
 675
 676 static u_int32_t
 677 sk_xmchash(addr)
 678         const uint8_t *addr;
 679 {
 680         uint32_t crc;
 681
 682         /* Compute CRC for the address value. */
 683         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 684
 685         return (~crc & ((1 << HASH_BITS) - 1));
 686 }
 687
 688 static void
 689 sk_setfilt(sc_if, addr, slot)
 690         struct sk_if_softc      *sc_if;
 691         u_int16_t               *addr;
 692         int                     slot;
 693 {
 694         int                     base;
 695
 696         base = XM_RXFILT_ENTRY(slot);
 697
 698         SK_XM_WRITE_2(sc_if, base, addr[0]);
 699         SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
 700         SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
 701
 702         return;
 703 }
 704
 705 static void
 706 sk_rxfilter(sc_if)
 707         struct sk_if_softc      *sc_if;
 708 {
 709         struct sk_softc         *sc;
 710
 711         SK_IF_LOCK_ASSERT(sc_if);
 712
 713         sc = sc_if->sk_softc;
 714         if (sc->sk_type == SK_GENESIS)
 715                 sk_rxfilter_genesis(sc_if);
 716         else
 717                 sk_rxfilter_yukon(sc_if);
 718 }
 719
 720 static void
 721 sk_rxfilter_genesis(sc_if)
 722         struct sk_if_softc      *sc_if;
 723 {
 724         struct ifnet            *ifp = sc_if->sk_ifp;
 725         u_int32_t               hashes[2] = { 0, 0 }, mode;
 726         int                     h = 0, i;
 727         struct ifmultiaddr      *ifma;
 728         u_int16_t               dummy[] = { 0, 0, 0 };
 729         u_int16_t               maddr[(ETHER_ADDR_LEN+1)/2];
 730
 731         SK_IF_LOCK_ASSERT(sc_if);
 732
 733         mode = SK_XM_READ_4(sc_if, XM_MODE);
 734         mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
 735             XM_MODE_RX_USE_PERFECT);
 736         /* First, zot all the existing perfect filters. */
 737         for (i = 1; i < XM_RXFILT_MAX; i++)
 738                 sk_setfilt(sc_if, dummy, i);
 739
 740         /* Now program new ones. */
 741         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 742                 if (ifp->if_flags & IFF_ALLMULTI)
 743                         mode |= XM_MODE_RX_USE_HASH;
 744                 if (ifp->if_flags & IFF_PROMISC)
 745                         mode |= XM_MODE_RX_PROMISC;
 746                 hashes[0] = 0xFFFFFFFF;
 747                 hashes[1] = 0xFFFFFFFF;
 748         } else {
 749                 i = 1;
 750                 if_maddr_rlock(ifp);
 751                 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
 752                     ifma_link) {
 753                         if (ifma->ifma_addr->sa_family != AF_LINK)
 754                                 continue;
 755                         /*
 756                          * Program the first XM_RXFILT_MAX multicast groups
 757                          * into the perfect filter.
 758                          */
 759                         bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 760                             maddr, ETHER_ADDR_LEN);
 761                         if (i < XM_RXFILT_MAX) {
 762                                 sk_setfilt(sc_if, maddr, i);
 763                                 mode |= XM_MODE_RX_USE_PERFECT;
 764                                 i++;
 765                                 continue;
 766                         }
 767                         h = sk_xmchash((const uint8_t *)maddr);
 768                         if (h < 32)
 769                                 hashes[0] |= (1 << h);
 770                         else
 771                                 hashes[1] |= (1 << (h - 32));
 772                         mode |= XM_MODE_RX_USE_HASH;
 773                 }
 774                 if_maddr_runlock(ifp);
 775         }
 776
 777         SK_XM_WRITE_4(sc_if, XM_MODE, mode);
 778         SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 779         SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 780 }
 781
 782 static void
 783 sk_rxfilter_yukon(sc_if)
 784         struct sk_if_softc      *sc_if;
 785 {
 786         struct ifnet            *ifp;
 787         u_int32_t               crc, hashes[2] = { 0, 0 }, mode;
 788         struct ifmultiaddr      *ifma;
 789
 790         SK_IF_LOCK_ASSERT(sc_if);
 791
 792         ifp = sc_if->sk_ifp;
 793         mode = SK_YU_READ_2(sc_if, YUKON_RCR);
 794         if (ifp->if_flags & IFF_PROMISC)
 795                 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
 796         else if (ifp->if_flags & IFF_ALLMULTI) {
 797                 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
 798                 hashes[0] = 0xFFFFFFFF;
 799                 hashes[1] = 0xFFFFFFFF;
 800         } else {
 801                 mode |= YU_RCR_UFLEN;
 802                 if_maddr_rlock(ifp);
 803                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 804                         if (ifma->ifma_addr->sa_family != AF_LINK)
 805                                 continue;
 806                         crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 807                             ifma->ifma_addr), ETHER_ADDR_LEN);
 808                         /* Just want the 6 least significant bits. */
 809                         crc &= 0x3f;
 810                         /* Set the corresponding bit in the hash table. */
 811                         hashes[crc >> 5] |= 1 << (crc & 0x1f);
 812                 }
 813                 if_maddr_runlock(ifp);
 814                 if (hashes[0] != 0 || hashes[1] != 0)
 815                         mode |= YU_RCR_MUFLEN;
 816         }
 817
 818         SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 819         SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 820         SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 821         SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 822         SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
 823 }
 824
 825 static int
 826 sk_init_rx_ring(sc_if)
 827         struct sk_if_softc      *sc_if;
 828 {
 829         struct sk_ring_data     *rd;
 830         bus_addr_t              addr;
 831         u_int32_t               csum_start;
 832         int                     i;
 833
 834         sc_if->sk_cdata.sk_rx_cons = 0;
 835
 836         csum_start = (ETHER_HDR_LEN + sizeof(struct ip))  << 16 |
 837             ETHER_HDR_LEN;
 838         rd = &sc_if->sk_rdata;
 839         bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 840         for (i = 0; i < SK_RX_RING_CNT; i++) {
 841                 if (sk_newbuf(sc_if, i) != 0)
 842                         return (ENOBUFS);
 843                 if (i == (SK_RX_RING_CNT - 1))
 844                         addr = SK_RX_RING_ADDR(sc_if, 0);
 845                 else
 846                         addr = SK_RX_RING_ADDR(sc_if, i + 1);
 847                 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 848                 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
 849         }
 850
 851         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
 852             sc_if->sk_cdata.sk_rx_ring_map,
 853             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 854
 855         return(0);
 856 }
 857
 858 static int
 859 sk_init_jumbo_rx_ring(sc_if)
 860         struct sk_if_softc      *sc_if;
 861 {
 862         struct sk_ring_data     *rd;
 863         bus_addr_t              addr;
 864         u_int32_t               csum_start;
 865         int                     i;
 866
 867         sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
 868
 869         csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
 870             ETHER_HDR_LEN;
 871         rd = &sc_if->sk_rdata;
 872         bzero(rd->sk_jumbo_rx_ring,
 873             sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
 874         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
 875                 if (sk_jumbo_newbuf(sc_if, i) != 0)
 876                         return (ENOBUFS);
 877                 if (i == (SK_JUMBO_RX_RING_CNT - 1))
 878                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
 879                 else
 880                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
 881                 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 882                 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
 883         }
 884
 885         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
 886             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
 887             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 888
 889         return (0);
 890 }
 891
 892 static void
 893 sk_init_tx_ring(sc_if)
 894         struct sk_if_softc      *sc_if;
 895 {
 896         struct sk_ring_data     *rd;
 897         struct sk_txdesc        *txd;
 898         bus_addr_t              addr;
 899         int                     i;
 900
 901         STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
 902         STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
 903
 904         sc_if->sk_cdata.sk_tx_prod = 0;
 905         sc_if->sk_cdata.sk_tx_cons = 0;
 906         sc_if->sk_cdata.sk_tx_cnt = 0;
 907
 908         rd = &sc_if->sk_rdata;
 909         bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 910         for (i = 0; i < SK_TX_RING_CNT; i++) {
 911                 if (i == (SK_TX_RING_CNT - 1))
 912                         addr = SK_TX_RING_ADDR(sc_if, 0);
 913                 else
 914                         addr = SK_TX_RING_ADDR(sc_if, i + 1);
 915                 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 916                 txd = &sc_if->sk_cdata.sk_txdesc[i];
 917                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
 918         }
 919
 920         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
 921             sc_if->sk_cdata.sk_tx_ring_map,
 922             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 923 }
 924
 925 static __inline void
 926 sk_discard_rxbuf(sc_if, idx)
 927         struct sk_if_softc      *sc_if;
 928         int                     idx;
 929 {
 930         struct sk_rx_desc       *r;
 931         struct sk_rxdesc        *rxd;
 932         struct mbuf             *m;
 933
 934
 935         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 936         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 937         m = rxd->rx_m;
 938         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 939 }
 940
 941 static __inline void
 942 sk_discard_jumbo_rxbuf(sc_if, idx)
 943         struct sk_if_softc      *sc_if;
 944         int                     idx;
 945 {
 946         struct sk_rx_desc       *r;
 947         struct sk_rxdesc        *rxd;
 948         struct mbuf             *m;
 949
 950         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
 951         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
 952         m = rxd->rx_m;
 953         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 954 }
 955
 956 static int
 957 sk_newbuf(sc_if, idx)
 958         struct sk_if_softc      *sc_if;
 959         int                     idx;
 960 {
 961         struct sk_rx_desc       *r;
 962         struct sk_rxdesc        *rxd;
 963         struct mbuf             *m;
 964         bus_dma_segment_t       segs[1];
 965         bus_dmamap_t            map;
 966         int                     nsegs;
 967
 968         m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
 969         if (m == NULL)
 970                 return (ENOBUFS);
 971         m->m_len = m->m_pkthdr.len = MCLBYTES;
 972         m_adj(m, ETHER_ALIGN);
 973
 974         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
 975             sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
 976                 m_freem(m);
 977                 return (ENOBUFS);
 978         }
 979         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 980
 981         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 982         if (rxd->rx_m != NULL) {
 983                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 984                     BUS_DMASYNC_POSTREAD);
 985                 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
 986         }
 987         map = rxd->rx_dmamap;
 988         rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
 989         sc_if->sk_cdata.sk_rx_sparemap = map;
 990         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 991             BUS_DMASYNC_PREREAD);
 992         rxd->rx_m = m;
 993         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 994         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
 995         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
 996         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
 997
 998         return (0);
 999 }
1000
1001 static int
1002 sk_jumbo_newbuf(sc_if, idx)
1003         struct sk_if_softc      *sc_if;
1004         int                     idx;
1005 {
1006         struct sk_rx_desc       *r;
1007         struct sk_rxdesc        *rxd;
1008         struct mbuf             *m;
1009         bus_dma_segment_t       segs[1];
1010         bus_dmamap_t            map;
1011         int                     nsegs;
1012
1013         m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1014         if (m == NULL)
1015                 return (ENOBUFS);
1016         if ((m->m_flags & M_EXT) == 0) {
1017                 m_freem(m);
1018                 return (ENOBUFS);
1019         }
1020         m->m_pkthdr.len = m->m_len = MJUM9BYTES;
1021         /*
1022          * Adjust alignment so packet payload begins on a
1023          * longword boundary. Mandatory for Alpha, useful on
1024          * x86 too.
1025          */
1026         m_adj(m, ETHER_ALIGN);
1027
1028         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1029             sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1030                 m_freem(m);
1031                 return (ENOBUFS);
1032         }
1033         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1034
1035         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1036         if (rxd->rx_m != NULL) {
1037                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1038                     BUS_DMASYNC_POSTREAD);
1039                 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1040                     rxd->rx_dmamap);
1041         }
1042         map = rxd->rx_dmamap;
1043         rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1044         sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1045         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1046             BUS_DMASYNC_PREREAD);
1047         rxd->rx_m = m;
1048         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1049         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1050         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1051         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1052
1053         return (0);
1054 }
1055
1056 /*
1057  * Set media options.
1058  */
1059 static int
1060 sk_ifmedia_upd(ifp)
1061         struct ifnet            *ifp;
1062 {
1063         struct sk_if_softc      *sc_if = ifp->if_softc;
1064         struct mii_data         *mii;
1065
1066         mii = device_get_softc(sc_if->sk_miibus);
1067         sk_init(sc_if);
1068         mii_mediachg(mii);
1069
1070         return(0);
1071 }
1072
1073 /*
1074  * Report current media status.
1075  */
1076 static void
1077 sk_ifmedia_sts(ifp, ifmr)
1078         struct ifnet            *ifp;
1079         struct ifmediareq       *ifmr;
1080 {
1081         struct sk_if_softc      *sc_if;
1082         struct mii_data         *mii;
1083
1084         sc_if = ifp->if_softc;
1085         mii = device_get_softc(sc_if->sk_miibus);
1086
1087         mii_pollstat(mii);
1088         ifmr->ifm_active = mii->mii_media_active;
1089         ifmr->ifm_status = mii->mii_media_status;
1090
1091         return;
1092 }
1093
1094 static int
1095 sk_ioctl(ifp, command, data)
1096         struct ifnet            *ifp;
1097         u_long                  command;
1098         caddr_t                 data;
1099 {
1100         struct sk_if_softc      *sc_if = ifp->if_softc;
1101         struct ifreq            *ifr = (struct ifreq *) data;
1102         int                     error, mask;
1103         struct mii_data         *mii;
1104
1105         error = 0;
1106         switch(command) {
1107         case SIOCSIFMTU:
1108                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1109                         error = EINVAL;
1110                 else if (ifp->if_mtu != ifr->ifr_mtu) {
1111                         if (sc_if->sk_jumbo_disable != 0 &&
1112                             ifr->ifr_mtu > SK_MAX_FRAMELEN)
1113                                 error = EINVAL;
1114                         else {
1115                                 SK_IF_LOCK(sc_if);
1116                                 ifp->if_mtu = ifr->ifr_mtu;
1117                                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1118                                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1119                                         sk_init_locked(sc_if);
1120                                 }
1121                                 SK_IF_UNLOCK(sc_if);
1122                         }
1123                 }
1124                 break;
1125         case SIOCSIFFLAGS:
1126                 SK_IF_LOCK(sc_if);
1127                 if (ifp->if_flags & IFF_UP) {
1128                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1129                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1130                                     & (IFF_PROMISC | IFF_ALLMULTI))
1131                                         sk_rxfilter(sc_if);
1132                         } else
1133                                 sk_init_locked(sc_if);
1134                 } else {
1135                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1136                                 sk_stop(sc_if);
1137                 }
1138                 sc_if->sk_if_flags = ifp->if_flags;
1139                 SK_IF_UNLOCK(sc_if);
1140                 break;
1141         case SIOCADDMULTI:
1142         case SIOCDELMULTI:
1143                 SK_IF_LOCK(sc_if);
1144                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1145                         sk_rxfilter(sc_if);
1146                 SK_IF_UNLOCK(sc_if);
1147                 break;
1148         case SIOCGIFMEDIA:
1149         case SIOCSIFMEDIA:
1150                 mii = device_get_softc(sc_if->sk_miibus);
1151                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1152                 break;
1153         case SIOCSIFCAP:
1154                 SK_IF_LOCK(sc_if);
1155                 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1156                         SK_IF_UNLOCK(sc_if);
1157                         break;
1158                 }
1159                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1160                 if ((mask & IFCAP_TXCSUM) != 0 &&
1161                     (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1162                         ifp->if_capenable ^= IFCAP_TXCSUM;
1163                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1164                                 ifp->if_hwassist |= SK_CSUM_FEATURES;
1165                         else
1166                                 ifp->if_hwassist &= ~SK_CSUM_FEATURES;
1167                 }
1168                 if ((mask & IFCAP_RXCSUM) != 0 &&
1169                     (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
1170                         ifp->if_capenable ^= IFCAP_RXCSUM;
1171                 SK_IF_UNLOCK(sc_if);
1172                 break;
1173         default:
1174                 error = ether_ioctl(ifp, command, data);
1175                 break;
1176         }
1177
1178         return (error);
1179 }
1180
1181 /*
1182  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1183  * IDs against our list and return a device name if we find a match.
1184  */
1185 static int
1186 skc_probe(dev)
1187         device_t                dev;
1188 {
1189         struct sk_type          *t = sk_devs;
1190
1191         while(t->sk_name != NULL) {
1192                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1193                     (pci_get_device(dev) == t->sk_did)) {
1194                         /*
1195                          * Only attach to rev. 2 of the Linksys EG1032 adapter.
1196                          * Rev. 3 is supported by re(4).
1197                          */
1198                         if ((t->sk_vid == VENDORID_LINKSYS) &&
1199                                 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1200                                 (pci_get_subdevice(dev) !=
1201                                  SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1202                                 t++;
1203                                 continue;
1204                         }
1205                         device_set_desc(dev, t->sk_name);
1206                         return (BUS_PROBE_DEFAULT);
1207                 }
1208                 t++;
1209         }
1210
1211         return(ENXIO);
1212 }
1213
1214 /*
1215  * Force the GEnesis into reset, then bring it out of reset.
1216  */
1217 static void
1218 sk_reset(sc)
1219         struct sk_softc         *sc;
1220 {
1221
1222         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1223         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1224         if (SK_YUKON_FAMILY(sc->sk_type))
1225                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1226
1227         DELAY(1000);
1228         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1229         DELAY(2);
1230         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1231         if (SK_YUKON_FAMILY(sc->sk_type))
1232                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1233
1234         if (sc->sk_type == SK_GENESIS) {
1235                 /* Configure packet arbiter */
1236                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1237                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1238                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1239                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1240                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1241         }
1242
1243         /* Enable RAM interface */
1244         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1245
1246         /*
1247          * Configure interrupt moderation. The moderation timer
1248          * defers interrupts specified in the interrupt moderation
1249          * timer mask based on the timeout specified in the interrupt
1250          * moderation timer init register. Each bit in the timer
1251          * register represents one tick, so to specify a timeout in
1252          * microseconds, we have to multiply by the correct number of
1253          * ticks-per-microsecond.
1254          */
1255         switch (sc->sk_type) {
1256         case SK_GENESIS:
1257                 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1258                 break;
1259         default:
1260                 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1261                 break;
1262         }
1263         if (bootverbose)
1264                 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1265                     sc->sk_int_mod);
1266         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1267             sc->sk_int_ticks));
1268         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1269             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1270         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1271
1272         return;
1273 }
1274
1275 static int
1276 sk_probe(dev)
1277         device_t                dev;
1278 {
1279         struct sk_softc         *sc;
1280
1281         sc = device_get_softc(device_get_parent(dev));
1282
1283         /*
1284          * Not much to do here. We always know there will be
1285          * at least one XMAC present, and if there are two,
1286          * skc_attach() will create a second device instance
1287          * for us.
1288          */
1289         switch (sc->sk_type) {
1290         case SK_GENESIS:
1291                 device_set_desc(dev, "XaQti Corp. XMAC II");
1292                 break;
1293         case SK_YUKON:
1294         case SK_YUKON_LITE:
1295         case SK_YUKON_LP:
1296                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1297                 break;
1298         }
1299
1300         return (BUS_PROBE_DEFAULT);
1301 }
1302
1303 /*
1304  * Each XMAC chip is attached as a separate logical IP interface.
1305  * Single port cards will have only one logical interface of course.
1306  */
1307 static int
1308 sk_attach(dev)
1309         device_t                dev;
1310 {
1311         struct sk_softc         *sc;
1312         struct sk_if_softc      *sc_if;
1313         struct ifnet            *ifp;
1314         u_int32_t               r;
1315         int                     error, i, phy, port;
1316         u_char                  eaddr[6];
1317         u_char                  inv_mac[] = {0, 0, 0, 0, 0, 0};
1318
1319         if (dev == NULL)
1320                 return(EINVAL);
1321
1322         error = 0;
1323         sc_if = device_get_softc(dev);
1324         sc = device_get_softc(device_get_parent(dev));
1325         port = *(int *)device_get_ivars(dev);
1326
1327         sc_if->sk_if_dev = dev;
1328         sc_if->sk_port = port;
1329         sc_if->sk_softc = sc;
1330         sc->sk_if[port] = sc_if;
1331         if (port == SK_PORT_A)
1332                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1333         if (port == SK_PORT_B)
1334                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1335
1336         callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1337         callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1338
1339         if (sk_dma_alloc(sc_if) != 0) {
1340                 error = ENOMEM;
1341                 goto fail;
1342         }
1343         sk_dma_jumbo_alloc(sc_if);
1344
1345         ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1346         if (ifp == NULL) {
1347                 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1348                 error = ENOSPC;
1349                 goto fail;
1350         }
1351         ifp->if_softc = sc_if;
1352         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1353         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1354         /*
1355          * SK_GENESIS has a bug in checksum offload - From linux.
1356          */
1357         if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1358                 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
1359                 ifp->if_hwassist = 0;
1360         } else {
1361                 ifp->if_capabilities = 0;
1362                 ifp->if_hwassist = 0;
1363         }
1364         ifp->if_capenable = ifp->if_capabilities;
1365         /*
1366          * Some revision of Yukon controller generates corrupted
1367          * frame when TX checksum offloading is enabled.  The
1368          * frame has a valid checksum value so payload might be
1369          * modified during TX checksum calculation. Disable TX
1370          * checksum offloading but give users chance to enable it
1371          * when they know their controller works without problems
1372          * with TX checksum offloading.
1373          */
1374         ifp->if_capenable &= ~IFCAP_TXCSUM;
1375         ifp->if_ioctl = sk_ioctl;
1376         ifp->if_start = sk_start;
1377         ifp->if_init = sk_init;
1378         IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1379         ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1380         IFQ_SET_READY(&ifp->if_snd);
1381
1382         /*
1383          * Get station address for this interface. Note that
1384          * dual port cards actually come with three station
1385          * addresses: one for each port, plus an extra. The
1386          * extra one is used by the SysKonnect driver software
1387          * as a 'virtual' station address for when both ports
1388          * are operating in failover mode. Currently we don't
1389          * use this extra address.
1390          */
1391         SK_IF_LOCK(sc_if);
1392         for (i = 0; i < ETHER_ADDR_LEN; i++)
1393                 eaddr[i] =
1394                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1395
1396         /* Verify whether the station address is invalid or not. */
1397         if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1398                 device_printf(sc_if->sk_if_dev,
1399                     "Generating random ethernet address\n");
1400                 r = arc4random();
1401                 /*
1402                  * Set OUI to convenient locally assigned address.  'b'
1403                  * is 0x62, which has the locally assigned bit set, and
1404                  * the broadcast/multicast bit clear.
1405                  */
1406                 eaddr[0] = 'b';
1407                 eaddr[1] = 's';
1408                 eaddr[2] = 'd';
1409                 eaddr[3] = (r >> 16) & 0xff;
1410                 eaddr[4] = (r >>  8) & 0xff;
1411                 eaddr[5] = (r >>  0) & 0xff;
1412         }
1413         /*
1414          * Set up RAM buffer addresses. The NIC will have a certain
1415          * amount of SRAM on it, somewhere between 512K and 2MB. We
1416          * need to divide this up a) between the transmitter and
1417          * receiver and b) between the two XMACs, if this is a
1418          * dual port NIC. Our algotithm is to divide up the memory
1419          * evenly so that everyone gets a fair share.
1420          *
1421          * Just to be contrary, Yukon2 appears to have separate memory
1422          * for each MAC.
1423          */
1424         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1425                 u_int32_t               chunk, val;
1426
1427                 chunk = sc->sk_ramsize / 2;
1428                 val = sc->sk_rboff / sizeof(u_int64_t);
1429                 sc_if->sk_rx_ramstart = val;
1430                 val += (chunk / sizeof(u_int64_t));
1431                 sc_if->sk_rx_ramend = val - 1;
1432                 sc_if->sk_tx_ramstart = val;
1433                 val += (chunk / sizeof(u_int64_t));
1434                 sc_if->sk_tx_ramend = val - 1;
1435         } else {
1436                 u_int32_t               chunk, val;
1437
1438                 chunk = sc->sk_ramsize / 4;
1439                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1440                     sizeof(u_int64_t);
1441                 sc_if->sk_rx_ramstart = val;
1442                 val += (chunk / sizeof(u_int64_t));
1443                 sc_if->sk_rx_ramend = val - 1;
1444                 sc_if->sk_tx_ramstart = val;
1445                 val += (chunk / sizeof(u_int64_t));
1446                 sc_if->sk_tx_ramend = val - 1;
1447         }
1448
1449         /* Read and save PHY type and set PHY address */
1450         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1451         if (!SK_YUKON_FAMILY(sc->sk_type)) {
1452                 switch(sc_if->sk_phytype) {
1453                 case SK_PHYTYPE_XMAC:
1454                         sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1455                         break;
1456                 case SK_PHYTYPE_BCOM:
1457                         sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1458                         break;
1459                 default:
1460                         device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1461                             sc_if->sk_phytype);
1462                         error = ENODEV;
1463                         SK_IF_UNLOCK(sc_if);
1464                         goto fail;
1465                 }
1466         } else {
1467                 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1468                     sc->sk_pmd != 'S') {
1469                         /* not initialized, punt */
1470                         sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1471                         sc->sk_coppertype = 1;
1472                 }
1473
1474                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1475
1476                 if (!(sc->sk_coppertype))
1477                         sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1478         }
1479
1480         /*
1481          * Call MI attach routine.  Can't hold locks when calling into ether_*.
1482          */
1483         SK_IF_UNLOCK(sc_if);
1484         ether_ifattach(ifp, eaddr);
1485         SK_IF_LOCK(sc_if);
1486
1487         /*
1488          * The hardware should be ready for VLAN_MTU by default:
1489          * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1490          * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1491          *
1492          */
1493         ifp->if_capabilities |= IFCAP_VLAN_MTU;
1494         ifp->if_capenable |= IFCAP_VLAN_MTU;
1495         /*
1496          * Tell the upper layer(s) we support long frames.
1497          * Must appear after the call to ether_ifattach() because
1498          * ether_ifattach() sets ifi_hdrlen to the default value.
1499          */
1500         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1501
1502         /*
1503          * Do miibus setup.
1504          */
1505         phy = MII_PHY_ANY;
1506         switch (sc->sk_type) {
1507         case SK_GENESIS:
1508                 sk_init_xmac(sc_if);
1509                 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1510                         phy = 0;
1511                 break;
1512         case SK_YUKON:
1513         case SK_YUKON_LITE:
1514         case SK_YUKON_LP:
1515                 sk_init_yukon(sc_if);
1516                 phy = 0;
1517                 break;
1518         }
1519
1520         SK_IF_UNLOCK(sc_if);
1521         error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1522             sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1523         if (error != 0) {
1524                 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1525                 ether_ifdetach(ifp);
1526                 goto fail;
1527         }
1528
1529 fail:
1530         if (error) {
1531                 /* Access should be ok even though lock has been dropped */
1532                 sc->sk_if[port] = NULL;
1533                 sk_detach(dev);
1534         }
1535
1536         return(error);
1537 }
1538
1539 /*
1540  * Attach the interface. Allocate softc structures, do ifmedia
1541  * setup and ethernet/BPF attach.
1542  */
1543 static int
1544 skc_attach(dev)
1545         device_t                dev;
1546 {
1547         struct sk_softc         *sc;
1548         int                     error = 0, *port;
1549         uint8_t                 skrs;
1550         const char              *pname = NULL;
1551         char                    *revstr;
1552
1553         sc = device_get_softc(dev);
1554         sc->sk_dev = dev;
1555
1556         mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1557             MTX_DEF);
1558         mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1559         /*
1560          * Map control/status registers.
1561          */
1562         pci_enable_busmaster(dev);
1563
1564         /* Allocate resources */
1565 #ifdef SK_USEIOSPACE
1566         sc->sk_res_spec = sk_res_spec_io;
1567 #else
1568         sc->sk_res_spec = sk_res_spec_mem;
1569 #endif
1570         error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1571         if (error) {
1572                 if (sc->sk_res_spec == sk_res_spec_mem)
1573                         sc->sk_res_spec = sk_res_spec_io;
1574                 else
1575                         sc->sk_res_spec = sk_res_spec_mem;
1576                 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1577                 if (error) {
1578                         device_printf(dev, "couldn't allocate %s resources\n",
1579                             sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1580                             "I/O");
1581                         goto fail;
1582                 }
1583         }
1584
1585         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1586         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1587
1588         /* Bail out if chip is not recognized. */
1589         if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1590                 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1591                     sc->sk_type, sc->sk_rev);
1592                 error = ENXIO;
1593                 goto fail;
1594         }
1595
1596         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1597                 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1598                 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1599                 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1600                 "SK interrupt moderation");
1601
1602         /* Pull in device tunables. */
1603         sc->sk_int_mod = SK_IM_DEFAULT;
1604         error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1605                 "int_mod", &sc->sk_int_mod);
1606         if (error == 0) {
1607                 if (sc->sk_int_mod < SK_IM_MIN ||
1608                     sc->sk_int_mod > SK_IM_MAX) {
1609                         device_printf(dev, "int_mod value out of range; "
1610                             "using default: %d\n", SK_IM_DEFAULT);
1611                         sc->sk_int_mod = SK_IM_DEFAULT;
1612                 }
1613         }
1614
1615         /* Reset the adapter. */
1616         sk_reset(sc);
1617
1618         skrs = sk_win_read_1(sc, SK_EPROM0);
1619         if (sc->sk_type == SK_GENESIS) {
1620                 /* Read and save RAM size and RAMbuffer offset */
1621                 switch(skrs) {
1622                 case SK_RAMSIZE_512K_64:
1623                         sc->sk_ramsize = 0x80000;
1624                         sc->sk_rboff = SK_RBOFF_0;
1625                         break;
1626                 case SK_RAMSIZE_1024K_64:
1627                         sc->sk_ramsize = 0x100000;
1628                         sc->sk_rboff = SK_RBOFF_80000;
1629                         break;
1630                 case SK_RAMSIZE_1024K_128:
1631                         sc->sk_ramsize = 0x100000;
1632                         sc->sk_rboff = SK_RBOFF_0;
1633                         break;
1634                 case SK_RAMSIZE_2048K_128:
1635                         sc->sk_ramsize = 0x200000;
1636                         sc->sk_rboff = SK_RBOFF_0;
1637                         break;
1638                 default:
1639                         device_printf(dev, "unknown ram size: %d\n", skrs);
1640                         error = ENXIO;
1641                         goto fail;
1642                 }
1643         } else { /* SK_YUKON_FAMILY */
1644                 if (skrs == 0x00)
1645                         sc->sk_ramsize = 0x20000;
1646                 else
1647                         sc->sk_ramsize = skrs * (1<<12);
1648                 sc->sk_rboff = SK_RBOFF_0;
1649         }
1650
1651         /* Read and save physical media type */
1652          sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1653
1654          if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1655                  sc->sk_coppertype = 1;
1656          else
1657                  sc->sk_coppertype = 0;
1658
1659         /* Determine whether to name it with VPD PN or just make it up.
1660          * Marvell Yukon VPD PN seems to freqently be bogus. */
1661         switch (pci_get_device(dev)) {
1662         case DEVICEID_SK_V1:
1663         case DEVICEID_BELKIN_5005:
1664         case DEVICEID_3COM_3C940:
1665         case DEVICEID_LINKSYS_EG1032:
1666         case DEVICEID_DLINK_DGE530T_A1:
1667         case DEVICEID_DLINK_DGE530T_B1:
1668                 /* Stay with VPD PN. */
1669                 (void) pci_get_vpd_ident(dev, &pname);
1670                 break;
1671         case DEVICEID_SK_V2:
1672                 /* YUKON VPD PN might bear no resemblance to reality. */
1673                 switch (sc->sk_type) {
1674                 case SK_GENESIS:
1675                         /* Stay with VPD PN. */
1676                         (void) pci_get_vpd_ident(dev, &pname);
1677                         break;
1678                 case SK_YUKON:
1679                         pname = "Marvell Yukon Gigabit Ethernet";
1680                         break;
1681                 case SK_YUKON_LITE:
1682                         pname = "Marvell Yukon Lite Gigabit Ethernet";
1683                         break;
1684                 case SK_YUKON_LP:
1685                         pname = "Marvell Yukon LP Gigabit Ethernet";
1686                         break;
1687                 default:
1688                         pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1689                         break;
1690                 }
1691
1692                 /* Yukon Lite Rev. A0 needs special test. */
1693                 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1694                         u_int32_t far;
1695                         u_int8_t testbyte;
1696
1697                         /* Save flash address register before testing. */
1698                         far = sk_win_read_4(sc, SK_EP_ADDR);
1699
1700                         sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1701                         testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1702
1703                         if (testbyte != 0x00) {
1704                                 /* Yukon Lite Rev. A0 detected. */
1705                                 sc->sk_type = SK_YUKON_LITE;
1706                                 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1707                                 /* Restore flash address register. */
1708                                 sk_win_write_4(sc, SK_EP_ADDR, far);
1709                         }
1710                 }
1711                 break;
1712         default:
1713                 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1714                         "chipver=%02x, rev=%x\n",
1715                         pci_get_vendor(dev), pci_get_device(dev),
1716                         sc->sk_type, sc->sk_rev);
1717                 error = ENXIO;
1718                 goto fail;
1719         }
1720
1721         if (sc->sk_type == SK_YUKON_LITE) {
1722                 switch (sc->sk_rev) {
1723                 case SK_YUKON_LITE_REV_A0:
1724                         revstr = "A0";
1725                         break;
1726                 case SK_YUKON_LITE_REV_A1:
1727                         revstr = "A1";
1728                         break;
1729                 case SK_YUKON_LITE_REV_A3:
1730                         revstr = "A3";
1731                         break;
1732                 default:
1733                         revstr = "";
1734                         break;
1735                 }
1736         } else {
1737                 revstr = "";
1738         }
1739
1740         /* Announce the product name and more VPD data if there. */
1741         if (pname != NULL)
1742                 device_printf(dev, "%s rev. %s(0x%x)\n",
1743                         pname, revstr, sc->sk_rev);
1744
1745         if (bootverbose) {
1746                 device_printf(dev, "chip ver  = 0x%02x\n", sc->sk_type);
1747                 device_printf(dev, "chip rev  = 0x%02x\n", sc->sk_rev);
1748                 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1749                 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1750         }
1751
1752         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1753         if (sc->sk_devs[SK_PORT_A] == NULL) {
1754                 device_printf(dev, "failed to add child for PORT_A\n");
1755                 error = ENXIO;
1756                 goto fail;
1757         }
1758         port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1759         if (port == NULL) {
1760                 device_printf(dev, "failed to allocate memory for "
1761                     "ivars of PORT_A\n");
1762                 error = ENXIO;
1763                 goto fail;
1764         }
1765         *port = SK_PORT_A;
1766         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1767
1768         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1769                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1770                 if (sc->sk_devs[SK_PORT_B] == NULL) {
1771                         device_printf(dev, "failed to add child for PORT_B\n");
1772                         error = ENXIO;
1773                         goto fail;
1774                 }
1775                 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1776                 if (port == NULL) {
1777                         device_printf(dev, "failed to allocate memory for "
1778                             "ivars of PORT_B\n");
1779                         error = ENXIO;
1780                         goto fail;
1781                 }
1782                 *port = SK_PORT_B;
1783                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1784         }
1785
1786         /* Turn on the 'driver is loaded' LED. */
1787         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1788
1789         error = bus_generic_attach(dev);
1790         if (error) {
1791                 device_printf(dev, "failed to attach port(s)\n");
1792                 goto fail;
1793         }
1794
1795         /* Hook interrupt last to avoid having to lock softc */
1796         error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1797             NULL, sk_intr, sc, &sc->sk_intrhand);
1798
1799         if (error) {
1800                 device_printf(dev, "couldn't set up irq\n");
1801                 goto fail;
1802         }
1803
1804 fail:
1805         if (error)
1806                 skc_detach(dev);
1807
1808         return(error);
1809 }
1810
1811 /*
1812  * Shutdown hardware and free up resources. This can be called any
1813  * time after the mutex has been initialized. It is called in both
1814  * the error case in attach and the normal detach case so it needs
1815  * to be careful about only freeing resources that have actually been
1816  * allocated.
1817  */
1818 static int
1819 sk_detach(dev)
1820         device_t                dev;
1821 {
1822         struct sk_if_softc      *sc_if;
1823         struct ifnet            *ifp;
1824
1825         sc_if = device_get_softc(dev);
1826         KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1827             ("sk mutex not initialized in sk_detach"));
1828         SK_IF_LOCK(sc_if);
1829
1830         ifp = sc_if->sk_ifp;
1831         /* These should only be active if attach_xmac succeeded */
1832         if (device_is_attached(dev)) {
1833                 sk_stop(sc_if);
1834                 /* Can't hold locks while calling detach */
1835                 SK_IF_UNLOCK(sc_if);
1836                 callout_drain(&sc_if->sk_tick_ch);
1837                 callout_drain(&sc_if->sk_watchdog_ch);
1838                 ether_ifdetach(ifp);
1839                 SK_IF_LOCK(sc_if);
1840         }
1841         if (ifp)
1842                 if_free(ifp);
1843         /*
1844          * We're generally called from skc_detach() which is using
1845          * device_delete_child() to get to here. It's already trashed
1846          * miibus for us, so don't do it here or we'll panic.
1847          */
1848         /*
1849         if (sc_if->sk_miibus != NULL)
1850                 device_delete_child(dev, sc_if->sk_miibus);
1851         */
1852         bus_generic_detach(dev);
1853         sk_dma_jumbo_free(sc_if);
1854         sk_dma_free(sc_if);
1855         SK_IF_UNLOCK(sc_if);
1856
1857         return(0);
1858 }
1859
1860 static int
1861 skc_detach(dev)
1862         device_t                dev;
1863 {
1864         struct sk_softc         *sc;
1865
1866         sc = device_get_softc(dev);
1867         KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1868
1869         if (device_is_alive(dev)) {
1870                 if (sc->sk_devs[SK_PORT_A] != NULL) {
1871                         free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1872                         device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1873                 }
1874                 if (sc->sk_devs[SK_PORT_B] != NULL) {
1875                         free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1876                         device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1877                 }
1878                 bus_generic_detach(dev);
1879         }
1880
1881         if (sc->sk_intrhand)
1882                 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1883         bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1884
1885         mtx_destroy(&sc->sk_mii_mtx);
1886         mtx_destroy(&sc->sk_mtx);
1887
1888         return(0);
1889 }
1890
1891 struct sk_dmamap_arg {
1892         bus_addr_t      sk_busaddr;
1893 };
1894
1895 static void
1896 sk_dmamap_cb(arg, segs, nseg, error)
1897         void                    *arg;
1898         bus_dma_segment_t       *segs;
1899         int                     nseg;
1900         int                     error;
1901 {
1902         struct sk_dmamap_arg    *ctx;
1903
1904         if (error != 0)
1905                 return;
1906
1907         ctx = arg;
1908         ctx->sk_busaddr = segs[0].ds_addr;
1909 }
1910
1911 /*
1912  * Allocate jumbo buffer storage. The SysKonnect adapters support
1913  * "jumbograms" (9K frames), although SysKonnect doesn't currently
1914  * use them in their drivers. In order for us to use them, we need
1915  * large 9K receive buffers, however standard mbuf clusters are only
1916  * 2048 bytes in size. Consequently, we need to allocate and manage
1917  * our own jumbo buffer pool. Fortunately, this does not require an
1918  * excessive amount of additional code.
1919  */
1920 static int
1921 sk_dma_alloc(sc_if)
1922         struct sk_if_softc      *sc_if;
1923 {
1924         struct sk_dmamap_arg    ctx;
1925         struct sk_txdesc        *txd;
1926         struct sk_rxdesc        *rxd;
1927         int                     error, i;
1928
1929         /* create parent tag */
1930         /*
1931          * XXX
1932          * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1933          * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1934          * However bz@ reported that it does not work on amd64 with > 4GB
1935          * RAM. Until we have more clues of the breakage, disable DAC mode
1936          * by limiting DMA address to be in 32bit address space.
1937          */
1938         error = bus_dma_tag_create(
1939                     bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1940                     1, 0,                       /* algnmnt, boundary */
1941                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1942                     BUS_SPACE_MAXADDR,          /* highaddr */
1943                     NULL, NULL,                 /* filter, filterarg */
1944                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1945                     0,                          /* nsegments */
1946                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1947                     0,                          /* flags */
1948                     NULL, NULL,                 /* lockfunc, lockarg */
1949                     &sc_if->sk_cdata.sk_parent_tag);
1950         if (error != 0) {
1951                 device_printf(sc_if->sk_if_dev,
1952                     "failed to create parent DMA tag\n");
1953                 goto fail;
1954         }
1955
1956         /* create tag for Tx ring */
1957         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1958                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1959                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1960                     BUS_SPACE_MAXADDR,          /* highaddr */
1961                     NULL, NULL,                 /* filter, filterarg */
1962                     SK_TX_RING_SZ,              /* maxsize */
1963                     1,                          /* nsegments */
1964                     SK_TX_RING_SZ,              /* maxsegsize */
1965                     0,                          /* flags */
1966                     NULL, NULL,                 /* lockfunc, lockarg */
1967                     &sc_if->sk_cdata.sk_tx_ring_tag);
1968         if (error != 0) {
1969                 device_printf(sc_if->sk_if_dev,
1970                     "failed to allocate Tx ring DMA tag\n");
1971                 goto fail;
1972         }
1973
1974         /* create tag for Rx ring */
1975         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1976                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1977                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1978                     BUS_SPACE_MAXADDR,          /* highaddr */
1979                     NULL, NULL,                 /* filter, filterarg */
1980                     SK_RX_RING_SZ,              /* maxsize */
1981                     1,                          /* nsegments */
1982                     SK_RX_RING_SZ,              /* maxsegsize */
1983                     0,                          /* flags */
1984                     NULL, NULL,                 /* lockfunc, lockarg */
1985                     &sc_if->sk_cdata.sk_rx_ring_tag);
1986         if (error != 0) {
1987                 device_printf(sc_if->sk_if_dev,
1988                     "failed to allocate Rx ring DMA tag\n");
1989                 goto fail;
1990         }
1991
1992         /* create tag for Tx buffers */
1993         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1994                     1, 0,                       /* algnmnt, boundary */
1995                     BUS_SPACE_MAXADDR,          /* lowaddr */
1996                     BUS_SPACE_MAXADDR,          /* highaddr */
1997                     NULL, NULL,                 /* filter, filterarg */
1998                     MCLBYTES * SK_MAXTXSEGS,    /* maxsize */
1999                     SK_MAXTXSEGS,               /* nsegments */
2000                     MCLBYTES,                   /* maxsegsize */
2001                     0,                          /* flags */
2002                     NULL, NULL,                 /* lockfunc, lockarg */
2003                     &sc_if->sk_cdata.sk_tx_tag);
2004         if (error != 0) {
2005                 device_printf(sc_if->sk_if_dev,
2006                     "failed to allocate Tx DMA tag\n");
2007                 goto fail;
2008         }
2009
2010         /* create tag for Rx buffers */
2011         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2012                     1, 0,                       /* algnmnt, boundary */
2013                     BUS_SPACE_MAXADDR,          /* lowaddr */
2014                     BUS_SPACE_MAXADDR,          /* highaddr */
2015                     NULL, NULL,                 /* filter, filterarg */
2016                     MCLBYTES,                   /* maxsize */
2017                     1,                          /* nsegments */
2018                     MCLBYTES,                   /* maxsegsize */
2019                     0,                          /* flags */
2020                     NULL, NULL,                 /* lockfunc, lockarg */
2021                     &sc_if->sk_cdata.sk_rx_tag);
2022         if (error != 0) {
2023                 device_printf(sc_if->sk_if_dev,
2024                     "failed to allocate Rx DMA tag\n");
2025                 goto fail;
2026         }
2027
2028         /* allocate DMA'able memory and load the DMA map for Tx ring */
2029         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2030             (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
2031             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
2032         if (error != 0) {
2033                 device_printf(sc_if->sk_if_dev,
2034                     "failed to allocate DMA'able memory for Tx ring\n");
2035                 goto fail;
2036         }
2037
2038         ctx.sk_busaddr = 0;
2039         error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2040             sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2041             SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2042         if (error != 0) {
2043                 device_printf(sc_if->sk_if_dev,
2044                     "failed to load DMA'able memory for Tx ring\n");
2045                 goto fail;
2046         }
2047         sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2048
2049         /* allocate DMA'able memory and load the DMA map for Rx ring */
2050         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2051             (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
2052             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
2053         if (error != 0) {
2054                 device_printf(sc_if->sk_if_dev,
2055                     "failed to allocate DMA'able memory for Rx ring\n");
2056                 goto fail;
2057         }
2058
2059         ctx.sk_busaddr = 0;
2060         error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2061             sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2062             SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2063         if (error != 0) {
2064                 device_printf(sc_if->sk_if_dev,
2065                     "failed to load DMA'able memory for Rx ring\n");
2066                 goto fail;
2067         }
2068         sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2069
2070         /* create DMA maps for Tx buffers */
2071         for (i = 0; i < SK_TX_RING_CNT; i++) {
2072                 txd = &sc_if->sk_cdata.sk_txdesc[i];
2073                 txd->tx_m = NULL;
2074                 txd->tx_dmamap = NULL;
2075                 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2076                     &txd->tx_dmamap);
2077                 if (error != 0) {
2078                         device_printf(sc_if->sk_if_dev,
2079                             "failed to create Tx dmamap\n");
2080                         goto fail;
2081                 }
2082         }
2083
2084         /* create DMA maps for Rx buffers */
2085         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2086             &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2087                 device_printf(sc_if->sk_if_dev,
2088                     "failed to create spare Rx dmamap\n");
2089                 goto fail;
2090         }
2091         for (i = 0; i < SK_RX_RING_CNT; i++) {
2092                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2093                 rxd->rx_m = NULL;
2094                 rxd->rx_dmamap = NULL;
2095                 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2096                     &rxd->rx_dmamap);
2097                 if (error != 0) {
2098                         device_printf(sc_if->sk_if_dev,
2099                             "failed to create Rx dmamap\n");
2100                         goto fail;
2101                 }
2102         }
2103
2104 fail:
2105         return (error);
2106 }
2107
2108 static int
2109 sk_dma_jumbo_alloc(sc_if)
2110         struct sk_if_softc      *sc_if;
2111 {
2112         struct sk_dmamap_arg    ctx;
2113         struct sk_rxdesc        *jrxd;
2114         int                     error, i;
2115
2116         if (jumbo_disable != 0) {
2117                 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2118                 sc_if->sk_jumbo_disable = 1;
2119                 return (0);
2120         }
2121         /* create tag for jumbo Rx ring */
2122         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2123                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
2124                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
2125                     BUS_SPACE_MAXADDR,          /* highaddr */
2126                     NULL, NULL,                 /* filter, filterarg */
2127                     SK_JUMBO_RX_RING_SZ,        /* maxsize */
2128                     1,                          /* nsegments */
2129                     SK_JUMBO_RX_RING_SZ,        /* maxsegsize */
2130                     0,                          /* flags */
2131                     NULL, NULL,                 /* lockfunc, lockarg */
2132                     &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2133         if (error != 0) {
2134                 device_printf(sc_if->sk_if_dev,
2135                     "failed to allocate jumbo Rx ring DMA tag\n");
2136                 goto jumbo_fail;
2137         }
2138
2139         /* create tag for jumbo Rx buffers */
2140         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2141                     1, 0,                       /* algnmnt, boundary */
2142                     BUS_SPACE_MAXADDR,          /* lowaddr */
2143                     BUS_SPACE_MAXADDR,          /* highaddr */
2144                     NULL, NULL,                 /* filter, filterarg */
2145                     MJUM9BYTES,                 /* maxsize */
2146                     1,                          /* nsegments */
2147                     MJUM9BYTES,                 /* maxsegsize */
2148                     0,                          /* flags */
2149                     NULL, NULL,                 /* lockfunc, lockarg */
2150                     &sc_if->sk_cdata.sk_jumbo_rx_tag);
2151         if (error != 0) {
2152                 device_printf(sc_if->sk_if_dev,
2153                     "failed to allocate jumbo Rx DMA tag\n");
2154                 goto jumbo_fail;
2155         }
2156
2157         /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2158         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2159             (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2160             BUS_DMA_COHERENT | BUS_DMA_ZERO,
2161             &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2162         if (error != 0) {
2163                 device_printf(sc_if->sk_if_dev,
2164                     "failed to allocate DMA'able memory for jumbo Rx ring\n");
2165                 goto jumbo_fail;
2166         }
2167
2168         ctx.sk_busaddr = 0;
2169         error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2170             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2171             sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2172             &ctx, BUS_DMA_NOWAIT);
2173         if (error != 0) {
2174                 device_printf(sc_if->sk_if_dev,
2175                     "failed to load DMA'able memory for jumbo Rx ring\n");
2176                 goto jumbo_fail;
2177         }
2178         sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2179
2180         /* create DMA maps for jumbo Rx buffers */
2181         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2182             &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2183                 device_printf(sc_if->sk_if_dev,
2184                     "failed to create spare jumbo Rx dmamap\n");
2185                 goto jumbo_fail;
2186         }
2187         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2188                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2189                 jrxd->rx_m = NULL;
2190                 jrxd->rx_dmamap = NULL;
2191                 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2192                     &jrxd->rx_dmamap);
2193                 if (error != 0) {
2194                         device_printf(sc_if->sk_if_dev,
2195                             "failed to create jumbo Rx dmamap\n");
2196                         goto jumbo_fail;
2197                 }
2198         }
2199
2200         return (0);
2201
2202 jumbo_fail:
2203         sk_dma_jumbo_free(sc_if);
2204         device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2205             "resource shortage\n");
2206         sc_if->sk_jumbo_disable = 1;
2207         return (0);
2208 }
2209
2210 static void
2211 sk_dma_free(sc_if)
2212         struct sk_if_softc      *sc_if;
2213 {
2214         struct sk_txdesc        *txd;
2215         struct sk_rxdesc        *rxd;
2216         int                     i;
2217
2218         /* Tx ring */
2219         if (sc_if->sk_cdata.sk_tx_ring_tag) {
2220                 if (sc_if->sk_cdata.sk_tx_ring_map)
2221                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2222                             sc_if->sk_cdata.sk_tx_ring_map);
2223                 if (sc_if->sk_cdata.sk_tx_ring_map &&
2224                     sc_if->sk_rdata.sk_tx_ring)
2225                         bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2226                             sc_if->sk_rdata.sk_tx_ring,
2227                             sc_if->sk_cdata.sk_tx_ring_map);
2228                 sc_if->sk_rdata.sk_tx_ring = NULL;
2229                 sc_if->sk_cdata.sk_tx_ring_map = NULL;
2230                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2231                 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2232         }
2233         /* Rx ring */
2234         if (sc_if->sk_cdata.sk_rx_ring_tag) {
2235                 if (sc_if->sk_cdata.sk_rx_ring_map)
2236                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2237                             sc_if->sk_cdata.sk_rx_ring_map);
2238                 if (sc_if->sk_cdata.sk_rx_ring_map &&
2239                     sc_if->sk_rdata.sk_rx_ring)
2240                         bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2241                             sc_if->sk_rdata.sk_rx_ring,
2242                             sc_if->sk_cdata.sk_rx_ring_map);
2243                 sc_if->sk_rdata.sk_rx_ring = NULL;
2244                 sc_if->sk_cdata.sk_rx_ring_map = NULL;
2245                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2246                 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2247         }
2248         /* Tx buffers */
2249         if (sc_if->sk_cdata.sk_tx_tag) {
2250                 for (i = 0; i < SK_TX_RING_CNT; i++) {
2251                         txd = &sc_if->sk_cdata.sk_txdesc[i];
2252                         if (txd->tx_dmamap) {
2253                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2254                                     txd->tx_dmamap);
2255                                 txd->tx_dmamap = NULL;
2256                         }
2257                 }
2258                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2259                 sc_if->sk_cdata.sk_tx_tag = NULL;
2260         }
2261         /* Rx buffers */
2262         if (sc_if->sk_cdata.sk_rx_tag) {
2263                 for (i = 0; i < SK_RX_RING_CNT; i++) {
2264                         rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2265                         if (rxd->rx_dmamap) {
2266                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2267                                     rxd->rx_dmamap);
2268                                 rxd->rx_dmamap = NULL;
2269                         }
2270                 }
2271                 if (sc_if->sk_cdata.sk_rx_sparemap) {
2272                         bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2273                             sc_if->sk_cdata.sk_rx_sparemap);
2274                         sc_if->sk_cdata.sk_rx_sparemap = NULL;
2275                 }
2276                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2277                 sc_if->sk_cdata.sk_rx_tag = NULL;
2278         }
2279
2280         if (sc_if->sk_cdata.sk_parent_tag) {
2281                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2282                 sc_if->sk_cdata.sk_parent_tag = NULL;
2283         }
2284 }
2285
2286 static void
2287 sk_dma_jumbo_free(sc_if)
2288         struct sk_if_softc      *sc_if;
2289 {
2290         struct sk_rxdesc        *jrxd;
2291         int                     i;
2292
2293         /* jumbo Rx ring */
2294         if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2295                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map)
2296                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2297                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2298                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map &&
2299                     sc_if->sk_rdata.sk_jumbo_rx_ring)
2300                         bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2301                             sc_if->sk_rdata.sk_jumbo_rx_ring,
2302                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2303                 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2304                 sc_if->sk_cdata.sk_jumbo_rx_ring_map = NULL;
2305                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2306                 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2307         }
2308
2309         /* jumbo Rx buffers */
2310         if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2311                 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2312                         jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2313                         if (jrxd->rx_dmamap) {
2314                                 bus_dmamap_destroy(
2315                                     sc_if->sk_cdata.sk_jumbo_rx_tag,
2316                                     jrxd->rx_dmamap);
2317                                 jrxd->rx_dmamap = NULL;
2318                         }
2319                 }
2320                 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2321                         bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2322                             sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2323                         sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2324                 }
2325                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2326                 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2327         }
2328 }
2329
2330 static void
2331 sk_txcksum(ifp, m, f)
2332         struct ifnet            *ifp;
2333         struct mbuf             *m;
2334         struct sk_tx_desc       *f;
2335 {
2336         struct ip               *ip;
2337         u_int16_t               offset;
2338         u_int8_t                *p;
2339
2340         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2341         for(; m && m->m_len == 0; m = m->m_next)
2342                 ;
2343         if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2344                 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2345                 /* checksum may be corrupted */
2346                 goto sendit;
2347         }
2348         if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2349                 if (m->m_len != ETHER_HDR_LEN) {
2350                         if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2351                             __func__);
2352                         /* checksum may be corrupted */
2353                         goto sendit;
2354                 }
2355                 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2356                         ;
2357                 if (m == NULL) {
2358                         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2359                         /* checksum may be corrupted */
2360                         goto sendit;
2361                 }
2362                 ip = mtod(m, struct ip *);
2363         } else {
2364                 p = mtod(m, u_int8_t *);
2365                 p += ETHER_HDR_LEN;
2366                 ip = (struct ip *)p;
2367         }
2368         offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2369
2370 sendit:
2371         f->sk_csum_startval = 0;
2372         f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2373             (offset << 16));
2374 }
2375
2376 static int
2377 sk_encap(sc_if, m_head)
2378         struct sk_if_softc      *sc_if;
2379         struct mbuf             **m_head;
2380 {
2381         struct sk_txdesc        *txd;
2382         struct sk_tx_desc       *f = NULL;
2383         struct mbuf             *m;
2384         bus_dma_segment_t       txsegs[SK_MAXTXSEGS];
2385         u_int32_t               cflags, frag, si, sk_ctl;
2386         int                     error, i, nseg;
2387
2388         SK_IF_LOCK_ASSERT(sc_if);
2389
2390         if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2391                 return (ENOBUFS);
2392
2393         error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2394             txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2395         if (error == EFBIG) {
2396                 m = m_defrag(*m_head, M_NOWAIT);
2397                 if (m == NULL) {
2398                         m_freem(*m_head);
2399                         *m_head = NULL;
2400                         return (ENOMEM);
2401                 }
2402                 *m_head = m;
2403                 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2404                     txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2405                 if (error != 0) {
2406                         m_freem(*m_head);
2407                         *m_head = NULL;
2408                         return (error);
2409                 }
2410         } else if (error != 0)
2411                 return (error);
2412         if (nseg == 0) {
2413                 m_freem(*m_head);
2414                 *m_head = NULL;
2415                 return (EIO);
2416         }
2417         if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2418                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2419                 return (ENOBUFS);
2420         }
2421
2422         m = *m_head;
2423         if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2424                 cflags = SK_OPCODE_CSUM;
2425         else
2426                 cflags = SK_OPCODE_DEFAULT;
2427         si = frag = sc_if->sk_cdata.sk_tx_prod;
2428         for (i = 0; i < nseg; i++) {
2429                 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2430                 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2431                 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2432                 sk_ctl = txsegs[i].ds_len | cflags;
2433                 if (i == 0) {
2434                         if (cflags == SK_OPCODE_CSUM)
2435                                 sk_txcksum(sc_if->sk_ifp, m, f);
2436                         sk_ctl |= SK_TXCTL_FIRSTFRAG;
2437                 } else
2438                         sk_ctl |= SK_TXCTL_OWN;
2439                 f->sk_ctl = htole32(sk_ctl);
2440                 sc_if->sk_cdata.sk_tx_cnt++;
2441                 SK_INC(frag, SK_TX_RING_CNT);
2442         }
2443         sc_if->sk_cdata.sk_tx_prod = frag;
2444
2445         /* set EOF on the last desciptor */
2446         frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2447         f = &sc_if->sk_rdata.sk_tx_ring[frag];
2448         f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2449
2450         /* turn the first descriptor ownership to NIC */
2451         f = &sc_if->sk_rdata.sk_tx_ring[si];
2452         f->sk_ctl |= htole32(SK_TXCTL_OWN);
2453
2454         STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2455         STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2456         txd->tx_m = m;
2457
2458         /* sync descriptors */
2459         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2460             BUS_DMASYNC_PREWRITE);
2461         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2462             sc_if->sk_cdata.sk_tx_ring_map,
2463             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2464
2465         return (0);
2466 }
2467
2468 static void
2469 sk_start(ifp)
2470         struct ifnet            *ifp;
2471 {
2472         struct sk_if_softc *sc_if;
2473
2474         sc_if = ifp->if_softc;
2475
2476         SK_IF_LOCK(sc_if);
2477         sk_start_locked(ifp);
2478         SK_IF_UNLOCK(sc_if);
2479
2480         return;
2481 }
2482
2483 static void
2484 sk_start_locked(ifp)
2485         struct ifnet            *ifp;
2486 {
2487         struct sk_softc         *sc;
2488         struct sk_if_softc      *sc_if;
2489         struct mbuf             *m_head;
2490         int                     enq;
2491
2492         sc_if = ifp->if_softc;
2493         sc = sc_if->sk_softc;
2494
2495         SK_IF_LOCK_ASSERT(sc_if);
2496
2497         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2498             sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2499                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2500                 if (m_head == NULL)
2501                         break;
2502
2503                 /*
2504                  * Pack the data into the transmit ring. If we
2505                  * don't have room, set the OACTIVE flag and wait
2506                  * for the NIC to drain the ring.
2507                  */
2508                 if (sk_encap(sc_if, &m_head)) {
2509                         if (m_head == NULL)
2510                                 break;
2511                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2512                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2513                         break;
2514                 }
2515
2516                 enq++;
2517                 /*
2518                  * If there's a BPF listener, bounce a copy of this frame
2519                  * to him.
2520                  */
2521                 BPF_MTAP(ifp, m_head);
2522         }
2523
2524         if (enq > 0) {
2525                 /* Transmit */
2526                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2527
2528                 /* Set a timeout in case the chip goes out to lunch. */
2529                 sc_if->sk_watchdog_timer = 5;
2530         }
2531 }
2532
2533
2534 static void
2535 sk_watchdog(arg)
2536         void                    *arg;
2537 {
2538         struct sk_if_softc      *sc_if;
2539         struct ifnet            *ifp;
2540
2541         ifp = arg;
2542         sc_if = ifp->if_softc;
2543
2544         SK_IF_LOCK_ASSERT(sc_if);
2545
2546         if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2547                 goto done;
2548
2549         /*
2550          * Reclaim first as there is a possibility of losing Tx completion
2551          * interrupts.
2552          */
2553         sk_txeof(sc_if);
2554         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2555                 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2556                 ifp->if_oerrors++;
2557                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2558                 sk_init_locked(sc_if);
2559         }
2560
2561 done:
2562         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2563
2564         return;
2565 }
2566
2567 static int
2568 skc_shutdown(dev)
2569         device_t                dev;
2570 {
2571         struct sk_softc         *sc;
2572
2573         sc = device_get_softc(dev);
2574         SK_LOCK(sc);
2575
2576         /* Turn off the 'driver is loaded' LED. */
2577         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2578
2579         /*
2580          * Reset the GEnesis controller. Doing this should also
2581          * assert the resets on the attached XMAC(s).
2582          */
2583         sk_reset(sc);
2584         SK_UNLOCK(sc);
2585
2586         return (0);
2587 }
2588
2589 static int
2590 skc_suspend(dev)
2591         device_t                dev;
2592 {
2593         struct sk_softc         *sc;
2594         struct sk_if_softc      *sc_if0, *sc_if1;
2595         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2596
2597         sc = device_get_softc(dev);
2598
2599         SK_LOCK(sc);
2600
2601         sc_if0 = sc->sk_if[SK_PORT_A];
2602         sc_if1 = sc->sk_if[SK_PORT_B];
2603         if (sc_if0 != NULL)
2604                 ifp0 = sc_if0->sk_ifp;
2605         if (sc_if1 != NULL)
2606                 ifp1 = sc_if1->sk_ifp;
2607         if (ifp0 != NULL)
2608                 sk_stop(sc_if0);
2609         if (ifp1 != NULL)
2610                 sk_stop(sc_if1);
2611         sc->sk_suspended = 1;
2612
2613         SK_UNLOCK(sc);
2614
2615         return (0);
2616 }
2617
2618 static int
2619 skc_resume(dev)
2620         device_t                dev;
2621 {
2622         struct sk_softc         *sc;
2623         struct sk_if_softc      *sc_if0, *sc_if1;
2624         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2625
2626         sc = device_get_softc(dev);
2627
2628         SK_LOCK(sc);
2629
2630         sc_if0 = sc->sk_if[SK_PORT_A];
2631         sc_if1 = sc->sk_if[SK_PORT_B];
2632         if (sc_if0 != NULL)
2633                 ifp0 = sc_if0->sk_ifp;
2634         if (sc_if1 != NULL)
2635                 ifp1 = sc_if1->sk_ifp;
2636         if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2637                 sk_init_locked(sc_if0);
2638         if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2639                 sk_init_locked(sc_if1);
2640         sc->sk_suspended = 0;
2641
2642         SK_UNLOCK(sc);
2643
2644         return (0);
2645 }
2646
2647 /*
2648  * According to the data sheet from SK-NET GENESIS the hardware can compute
2649  * two Rx checksums at the same time(Each checksum start position is
2650  * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2651  * does not work at least on my Yukon hardware. I tried every possible ways
2652  * to get correct checksum value but couldn't get correct one. So TCP/UDP
2653  * checksum offload was disabled at the moment and only IP checksum offload
2654  * was enabled.
2655  * As nomral IP header size is 20 bytes I can't expect it would give an
2656  * increase in throughput. However it seems it doesn't hurt performance in
2657  * my testing. If there is a more detailed information for checksum secret
2658  * of the hardware in question please contact yongari@FreeBSD.org to add
2659  * TCP/UDP checksum offload support.
2660  */
2661 static __inline void
2662 sk_rxcksum(ifp, m, csum)
2663         struct ifnet            *ifp;
2664         struct mbuf             *m;
2665         u_int32_t               csum;
2666 {
2667         struct ether_header     *eh;
2668         struct ip               *ip;
2669         int32_t                 hlen, len, pktlen;
2670         u_int16_t               csum1, csum2, ipcsum;
2671
2672         pktlen = m->m_pkthdr.len;
2673         if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2674                 return;
2675         eh = mtod(m, struct ether_header *);
2676         if (eh->ether_type != htons(ETHERTYPE_IP))
2677                 return;
2678         ip = (struct ip *)(eh + 1);
2679         if (ip->ip_v != IPVERSION)
2680                 return;
2681         hlen = ip->ip_hl << 2;
2682         pktlen -= sizeof(struct ether_header);
2683         if (hlen < sizeof(struct ip))
2684                 return;
2685         if (ntohs(ip->ip_len) < hlen)
2686                 return;
2687         if (ntohs(ip->ip_len) != pktlen)
2688                 return;
2689
2690         csum1 = htons(csum & 0xffff);
2691         csum2 = htons((csum >> 16) & 0xffff);
2692         ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2693         /* checksum fixup for IP options */
2694         len = hlen - sizeof(struct ip);
2695         if (len > 0) {
2696                 /*
2697                  * If the second checksum value is correct we can compute IP
2698                  * checksum with simple math. Unfortunately the second checksum
2699                  * value is wrong so we can't verify the checksum from the
2700                  * value(It seems there is some magic here to get correct
2701                  * value). If the second checksum value is correct it also
2702                  * means we can get TCP/UDP checksum) here. However, it still
2703                  * needs pseudo header checksum calculation due to hardware
2704                  * limitations.
2705                  */
2706                 return;
2707         }
2708         m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2709         if (ipcsum == 0xffff)
2710                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2711 }
2712
2713 static __inline int
2714 sk_rxvalid(sc, stat, len)
2715         struct sk_softc         *sc;
2716         u_int32_t               stat, len;
2717 {
2718
2719         if (sc->sk_type == SK_GENESIS) {
2720                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2721                     XM_RXSTAT_BYTES(stat) != len)
2722                         return (0);
2723         } else {
2724                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2725                     YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2726                     YU_RXSTAT_JABBER)) != 0 ||
2727                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2728                     YU_RXSTAT_BYTES(stat) != len)
2729                         return (0);
2730         }
2731
2732         return (1);
2733 }
2734
2735 static void
2736 sk_rxeof(sc_if)
2737         struct sk_if_softc      *sc_if;
2738 {
2739         struct sk_softc         *sc;
2740         struct mbuf             *m;
2741         struct ifnet            *ifp;
2742         struct sk_rx_desc       *cur_rx;
2743         struct sk_rxdesc        *rxd;
2744         int                     cons, prog;
2745         u_int32_t               csum, rxstat, sk_ctl;
2746
2747         sc = sc_if->sk_softc;
2748         ifp = sc_if->sk_ifp;
2749
2750         SK_IF_LOCK_ASSERT(sc_if);
2751
2752         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2753             sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2754
2755         prog = 0;
2756         for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2757             prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2758                 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2759                 sk_ctl = le32toh(cur_rx->sk_ctl);
2760                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2761                         break;
2762                 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2763                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2764
2765                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2766                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2767                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2768                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2769                     SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2770                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2771                         ifp->if_ierrors++;
2772                         sk_discard_rxbuf(sc_if, cons);
2773                         continue;
2774                 }
2775
2776                 m = rxd->rx_m;
2777                 csum = le32toh(cur_rx->sk_csum);
2778                 if (sk_newbuf(sc_if, cons) != 0) {
2779                         ifp->if_iqdrops++;
2780                         /* reuse old buffer */
2781                         sk_discard_rxbuf(sc_if, cons);
2782                         continue;
2783                 }
2784                 m->m_pkthdr.rcvif = ifp;
2785                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2786                 ifp->if_ipackets++;
2787                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2788                         sk_rxcksum(ifp, m, csum);
2789                 SK_IF_UNLOCK(sc_if);
2790                 (*ifp->if_input)(ifp, m);
2791                 SK_IF_LOCK(sc_if);
2792         }
2793
2794         if (prog > 0) {
2795                 sc_if->sk_cdata.sk_rx_cons = cons;
2796                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2797                     sc_if->sk_cdata.sk_rx_ring_map,
2798                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2799         }
2800 }
2801
2802 static void
2803 sk_jumbo_rxeof(sc_if)
2804         struct sk_if_softc      *sc_if;
2805 {
2806         struct sk_softc         *sc;
2807         struct mbuf             *m;
2808         struct ifnet            *ifp;
2809         struct sk_rx_desc       *cur_rx;
2810         struct sk_rxdesc        *jrxd;
2811         int                     cons, prog;
2812         u_int32_t               csum, rxstat, sk_ctl;
2813
2814         sc = sc_if->sk_softc;
2815         ifp = sc_if->sk_ifp;
2816
2817         SK_IF_LOCK_ASSERT(sc_if);
2818
2819         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2820             sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2821
2822         prog = 0;
2823         for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2824             prog < SK_JUMBO_RX_RING_CNT;
2825             prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2826                 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2827                 sk_ctl = le32toh(cur_rx->sk_ctl);
2828                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2829                         break;
2830                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2831                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2832
2833                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2834                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2835                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2836                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2837                     SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2838                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2839                         ifp->if_ierrors++;
2840                         sk_discard_jumbo_rxbuf(sc_if, cons);
2841                         continue;
2842                 }
2843
2844                 m = jrxd->rx_m;
2845                 csum = le32toh(cur_rx->sk_csum);
2846                 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2847                         ifp->if_iqdrops++;
2848                         /* reuse old buffer */
2849                         sk_discard_jumbo_rxbuf(sc_if, cons);
2850                         continue;
2851                 }
2852                 m->m_pkthdr.rcvif = ifp;
2853                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2854                 ifp->if_ipackets++;
2855                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2856                         sk_rxcksum(ifp, m, csum);
2857                 SK_IF_UNLOCK(sc_if);
2858                 (*ifp->if_input)(ifp, m);
2859                 SK_IF_LOCK(sc_if);
2860         }
2861
2862         if (prog > 0) {
2863                 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2864                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2865                     sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2866                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2867         }
2868 }
2869
2870 static void
2871 sk_txeof(sc_if)
2872         struct sk_if_softc      *sc_if;
2873 {
2874         struct sk_softc         *sc;
2875         struct sk_txdesc        *txd;
2876         struct sk_tx_desc       *cur_tx;
2877         struct ifnet            *ifp;
2878         u_int32_t               idx, sk_ctl;
2879
2880         sc = sc_if->sk_softc;
2881         ifp = sc_if->sk_ifp;
2882
2883         txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2884         if (txd == NULL)
2885                 return;
2886         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2887             sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2888         /*
2889          * Go through our tx ring and free mbufs for those
2890          * frames that have been sent.
2891          */
2892         for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2893                 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2894                         break;
2895                 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2896                 sk_ctl = le32toh(cur_tx->sk_ctl);
2897                 if (sk_ctl & SK_TXCTL_OWN)
2898                         break;
2899                 sc_if->sk_cdata.sk_tx_cnt--;
2900                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2901                 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2902                         continue;
2903                 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2904                     BUS_DMASYNC_POSTWRITE);
2905                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2906
2907                 ifp->if_opackets++;
2908                 m_freem(txd->tx_m);
2909                 txd->tx_m = NULL;
2910                 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2911                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2912                 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2913         }
2914         sc_if->sk_cdata.sk_tx_cons = idx;
2915         sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2916
2917         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2918             sc_if->sk_cdata.sk_tx_ring_map,
2919             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2920 }
2921
2922 static void
2923 sk_tick(xsc_if)
2924         void                    *xsc_if;
2925 {
2926         struct sk_if_softc      *sc_if;
2927         struct mii_data         *mii;
2928         struct ifnet            *ifp;
2929         int                     i;
2930
2931         sc_if = xsc_if;
2932         ifp = sc_if->sk_ifp;
2933         mii = device_get_softc(sc_if->sk_miibus);
2934
2935         if (!(ifp->if_flags & IFF_UP))
2936                 return;
2937
2938         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2939                 sk_intr_bcom(sc_if);
2940                 return;
2941         }
2942
2943         /*
2944          * According to SysKonnect, the correct way to verify that
2945          * the link has come back up is to poll bit 0 of the GPIO
2946          * register three times. This pin has the signal from the
2947          * link_sync pin connected to it; if we read the same link
2948          * state 3 times in a row, we know the link is up.
2949          */
2950         for (i = 0; i < 3; i++) {
2951                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2952                         break;
2953         }
2954
2955         if (i != 3) {
2956                 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2957                 return;
2958         }
2959
2960         /* Turn the GP0 interrupt back on. */
2961         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2962         SK_XM_READ_2(sc_if, XM_ISR);
2963         mii_tick(mii);
2964         callout_stop(&sc_if->sk_tick_ch);
2965 }
2966
2967 static void
2968 sk_yukon_tick(xsc_if)
2969         void                    *xsc_if;
2970 {
2971         struct sk_if_softc      *sc_if;
2972         struct mii_data         *mii;
2973
2974         sc_if = xsc_if;
2975         mii = device_get_softc(sc_if->sk_miibus);
2976
2977         mii_tick(mii);
2978         callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2979 }
2980
2981 static void
2982 sk_intr_bcom(sc_if)
2983         struct sk_if_softc      *sc_if;
2984 {
2985         struct mii_data         *mii;
2986         struct ifnet            *ifp;
2987         int                     status;
2988         mii = device_get_softc(sc_if->sk_miibus);
2989         ifp = sc_if->sk_ifp;
2990
2991         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2992
2993         /*
2994          * Read the PHY interrupt register to make sure
2995          * we clear any pending interrupts.
2996          */
2997         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2998
2999         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3000                 sk_init_xmac(sc_if);
3001                 return;
3002         }
3003
3004         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
3005                 int                     lstat;
3006                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
3007                     BRGPHY_MII_AUXSTS);
3008
3009                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
3010                         mii_mediachg(mii);
3011                         /* Turn off the link LED. */
3012                         SK_IF_WRITE_1(sc_if, 0,
3013                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
3014                         sc_if->sk_link = 0;
3015                 } else if (status & BRGPHY_ISR_LNK_CHG) {
3016                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3017                             BRGPHY_MII_IMR, 0xFF00);
3018                         mii_tick(mii);
3019                         sc_if->sk_link = 1;
3020                         /* Turn on the link LED. */
3021                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3022                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
3023                             SK_LINKLED_BLINK_OFF);
3024                 } else {
3025                         mii_tick(mii);
3026                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3027                 }
3028         }
3029
3030         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3031
3032         return;
3033 }
3034
3035 static void
3036 sk_intr_xmac(sc_if)
3037         struct sk_if_softc      *sc_if;
3038 {
3039         struct sk_softc         *sc;
3040         u_int16_t               status;
3041
3042         sc = sc_if->sk_softc;
3043         status = SK_XM_READ_2(sc_if, XM_ISR);
3044
3045         /*
3046          * Link has gone down. Start MII tick timeout to
3047          * watch for link resync.
3048          */
3049         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3050                 if (status & XM_ISR_GP0_SET) {
3051                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3052                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3053                 }
3054
3055                 if (status & XM_ISR_AUTONEG_DONE) {
3056                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3057                 }
3058         }
3059
3060         if (status & XM_IMR_TX_UNDERRUN)
3061                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3062
3063         if (status & XM_IMR_RX_OVERRUN)
3064                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3065
3066         status = SK_XM_READ_2(sc_if, XM_ISR);
3067
3068         return;
3069 }
3070
3071 static void
3072 sk_intr_yukon(sc_if)
3073         struct sk_if_softc      *sc_if;
3074 {
3075         u_int8_t status;
3076
3077         status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3078         /* RX overrun */
3079         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3080                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3081                     SK_RFCTL_RX_FIFO_OVER);
3082         }
3083         /* TX underrun */
3084         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3085                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3086                     SK_TFCTL_TX_FIFO_UNDER);
3087         }
3088 }
3089
3090 static void
3091 sk_intr(xsc)
3092         void                    *xsc;
3093 {
3094         struct sk_softc         *sc = xsc;
3095         struct sk_if_softc      *sc_if0, *sc_if1;
3096         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
3097         u_int32_t               status;
3098
3099         SK_LOCK(sc);
3100
3101         status = CSR_READ_4(sc, SK_ISSR);
3102         if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3103                 goto done_locked;
3104
3105         sc_if0 = sc->sk_if[SK_PORT_A];
3106         sc_if1 = sc->sk_if[SK_PORT_B];
3107
3108         if (sc_if0 != NULL)
3109                 ifp0 = sc_if0->sk_ifp;
3110         if (sc_if1 != NULL)
3111                 ifp1 = sc_if1->sk_ifp;
3112
3113         for (; (status &= sc->sk_intrmask) != 0;) {
3114                 /* Handle receive interrupts first. */
3115                 if (status & SK_ISR_RX1_EOF) {
3116                         if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3117                                 sk_jumbo_rxeof(sc_if0);
3118                         else
3119                                 sk_rxeof(sc_if0);
3120                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3121                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3122                 }
3123                 if (status & SK_ISR_RX2_EOF) {
3124                         if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3125                                 sk_jumbo_rxeof(sc_if1);
3126                         else
3127                                 sk_rxeof(sc_if1);
3128                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3129                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3130                 }
3131
3132                 /* Then transmit interrupts. */
3133                 if (status & SK_ISR_TX1_S_EOF) {
3134                         sk_txeof(sc_if0);
3135                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3136                 }
3137                 if (status & SK_ISR_TX2_S_EOF) {
3138                         sk_txeof(sc_if1);
3139                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3140                 }
3141
3142                 /* Then MAC interrupts. */
3143                 if (status & SK_ISR_MAC1 &&
3144                     ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3145                         if (sc->sk_type == SK_GENESIS)
3146                                 sk_intr_xmac(sc_if0);
3147                         else
3148                                 sk_intr_yukon(sc_if0);
3149                 }
3150
3151                 if (status & SK_ISR_MAC2 &&
3152                     ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3153                         if (sc->sk_type == SK_GENESIS)
3154                                 sk_intr_xmac(sc_if1);
3155                         else
3156                                 sk_intr_yukon(sc_if1);
3157                 }
3158
3159                 if (status & SK_ISR_EXTERNAL_REG) {
3160                         if (ifp0 != NULL &&
3161                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3162                                 sk_intr_bcom(sc_if0);
3163                         if (ifp1 != NULL &&
3164                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3165                                 sk_intr_bcom(sc_if1);
3166                 }
3167                 status = CSR_READ_4(sc, SK_ISSR);
3168         }
3169
3170         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3171
3172         if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3173                 sk_start_locked(ifp0);
3174         if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3175                 sk_start_locked(ifp1);
3176
3177 done_locked:
3178         SK_UNLOCK(sc);
3179 }
3180
3181 static void
3182 sk_init_xmac(sc_if)
3183         struct sk_if_softc      *sc_if;
3184 {
3185         struct sk_softc         *sc;
3186         struct ifnet            *ifp;
3187         u_int16_t               eaddr[(ETHER_ADDR_LEN+1)/2];
3188         struct sk_bcom_hack     bhack[] = {
3189         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3190         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3191         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3192         { 0, 0 } };
3193
3194         SK_IF_LOCK_ASSERT(sc_if);
3195
3196         sc = sc_if->sk_softc;
3197         ifp = sc_if->sk_ifp;
3198
3199         /* Unreset the XMAC. */
3200         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3201         DELAY(1000);
3202
3203         /* Reset the XMAC's internal state. */
3204         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3205
3206         /* Save the XMAC II revision */
3207         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3208
3209         /*
3210          * Perform additional initialization for external PHYs,
3211          * namely for the 1000baseTX cards that use the XMAC's
3212          * GMII mode.
3213          */
3214         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3215                 int                     i = 0;
3216                 u_int32_t               val;
3217
3218                 /* Take PHY out of reset. */
3219                 val = sk_win_read_4(sc, SK_GPIO);
3220                 if (sc_if->sk_port == SK_PORT_A)
3221                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3222                 else
3223                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3224                 sk_win_write_4(sc, SK_GPIO, val);
3225
3226                 /* Enable GMII mode on the XMAC. */
3227                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3228
3229                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3230                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3231                 DELAY(10000);
3232                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3233                     BRGPHY_MII_IMR, 0xFFF0);
3234
3235                 /*
3236                  * Early versions of the BCM5400 apparently have
3237                  * a bug that requires them to have their reserved
3238                  * registers initialized to some magic values. I don't
3239                  * know what the numbers do, I'm just the messenger.
3240                  */
3241                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3242                     == 0x6041) {
3243                         while(bhack[i].reg) {
3244                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3245                                     bhack[i].reg, bhack[i].val);
3246                                 i++;
3247                         }
3248                 }
3249         }
3250
3251         /* Set station address */
3252         bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3253         SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3254         SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3255         SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3256         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3257
3258         if (ifp->if_flags & IFF_BROADCAST) {
3259                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3260         } else {
3261                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3262         }
3263
3264         /* We don't need the FCS appended to the packet. */
3265         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3266
3267         /* We want short frames padded to 60 bytes. */
3268         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3269
3270         /*
3271          * Enable the reception of all error frames. This is is
3272          * a necessary evil due to the design of the XMAC. The
3273          * XMAC's receive FIFO is only 8K in size, however jumbo
3274          * frames can be up to 9000 bytes in length. When bad
3275          * frame filtering is enabled, the XMAC's RX FIFO operates
3276          * in 'store and forward' mode. For this to work, the
3277          * entire frame has to fit into the FIFO, but that means
3278          * that jumbo frames larger than 8192 bytes will be
3279          * truncated. Disabling all bad frame filtering causes
3280          * the RX FIFO to operate in streaming mode, in which
3281          * case the XMAC will start transfering frames out of the
3282          * RX FIFO as soon as the FIFO threshold is reached.
3283          */
3284         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3285                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3286                     XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3287                     XM_MODE_RX_INRANGELEN);
3288                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3289         } else
3290                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3291
3292         /*
3293          * Bump up the transmit threshold. This helps hold off transmit
3294          * underruns when we're blasting traffic from both ports at once.
3295          */
3296         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3297
3298         /* Set Rx filter */
3299         sk_rxfilter_genesis(sc_if);
3300
3301         /* Clear and enable interrupts */
3302         SK_XM_READ_2(sc_if, XM_ISR);
3303         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3304                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3305         else
3306                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3307
3308         /* Configure MAC arbiter */
3309         switch(sc_if->sk_xmac_rev) {
3310         case XM_XMAC_REV_B2:
3311                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3312                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3313                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3314                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3315                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3316                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3317                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3318                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3319                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3320                 break;
3321         case XM_XMAC_REV_C1:
3322                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3323                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3324                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3325                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3326                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3327                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3328                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3329                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3330                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3331                 break;
3332         default:
3333                 break;
3334         }
3335         sk_win_write_2(sc, SK_MACARB_CTL,
3336             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3337
3338         sc_if->sk_link = 1;
3339
3340         return;
3341 }
3342
3343 static void
3344 sk_init_yukon(sc_if)
3345         struct sk_if_softc      *sc_if;
3346 {
3347         u_int32_t               phy, v;
3348         u_int16_t               reg;
3349         struct sk_softc         *sc;
3350         struct ifnet            *ifp;
3351         u_int8_t                *eaddr;
3352         int                     i;
3353
3354         SK_IF_LOCK_ASSERT(sc_if);
3355
3356         sc = sc_if->sk_softc;
3357         ifp = sc_if->sk_ifp;
3358
3359         if (sc->sk_type == SK_YUKON_LITE &&
3360             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3361                 /*
3362                  * Workaround code for COMA mode, set PHY reset.
3363                  * Otherwise it will not correctly take chip out of
3364                  * powerdown (coma)
3365                  */
3366                 v = sk_win_read_4(sc, SK_GPIO);
3367                 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3368                 sk_win_write_4(sc, SK_GPIO, v);
3369         }
3370
3371         /* GMAC and GPHY Reset */
3372         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3373         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3374         DELAY(1000);
3375
3376         if (sc->sk_type == SK_YUKON_LITE &&
3377             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3378                 /*
3379                  * Workaround code for COMA mode, clear PHY reset
3380                  */
3381                 v = sk_win_read_4(sc, SK_GPIO);
3382                 v |= SK_GPIO_DIR9;
3383                 v &= ~SK_GPIO_DAT9;
3384                 sk_win_write_4(sc, SK_GPIO, v);
3385         }
3386
3387         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3388                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3389
3390         if (sc->sk_coppertype)
3391                 phy |= SK_GPHY_COPPER;
3392         else
3393                 phy |= SK_GPHY_FIBER;
3394
3395         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3396         DELAY(1000);
3397         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3398         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3399                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3400
3401         /* unused read of the interrupt source register */
3402         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3403
3404         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3405
3406         /* MIB Counter Clear Mode set */
3407         reg |= YU_PAR_MIB_CLR;
3408         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3409
3410         /* MIB Counter Clear Mode clear */
3411         reg &= ~YU_PAR_MIB_CLR;
3412         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3413
3414         /* receive control reg */
3415         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3416
3417         /* transmit parameter register */
3418         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3419                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3420
3421         /* serial mode register */
3422         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3423         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3424                 reg |= YU_SMR_MFL_JUMBO;
3425         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3426
3427         /* Setup Yukon's station address */
3428         eaddr = IF_LLADDR(sc_if->sk_ifp);
3429         for (i = 0; i < 3; i++)
3430                 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3431                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3432         /* Set GMAC source address of flow control. */
3433         for (i = 0; i < 3; i++)
3434                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3435                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3436         /* Set GMAC virtual address. */
3437         for (i = 0; i < 3; i++)
3438                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3439                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3440
3441         /* Set Rx filter */
3442         sk_rxfilter_yukon(sc_if);
3443
3444         /* enable interrupt mask for counter overflows */
3445         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3446         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3447         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3448
3449         /* Configure RX MAC FIFO Flush Mask */
3450         v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3451             YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3452             YU_RXSTAT_JABBER;
3453         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3454
3455         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3456         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3457                 v = SK_TFCTL_OPERATION_ON;
3458         else
3459                 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3460         /* Configure RX MAC FIFO */
3461         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3462         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3463
3464         /* Increase flush threshould to 64 bytes */
3465         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3466             SK_RFCTL_FIFO_THRESHOLD + 1);
3467
3468         /* Configure TX MAC FIFO */
3469         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3470         SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3471 }
3472
3473 /*
3474  * Note that to properly initialize any part of the GEnesis chip,
3475  * you first have to take it out of reset mode.
3476  */
3477 static void
3478 sk_init(xsc)
3479         void                    *xsc;
3480 {
3481         struct sk_if_softc      *sc_if = xsc;
3482
3483         SK_IF_LOCK(sc_if);
3484         sk_init_locked(sc_if);
3485         SK_IF_UNLOCK(sc_if);
3486
3487         return;
3488 }
3489
3490 static void
3491 sk_init_locked(sc_if)
3492         struct sk_if_softc      *sc_if;
3493 {
3494         struct sk_softc         *sc;
3495         struct ifnet            *ifp;
3496         struct mii_data         *mii;
3497         u_int16_t               reg;
3498         u_int32_t               imr;
3499         int                     error;
3500
3501         SK_IF_LOCK_ASSERT(sc_if);
3502
3503         ifp = sc_if->sk_ifp;
3504         sc = sc_if->sk_softc;
3505         mii = device_get_softc(sc_if->sk_miibus);
3506
3507         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3508                 return;
3509
3510         /* Cancel pending I/O and free all RX/TX buffers. */
3511         sk_stop(sc_if);
3512
3513         if (sc->sk_type == SK_GENESIS) {
3514                 /* Configure LINK_SYNC LED */
3515                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3516                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3517                         SK_LINKLED_LINKSYNC_ON);
3518
3519                 /* Configure RX LED */
3520                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3521                         SK_RXLEDCTL_COUNTER_START);
3522
3523                 /* Configure TX LED */
3524                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3525                         SK_TXLEDCTL_COUNTER_START);
3526         }
3527
3528         /*
3529          * Configure descriptor poll timer
3530          *
3531          * SK-NET GENESIS data sheet says that possibility of losing Start
3532          * transmit command due to CPU/cache related interim storage problems
3533          * under certain conditions. The document recommends a polling
3534          * mechanism to send a Start transmit command to initiate transfer
3535          * of ready descriptors regulary. To cope with this issue sk(4) now
3536          * enables descriptor poll timer to initiate descriptor processing
3537          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3538          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3539          * command instead of waiting for next descriptor polling time.
3540          * The same rule may apply to Rx side too but it seems that is not
3541          * needed at the moment.
3542          * Since sk(4) uses descriptor polling as a last resort there is no
3543          * need to set smaller polling time than maximum allowable one.
3544          */
3545         SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3546
3547         /* Configure I2C registers */
3548
3549         /* Configure XMAC(s) */
3550         switch (sc->sk_type) {
3551         case SK_GENESIS:
3552                 sk_init_xmac(sc_if);
3553                 break;
3554         case SK_YUKON:
3555         case SK_YUKON_LITE:
3556         case SK_YUKON_LP:
3557                 sk_init_yukon(sc_if);
3558                 break;
3559         }
3560         mii_mediachg(mii);
3561
3562         if (sc->sk_type == SK_GENESIS) {
3563                 /* Configure MAC FIFOs */
3564                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3565                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3566                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3567
3568                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3569                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3570                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3571         }
3572
3573         /* Configure transmit arbiter(s) */
3574         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3575             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3576
3577         /* Configure RAMbuffers */
3578         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3579         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3580         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3581         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3582         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3583         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3584
3585         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3586         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3587         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3588         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3589         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3590         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3591         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3592
3593         /* Configure BMUs */
3594         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3595         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3596                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3597                     SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3598                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3599                     SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3600         } else {
3601                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3602                     SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3603                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3604                     SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3605         }
3606
3607         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3608         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3609             SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3610         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3611             SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3612
3613         /* Init descriptors */
3614         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3615                 error = sk_init_jumbo_rx_ring(sc_if);
3616         else
3617                 error = sk_init_rx_ring(sc_if);
3618         if (error != 0) {
3619                 device_printf(sc_if->sk_if_dev,
3620                     "initialization failed: no memory for rx buffers\n");
3621                 sk_stop(sc_if);
3622                 return;
3623         }
3624         sk_init_tx_ring(sc_if);
3625
3626         /* Set interrupt moderation if changed via sysctl. */
3627         imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3628         if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3629                 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3630                     sc->sk_int_ticks));
3631                 if (bootverbose)
3632                         device_printf(sc_if->sk_if_dev,
3633                             "interrupt moderation is %d us.\n",
3634                             sc->sk_int_mod);
3635         }
3636
3637         /* Configure interrupt handling */
3638         CSR_READ_4(sc, SK_ISSR);
3639         if (sc_if->sk_port == SK_PORT_A)
3640                 sc->sk_intrmask |= SK_INTRS1;
3641         else
3642                 sc->sk_intrmask |= SK_INTRS2;
3643
3644         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3645
3646         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3647
3648         /* Start BMUs. */
3649         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3650
3651         switch(sc->sk_type) {
3652         case SK_GENESIS:
3653                 /* Enable XMACs TX and RX state machines */
3654                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3655                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3656                 break;
3657         case SK_YUKON:
3658         case SK_YUKON_LITE:
3659         case SK_YUKON_LP:
3660                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3661                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3662 #if 0
3663                 /* XXX disable 100Mbps and full duplex mode? */
3664                 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3665 #endif
3666                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3667         }
3668
3669         /* Activate descriptor polling timer */
3670         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3671         /* start transfer of Tx descriptors */
3672         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3673
3674         ifp->if_drv_flags |= IFF_DRV_RUNNING;
3675         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3676
3677         switch (sc->sk_type) {
3678         case SK_YUKON:
3679         case SK_YUKON_LITE:
3680         case SK_YUKON_LP:
3681                 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3682                 break;
3683         }
3684
3685         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3686
3687         return;
3688 }
3689
3690 static void
3691 sk_stop(sc_if)
3692         struct sk_if_softc      *sc_if;
3693 {
3694         int                     i;
3695         struct sk_softc         *sc;
3696         struct sk_txdesc        *txd;
3697         struct sk_rxdesc        *rxd;
3698         struct sk_rxdesc        *jrxd;
3699         struct ifnet            *ifp;
3700         u_int32_t               val;
3701
3702         SK_IF_LOCK_ASSERT(sc_if);
3703         sc = sc_if->sk_softc;
3704         ifp = sc_if->sk_ifp;
3705
3706         callout_stop(&sc_if->sk_tick_ch);
3707         callout_stop(&sc_if->sk_watchdog_ch);
3708
3709         /* stop Tx descriptor polling timer */
3710         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3711         /* stop transfer of Tx descriptors */
3712         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3713         for (i = 0; i < SK_TIMEOUT; i++) {
3714                 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3715                 if ((val & SK_TXBMU_TX_STOP) == 0)
3716                         break;
3717                 DELAY(1);
3718         }
3719         if (i == SK_TIMEOUT)
3720                 device_printf(sc_if->sk_if_dev,
3721                     "can not stop transfer of Tx descriptor\n");
3722         /* stop transfer of Rx descriptors */
3723         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3724         for (i = 0; i < SK_TIMEOUT; i++) {
3725                 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3726                 if ((val & SK_RXBMU_RX_STOP) == 0)
3727                         break;
3728                 DELAY(1);
3729         }
3730         if (i == SK_TIMEOUT)
3731                 device_printf(sc_if->sk_if_dev,
3732                     "can not stop transfer of Rx descriptor\n");
3733
3734         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3735                 /* Put PHY back into reset. */
3736                 val = sk_win_read_4(sc, SK_GPIO);
3737                 if (sc_if->sk_port == SK_PORT_A) {
3738                         val |= SK_GPIO_DIR0;
3739                         val &= ~SK_GPIO_DAT0;
3740                 } else {
3741                         val |= SK_GPIO_DIR2;
3742                         val &= ~SK_GPIO_DAT2;
3743                 }
3744                 sk_win_write_4(sc, SK_GPIO, val);
3745         }
3746
3747         /* Turn off various components of this interface. */
3748         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3749         switch (sc->sk_type) {
3750         case SK_GENESIS:
3751                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3752                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3753                 break;
3754         case SK_YUKON:
3755         case SK_YUKON_LITE:
3756         case SK_YUKON_LP:
3757                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3758                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3759                 break;
3760         }
3761         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3762         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3763         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3764         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3765         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3766         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3767         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3768         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3769         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3770
3771         /* Disable interrupts */
3772         if (sc_if->sk_port == SK_PORT_A)
3773                 sc->sk_intrmask &= ~SK_INTRS1;
3774         else
3775                 sc->sk_intrmask &= ~SK_INTRS2;
3776         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3777
3778         SK_XM_READ_2(sc_if, XM_ISR);
3779         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3780
3781         /* Free RX and TX mbufs still in the queues. */
3782         for (i = 0; i < SK_RX_RING_CNT; i++) {
3783                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3784                 if (rxd->rx_m != NULL) {
3785                         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3786                             rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3787                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3788                             rxd->rx_dmamap);
3789                         m_freem(rxd->rx_m);
3790                         rxd->rx_m = NULL;
3791                 }
3792         }
3793         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3794                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3795                 if (jrxd->rx_m != NULL) {
3796                         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3797                             jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3798                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3799                             jrxd->rx_dmamap);
3800                         m_freem(jrxd->rx_m);
3801                         jrxd->rx_m = NULL;
3802                 }
3803         }
3804         for (i = 0; i < SK_TX_RING_CNT; i++) {
3805                 txd = &sc_if->sk_cdata.sk_txdesc[i];
3806                 if (txd->tx_m != NULL) {
3807                         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3808                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3809                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3810                             txd->tx_dmamap);
3811                         m_freem(txd->tx_m);
3812                         txd->tx_m = NULL;
3813                 }
3814         }
3815
3816         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
3817
3818         return;
3819 }
3820
3821 static int
3822 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3823 {
3824         int error, value;
3825
3826         if (!arg1)
3827                 return (EINVAL);
3828         value = *(int *)arg1;
3829         error = sysctl_handle_int(oidp, &value, 0, req);
3830         if (error || !req->newptr)
3831                 return (error);
3832         if (value < low || value > high)
3833                 return (EINVAL);
3834         *(int *)arg1 = value;
3835         return (0);
3836 }
3837
3838 static int
3839 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3840 {
3841         return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
3842 }