1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
4 * Copyright (c) 1997, 1998, 1999, 2000
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
37 * Permission to use, copy, modify, and distribute this software for any
38 * purpose with or without fee is hereby granted, provided that the above
39 * copyright notice and this permission notice appear in all copies.
41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
57 * The XaQti XMAC II datasheet,
58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
59 * The SysKonnect GEnesis manual, http://www.syskonnect.com
61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63 * convenience to others until Vitesse corrects this problem:
65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
67 * Written by Bill Paul <wpaul@ee.columbia.edu>
68 * Department of Electrical Engineering
69 * Columbia University, New York City
72 * The SysKonnect gigabit ethernet adapters consist of two main
73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
75 * components and a PHY while the GEnesis controller provides a PCI
76 * interface with DMA support. Each card may have between 512K and
77 * 2MB of SRAM on board depending on the configuration.
79 * The SysKonnect GEnesis controller can have either one or two XMAC
80 * chips connected to it, allowing single or dual port NIC configurations.
81 * SysKonnect has the distinction of being the only vendor on the market
82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
84 * XMAC registers. This driver takes advantage of these features to allow
85 * both XMACs to operate as independent interfaces.
88 #include <sys/param.h>
89 #include <sys/systm.h>
91 #include <sys/endian.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/sockio.h>
98 #include <sys/queue.h>
99 #include <sys/sysctl.h>
102 #include <net/ethernet.h>
104 #include <net/if_var.h>
105 #include <net/if_arp.h>
106 #include <net/if_dl.h>
107 #include <net/if_media.h>
108 #include <net/if_types.h>
109 #include <net/if_vlan_var.h>
111 #include <netinet/in.h>
112 #include <netinet/in_systm.h>
113 #include <netinet/ip.h>
115 #include <machine/bus.h>
116 #include <machine/in_cksum.h>
117 #include <machine/resource.h>
118 #include <sys/rman.h>
120 #include <dev/mii/mii.h>
121 #include <dev/mii/miivar.h>
122 #include <dev/mii/brgphyreg.h>
124 #include <dev/pci/pcireg.h>
125 #include <dev/pci/pcivar.h>
128 #define SK_USEIOSPACE
131 #include <dev/sk/if_skreg.h>
132 #include <dev/sk/xmaciireg.h>
133 #include <dev/sk/yukonreg.h>
135 MODULE_DEPEND(sk, pci, 1, 1, 1);
136 MODULE_DEPEND(sk, ether, 1, 1, 1);
137 MODULE_DEPEND(sk, miibus, 1, 1, 1);
139 /* "device miibus" required. See GENERIC if you get errors here. */
140 #include "miibus_if.h"
143 static const char rcsid[] =
147 static const struct sk_type sk_devs[] = {
151 "SysKonnect Gigabit Ethernet (V1.0)"
156 "SysKonnect Gigabit Ethernet (V2.0)"
161 "Marvell Gigabit Ethernet"
165 DEVICEID_BELKIN_5005,
166 "Belkin F5D5005 Gigabit Ethernet"
171 "3Com 3C940 Gigabit Ethernet"
175 DEVICEID_LINKSYS_EG1032,
176 "Linksys EG1032 Gigabit Ethernet"
180 DEVICEID_DLINK_DGE530T_A1,
181 "D-Link DGE-530T Gigabit Ethernet"
185 DEVICEID_DLINK_DGE530T_B1,
186 "D-Link DGE-530T Gigabit Ethernet"
191 static int skc_probe(device_t);
192 static int skc_attach(device_t);
193 static int skc_detach(device_t);
194 static int skc_shutdown(device_t);
195 static int skc_suspend(device_t);
196 static int skc_resume(device_t);
197 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t);
198 static int sk_detach(device_t);
199 static int sk_probe(device_t);
200 static int sk_attach(device_t);
201 static void sk_tick(void *);
202 static void sk_yukon_tick(void *);
203 static void sk_intr(void *);
204 static void sk_intr_xmac(struct sk_if_softc *);
205 static void sk_intr_bcom(struct sk_if_softc *);
206 static void sk_intr_yukon(struct sk_if_softc *);
207 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
208 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
209 static void sk_rxeof(struct sk_if_softc *);
210 static void sk_jumbo_rxeof(struct sk_if_softc *);
211 static void sk_txeof(struct sk_if_softc *);
212 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
213 static int sk_encap(struct sk_if_softc *, struct mbuf **);
214 static void sk_start(struct ifnet *);
215 static void sk_start_locked(struct ifnet *);
216 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
217 static void sk_init(void *);
218 static void sk_init_locked(struct sk_if_softc *);
219 static void sk_init_xmac(struct sk_if_softc *);
220 static void sk_init_yukon(struct sk_if_softc *);
221 static void sk_stop(struct sk_if_softc *);
222 static void sk_watchdog(void *);
223 static int sk_ifmedia_upd(struct ifnet *);
224 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
225 static void sk_reset(struct sk_softc *);
226 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
227 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
228 static int sk_newbuf(struct sk_if_softc *, int);
229 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
230 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
231 static int sk_dma_alloc(struct sk_if_softc *);
232 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
233 static void sk_dma_free(struct sk_if_softc *);
234 static void sk_dma_jumbo_free(struct sk_if_softc *);
235 static int sk_init_rx_ring(struct sk_if_softc *);
236 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
237 static void sk_init_tx_ring(struct sk_if_softc *);
238 static u_int32_t sk_win_read_4(struct sk_softc *, int);
239 static u_int16_t sk_win_read_2(struct sk_softc *, int);
240 static u_int8_t sk_win_read_1(struct sk_softc *, int);
241 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
242 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
243 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
245 static int sk_miibus_readreg(device_t, int, int);
246 static int sk_miibus_writereg(device_t, int, int, int);
247 static void sk_miibus_statchg(device_t);
249 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
250 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
252 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
254 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
255 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
257 static void sk_marv_miibus_statchg(struct sk_if_softc *);
259 static uint32_t sk_xmchash(const uint8_t *);
260 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
261 static void sk_rxfilter(struct sk_if_softc *);
262 static void sk_rxfilter_genesis(struct sk_if_softc *);
263 static void sk_rxfilter_yukon(struct sk_if_softc *);
265 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
266 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
269 static int jumbo_disable = 0;
270 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
273 * It seems that SK-NET GENESIS supports very simple checksum offload
274 * capability for Tx and I believe it can generate 0 checksum value for
275 * UDP packets in Tx as the hardware can't differenciate UDP packets from
276 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
277 * means sender didn't perforam checksum computation. For the safety I
278 * disabled UDP checksum offload capability at the moment. Alternatively
279 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
282 #define SK_CSUM_FEATURES (CSUM_TCP)
285 * Note that we have newbus methods for both the GEnesis controller
286 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
287 * the miibus code is a child of the XMACs. We need to do it this way
288 * so that the miibus drivers can access the PHY registers on the
289 * right PHY. It's not quite what I had in mind, but it's the only
290 * design that achieves the desired effect.
292 static device_method_t skc_methods[] = {
293 /* Device interface */
294 DEVMETHOD(device_probe, skc_probe),
295 DEVMETHOD(device_attach, skc_attach),
296 DEVMETHOD(device_detach, skc_detach),
297 DEVMETHOD(device_suspend, skc_suspend),
298 DEVMETHOD(device_resume, skc_resume),
299 DEVMETHOD(device_shutdown, skc_shutdown),
301 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag),
306 static driver_t skc_driver = {
309 sizeof(struct sk_softc)
312 static devclass_t skc_devclass;
314 static device_method_t sk_methods[] = {
315 /* Device interface */
316 DEVMETHOD(device_probe, sk_probe),
317 DEVMETHOD(device_attach, sk_attach),
318 DEVMETHOD(device_detach, sk_detach),
319 DEVMETHOD(device_shutdown, bus_generic_shutdown),
322 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
323 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
324 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
329 static driver_t sk_driver = {
332 sizeof(struct sk_if_softc)
335 static devclass_t sk_devclass;
337 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, NULL, NULL);
338 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, NULL, NULL);
339 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL);
341 static struct resource_spec sk_res_spec_io[] = {
342 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
343 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
347 static struct resource_spec sk_res_spec_mem[] = {
348 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
349 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
353 #define SK_SETBIT(sc, reg, x) \
354 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
356 #define SK_CLRBIT(sc, reg, x) \
357 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
359 #define SK_WIN_SETBIT_4(sc, reg, x) \
360 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
362 #define SK_WIN_CLRBIT_4(sc, reg, x) \
363 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
365 #define SK_WIN_SETBIT_2(sc, reg, x) \
366 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
368 #define SK_WIN_CLRBIT_2(sc, reg, x) \
369 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
372 sk_win_read_4(sc, reg)
377 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
378 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
380 return(CSR_READ_4(sc, reg));
385 sk_win_read_2(sc, reg)
390 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
391 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
393 return(CSR_READ_2(sc, reg));
398 sk_win_read_1(sc, reg)
403 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
404 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
406 return(CSR_READ_1(sc, reg));
411 sk_win_write_4(sc, reg, val)
417 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
418 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
420 CSR_WRITE_4(sc, reg, val);
426 sk_win_write_2(sc, reg, val)
432 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
433 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
435 CSR_WRITE_2(sc, reg, val);
441 sk_win_write_1(sc, reg, val)
447 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
448 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
450 CSR_WRITE_1(sc, reg, val);
456 sk_miibus_readreg(dev, phy, reg)
460 struct sk_if_softc *sc_if;
463 sc_if = device_get_softc(dev);
465 SK_IF_MII_LOCK(sc_if);
466 switch(sc_if->sk_softc->sk_type) {
468 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
473 v = sk_marv_miibus_readreg(sc_if, phy, reg);
479 SK_IF_MII_UNLOCK(sc_if);
485 sk_miibus_writereg(dev, phy, reg, val)
489 struct sk_if_softc *sc_if;
492 sc_if = device_get_softc(dev);
494 SK_IF_MII_LOCK(sc_if);
495 switch(sc_if->sk_softc->sk_type) {
497 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
502 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
508 SK_IF_MII_UNLOCK(sc_if);
514 sk_miibus_statchg(dev)
517 struct sk_if_softc *sc_if;
519 sc_if = device_get_softc(dev);
521 SK_IF_MII_LOCK(sc_if);
522 switch(sc_if->sk_softc->sk_type) {
524 sk_xmac_miibus_statchg(sc_if);
529 sk_marv_miibus_statchg(sc_if);
532 SK_IF_MII_UNLOCK(sc_if);
538 sk_xmac_miibus_readreg(sc_if, phy, reg)
539 struct sk_if_softc *sc_if;
544 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
545 SK_XM_READ_2(sc_if, XM_PHY_DATA);
546 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
547 for (i = 0; i < SK_TIMEOUT; i++) {
549 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
550 XM_MMUCMD_PHYDATARDY)
554 if (i == SK_TIMEOUT) {
555 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
560 i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
566 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
567 struct sk_if_softc *sc_if;
572 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
573 for (i = 0; i < SK_TIMEOUT; i++) {
574 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
578 if (i == SK_TIMEOUT) {
579 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
583 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
584 for (i = 0; i < SK_TIMEOUT; i++) {
586 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
590 if_printf(sc_if->sk_ifp, "phy write timed out\n");
596 sk_xmac_miibus_statchg(sc_if)
597 struct sk_if_softc *sc_if;
599 struct mii_data *mii;
601 mii = device_get_softc(sc_if->sk_miibus);
604 * If this is a GMII PHY, manually set the XMAC's
605 * duplex mode accordingly.
607 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
608 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
609 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
611 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
617 sk_marv_miibus_readreg(sc_if, phy, reg)
618 struct sk_if_softc *sc_if;
624 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
625 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
629 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
630 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
632 for (i = 0; i < SK_TIMEOUT; i++) {
634 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
635 if (val & YU_SMICR_READ_VALID)
639 if (i == SK_TIMEOUT) {
640 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
644 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
650 sk_marv_miibus_writereg(sc_if, phy, reg, val)
651 struct sk_if_softc *sc_if;
656 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
657 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
658 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
660 for (i = 0; i < SK_TIMEOUT; i++) {
662 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
666 if_printf(sc_if->sk_ifp, "phy write timeout\n");
672 sk_marv_miibus_statchg(sc_if)
673 struct sk_if_softc *sc_if;
686 /* Compute CRC for the address value. */
687 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
689 return (~crc & ((1 << HASH_BITS) - 1));
693 sk_setfilt(sc_if, addr, slot)
694 struct sk_if_softc *sc_if;
700 base = XM_RXFILT_ENTRY(slot);
702 SK_XM_WRITE_2(sc_if, base, addr[0]);
703 SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
704 SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
711 struct sk_if_softc *sc_if;
715 SK_IF_LOCK_ASSERT(sc_if);
717 sc = sc_if->sk_softc;
718 if (sc->sk_type == SK_GENESIS)
719 sk_rxfilter_genesis(sc_if);
721 sk_rxfilter_yukon(sc_if);
725 sk_rxfilter_genesis(sc_if)
726 struct sk_if_softc *sc_if;
728 struct ifnet *ifp = sc_if->sk_ifp;
729 u_int32_t hashes[2] = { 0, 0 }, mode;
731 struct ifmultiaddr *ifma;
732 u_int16_t dummy[] = { 0, 0, 0 };
733 u_int16_t maddr[(ETHER_ADDR_LEN+1)/2];
735 SK_IF_LOCK_ASSERT(sc_if);
737 mode = SK_XM_READ_4(sc_if, XM_MODE);
738 mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
739 XM_MODE_RX_USE_PERFECT);
740 /* First, zot all the existing perfect filters. */
741 for (i = 1; i < XM_RXFILT_MAX; i++)
742 sk_setfilt(sc_if, dummy, i);
744 /* Now program new ones. */
745 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
746 if (ifp->if_flags & IFF_ALLMULTI)
747 mode |= XM_MODE_RX_USE_HASH;
748 if (ifp->if_flags & IFF_PROMISC)
749 mode |= XM_MODE_RX_PROMISC;
750 hashes[0] = 0xFFFFFFFF;
751 hashes[1] = 0xFFFFFFFF;
755 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
757 if (ifma->ifma_addr->sa_family != AF_LINK)
760 * Program the first XM_RXFILT_MAX multicast groups
761 * into the perfect filter.
763 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
764 maddr, ETHER_ADDR_LEN);
765 if (i < XM_RXFILT_MAX) {
766 sk_setfilt(sc_if, maddr, i);
767 mode |= XM_MODE_RX_USE_PERFECT;
771 h = sk_xmchash((const uint8_t *)maddr);
773 hashes[0] |= (1 << h);
775 hashes[1] |= (1 << (h - 32));
776 mode |= XM_MODE_RX_USE_HASH;
778 if_maddr_runlock(ifp);
781 SK_XM_WRITE_4(sc_if, XM_MODE, mode);
782 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
783 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
787 sk_rxfilter_yukon(sc_if)
788 struct sk_if_softc *sc_if;
791 u_int32_t crc, hashes[2] = { 0, 0 }, mode;
792 struct ifmultiaddr *ifma;
794 SK_IF_LOCK_ASSERT(sc_if);
797 mode = SK_YU_READ_2(sc_if, YUKON_RCR);
798 if (ifp->if_flags & IFF_PROMISC)
799 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
800 else if (ifp->if_flags & IFF_ALLMULTI) {
801 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
802 hashes[0] = 0xFFFFFFFF;
803 hashes[1] = 0xFFFFFFFF;
805 mode |= YU_RCR_UFLEN;
807 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
808 if (ifma->ifma_addr->sa_family != AF_LINK)
810 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
811 ifma->ifma_addr), ETHER_ADDR_LEN);
812 /* Just want the 6 least significant bits. */
814 /* Set the corresponding bit in the hash table. */
815 hashes[crc >> 5] |= 1 << (crc & 0x1f);
817 if_maddr_runlock(ifp);
818 if (hashes[0] != 0 || hashes[1] != 0)
819 mode |= YU_RCR_MUFLEN;
822 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
823 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
824 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
825 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
826 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
830 sk_init_rx_ring(sc_if)
831 struct sk_if_softc *sc_if;
833 struct sk_ring_data *rd;
835 u_int32_t csum_start;
838 sc_if->sk_cdata.sk_rx_cons = 0;
840 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 |
842 rd = &sc_if->sk_rdata;
843 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
844 for (i = 0; i < SK_RX_RING_CNT; i++) {
845 if (sk_newbuf(sc_if, i) != 0)
847 if (i == (SK_RX_RING_CNT - 1))
848 addr = SK_RX_RING_ADDR(sc_if, 0);
850 addr = SK_RX_RING_ADDR(sc_if, i + 1);
851 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
852 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
855 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
856 sc_if->sk_cdata.sk_rx_ring_map,
857 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
863 sk_init_jumbo_rx_ring(sc_if)
864 struct sk_if_softc *sc_if;
866 struct sk_ring_data *rd;
868 u_int32_t csum_start;
871 sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
873 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
875 rd = &sc_if->sk_rdata;
876 bzero(rd->sk_jumbo_rx_ring,
877 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
878 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
879 if (sk_jumbo_newbuf(sc_if, i) != 0)
881 if (i == (SK_JUMBO_RX_RING_CNT - 1))
882 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
884 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
885 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
886 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
889 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
890 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
891 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
897 sk_init_tx_ring(sc_if)
898 struct sk_if_softc *sc_if;
900 struct sk_ring_data *rd;
901 struct sk_txdesc *txd;
905 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
906 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
908 sc_if->sk_cdata.sk_tx_prod = 0;
909 sc_if->sk_cdata.sk_tx_cons = 0;
910 sc_if->sk_cdata.sk_tx_cnt = 0;
912 rd = &sc_if->sk_rdata;
913 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
914 for (i = 0; i < SK_TX_RING_CNT; i++) {
915 if (i == (SK_TX_RING_CNT - 1))
916 addr = SK_TX_RING_ADDR(sc_if, 0);
918 addr = SK_TX_RING_ADDR(sc_if, i + 1);
919 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
920 txd = &sc_if->sk_cdata.sk_txdesc[i];
921 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
924 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
925 sc_if->sk_cdata.sk_tx_ring_map,
926 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
930 sk_discard_rxbuf(sc_if, idx)
931 struct sk_if_softc *sc_if;
934 struct sk_rx_desc *r;
935 struct sk_rxdesc *rxd;
939 r = &sc_if->sk_rdata.sk_rx_ring[idx];
940 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
942 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
946 sk_discard_jumbo_rxbuf(sc_if, idx)
947 struct sk_if_softc *sc_if;
950 struct sk_rx_desc *r;
951 struct sk_rxdesc *rxd;
954 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
955 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
957 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
961 sk_newbuf(sc_if, idx)
962 struct sk_if_softc *sc_if;
965 struct sk_rx_desc *r;
966 struct sk_rxdesc *rxd;
968 bus_dma_segment_t segs[1];
972 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
975 m->m_len = m->m_pkthdr.len = MCLBYTES;
976 m_adj(m, ETHER_ALIGN);
978 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
979 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
983 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
985 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
986 if (rxd->rx_m != NULL) {
987 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
988 BUS_DMASYNC_POSTREAD);
989 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
991 map = rxd->rx_dmamap;
992 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
993 sc_if->sk_cdata.sk_rx_sparemap = map;
994 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
995 BUS_DMASYNC_PREREAD);
997 r = &sc_if->sk_rdata.sk_rx_ring[idx];
998 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
999 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1000 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1006 sk_jumbo_newbuf(sc_if, idx)
1007 struct sk_if_softc *sc_if;
1010 struct sk_rx_desc *r;
1011 struct sk_rxdesc *rxd;
1013 bus_dma_segment_t segs[1];
1017 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1020 if ((m->m_flags & M_EXT) == 0) {
1024 m->m_pkthdr.len = m->m_len = MJUM9BYTES;
1026 * Adjust alignment so packet payload begins on a
1027 * longword boundary. Mandatory for Alpha, useful on
1030 m_adj(m, ETHER_ALIGN);
1032 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1033 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1037 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1039 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1040 if (rxd->rx_m != NULL) {
1041 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1042 BUS_DMASYNC_POSTREAD);
1043 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1046 map = rxd->rx_dmamap;
1047 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1048 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1049 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1050 BUS_DMASYNC_PREREAD);
1052 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1053 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1054 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1055 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1061 * Set media options.
1067 struct sk_if_softc *sc_if = ifp->if_softc;
1068 struct mii_data *mii;
1070 mii = device_get_softc(sc_if->sk_miibus);
1078 * Report current media status.
1081 sk_ifmedia_sts(ifp, ifmr)
1083 struct ifmediareq *ifmr;
1085 struct sk_if_softc *sc_if;
1086 struct mii_data *mii;
1088 sc_if = ifp->if_softc;
1089 mii = device_get_softc(sc_if->sk_miibus);
1092 ifmr->ifm_active = mii->mii_media_active;
1093 ifmr->ifm_status = mii->mii_media_status;
1099 sk_ioctl(ifp, command, data)
1104 struct sk_if_softc *sc_if = ifp->if_softc;
1105 struct ifreq *ifr = (struct ifreq *) data;
1107 struct mii_data *mii;
1112 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1114 else if (ifp->if_mtu != ifr->ifr_mtu) {
1115 if (sc_if->sk_jumbo_disable != 0 &&
1116 ifr->ifr_mtu > SK_MAX_FRAMELEN)
1120 ifp->if_mtu = ifr->ifr_mtu;
1121 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1122 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1123 sk_init_locked(sc_if);
1125 SK_IF_UNLOCK(sc_if);
1131 if (ifp->if_flags & IFF_UP) {
1132 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1133 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1134 & (IFF_PROMISC | IFF_ALLMULTI))
1137 sk_init_locked(sc_if);
1139 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1142 sc_if->sk_if_flags = ifp->if_flags;
1143 SK_IF_UNLOCK(sc_if);
1148 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1150 SK_IF_UNLOCK(sc_if);
1154 mii = device_get_softc(sc_if->sk_miibus);
1155 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1159 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1160 SK_IF_UNLOCK(sc_if);
1163 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1164 if ((mask & IFCAP_TXCSUM) != 0 &&
1165 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1166 ifp->if_capenable ^= IFCAP_TXCSUM;
1167 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1168 ifp->if_hwassist |= SK_CSUM_FEATURES;
1170 ifp->if_hwassist &= ~SK_CSUM_FEATURES;
1172 if ((mask & IFCAP_RXCSUM) != 0 &&
1173 (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
1174 ifp->if_capenable ^= IFCAP_RXCSUM;
1175 SK_IF_UNLOCK(sc_if);
1178 error = ether_ioctl(ifp, command, data);
1186 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1187 * IDs against our list and return a device name if we find a match.
1193 const struct sk_type *t = sk_devs;
1195 while(t->sk_name != NULL) {
1196 if ((pci_get_vendor(dev) == t->sk_vid) &&
1197 (pci_get_device(dev) == t->sk_did)) {
1199 * Only attach to rev. 2 of the Linksys EG1032 adapter.
1200 * Rev. 3 is supported by re(4).
1202 if ((t->sk_vid == VENDORID_LINKSYS) &&
1203 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1204 (pci_get_subdevice(dev) !=
1205 SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1209 device_set_desc(dev, t->sk_name);
1210 return (BUS_PROBE_DEFAULT);
1219 * Force the GEnesis into reset, then bring it out of reset.
1223 struct sk_softc *sc;
1226 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1227 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1228 if (SK_YUKON_FAMILY(sc->sk_type))
1229 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1232 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1234 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1235 if (SK_YUKON_FAMILY(sc->sk_type))
1236 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1238 if (sc->sk_type == SK_GENESIS) {
1239 /* Configure packet arbiter */
1240 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1241 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1242 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1243 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1244 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1247 /* Enable RAM interface */
1248 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1251 * Configure interrupt moderation. The moderation timer
1252 * defers interrupts specified in the interrupt moderation
1253 * timer mask based on the timeout specified in the interrupt
1254 * moderation timer init register. Each bit in the timer
1255 * register represents one tick, so to specify a timeout in
1256 * microseconds, we have to multiply by the correct number of
1257 * ticks-per-microsecond.
1259 switch (sc->sk_type) {
1261 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1264 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1268 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1270 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1272 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1273 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1274 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1283 struct sk_softc *sc;
1285 sc = device_get_softc(device_get_parent(dev));
1288 * Not much to do here. We always know there will be
1289 * at least one XMAC present, and if there are two,
1290 * skc_attach() will create a second device instance
1293 switch (sc->sk_type) {
1295 device_set_desc(dev, "XaQti Corp. XMAC II");
1300 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1304 return (BUS_PROBE_DEFAULT);
1308 * Each XMAC chip is attached as a separate logical IP interface.
1309 * Single port cards will have only one logical interface of course.
1315 struct sk_softc *sc;
1316 struct sk_if_softc *sc_if;
1319 int error, i, phy, port;
1321 u_char inv_mac[] = {0, 0, 0, 0, 0, 0};
1327 sc_if = device_get_softc(dev);
1328 sc = device_get_softc(device_get_parent(dev));
1329 port = *(int *)device_get_ivars(dev);
1331 sc_if->sk_if_dev = dev;
1332 sc_if->sk_port = port;
1333 sc_if->sk_softc = sc;
1334 sc->sk_if[port] = sc_if;
1335 if (port == SK_PORT_A)
1336 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1337 if (port == SK_PORT_B)
1338 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1340 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1341 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1343 if (sk_dma_alloc(sc_if) != 0) {
1347 sk_dma_jumbo_alloc(sc_if);
1349 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1351 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1355 ifp->if_softc = sc_if;
1356 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1357 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1359 * SK_GENESIS has a bug in checksum offload - From linux.
1361 if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1362 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
1363 ifp->if_hwassist = 0;
1365 ifp->if_capabilities = 0;
1366 ifp->if_hwassist = 0;
1368 ifp->if_capenable = ifp->if_capabilities;
1370 * Some revision of Yukon controller generates corrupted
1371 * frame when TX checksum offloading is enabled. The
1372 * frame has a valid checksum value so payload might be
1373 * modified during TX checksum calculation. Disable TX
1374 * checksum offloading but give users chance to enable it
1375 * when they know their controller works without problems
1376 * with TX checksum offloading.
1378 ifp->if_capenable &= ~IFCAP_TXCSUM;
1379 ifp->if_ioctl = sk_ioctl;
1380 ifp->if_start = sk_start;
1381 ifp->if_init = sk_init;
1382 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1383 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1384 IFQ_SET_READY(&ifp->if_snd);
1387 * Get station address for this interface. Note that
1388 * dual port cards actually come with three station
1389 * addresses: one for each port, plus an extra. The
1390 * extra one is used by the SysKonnect driver software
1391 * as a 'virtual' station address for when both ports
1392 * are operating in failover mode. Currently we don't
1393 * use this extra address.
1396 for (i = 0; i < ETHER_ADDR_LEN; i++)
1398 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1400 /* Verify whether the station address is invalid or not. */
1401 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1402 device_printf(sc_if->sk_if_dev,
1403 "Generating random ethernet address\n");
1406 * Set OUI to convenient locally assigned address. 'b'
1407 * is 0x62, which has the locally assigned bit set, and
1408 * the broadcast/multicast bit clear.
1413 eaddr[3] = (r >> 16) & 0xff;
1414 eaddr[4] = (r >> 8) & 0xff;
1415 eaddr[5] = (r >> 0) & 0xff;
1418 * Set up RAM buffer addresses. The NIC will have a certain
1419 * amount of SRAM on it, somewhere between 512K and 2MB. We
1420 * need to divide this up a) between the transmitter and
1421 * receiver and b) between the two XMACs, if this is a
1422 * dual port NIC. Our algotithm is to divide up the memory
1423 * evenly so that everyone gets a fair share.
1425 * Just to be contrary, Yukon2 appears to have separate memory
1428 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1429 u_int32_t chunk, val;
1431 chunk = sc->sk_ramsize / 2;
1432 val = sc->sk_rboff / sizeof(u_int64_t);
1433 sc_if->sk_rx_ramstart = val;
1434 val += (chunk / sizeof(u_int64_t));
1435 sc_if->sk_rx_ramend = val - 1;
1436 sc_if->sk_tx_ramstart = val;
1437 val += (chunk / sizeof(u_int64_t));
1438 sc_if->sk_tx_ramend = val - 1;
1440 u_int32_t chunk, val;
1442 chunk = sc->sk_ramsize / 4;
1443 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1445 sc_if->sk_rx_ramstart = val;
1446 val += (chunk / sizeof(u_int64_t));
1447 sc_if->sk_rx_ramend = val - 1;
1448 sc_if->sk_tx_ramstart = val;
1449 val += (chunk / sizeof(u_int64_t));
1450 sc_if->sk_tx_ramend = val - 1;
1453 /* Read and save PHY type and set PHY address */
1454 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1455 if (!SK_YUKON_FAMILY(sc->sk_type)) {
1456 switch(sc_if->sk_phytype) {
1457 case SK_PHYTYPE_XMAC:
1458 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1460 case SK_PHYTYPE_BCOM:
1461 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1464 device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1467 SK_IF_UNLOCK(sc_if);
1471 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1472 sc->sk_pmd != 'S') {
1473 /* not initialized, punt */
1474 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1475 sc->sk_coppertype = 1;
1478 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1480 if (!(sc->sk_coppertype))
1481 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1485 * Call MI attach routine. Can't hold locks when calling into ether_*.
1487 SK_IF_UNLOCK(sc_if);
1488 ether_ifattach(ifp, eaddr);
1492 * The hardware should be ready for VLAN_MTU by default:
1493 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1494 * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1497 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1498 ifp->if_capenable |= IFCAP_VLAN_MTU;
1500 * Tell the upper layer(s) we support long frames.
1501 * Must appear after the call to ether_ifattach() because
1502 * ether_ifattach() sets ifi_hdrlen to the default value.
1504 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1510 switch (sc->sk_type) {
1512 sk_init_xmac(sc_if);
1513 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1519 sk_init_yukon(sc_if);
1524 SK_IF_UNLOCK(sc_if);
1525 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1526 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1528 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1529 ether_ifdetach(ifp);
1535 /* Access should be ok even though lock has been dropped */
1536 sc->sk_if[port] = NULL;
1544 * Attach the interface. Allocate softc structures, do ifmedia
1545 * setup and ethernet/BPF attach.
1551 struct sk_softc *sc;
1552 int error = 0, *port;
1554 const char *pname = NULL;
1557 sc = device_get_softc(dev);
1560 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1562 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1564 * Map control/status registers.
1566 pci_enable_busmaster(dev);
1568 /* Allocate resources */
1569 #ifdef SK_USEIOSPACE
1570 sc->sk_res_spec = sk_res_spec_io;
1572 sc->sk_res_spec = sk_res_spec_mem;
1574 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1576 if (sc->sk_res_spec == sk_res_spec_mem)
1577 sc->sk_res_spec = sk_res_spec_io;
1579 sc->sk_res_spec = sk_res_spec_mem;
1580 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1582 device_printf(dev, "couldn't allocate %s resources\n",
1583 sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1589 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1590 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1592 /* Bail out if chip is not recognized. */
1593 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1594 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1595 sc->sk_type, sc->sk_rev);
1600 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1601 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1602 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1603 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1604 "SK interrupt moderation");
1606 /* Pull in device tunables. */
1607 sc->sk_int_mod = SK_IM_DEFAULT;
1608 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1609 "int_mod", &sc->sk_int_mod);
1611 if (sc->sk_int_mod < SK_IM_MIN ||
1612 sc->sk_int_mod > SK_IM_MAX) {
1613 device_printf(dev, "int_mod value out of range; "
1614 "using default: %d\n", SK_IM_DEFAULT);
1615 sc->sk_int_mod = SK_IM_DEFAULT;
1619 /* Reset the adapter. */
1622 skrs = sk_win_read_1(sc, SK_EPROM0);
1623 if (sc->sk_type == SK_GENESIS) {
1624 /* Read and save RAM size and RAMbuffer offset */
1626 case SK_RAMSIZE_512K_64:
1627 sc->sk_ramsize = 0x80000;
1628 sc->sk_rboff = SK_RBOFF_0;
1630 case SK_RAMSIZE_1024K_64:
1631 sc->sk_ramsize = 0x100000;
1632 sc->sk_rboff = SK_RBOFF_80000;
1634 case SK_RAMSIZE_1024K_128:
1635 sc->sk_ramsize = 0x100000;
1636 sc->sk_rboff = SK_RBOFF_0;
1638 case SK_RAMSIZE_2048K_128:
1639 sc->sk_ramsize = 0x200000;
1640 sc->sk_rboff = SK_RBOFF_0;
1643 device_printf(dev, "unknown ram size: %d\n", skrs);
1647 } else { /* SK_YUKON_FAMILY */
1649 sc->sk_ramsize = 0x20000;
1651 sc->sk_ramsize = skrs * (1<<12);
1652 sc->sk_rboff = SK_RBOFF_0;
1655 /* Read and save physical media type */
1656 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1658 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1659 sc->sk_coppertype = 1;
1661 sc->sk_coppertype = 0;
1663 /* Determine whether to name it with VPD PN or just make it up.
1664 * Marvell Yukon VPD PN seems to freqently be bogus. */
1665 switch (pci_get_device(dev)) {
1666 case DEVICEID_SK_V1:
1667 case DEVICEID_BELKIN_5005:
1668 case DEVICEID_3COM_3C940:
1669 case DEVICEID_LINKSYS_EG1032:
1670 case DEVICEID_DLINK_DGE530T_A1:
1671 case DEVICEID_DLINK_DGE530T_B1:
1672 /* Stay with VPD PN. */
1673 (void) pci_get_vpd_ident(dev, &pname);
1675 case DEVICEID_SK_V2:
1676 /* YUKON VPD PN might bear no resemblance to reality. */
1677 switch (sc->sk_type) {
1679 /* Stay with VPD PN. */
1680 (void) pci_get_vpd_ident(dev, &pname);
1683 pname = "Marvell Yukon Gigabit Ethernet";
1686 pname = "Marvell Yukon Lite Gigabit Ethernet";
1689 pname = "Marvell Yukon LP Gigabit Ethernet";
1692 pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1696 /* Yukon Lite Rev. A0 needs special test. */
1697 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1701 /* Save flash address register before testing. */
1702 far = sk_win_read_4(sc, SK_EP_ADDR);
1704 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1705 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1707 if (testbyte != 0x00) {
1708 /* Yukon Lite Rev. A0 detected. */
1709 sc->sk_type = SK_YUKON_LITE;
1710 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1711 /* Restore flash address register. */
1712 sk_win_write_4(sc, SK_EP_ADDR, far);
1717 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1718 "chipver=%02x, rev=%x\n",
1719 pci_get_vendor(dev), pci_get_device(dev),
1720 sc->sk_type, sc->sk_rev);
1725 if (sc->sk_type == SK_YUKON_LITE) {
1726 switch (sc->sk_rev) {
1727 case SK_YUKON_LITE_REV_A0:
1730 case SK_YUKON_LITE_REV_A1:
1733 case SK_YUKON_LITE_REV_A3:
1744 /* Announce the product name and more VPD data if there. */
1746 device_printf(dev, "%s rev. %s(0x%x)\n",
1747 pname, revstr, sc->sk_rev);
1750 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type);
1751 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev);
1752 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1753 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1756 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1757 if (sc->sk_devs[SK_PORT_A] == NULL) {
1758 device_printf(dev, "failed to add child for PORT_A\n");
1762 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1764 device_printf(dev, "failed to allocate memory for "
1765 "ivars of PORT_A\n");
1770 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1772 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1773 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1774 if (sc->sk_devs[SK_PORT_B] == NULL) {
1775 device_printf(dev, "failed to add child for PORT_B\n");
1779 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1781 device_printf(dev, "failed to allocate memory for "
1782 "ivars of PORT_B\n");
1787 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1790 /* Turn on the 'driver is loaded' LED. */
1791 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1793 error = bus_generic_attach(dev);
1795 device_printf(dev, "failed to attach port(s)\n");
1799 /* Hook interrupt last to avoid having to lock softc */
1800 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1801 NULL, sk_intr, sc, &sc->sk_intrhand);
1804 device_printf(dev, "couldn't set up irq\n");
1816 * Shutdown hardware and free up resources. This can be called any
1817 * time after the mutex has been initialized. It is called in both
1818 * the error case in attach and the normal detach case so it needs
1819 * to be careful about only freeing resources that have actually been
1826 struct sk_if_softc *sc_if;
1829 sc_if = device_get_softc(dev);
1830 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1831 ("sk mutex not initialized in sk_detach"));
1834 ifp = sc_if->sk_ifp;
1835 /* These should only be active if attach_xmac succeeded */
1836 if (device_is_attached(dev)) {
1838 /* Can't hold locks while calling detach */
1839 SK_IF_UNLOCK(sc_if);
1840 callout_drain(&sc_if->sk_tick_ch);
1841 callout_drain(&sc_if->sk_watchdog_ch);
1842 ether_ifdetach(ifp);
1848 * We're generally called from skc_detach() which is using
1849 * device_delete_child() to get to here. It's already trashed
1850 * miibus for us, so don't do it here or we'll panic.
1853 if (sc_if->sk_miibus != NULL)
1854 device_delete_child(dev, sc_if->sk_miibus);
1856 bus_generic_detach(dev);
1857 sk_dma_jumbo_free(sc_if);
1859 SK_IF_UNLOCK(sc_if);
1868 struct sk_softc *sc;
1870 sc = device_get_softc(dev);
1871 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1873 if (device_is_alive(dev)) {
1874 if (sc->sk_devs[SK_PORT_A] != NULL) {
1875 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1876 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1878 if (sc->sk_devs[SK_PORT_B] != NULL) {
1879 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1880 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1882 bus_generic_detach(dev);
1885 if (sc->sk_intrhand)
1886 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1887 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1889 mtx_destroy(&sc->sk_mii_mtx);
1890 mtx_destroy(&sc->sk_mtx);
1895 static bus_dma_tag_t
1896 skc_get_dma_tag(device_t bus, device_t child __unused)
1899 return (bus_get_dma_tag(bus));
1902 struct sk_dmamap_arg {
1903 bus_addr_t sk_busaddr;
1907 sk_dmamap_cb(arg, segs, nseg, error)
1909 bus_dma_segment_t *segs;
1913 struct sk_dmamap_arg *ctx;
1919 ctx->sk_busaddr = segs[0].ds_addr;
1923 * Allocate jumbo buffer storage. The SysKonnect adapters support
1924 * "jumbograms" (9K frames), although SysKonnect doesn't currently
1925 * use them in their drivers. In order for us to use them, we need
1926 * large 9K receive buffers, however standard mbuf clusters are only
1927 * 2048 bytes in size. Consequently, we need to allocate and manage
1928 * our own jumbo buffer pool. Fortunately, this does not require an
1929 * excessive amount of additional code.
1933 struct sk_if_softc *sc_if;
1935 struct sk_dmamap_arg ctx;
1936 struct sk_txdesc *txd;
1937 struct sk_rxdesc *rxd;
1940 /* create parent tag */
1943 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1944 * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1945 * However bz@ reported that it does not work on amd64 with > 4GB
1946 * RAM. Until we have more clues of the breakage, disable DAC mode
1947 * by limiting DMA address to be in 32bit address space.
1949 error = bus_dma_tag_create(
1950 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1951 1, 0, /* algnmnt, boundary */
1952 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1953 BUS_SPACE_MAXADDR, /* highaddr */
1954 NULL, NULL, /* filter, filterarg */
1955 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1957 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1959 NULL, NULL, /* lockfunc, lockarg */
1960 &sc_if->sk_cdata.sk_parent_tag);
1962 device_printf(sc_if->sk_if_dev,
1963 "failed to create parent DMA tag\n");
1967 /* create tag for Tx ring */
1968 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1969 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1970 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1971 BUS_SPACE_MAXADDR, /* highaddr */
1972 NULL, NULL, /* filter, filterarg */
1973 SK_TX_RING_SZ, /* maxsize */
1975 SK_TX_RING_SZ, /* maxsegsize */
1977 NULL, NULL, /* lockfunc, lockarg */
1978 &sc_if->sk_cdata.sk_tx_ring_tag);
1980 device_printf(sc_if->sk_if_dev,
1981 "failed to allocate Tx ring DMA tag\n");
1985 /* create tag for Rx ring */
1986 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1987 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1988 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1989 BUS_SPACE_MAXADDR, /* highaddr */
1990 NULL, NULL, /* filter, filterarg */
1991 SK_RX_RING_SZ, /* maxsize */
1993 SK_RX_RING_SZ, /* maxsegsize */
1995 NULL, NULL, /* lockfunc, lockarg */
1996 &sc_if->sk_cdata.sk_rx_ring_tag);
1998 device_printf(sc_if->sk_if_dev,
1999 "failed to allocate Rx ring DMA tag\n");
2003 /* create tag for Tx buffers */
2004 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2005 1, 0, /* algnmnt, boundary */
2006 BUS_SPACE_MAXADDR, /* lowaddr */
2007 BUS_SPACE_MAXADDR, /* highaddr */
2008 NULL, NULL, /* filter, filterarg */
2009 MCLBYTES * SK_MAXTXSEGS, /* maxsize */
2010 SK_MAXTXSEGS, /* nsegments */
2011 MCLBYTES, /* maxsegsize */
2013 NULL, NULL, /* lockfunc, lockarg */
2014 &sc_if->sk_cdata.sk_tx_tag);
2016 device_printf(sc_if->sk_if_dev,
2017 "failed to allocate Tx DMA tag\n");
2021 /* create tag for Rx buffers */
2022 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2023 1, 0, /* algnmnt, boundary */
2024 BUS_SPACE_MAXADDR, /* lowaddr */
2025 BUS_SPACE_MAXADDR, /* highaddr */
2026 NULL, NULL, /* filter, filterarg */
2027 MCLBYTES, /* maxsize */
2029 MCLBYTES, /* maxsegsize */
2031 NULL, NULL, /* lockfunc, lockarg */
2032 &sc_if->sk_cdata.sk_rx_tag);
2034 device_printf(sc_if->sk_if_dev,
2035 "failed to allocate Rx DMA tag\n");
2039 /* allocate DMA'able memory and load the DMA map for Tx ring */
2040 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2041 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
2042 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
2044 device_printf(sc_if->sk_if_dev,
2045 "failed to allocate DMA'able memory for Tx ring\n");
2050 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2051 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2052 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2054 device_printf(sc_if->sk_if_dev,
2055 "failed to load DMA'able memory for Tx ring\n");
2058 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2060 /* allocate DMA'able memory and load the DMA map for Rx ring */
2061 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2062 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
2063 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
2065 device_printf(sc_if->sk_if_dev,
2066 "failed to allocate DMA'able memory for Rx ring\n");
2071 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2072 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2073 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2075 device_printf(sc_if->sk_if_dev,
2076 "failed to load DMA'able memory for Rx ring\n");
2079 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2081 /* create DMA maps for Tx buffers */
2082 for (i = 0; i < SK_TX_RING_CNT; i++) {
2083 txd = &sc_if->sk_cdata.sk_txdesc[i];
2085 txd->tx_dmamap = NULL;
2086 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2089 device_printf(sc_if->sk_if_dev,
2090 "failed to create Tx dmamap\n");
2095 /* create DMA maps for Rx buffers */
2096 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2097 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2098 device_printf(sc_if->sk_if_dev,
2099 "failed to create spare Rx dmamap\n");
2102 for (i = 0; i < SK_RX_RING_CNT; i++) {
2103 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2105 rxd->rx_dmamap = NULL;
2106 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2109 device_printf(sc_if->sk_if_dev,
2110 "failed to create Rx dmamap\n");
2120 sk_dma_jumbo_alloc(sc_if)
2121 struct sk_if_softc *sc_if;
2123 struct sk_dmamap_arg ctx;
2124 struct sk_rxdesc *jrxd;
2127 if (jumbo_disable != 0) {
2128 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2129 sc_if->sk_jumbo_disable = 1;
2132 /* create tag for jumbo Rx ring */
2133 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2134 SK_RING_ALIGN, 0, /* algnmnt, boundary */
2135 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2136 BUS_SPACE_MAXADDR, /* highaddr */
2137 NULL, NULL, /* filter, filterarg */
2138 SK_JUMBO_RX_RING_SZ, /* maxsize */
2140 SK_JUMBO_RX_RING_SZ, /* maxsegsize */
2142 NULL, NULL, /* lockfunc, lockarg */
2143 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2145 device_printf(sc_if->sk_if_dev,
2146 "failed to allocate jumbo Rx ring DMA tag\n");
2150 /* create tag for jumbo Rx buffers */
2151 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2152 1, 0, /* algnmnt, boundary */
2153 BUS_SPACE_MAXADDR, /* lowaddr */
2154 BUS_SPACE_MAXADDR, /* highaddr */
2155 NULL, NULL, /* filter, filterarg */
2156 MJUM9BYTES, /* maxsize */
2158 MJUM9BYTES, /* maxsegsize */
2160 NULL, NULL, /* lockfunc, lockarg */
2161 &sc_if->sk_cdata.sk_jumbo_rx_tag);
2163 device_printf(sc_if->sk_if_dev,
2164 "failed to allocate jumbo Rx DMA tag\n");
2168 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2169 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2170 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2171 BUS_DMA_COHERENT | BUS_DMA_ZERO,
2172 &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2174 device_printf(sc_if->sk_if_dev,
2175 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2180 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2181 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2182 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2183 &ctx, BUS_DMA_NOWAIT);
2185 device_printf(sc_if->sk_if_dev,
2186 "failed to load DMA'able memory for jumbo Rx ring\n");
2189 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2191 /* create DMA maps for jumbo Rx buffers */
2192 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2193 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2194 device_printf(sc_if->sk_if_dev,
2195 "failed to create spare jumbo Rx dmamap\n");
2198 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2199 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2201 jrxd->rx_dmamap = NULL;
2202 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2205 device_printf(sc_if->sk_if_dev,
2206 "failed to create jumbo Rx dmamap\n");
2214 sk_dma_jumbo_free(sc_if);
2215 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2216 "resource shortage\n");
2217 sc_if->sk_jumbo_disable = 1;
2223 struct sk_if_softc *sc_if;
2225 struct sk_txdesc *txd;
2226 struct sk_rxdesc *rxd;
2230 if (sc_if->sk_cdata.sk_tx_ring_tag) {
2231 if (sc_if->sk_cdata.sk_tx_ring_map)
2232 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2233 sc_if->sk_cdata.sk_tx_ring_map);
2234 if (sc_if->sk_cdata.sk_tx_ring_map &&
2235 sc_if->sk_rdata.sk_tx_ring)
2236 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2237 sc_if->sk_rdata.sk_tx_ring,
2238 sc_if->sk_cdata.sk_tx_ring_map);
2239 sc_if->sk_rdata.sk_tx_ring = NULL;
2240 sc_if->sk_cdata.sk_tx_ring_map = NULL;
2241 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2242 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2245 if (sc_if->sk_cdata.sk_rx_ring_tag) {
2246 if (sc_if->sk_cdata.sk_rx_ring_map)
2247 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2248 sc_if->sk_cdata.sk_rx_ring_map);
2249 if (sc_if->sk_cdata.sk_rx_ring_map &&
2250 sc_if->sk_rdata.sk_rx_ring)
2251 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2252 sc_if->sk_rdata.sk_rx_ring,
2253 sc_if->sk_cdata.sk_rx_ring_map);
2254 sc_if->sk_rdata.sk_rx_ring = NULL;
2255 sc_if->sk_cdata.sk_rx_ring_map = NULL;
2256 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2257 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2260 if (sc_if->sk_cdata.sk_tx_tag) {
2261 for (i = 0; i < SK_TX_RING_CNT; i++) {
2262 txd = &sc_if->sk_cdata.sk_txdesc[i];
2263 if (txd->tx_dmamap) {
2264 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2266 txd->tx_dmamap = NULL;
2269 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2270 sc_if->sk_cdata.sk_tx_tag = NULL;
2273 if (sc_if->sk_cdata.sk_rx_tag) {
2274 for (i = 0; i < SK_RX_RING_CNT; i++) {
2275 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2276 if (rxd->rx_dmamap) {
2277 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2279 rxd->rx_dmamap = NULL;
2282 if (sc_if->sk_cdata.sk_rx_sparemap) {
2283 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2284 sc_if->sk_cdata.sk_rx_sparemap);
2285 sc_if->sk_cdata.sk_rx_sparemap = NULL;
2287 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2288 sc_if->sk_cdata.sk_rx_tag = NULL;
2291 if (sc_if->sk_cdata.sk_parent_tag) {
2292 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2293 sc_if->sk_cdata.sk_parent_tag = NULL;
2298 sk_dma_jumbo_free(sc_if)
2299 struct sk_if_softc *sc_if;
2301 struct sk_rxdesc *jrxd;
2305 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2306 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map)
2307 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2308 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2309 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map &&
2310 sc_if->sk_rdata.sk_jumbo_rx_ring)
2311 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2312 sc_if->sk_rdata.sk_jumbo_rx_ring,
2313 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2314 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2315 sc_if->sk_cdata.sk_jumbo_rx_ring_map = NULL;
2316 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2317 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2320 /* jumbo Rx buffers */
2321 if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2322 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2323 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2324 if (jrxd->rx_dmamap) {
2326 sc_if->sk_cdata.sk_jumbo_rx_tag,
2328 jrxd->rx_dmamap = NULL;
2331 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2332 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2333 sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2334 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2336 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2337 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2342 sk_txcksum(ifp, m, f)
2345 struct sk_tx_desc *f;
2351 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2352 for(; m && m->m_len == 0; m = m->m_next)
2354 if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2355 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2356 /* checksum may be corrupted */
2359 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2360 if (m->m_len != ETHER_HDR_LEN) {
2361 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2363 /* checksum may be corrupted */
2366 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2369 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2370 /* checksum may be corrupted */
2373 ip = mtod(m, struct ip *);
2375 p = mtod(m, u_int8_t *);
2377 ip = (struct ip *)p;
2379 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2382 f->sk_csum_startval = 0;
2383 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2388 sk_encap(sc_if, m_head)
2389 struct sk_if_softc *sc_if;
2390 struct mbuf **m_head;
2392 struct sk_txdesc *txd;
2393 struct sk_tx_desc *f = NULL;
2395 bus_dma_segment_t txsegs[SK_MAXTXSEGS];
2396 u_int32_t cflags, frag, si, sk_ctl;
2399 SK_IF_LOCK_ASSERT(sc_if);
2401 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2404 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2405 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2406 if (error == EFBIG) {
2407 m = m_defrag(*m_head, M_NOWAIT);
2414 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2415 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2421 } else if (error != 0)
2428 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2429 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2434 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2435 cflags = SK_OPCODE_CSUM;
2437 cflags = SK_OPCODE_DEFAULT;
2438 si = frag = sc_if->sk_cdata.sk_tx_prod;
2439 for (i = 0; i < nseg; i++) {
2440 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2441 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2442 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2443 sk_ctl = txsegs[i].ds_len | cflags;
2445 if (cflags == SK_OPCODE_CSUM)
2446 sk_txcksum(sc_if->sk_ifp, m, f);
2447 sk_ctl |= SK_TXCTL_FIRSTFRAG;
2449 sk_ctl |= SK_TXCTL_OWN;
2450 f->sk_ctl = htole32(sk_ctl);
2451 sc_if->sk_cdata.sk_tx_cnt++;
2452 SK_INC(frag, SK_TX_RING_CNT);
2454 sc_if->sk_cdata.sk_tx_prod = frag;
2456 /* set EOF on the last desciptor */
2457 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2458 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2459 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2461 /* turn the first descriptor ownership to NIC */
2462 f = &sc_if->sk_rdata.sk_tx_ring[si];
2463 f->sk_ctl |= htole32(SK_TXCTL_OWN);
2465 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2466 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2469 /* sync descriptors */
2470 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2471 BUS_DMASYNC_PREWRITE);
2472 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2473 sc_if->sk_cdata.sk_tx_ring_map,
2474 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2483 struct sk_if_softc *sc_if;
2485 sc_if = ifp->if_softc;
2488 sk_start_locked(ifp);
2489 SK_IF_UNLOCK(sc_if);
2495 sk_start_locked(ifp)
2498 struct sk_softc *sc;
2499 struct sk_if_softc *sc_if;
2500 struct mbuf *m_head;
2503 sc_if = ifp->if_softc;
2504 sc = sc_if->sk_softc;
2506 SK_IF_LOCK_ASSERT(sc_if);
2508 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2509 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2510 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2515 * Pack the data into the transmit ring. If we
2516 * don't have room, set the OACTIVE flag and wait
2517 * for the NIC to drain the ring.
2519 if (sk_encap(sc_if, &m_head)) {
2522 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2523 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2529 * If there's a BPF listener, bounce a copy of this frame
2532 BPF_MTAP(ifp, m_head);
2537 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2539 /* Set a timeout in case the chip goes out to lunch. */
2540 sc_if->sk_watchdog_timer = 5;
2549 struct sk_if_softc *sc_if;
2553 sc_if = ifp->if_softc;
2555 SK_IF_LOCK_ASSERT(sc_if);
2557 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2561 * Reclaim first as there is a possibility of losing Tx completion
2565 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2566 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2568 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2569 sk_init_locked(sc_if);
2573 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2582 struct sk_softc *sc;
2584 sc = device_get_softc(dev);
2587 /* Turn off the 'driver is loaded' LED. */
2588 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2591 * Reset the GEnesis controller. Doing this should also
2592 * assert the resets on the attached XMAC(s).
2604 struct sk_softc *sc;
2605 struct sk_if_softc *sc_if0, *sc_if1;
2606 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2608 sc = device_get_softc(dev);
2612 sc_if0 = sc->sk_if[SK_PORT_A];
2613 sc_if1 = sc->sk_if[SK_PORT_B];
2615 ifp0 = sc_if0->sk_ifp;
2617 ifp1 = sc_if1->sk_ifp;
2622 sc->sk_suspended = 1;
2633 struct sk_softc *sc;
2634 struct sk_if_softc *sc_if0, *sc_if1;
2635 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2637 sc = device_get_softc(dev);
2641 sc_if0 = sc->sk_if[SK_PORT_A];
2642 sc_if1 = sc->sk_if[SK_PORT_B];
2644 ifp0 = sc_if0->sk_ifp;
2646 ifp1 = sc_if1->sk_ifp;
2647 if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2648 sk_init_locked(sc_if0);
2649 if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2650 sk_init_locked(sc_if1);
2651 sc->sk_suspended = 0;
2659 * According to the data sheet from SK-NET GENESIS the hardware can compute
2660 * two Rx checksums at the same time(Each checksum start position is
2661 * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2662 * does not work at least on my Yukon hardware. I tried every possible ways
2663 * to get correct checksum value but couldn't get correct one. So TCP/UDP
2664 * checksum offload was disabled at the moment and only IP checksum offload
2666 * As nomral IP header size is 20 bytes I can't expect it would give an
2667 * increase in throughput. However it seems it doesn't hurt performance in
2668 * my testing. If there is a more detailed information for checksum secret
2669 * of the hardware in question please contact yongari@FreeBSD.org to add
2670 * TCP/UDP checksum offload support.
2672 static __inline void
2673 sk_rxcksum(ifp, m, csum)
2678 struct ether_header *eh;
2680 int32_t hlen, len, pktlen;
2681 u_int16_t csum1, csum2, ipcsum;
2683 pktlen = m->m_pkthdr.len;
2684 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2686 eh = mtod(m, struct ether_header *);
2687 if (eh->ether_type != htons(ETHERTYPE_IP))
2689 ip = (struct ip *)(eh + 1);
2690 if (ip->ip_v != IPVERSION)
2692 hlen = ip->ip_hl << 2;
2693 pktlen -= sizeof(struct ether_header);
2694 if (hlen < sizeof(struct ip))
2696 if (ntohs(ip->ip_len) < hlen)
2698 if (ntohs(ip->ip_len) != pktlen)
2701 csum1 = htons(csum & 0xffff);
2702 csum2 = htons((csum >> 16) & 0xffff);
2703 ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2704 /* checksum fixup for IP options */
2705 len = hlen - sizeof(struct ip);
2708 * If the second checksum value is correct we can compute IP
2709 * checksum with simple math. Unfortunately the second checksum
2710 * value is wrong so we can't verify the checksum from the
2711 * value(It seems there is some magic here to get correct
2712 * value). If the second checksum value is correct it also
2713 * means we can get TCP/UDP checksum) here. However, it still
2714 * needs pseudo header checksum calculation due to hardware
2719 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2720 if (ipcsum == 0xffff)
2721 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2725 sk_rxvalid(sc, stat, len)
2726 struct sk_softc *sc;
2727 u_int32_t stat, len;
2730 if (sc->sk_type == SK_GENESIS) {
2731 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2732 XM_RXSTAT_BYTES(stat) != len)
2735 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2736 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2737 YU_RXSTAT_JABBER)) != 0 ||
2738 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2739 YU_RXSTAT_BYTES(stat) != len)
2748 struct sk_if_softc *sc_if;
2750 struct sk_softc *sc;
2753 struct sk_rx_desc *cur_rx;
2754 struct sk_rxdesc *rxd;
2756 u_int32_t csum, rxstat, sk_ctl;
2758 sc = sc_if->sk_softc;
2759 ifp = sc_if->sk_ifp;
2761 SK_IF_LOCK_ASSERT(sc_if);
2763 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2764 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2767 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2768 prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2769 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2770 sk_ctl = le32toh(cur_rx->sk_ctl);
2771 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2773 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2774 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2776 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2777 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2778 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2779 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2780 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2781 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2783 sk_discard_rxbuf(sc_if, cons);
2788 csum = le32toh(cur_rx->sk_csum);
2789 if (sk_newbuf(sc_if, cons) != 0) {
2791 /* reuse old buffer */
2792 sk_discard_rxbuf(sc_if, cons);
2795 m->m_pkthdr.rcvif = ifp;
2796 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2798 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2799 sk_rxcksum(ifp, m, csum);
2800 SK_IF_UNLOCK(sc_if);
2801 (*ifp->if_input)(ifp, m);
2806 sc_if->sk_cdata.sk_rx_cons = cons;
2807 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2808 sc_if->sk_cdata.sk_rx_ring_map,
2809 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2814 sk_jumbo_rxeof(sc_if)
2815 struct sk_if_softc *sc_if;
2817 struct sk_softc *sc;
2820 struct sk_rx_desc *cur_rx;
2821 struct sk_rxdesc *jrxd;
2823 u_int32_t csum, rxstat, sk_ctl;
2825 sc = sc_if->sk_softc;
2826 ifp = sc_if->sk_ifp;
2828 SK_IF_LOCK_ASSERT(sc_if);
2830 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2831 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2834 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2835 prog < SK_JUMBO_RX_RING_CNT;
2836 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2837 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2838 sk_ctl = le32toh(cur_rx->sk_ctl);
2839 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2841 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2842 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2844 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2845 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2846 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2847 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2848 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2849 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2851 sk_discard_jumbo_rxbuf(sc_if, cons);
2856 csum = le32toh(cur_rx->sk_csum);
2857 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2859 /* reuse old buffer */
2860 sk_discard_jumbo_rxbuf(sc_if, cons);
2863 m->m_pkthdr.rcvif = ifp;
2864 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2866 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2867 sk_rxcksum(ifp, m, csum);
2868 SK_IF_UNLOCK(sc_if);
2869 (*ifp->if_input)(ifp, m);
2874 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2875 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2876 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2883 struct sk_if_softc *sc_if;
2885 struct sk_softc *sc;
2886 struct sk_txdesc *txd;
2887 struct sk_tx_desc *cur_tx;
2889 u_int32_t idx, sk_ctl;
2891 sc = sc_if->sk_softc;
2892 ifp = sc_if->sk_ifp;
2894 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2897 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2898 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2900 * Go through our tx ring and free mbufs for those
2901 * frames that have been sent.
2903 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2904 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2906 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2907 sk_ctl = le32toh(cur_tx->sk_ctl);
2908 if (sk_ctl & SK_TXCTL_OWN)
2910 sc_if->sk_cdata.sk_tx_cnt--;
2911 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2912 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2914 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2915 BUS_DMASYNC_POSTWRITE);
2916 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2921 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2922 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2923 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2925 sc_if->sk_cdata.sk_tx_cons = idx;
2926 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2928 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2929 sc_if->sk_cdata.sk_tx_ring_map,
2930 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2937 struct sk_if_softc *sc_if;
2938 struct mii_data *mii;
2943 ifp = sc_if->sk_ifp;
2944 mii = device_get_softc(sc_if->sk_miibus);
2946 if (!(ifp->if_flags & IFF_UP))
2949 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2950 sk_intr_bcom(sc_if);
2955 * According to SysKonnect, the correct way to verify that
2956 * the link has come back up is to poll bit 0 of the GPIO
2957 * register three times. This pin has the signal from the
2958 * link_sync pin connected to it; if we read the same link
2959 * state 3 times in a row, we know the link is up.
2961 for (i = 0; i < 3; i++) {
2962 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2967 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2971 /* Turn the GP0 interrupt back on. */
2972 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2973 SK_XM_READ_2(sc_if, XM_ISR);
2975 callout_stop(&sc_if->sk_tick_ch);
2979 sk_yukon_tick(xsc_if)
2982 struct sk_if_softc *sc_if;
2983 struct mii_data *mii;
2986 mii = device_get_softc(sc_if->sk_miibus);
2989 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2994 struct sk_if_softc *sc_if;
2996 struct mii_data *mii;
2999 mii = device_get_softc(sc_if->sk_miibus);
3000 ifp = sc_if->sk_ifp;
3002 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3005 * Read the PHY interrupt register to make sure
3006 * we clear any pending interrupts.
3008 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
3010 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3011 sk_init_xmac(sc_if);
3015 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
3017 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
3020 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
3022 /* Turn off the link LED. */
3023 SK_IF_WRITE_1(sc_if, 0,
3024 SK_LINKLED1_CTL, SK_LINKLED_OFF);
3026 } else if (status & BRGPHY_ISR_LNK_CHG) {
3027 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3028 BRGPHY_MII_IMR, 0xFF00);
3031 /* Turn on the link LED. */
3032 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3033 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
3034 SK_LINKLED_BLINK_OFF);
3037 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3041 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3048 struct sk_if_softc *sc_if;
3050 struct sk_softc *sc;
3053 sc = sc_if->sk_softc;
3054 status = SK_XM_READ_2(sc_if, XM_ISR);
3057 * Link has gone down. Start MII tick timeout to
3058 * watch for link resync.
3060 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3061 if (status & XM_ISR_GP0_SET) {
3062 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3063 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3066 if (status & XM_ISR_AUTONEG_DONE) {
3067 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3071 if (status & XM_IMR_TX_UNDERRUN)
3072 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3074 if (status & XM_IMR_RX_OVERRUN)
3075 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3077 status = SK_XM_READ_2(sc_if, XM_ISR);
3083 sk_intr_yukon(sc_if)
3084 struct sk_if_softc *sc_if;
3088 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3090 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3091 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3092 SK_RFCTL_RX_FIFO_OVER);
3095 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3096 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3097 SK_TFCTL_TX_FIFO_UNDER);
3105 struct sk_softc *sc = xsc;
3106 struct sk_if_softc *sc_if0, *sc_if1;
3107 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
3112 status = CSR_READ_4(sc, SK_ISSR);
3113 if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3116 sc_if0 = sc->sk_if[SK_PORT_A];
3117 sc_if1 = sc->sk_if[SK_PORT_B];
3120 ifp0 = sc_if0->sk_ifp;
3122 ifp1 = sc_if1->sk_ifp;
3124 for (; (status &= sc->sk_intrmask) != 0;) {
3125 /* Handle receive interrupts first. */
3126 if (status & SK_ISR_RX1_EOF) {
3127 if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3128 sk_jumbo_rxeof(sc_if0);
3131 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3132 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3134 if (status & SK_ISR_RX2_EOF) {
3135 if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3136 sk_jumbo_rxeof(sc_if1);
3139 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3140 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3143 /* Then transmit interrupts. */
3144 if (status & SK_ISR_TX1_S_EOF) {
3146 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3148 if (status & SK_ISR_TX2_S_EOF) {
3150 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3153 /* Then MAC interrupts. */
3154 if (status & SK_ISR_MAC1 &&
3155 ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3156 if (sc->sk_type == SK_GENESIS)
3157 sk_intr_xmac(sc_if0);
3159 sk_intr_yukon(sc_if0);
3162 if (status & SK_ISR_MAC2 &&
3163 ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3164 if (sc->sk_type == SK_GENESIS)
3165 sk_intr_xmac(sc_if1);
3167 sk_intr_yukon(sc_if1);
3170 if (status & SK_ISR_EXTERNAL_REG) {
3172 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3173 sk_intr_bcom(sc_if0);
3175 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3176 sk_intr_bcom(sc_if1);
3178 status = CSR_READ_4(sc, SK_ISSR);
3181 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3183 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3184 sk_start_locked(ifp0);
3185 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3186 sk_start_locked(ifp1);
3194 struct sk_if_softc *sc_if;
3196 struct sk_softc *sc;
3198 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2];
3199 static const struct sk_bcom_hack bhack[] = {
3200 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3201 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3202 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3205 SK_IF_LOCK_ASSERT(sc_if);
3207 sc = sc_if->sk_softc;
3208 ifp = sc_if->sk_ifp;
3210 /* Unreset the XMAC. */
3211 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3214 /* Reset the XMAC's internal state. */
3215 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3217 /* Save the XMAC II revision */
3218 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3221 * Perform additional initialization for external PHYs,
3222 * namely for the 1000baseTX cards that use the XMAC's
3225 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3229 /* Take PHY out of reset. */
3230 val = sk_win_read_4(sc, SK_GPIO);
3231 if (sc_if->sk_port == SK_PORT_A)
3232 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3234 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3235 sk_win_write_4(sc, SK_GPIO, val);
3237 /* Enable GMII mode on the XMAC. */
3238 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3240 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3241 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3243 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3244 BRGPHY_MII_IMR, 0xFFF0);
3247 * Early versions of the BCM5400 apparently have
3248 * a bug that requires them to have their reserved
3249 * registers initialized to some magic values. I don't
3250 * know what the numbers do, I'm just the messenger.
3252 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3254 while(bhack[i].reg) {
3255 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3256 bhack[i].reg, bhack[i].val);
3262 /* Set station address */
3263 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3264 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3265 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3266 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3267 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3269 if (ifp->if_flags & IFF_BROADCAST) {
3270 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3272 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3275 /* We don't need the FCS appended to the packet. */
3276 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3278 /* We want short frames padded to 60 bytes. */
3279 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3282 * Enable the reception of all error frames. This is is
3283 * a necessary evil due to the design of the XMAC. The
3284 * XMAC's receive FIFO is only 8K in size, however jumbo
3285 * frames can be up to 9000 bytes in length. When bad
3286 * frame filtering is enabled, the XMAC's RX FIFO operates
3287 * in 'store and forward' mode. For this to work, the
3288 * entire frame has to fit into the FIFO, but that means
3289 * that jumbo frames larger than 8192 bytes will be
3290 * truncated. Disabling all bad frame filtering causes
3291 * the RX FIFO to operate in streaming mode, in which
3292 * case the XMAC will start transfering frames out of the
3293 * RX FIFO as soon as the FIFO threshold is reached.
3295 if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3296 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3297 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3298 XM_MODE_RX_INRANGELEN);
3299 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3301 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3304 * Bump up the transmit threshold. This helps hold off transmit
3305 * underruns when we're blasting traffic from both ports at once.
3307 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3310 sk_rxfilter_genesis(sc_if);
3312 /* Clear and enable interrupts */
3313 SK_XM_READ_2(sc_if, XM_ISR);
3314 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3315 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3317 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3319 /* Configure MAC arbiter */
3320 switch(sc_if->sk_xmac_rev) {
3321 case XM_XMAC_REV_B2:
3322 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3323 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3324 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3325 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3326 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3327 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3328 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3329 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3330 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3332 case XM_XMAC_REV_C1:
3333 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3334 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3335 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3336 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3337 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3338 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3339 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3340 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3341 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3346 sk_win_write_2(sc, SK_MACARB_CTL,
3347 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3355 sk_init_yukon(sc_if)
3356 struct sk_if_softc *sc_if;
3360 struct sk_softc *sc;
3365 SK_IF_LOCK_ASSERT(sc_if);
3367 sc = sc_if->sk_softc;
3368 ifp = sc_if->sk_ifp;
3370 if (sc->sk_type == SK_YUKON_LITE &&
3371 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3373 * Workaround code for COMA mode, set PHY reset.
3374 * Otherwise it will not correctly take chip out of
3377 v = sk_win_read_4(sc, SK_GPIO);
3378 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3379 sk_win_write_4(sc, SK_GPIO, v);
3382 /* GMAC and GPHY Reset */
3383 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3384 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3387 if (sc->sk_type == SK_YUKON_LITE &&
3388 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3390 * Workaround code for COMA mode, clear PHY reset
3392 v = sk_win_read_4(sc, SK_GPIO);
3395 sk_win_write_4(sc, SK_GPIO, v);
3398 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3399 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3401 if (sc->sk_coppertype)
3402 phy |= SK_GPHY_COPPER;
3404 phy |= SK_GPHY_FIBER;
3406 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3408 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3409 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3410 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3412 /* unused read of the interrupt source register */
3413 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3415 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3417 /* MIB Counter Clear Mode set */
3418 reg |= YU_PAR_MIB_CLR;
3419 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3421 /* MIB Counter Clear Mode clear */
3422 reg &= ~YU_PAR_MIB_CLR;
3423 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3425 /* receive control reg */
3426 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3428 /* transmit parameter register */
3429 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3430 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3432 /* serial mode register */
3433 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3434 if (ifp->if_mtu > SK_MAX_FRAMELEN)
3435 reg |= YU_SMR_MFL_JUMBO;
3436 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3438 /* Setup Yukon's station address */
3439 eaddr = IF_LLADDR(sc_if->sk_ifp);
3440 for (i = 0; i < 3; i++)
3441 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3442 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3443 /* Set GMAC source address of flow control. */
3444 for (i = 0; i < 3; i++)
3445 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3446 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3447 /* Set GMAC virtual address. */
3448 for (i = 0; i < 3; i++)
3449 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3450 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3453 sk_rxfilter_yukon(sc_if);
3455 /* enable interrupt mask for counter overflows */
3456 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3457 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3458 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3460 /* Configure RX MAC FIFO Flush Mask */
3461 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3462 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3464 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3466 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3467 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3468 v = SK_TFCTL_OPERATION_ON;
3470 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3471 /* Configure RX MAC FIFO */
3472 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3473 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3475 /* Increase flush threshould to 64 bytes */
3476 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3477 SK_RFCTL_FIFO_THRESHOLD + 1);
3479 /* Configure TX MAC FIFO */
3480 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3481 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3485 * Note that to properly initialize any part of the GEnesis chip,
3486 * you first have to take it out of reset mode.
3492 struct sk_if_softc *sc_if = xsc;
3495 sk_init_locked(sc_if);
3496 SK_IF_UNLOCK(sc_if);
3502 sk_init_locked(sc_if)
3503 struct sk_if_softc *sc_if;
3505 struct sk_softc *sc;
3507 struct mii_data *mii;
3512 SK_IF_LOCK_ASSERT(sc_if);
3514 ifp = sc_if->sk_ifp;
3515 sc = sc_if->sk_softc;
3516 mii = device_get_softc(sc_if->sk_miibus);
3518 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3521 /* Cancel pending I/O and free all RX/TX buffers. */
3524 if (sc->sk_type == SK_GENESIS) {
3525 /* Configure LINK_SYNC LED */
3526 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3527 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3528 SK_LINKLED_LINKSYNC_ON);
3530 /* Configure RX LED */
3531 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3532 SK_RXLEDCTL_COUNTER_START);
3534 /* Configure TX LED */
3535 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3536 SK_TXLEDCTL_COUNTER_START);
3540 * Configure descriptor poll timer
3542 * SK-NET GENESIS data sheet says that possibility of losing Start
3543 * transmit command due to CPU/cache related interim storage problems
3544 * under certain conditions. The document recommends a polling
3545 * mechanism to send a Start transmit command to initiate transfer
3546 * of ready descriptors regulary. To cope with this issue sk(4) now
3547 * enables descriptor poll timer to initiate descriptor processing
3548 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3549 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3550 * command instead of waiting for next descriptor polling time.
3551 * The same rule may apply to Rx side too but it seems that is not
3552 * needed at the moment.
3553 * Since sk(4) uses descriptor polling as a last resort there is no
3554 * need to set smaller polling time than maximum allowable one.
3556 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3558 /* Configure I2C registers */
3560 /* Configure XMAC(s) */
3561 switch (sc->sk_type) {
3563 sk_init_xmac(sc_if);
3568 sk_init_yukon(sc_if);
3573 if (sc->sk_type == SK_GENESIS) {
3574 /* Configure MAC FIFOs */
3575 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3576 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3577 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3579 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3580 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3581 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3584 /* Configure transmit arbiter(s) */
3585 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3586 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3588 /* Configure RAMbuffers */
3589 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3590 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3591 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3592 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3593 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3594 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3596 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3597 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3598 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3599 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3600 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3601 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3602 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3604 /* Configure BMUs */
3605 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3606 if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3607 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3608 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3609 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3610 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3612 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3613 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3614 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3615 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3618 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3619 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3620 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3621 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3622 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3624 /* Init descriptors */
3625 if (ifp->if_mtu > SK_MAX_FRAMELEN)
3626 error = sk_init_jumbo_rx_ring(sc_if);
3628 error = sk_init_rx_ring(sc_if);
3630 device_printf(sc_if->sk_if_dev,
3631 "initialization failed: no memory for rx buffers\n");
3635 sk_init_tx_ring(sc_if);
3637 /* Set interrupt moderation if changed via sysctl. */
3638 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3639 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3640 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3643 device_printf(sc_if->sk_if_dev,
3644 "interrupt moderation is %d us.\n",
3648 /* Configure interrupt handling */
3649 CSR_READ_4(sc, SK_ISSR);
3650 if (sc_if->sk_port == SK_PORT_A)
3651 sc->sk_intrmask |= SK_INTRS1;
3653 sc->sk_intrmask |= SK_INTRS2;
3655 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3657 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3660 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3662 switch(sc->sk_type) {
3664 /* Enable XMACs TX and RX state machines */
3665 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3666 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3671 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3672 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3674 /* XXX disable 100Mbps and full duplex mode? */
3675 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3677 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3680 /* Activate descriptor polling timer */
3681 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3682 /* start transfer of Tx descriptors */
3683 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3685 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3686 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3688 switch (sc->sk_type) {
3692 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3696 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3703 struct sk_if_softc *sc_if;
3706 struct sk_softc *sc;
3707 struct sk_txdesc *txd;
3708 struct sk_rxdesc *rxd;
3709 struct sk_rxdesc *jrxd;
3713 SK_IF_LOCK_ASSERT(sc_if);
3714 sc = sc_if->sk_softc;
3715 ifp = sc_if->sk_ifp;
3717 callout_stop(&sc_if->sk_tick_ch);
3718 callout_stop(&sc_if->sk_watchdog_ch);
3720 /* stop Tx descriptor polling timer */
3721 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3722 /* stop transfer of Tx descriptors */
3723 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3724 for (i = 0; i < SK_TIMEOUT; i++) {
3725 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3726 if ((val & SK_TXBMU_TX_STOP) == 0)
3730 if (i == SK_TIMEOUT)
3731 device_printf(sc_if->sk_if_dev,
3732 "can not stop transfer of Tx descriptor\n");
3733 /* stop transfer of Rx descriptors */
3734 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3735 for (i = 0; i < SK_TIMEOUT; i++) {
3736 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3737 if ((val & SK_RXBMU_RX_STOP) == 0)
3741 if (i == SK_TIMEOUT)
3742 device_printf(sc_if->sk_if_dev,
3743 "can not stop transfer of Rx descriptor\n");
3745 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3746 /* Put PHY back into reset. */
3747 val = sk_win_read_4(sc, SK_GPIO);
3748 if (sc_if->sk_port == SK_PORT_A) {
3749 val |= SK_GPIO_DIR0;
3750 val &= ~SK_GPIO_DAT0;
3752 val |= SK_GPIO_DIR2;
3753 val &= ~SK_GPIO_DAT2;
3755 sk_win_write_4(sc, SK_GPIO, val);
3758 /* Turn off various components of this interface. */
3759 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3760 switch (sc->sk_type) {
3762 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3763 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3768 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3769 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3772 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3773 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3774 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3775 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3776 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3777 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3778 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3779 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3780 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3782 /* Disable interrupts */
3783 if (sc_if->sk_port == SK_PORT_A)
3784 sc->sk_intrmask &= ~SK_INTRS1;
3786 sc->sk_intrmask &= ~SK_INTRS2;
3787 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3789 SK_XM_READ_2(sc_if, XM_ISR);
3790 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3792 /* Free RX and TX mbufs still in the queues. */
3793 for (i = 0; i < SK_RX_RING_CNT; i++) {
3794 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3795 if (rxd->rx_m != NULL) {
3796 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3797 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3798 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3804 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3805 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3806 if (jrxd->rx_m != NULL) {
3807 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3808 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3809 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3811 m_freem(jrxd->rx_m);
3815 for (i = 0; i < SK_TX_RING_CNT; i++) {
3816 txd = &sc_if->sk_cdata.sk_txdesc[i];
3817 if (txd->tx_m != NULL) {
3818 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3819 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3820 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3827 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
3833 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3839 value = *(int *)arg1;
3840 error = sysctl_handle_int(oidp, &value, 0, req);
3841 if (error || !req->newptr)
3843 if (value < low || value > high)
3845 *(int *)arg1 = value;
3850 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3852 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));