1 /* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */
4 * Copyright (c) 1997, 1998, 1999, 2000
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
40 * Permission to use, copy, modify, and distribute this software for any
41 * purpose with or without fee is hereby granted, provided that the above
42 * copyright notice and this permission notice appear in all copies.
44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
53 /* Values to keep the different chip revisions apart (SK_CHIPVER). */
54 #define SK_GENESIS 0x0A
56 #define SK_YUKON_LITE 0xB1
57 #define SK_YUKON_LP 0xB2
58 #define SK_YUKON_FAMILY(x) ((x) & 0xB0)
60 /* Known revisions in SK_CONFIG. */
61 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */
62 #define SK_YUKON_LITE_REV_A1 0x3
63 #define SK_YUKON_LITE_REV_A3 0x7
66 * SysKonnect PCI vendor ID
68 #define VENDORID_SK 0x1148
71 * Marvell PCI vendor ID
73 #define VENDORID_MARVELL 0x11AB
76 * SK-NET gigabit ethernet device IDs
78 #define DEVICEID_SK_V1 0x4300
79 #define DEVICEID_SK_V2 0x4320
84 #define DEVICEID_BELKIN_5005 0x5005
89 #define VENDORID_3COM 0x10b7
92 * 3Com gigabit ethernet device ID
94 #define DEVICEID_3COM_3C940 0x1700
97 * Linksys PCI vendor ID
99 #define VENDORID_LINKSYS 0x1737
102 * Linksys gigabit ethernet device ID
104 #define DEVICEID_LINKSYS_EG1032 0x1032
107 * Linksys gigabit ethernet rev 2 sub-device ID
109 #define SUBDEVICEID_LINKSYS_EG1032_REV2 0x0015
112 * D-Link PCI vendor ID
114 #define VENDORID_DLINK 0x1186
117 * D-Link gigabit ethernet device ID
119 #define DEVICEID_DLINK_DGE530T_A1 0x4c00
120 #define DEVICEID_DLINK_DGE530T_B1 0x4b01
123 * GEnesis registers. The GEnesis chip has a 256-byte I/O window
124 * but internally it has a 16K register space. This 16K space is
125 * divided into 128-byte blocks. The first 128 bytes of the I/O
126 * window represent the first block, which is permanently mapped
127 * at the start of the window. The other 127 blocks can be mapped
128 * to the second 128 bytes of the I/O window by setting the desired
129 * block value in the RAP register in block 0. Not all of the 127
130 * blocks are actually used. Most registers are 32 bits wide, but
131 * there are a few 16-bit and 8-bit ones as well.
135 /* Start of remappable register window. */
136 #define SK_WIN_BASE 0x0080
138 /* Size of a window */
139 #define SK_WIN_LEN 0x80
141 #define SK_WIN_MASK 0x3F80
142 #define SK_REG_MASK 0x7F
144 /* Compute the window of a given register (for the RAP register) */
145 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN)
147 /* Compute the relative offset of a register within the window */
148 #define SK_REG(reg) ((reg) & SK_REG_MASK)
154 * Compute offset of port-specific register. Since there are two
155 * ports, there are two of some GEnesis modules (e.g. two sets of
156 * DMA queues, two sets of FIFO control registers, etc...). Normally,
157 * the block for port 0 is at offset 0x0 and the block for port 1 is
158 * at offset 0x80 (i.e. the next page over). However for the transmit
159 * BMUs and RAMbuffers, there are two blocks for each port: one for
160 * the sync transmit queue and one for the async queue (which we don't
161 * use). However instead of ordering them like this:
162 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2
163 * SysKonnect has instead ordered them like this:
164 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2
165 * This means that when referencing the TX BMU and RAMbuffer registers,
166 * we have to double the block offset (0x80 * 2) in order to reach the
167 * second queue. This prevents us from using the same formula
168 * (sk_port * 0x80) to compute the offsets for all of the port-specific
169 * blocks: we need an extra offset for the BMU and RAMbuffer registers.
170 * The simplest thing is to provide an extra argument to these macros:
171 * the 'skip' parameter. The 'skip' value is the number of extra pages
172 * for skip when computing the port0/port1 offsets. For most registers,
173 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1.
175 #define SK_IF_READ_4(sc_if, skip, reg) \
176 sk_win_read_4(sc_if->sk_softc, reg + \
177 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
178 #define SK_IF_READ_2(sc_if, skip, reg) \
179 sk_win_read_2(sc_if->sk_softc, reg + \
180 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
181 #define SK_IF_READ_1(sc_if, skip, reg) \
182 sk_win_read_1(sc_if->sk_softc, reg + \
183 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
185 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \
186 sk_win_write_4(sc_if->sk_softc, \
187 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
188 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \
189 sk_win_write_2(sc_if->sk_softc, \
190 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
191 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \
192 sk_win_write_1(sc_if->sk_softc, \
193 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
195 /* Block 0 registers, permanently mapped at iobase. */
196 #define SK_RAP 0x0000
197 #define SK_CSR 0x0004
198 #define SK_LED 0x0006
199 #define SK_ISR 0x0008 /* interrupt source */
200 #define SK_IMR 0x000C /* interrupt mask */
201 #define SK_IESR 0x0010 /* interrupt hardware error source */
202 #define SK_IEMR 0x0014 /* interrupt hardware error mask */
203 #define SK_ISSR 0x0018 /* special interrupt source */
204 #define SK_XM_IMR0 0x0020
205 #define SK_XM_ISR0 0x0028
206 #define SK_XM_PHYADDR0 0x0030
207 #define SK_XM_PHYDATA0 0x0034
208 #define SK_XM_IMR1 0x0040
209 #define SK_XM_ISR1 0x0048
210 #define SK_XM_PHYADDR1 0x0050
211 #define SK_XM_PHYDATA1 0x0054
212 #define SK_BMU_RX_CSR0 0x0060
213 #define SK_BMU_RX_CSR1 0x0064
214 #define SK_BMU_TXS_CSR0 0x0068
215 #define SK_BMU_TXA_CSR0 0x006C
216 #define SK_BMU_TXS_CSR1 0x0070
217 #define SK_BMU_TXA_CSR1 0x0074
219 /* SK_CSR register */
220 #define SK_CSR_SW_RESET 0x0001
221 #define SK_CSR_SW_UNRESET 0x0002
222 #define SK_CSR_MASTER_RESET 0x0004
223 #define SK_CSR_MASTER_UNRESET 0x0008
224 #define SK_CSR_MASTER_STOP 0x0010
225 #define SK_CSR_MASTER_DONE 0x0020
226 #define SK_CSR_SW_IRQ_CLEAR 0x0040
227 #define SK_CSR_SW_IRQ_SET 0x0080
228 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */
229 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */
231 /* SK_LED register */
232 #define SK_LED_GREEN_OFF 0x01
233 #define SK_LED_GREEN_ON 0x02
235 /* SK_ISR register */
236 #define SK_ISR_TX2_AS_CHECK 0x00000001
237 #define SK_ISR_TX2_AS_EOF 0x00000002
238 #define SK_ISR_TX2_AS_EOB 0x00000004
239 #define SK_ISR_TX2_S_CHECK 0x00000008
240 #define SK_ISR_TX2_S_EOF 0x00000010
241 #define SK_ISR_TX2_S_EOB 0x00000020
242 #define SK_ISR_TX1_AS_CHECK 0x00000040
243 #define SK_ISR_TX1_AS_EOF 0x00000080
244 #define SK_ISR_TX1_AS_EOB 0x00000100
245 #define SK_ISR_TX1_S_CHECK 0x00000200
246 #define SK_ISR_TX1_S_EOF 0x00000400
247 #define SK_ISR_TX1_S_EOB 0x00000800
248 #define SK_ISR_RX2_CHECK 0x00001000
249 #define SK_ISR_RX2_EOF 0x00002000
250 #define SK_ISR_RX2_EOB 0x00004000
251 #define SK_ISR_RX1_CHECK 0x00008000
252 #define SK_ISR_RX1_EOF 0x00010000
253 #define SK_ISR_RX1_EOB 0x00020000
254 #define SK_ISR_LINK2_OFLOW 0x00040000
255 #define SK_ISR_MAC2 0x00080000
256 #define SK_ISR_LINK1_OFLOW 0x00100000
257 #define SK_ISR_MAC1 0x00200000
258 #define SK_ISR_TIMER 0x00400000
259 #define SK_ISR_EXTERNAL_REG 0x00800000
260 #define SK_ISR_SW 0x01000000
261 #define SK_ISR_I2C_RDY 0x02000000
262 #define SK_ISR_TX2_TIMEO 0x04000000
263 #define SK_ISR_TX1_TIMEO 0x08000000
264 #define SK_ISR_RX2_TIMEO 0x10000000
265 #define SK_ISR_RX1_TIMEO 0x20000000
266 #define SK_ISR_RSVD 0x40000000
267 #define SK_ISR_HWERR 0x80000000
269 /* SK_IMR register */
270 #define SK_IMR_TX2_AS_CHECK 0x00000001
271 #define SK_IMR_TX2_AS_EOF 0x00000002
272 #define SK_IMR_TX2_AS_EOB 0x00000004
273 #define SK_IMR_TX2_S_CHECK 0x00000008
274 #define SK_IMR_TX2_S_EOF 0x00000010
275 #define SK_IMR_TX2_S_EOB 0x00000020
276 #define SK_IMR_TX1_AS_CHECK 0x00000040
277 #define SK_IMR_TX1_AS_EOF 0x00000080
278 #define SK_IMR_TX1_AS_EOB 0x00000100
279 #define SK_IMR_TX1_S_CHECK 0x00000200
280 #define SK_IMR_TX1_S_EOF 0x00000400
281 #define SK_IMR_TX1_S_EOB 0x00000800
282 #define SK_IMR_RX2_CHECK 0x00001000
283 #define SK_IMR_RX2_EOF 0x00002000
284 #define SK_IMR_RX2_EOB 0x00004000
285 #define SK_IMR_RX1_CHECK 0x00008000
286 #define SK_IMR_RX1_EOF 0x00010000
287 #define SK_IMR_RX1_EOB 0x00020000
288 #define SK_IMR_LINK2_OFLOW 0x00040000
289 #define SK_IMR_MAC2 0x00080000
290 #define SK_IMR_LINK1_OFLOW 0x00100000
291 #define SK_IMR_MAC1 0x00200000
292 #define SK_IMR_TIMER 0x00400000
293 #define SK_IMR_EXTERNAL_REG 0x00800000
294 #define SK_IMR_SW 0x01000000
295 #define SK_IMR_I2C_RDY 0x02000000
296 #define SK_IMR_TX2_TIMEO 0x04000000
297 #define SK_IMR_TX1_TIMEO 0x08000000
298 #define SK_IMR_RX2_TIMEO 0x10000000
299 #define SK_IMR_RX1_TIMEO 0x20000000
300 #define SK_IMR_RSVD 0x40000000
301 #define SK_IMR_HWERR 0x80000000
304 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1)
307 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2)
309 /* SK_IESR register */
310 #define SK_IESR_PAR_RX2 0x00000001
311 #define SK_IESR_PAR_RX1 0x00000002
312 #define SK_IESR_PAR_MAC2 0x00000004
313 #define SK_IESR_PAR_MAC1 0x00000008
314 #define SK_IESR_PAR_WR_RAM 0x00000010
315 #define SK_IESR_PAR_RD_RAM 0x00000020
316 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040
317 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080
318 #define SK_IESR_NO_STS_MAC2 0x00000100
319 #define SK_IESR_NO_STS_MAC1 0x00000200
320 #define SK_IESR_IRQ_STS 0x00000400
321 #define SK_IESR_MASTERERR 0x00000800
323 /* SK_IEMR register */
324 #define SK_IEMR_PAR_RX2 0x00000001
325 #define SK_IEMR_PAR_RX1 0x00000002
326 #define SK_IEMR_PAR_MAC2 0x00000004
327 #define SK_IEMR_PAR_MAC1 0x00000008
328 #define SK_IEMR_PAR_WR_RAM 0x00000010
329 #define SK_IEMR_PAR_RD_RAM 0x00000020
330 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040
331 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080
332 #define SK_IEMR_NO_STS_MAC2 0x00000100
333 #define SK_IEMR_NO_STS_MAC1 0x00000200
334 #define SK_IEMR_IRQ_STS 0x00000400
335 #define SK_IEMR_MASTERERR 0x00000800
338 #define SK_MAC0_0 0x0100
339 #define SK_MAC0_1 0x0104
340 #define SK_MAC1_0 0x0108
341 #define SK_MAC1_1 0x010C
342 #define SK_MAC2_0 0x0110
343 #define SK_MAC2_1 0x0114
344 #define SK_CONNTYPE 0x0118
345 #define SK_PMDTYPE 0x0119
346 #define SK_CONFIG 0x011A
347 #define SK_CHIPVER 0x011B
348 #define SK_EPROM0 0x011C
349 #define SK_EPROM1 0x011D /* yukon/genesis */
350 #define SK_EPROM2 0x011E /* yukon/genesis */
351 #define SK_EPROM3 0x011F
352 #define SK_EP_ADDR 0x0120
353 #define SK_EP_DATA 0x0124
354 #define SK_EP_LOADCTL 0x0128
355 #define SK_EP_LOADTST 0x0129
356 #define SK_TIMERINIT 0x0130
357 #define SK_TIMER 0x0134
358 #define SK_TIMERCTL 0x0138
359 #define SK_TIMERTST 0x0139
360 #define SK_IMTIMERINIT 0x0140
361 #define SK_IMTIMER 0x0144
362 #define SK_IMTIMERCTL 0x0148
363 #define SK_IMTIMERTST 0x0149
364 #define SK_IMMR 0x014C
365 #define SK_IHWEMR 0x0150
366 #define SK_TESTCTL1 0x0158
367 #define SK_TESTCTL2 0x0159
368 #define SK_GPIO 0x015C
369 #define SK_I2CHWCTL 0x0160
370 #define SK_I2CHWDATA 0x0164
371 #define SK_I2CHWIRQ 0x0168
372 #define SK_I2CSW 0x016C
373 #define SK_BLNKINIT 0x0170
374 #define SK_BLNKCOUNT 0x0174
375 #define SK_BLNKCTL 0x0178
376 #define SK_BLNKSTS 0x0179
377 #define SK_BLNKTST 0x017A
379 #define SK_IMCTL_STOP 0x02
380 #define SK_IMCTL_START 0x04
382 #define SK_IMTIMER_TICKS_GENESIS 53
383 #define SK_IMTIMER_TICKS_YUKON 78
384 #define SK_IM_USECS(x, t) ((x) * (t))
387 #define SK_IM_DEFAULT 100
388 #define SK_IM_MAX 10000
391 * The SK_EPROM0 register contains a byte that describes the
392 * amount of SRAM mounted on the NIC. The value also tells if
393 * the chips are 64K or 128K. This affects the RAMbuffer address
394 * offset that we need to use.
396 #define SK_RAMSIZE_512K_64 0x1
397 #define SK_RAMSIZE_1024K_128 0x2
398 #define SK_RAMSIZE_1024K_64 0x3
399 #define SK_RAMSIZE_2048K_128 0x4
401 #define SK_RBOFF_0 0x0
402 #define SK_RBOFF_80000 0x80000
405 * SK_EEPROM1 contains the PHY type, which may be XMAC for
406 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom
409 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */
410 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */
411 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */
412 #define SK_PHYTYPE_NAT 3 /* National DP83891 */
413 #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */
414 #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */
419 #define SK_PHYADDR_XMAC 0x0
420 #define SK_PHYADDR_BCOM 0x1
421 #define SK_PHYADDR_LONE 0x3
422 #define SK_PHYADDR_NAT 0x0
423 #define SK_PHYADDR_MARV 0x0
425 #define SK_CONFIG_SINGLEMAC 0x01
426 #define SK_CONFIG_DIS_DSL_CLK 0x02
428 #define SK_PMD_1000BASELX 0x4C
429 #define SK_PMD_1000BASESX 0x53
430 #define SK_PMD_1000BASECX 0x43
431 #define SK_PMD_1000BASETX 0x54
434 #define SK_GPIO_DAT0 0x00000001
435 #define SK_GPIO_DAT1 0x00000002
436 #define SK_GPIO_DAT2 0x00000004
437 #define SK_GPIO_DAT3 0x00000008
438 #define SK_GPIO_DAT4 0x00000010
439 #define SK_GPIO_DAT5 0x00000020
440 #define SK_GPIO_DAT6 0x00000040
441 #define SK_GPIO_DAT7 0x00000080
442 #define SK_GPIO_DAT8 0x00000100
443 #define SK_GPIO_DAT9 0x00000200
444 #define SK_GPIO_DIR0 0x00010000
445 #define SK_GPIO_DIR1 0x00020000
446 #define SK_GPIO_DIR2 0x00040000
447 #define SK_GPIO_DIR3 0x00080000
448 #define SK_GPIO_DIR4 0x00100000
449 #define SK_GPIO_DIR5 0x00200000
450 #define SK_GPIO_DIR6 0x00400000
451 #define SK_GPIO_DIR7 0x00800000
452 #define SK_GPIO_DIR8 0x01000000
453 #define SK_GPIO_DIR9 0x02000000
455 /* Block 3 Ram interface and MAC arbiter registers */
456 #define SK_RAMADDR 0x0180
457 #define SK_RAMDATA0 0x0184
458 #define SK_RAMDATA1 0x0188
459 #define SK_TO0 0x0190
460 #define SK_TO1 0x0191
461 #define SK_TO2 0x0192
462 #define SK_TO3 0x0193
463 #define SK_TO4 0x0194
464 #define SK_TO5 0x0195
465 #define SK_TO6 0x0196
466 #define SK_TO7 0x0197
467 #define SK_TO8 0x0198
468 #define SK_TO9 0x0199
469 #define SK_TO10 0x019A
470 #define SK_TO11 0x019B
471 #define SK_RITIMEO_TMR 0x019C
472 #define SK_RAMCTL 0x01A0
473 #define SK_RITIMER_TST 0x01A2
475 #define SK_RAMCTL_RESET 0x0001
476 #define SK_RAMCTL_UNRESET 0x0002
477 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100
478 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200
480 /* Mac arbiter registers */
481 #define SK_MINIT_RX1 0x01B0
482 #define SK_MINIT_RX2 0x01B1
483 #define SK_MINIT_TX1 0x01B2
484 #define SK_MINIT_TX2 0x01B3
485 #define SK_MTIMEO_RX1 0x01B4
486 #define SK_MTIMEO_RX2 0x01B5
487 #define SK_MTIMEO_TX1 0x01B6
488 #define SK_MTIEMO_TX2 0x01B7
489 #define SK_MACARB_CTL 0x01B8
490 #define SK_MTIMER_TST 0x01BA
491 #define SK_RCINIT_RX1 0x01C0
492 #define SK_RCINIT_RX2 0x01C1
493 #define SK_RCINIT_TX1 0x01C2
494 #define SK_RCINIT_TX2 0x01C3
495 #define SK_RCTIMEO_RX1 0x01C4
496 #define SK_RCTIMEO_RX2 0x01C5
497 #define SK_RCTIMEO_TX1 0x01C6
498 #define SK_RCTIMEO_TX2 0x01C7
499 #define SK_RECOVERY_CTL 0x01C8
500 #define SK_RCTIMER_TST 0x01CA
502 /* Packet arbiter registers */
503 #define SK_RXPA1_TINIT 0x01D0
504 #define SK_RXPA2_TINIT 0x01D4
505 #define SK_TXPA1_TINIT 0x01D8
506 #define SK_TXPA2_TINIT 0x01DC
507 #define SK_RXPA1_TIMEO 0x01E0
508 #define SK_RXPA2_TIMEO 0x01E4
509 #define SK_TXPA1_TIMEO 0x01E8
510 #define SK_TXPA2_TIMEO 0x01EC
511 #define SK_PKTARB_CTL 0x01F0
512 #define SK_PKTATB_TST 0x01F2
514 #define SK_PKTARB_TIMEOUT 0x2000
516 #define SK_PKTARBCTL_RESET 0x0001
517 #define SK_PKTARBCTL_UNRESET 0x0002
518 #define SK_PKTARBCTL_RXTO1_OFF 0x0004
519 #define SK_PKTARBCTL_RXTO1_ON 0x0008
520 #define SK_PKTARBCTL_RXTO2_OFF 0x0010
521 #define SK_PKTARBCTL_RXTO2_ON 0x0020
522 #define SK_PKTARBCTL_TXTO1_OFF 0x0040
523 #define SK_PKTARBCTL_TXTO1_ON 0x0080
524 #define SK_PKTARBCTL_TXTO2_OFF 0x0100
525 #define SK_PKTARBCTL_TXTO2_ON 0x0200
526 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400
527 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800
528 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000
529 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000
531 #define SK_MINIT_XMAC_B2 54
532 #define SK_MINIT_XMAC_C1 63
534 #define SK_MACARBCTL_RESET 0x0001
535 #define SK_MACARBCTL_UNRESET 0x0002
536 #define SK_MACARBCTL_FASTOE_OFF 0x0004
537 #define SK_MACARBCRL_FASTOE_ON 0x0008
539 #define SK_RCINIT_XMAC_B2 54
540 #define SK_RCINIT_XMAC_C1 0
542 #define SK_RECOVERYCTL_RX1_OFF 0x0001
543 #define SK_RECOVERYCTL_RX1_ON 0x0002
544 #define SK_RECOVERYCTL_RX2_OFF 0x0004
545 #define SK_RECOVERYCTL_RX2_ON 0x0008
546 #define SK_RECOVERYCTL_TX1_OFF 0x0010
547 #define SK_RECOVERYCTL_TX1_ON 0x0020
548 #define SK_RECOVERYCTL_TX2_OFF 0x0040
549 #define SK_RECOVERYCTL_TX2_ON 0x0080
551 #define SK_RECOVERY_XMAC_B2 \
552 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \
553 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON)
555 #define SK_RECOVERY_XMAC_C1 \
556 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \
557 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF)
559 /* Block 4 -- TX Arbiter MAC 1 */
560 #define SK_TXAR1_TIMERINIT 0x0200
561 #define SK_TXAR1_TIMERVAL 0x0204
562 #define SK_TXAR1_LIMITINIT 0x0208
563 #define SK_TXAR1_LIMITCNT 0x020C
564 #define SK_TXAR1_COUNTERCTL 0x0210
565 #define SK_TXAR1_COUNTERTST 0x0212
566 #define SK_TXAR1_COUNTERSTS 0x0212
568 /* Block 5 -- TX Arbiter MAC 2 */
569 #define SK_TXAR2_TIMERINIT 0x0280
570 #define SK_TXAR2_TIMERVAL 0x0284
571 #define SK_TXAR2_LIMITINIT 0x0288
572 #define SK_TXAR2_LIMITCNT 0x028C
573 #define SK_TXAR2_COUNTERCTL 0x0290
574 #define SK_TXAR2_COUNTERTST 0x0291
575 #define SK_TXAR2_COUNTERSTS 0x0292
577 #define SK_TXARCTL_OFF 0x01
578 #define SK_TXARCTL_ON 0x02
579 #define SK_TXARCTL_RATECTL_OFF 0x04
580 #define SK_TXARCTL_RATECTL_ON 0x08
581 #define SK_TXARCTL_ALLOC_OFF 0x10
582 #define SK_TXARCTL_ALLOC_ON 0x20
583 #define SK_TXARCTL_FSYNC_OFF 0x40
584 #define SK_TXARCTL_FSYNC_ON 0x80
586 /* Block 6 -- External registers */
587 #define SK_EXTREG_BASE 0x300
588 #define SK_EXTREG_END 0x37C
590 /* Block 7 -- PCI config registers */
591 #define SK_PCI_BASE 0x0380
592 #define SK_PCI_END 0x03FC
594 /* Compute offset of mirrored PCI register */
595 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE)
597 /* Block 8 -- RX queue 1 */
598 #define SK_RXQ1_BUFCNT 0x0400
599 #define SK_RXQ1_BUFCTL 0x0402
600 #define SK_RXQ1_NEXTDESC 0x0404
601 #define SK_RXQ1_RXBUF_LO 0x0408
602 #define SK_RXQ1_RXBUF_HI 0x040C
603 #define SK_RXQ1_RXSTAT 0x0410
604 #define SK_RXQ1_TIMESTAMP 0x0414
605 #define SK_RXQ1_CSUM1 0x0418
606 #define SK_RXQ1_CSUM2 0x041A
607 #define SK_RXQ1_CSUM1_START 0x041C
608 #define SK_RXQ1_CSUM2_START 0x041E
609 #define SK_RXQ1_CURADDR_LO 0x0420
610 #define SK_RXQ1_CURADDR_HI 0x0424
611 #define SK_RXQ1_CURCNT_LO 0x0428
612 #define SK_RXQ1_CURCNT_HI 0x042C
613 #define SK_RXQ1_CURBYTES 0x0430
614 #define SK_RXQ1_BMU_CSR 0x0434
615 #define SK_RXQ1_WATERMARK 0x0438
616 #define SK_RXQ1_FLAG 0x043A
617 #define SK_RXQ1_TEST1 0x043C
618 #define SK_RXQ1_TEST2 0x0440
619 #define SK_RXQ1_TEST3 0x0444
621 /* Block 9 -- RX queue 2 */
622 #define SK_RXQ2_BUFCNT 0x0480
623 #define SK_RXQ2_BUFCTL 0x0482
624 #define SK_RXQ2_NEXTDESC 0x0484
625 #define SK_RXQ2_RXBUF_LO 0x0488
626 #define SK_RXQ2_RXBUF_HI 0x048C
627 #define SK_RXQ2_RXSTAT 0x0490
628 #define SK_RXQ2_TIMESTAMP 0x0494
629 #define SK_RXQ2_CSUM1 0x0498
630 #define SK_RXQ2_CSUM2 0x049A
631 #define SK_RXQ2_CSUM1_START 0x049C
632 #define SK_RXQ2_CSUM2_START 0x049E
633 #define SK_RXQ2_CURADDR_LO 0x04A0
634 #define SK_RXQ2_CURADDR_HI 0x04A4
635 #define SK_RXQ2_CURCNT_LO 0x04A8
636 #define SK_RXQ2_CURCNT_HI 0x04AC
637 #define SK_RXQ2_CURBYTES 0x04B0
638 #define SK_RXQ2_BMU_CSR 0x04B4
639 #define SK_RXQ2_WATERMARK 0x04B8
640 #define SK_RXQ2_FLAG 0x04BA
641 #define SK_RXQ2_TEST1 0x04BC
642 #define SK_RXQ2_TEST2 0x04C0
643 #define SK_RXQ2_TEST3 0x04C4
645 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001
646 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002
647 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004
648 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008
649 #define SK_RXBMU_RX_START 0x00000010
650 #define SK_RXBMU_RX_STOP 0x00000020
651 #define SK_RXBMU_POLL_OFF 0x00000040
652 #define SK_RXBMU_POLL_ON 0x00000080
653 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100
654 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200
655 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400
656 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800
657 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000
658 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000
659 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000
660 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000
661 #define SK_RXBMU_PFI_SM_RESET 0x00010000
662 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000
663 #define SK_RXBMU_FIFO_RESET 0x00040000
664 #define SK_RXBMU_FIFO_UNRESET 0x00080000
665 #define SK_RXBMU_DESC_RESET 0x00100000
666 #define SK_RXBMU_DESC_UNRESET 0x00200000
667 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000
669 #define SK_RXBMU_ONLINE \
670 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \
671 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \
672 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \
673 SK_RXBMU_DESC_UNRESET)
675 #define SK_RXBMU_OFFLINE \
676 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \
677 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \
678 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \
681 /* Block 12 -- TX sync queue 1 */
682 #define SK_TXQS1_BUFCNT 0x0600
683 #define SK_TXQS1_BUFCTL 0x0602
684 #define SK_TXQS1_NEXTDESC 0x0604
685 #define SK_TXQS1_RXBUF_LO 0x0608
686 #define SK_TXQS1_RXBUF_HI 0x060C
687 #define SK_TXQS1_RXSTAT 0x0610
688 #define SK_TXQS1_CSUM_STARTVAL 0x0614
689 #define SK_TXQS1_CSUM_STARTPOS 0x0618
690 #define SK_TXQS1_CSUM_WRITEPOS 0x061A
691 #define SK_TXQS1_CURADDR_LO 0x0620
692 #define SK_TXQS1_CURADDR_HI 0x0624
693 #define SK_TXQS1_CURCNT_LO 0x0628
694 #define SK_TXQS1_CURCNT_HI 0x062C
695 #define SK_TXQS1_CURBYTES 0x0630
696 #define SK_TXQS1_BMU_CSR 0x0634
697 #define SK_TXQS1_WATERMARK 0x0638
698 #define SK_TXQS1_FLAG 0x063A
699 #define SK_TXQS1_TEST1 0x063C
700 #define SK_TXQS1_TEST2 0x0640
701 #define SK_TXQS1_TEST3 0x0644
703 /* Block 13 -- TX async queue 1 */
704 #define SK_TXQA1_BUFCNT 0x0680
705 #define SK_TXQA1_BUFCTL 0x0682
706 #define SK_TXQA1_NEXTDESC 0x0684
707 #define SK_TXQA1_RXBUF_LO 0x0688
708 #define SK_TXQA1_RXBUF_HI 0x068C
709 #define SK_TXQA1_RXSTAT 0x0690
710 #define SK_TXQA1_CSUM_STARTVAL 0x0694
711 #define SK_TXQA1_CSUM_STARTPOS 0x0698
712 #define SK_TXQA1_CSUM_WRITEPOS 0x069A
713 #define SK_TXQA1_CURADDR_LO 0x06A0
714 #define SK_TXQA1_CURADDR_HI 0x06A4
715 #define SK_TXQA1_CURCNT_LO 0x06A8
716 #define SK_TXQA1_CURCNT_HI 0x06AC
717 #define SK_TXQA1_CURBYTES 0x06B0
718 #define SK_TXQA1_BMU_CSR 0x06B4
719 #define SK_TXQA1_WATERMARK 0x06B8
720 #define SK_TXQA1_FLAG 0x06BA
721 #define SK_TXQA1_TEST1 0x06BC
722 #define SK_TXQA1_TEST2 0x06C0
723 #define SK_TXQA1_TEST3 0x06C4
725 /* Block 14 -- TX sync queue 2 */
726 #define SK_TXQS2_BUFCNT 0x0700
727 #define SK_TXQS2_BUFCTL 0x0702
728 #define SK_TXQS2_NEXTDESC 0x0704
729 #define SK_TXQS2_RXBUF_LO 0x0708
730 #define SK_TXQS2_RXBUF_HI 0x070C
731 #define SK_TXQS2_RXSTAT 0x0710
732 #define SK_TXQS2_CSUM_STARTVAL 0x0714
733 #define SK_TXQS2_CSUM_STARTPOS 0x0718
734 #define SK_TXQS2_CSUM_WRITEPOS 0x071A
735 #define SK_TXQS2_CURADDR_LO 0x0720
736 #define SK_TXQS2_CURADDR_HI 0x0724
737 #define SK_TXQS2_CURCNT_LO 0x0728
738 #define SK_TXQS2_CURCNT_HI 0x072C
739 #define SK_TXQS2_CURBYTES 0x0730
740 #define SK_TXQS2_BMU_CSR 0x0734
741 #define SK_TXQS2_WATERMARK 0x0738
742 #define SK_TXQS2_FLAG 0x073A
743 #define SK_TXQS2_TEST1 0x073C
744 #define SK_TXQS2_TEST2 0x0740
745 #define SK_TXQS2_TEST3 0x0744
747 /* Block 15 -- TX async queue 2 */
748 #define SK_TXQA2_BUFCNT 0x0780
749 #define SK_TXQA2_BUFCTL 0x0782
750 #define SK_TXQA2_NEXTDESC 0x0784
751 #define SK_TXQA2_RXBUF_LO 0x0788
752 #define SK_TXQA2_RXBUF_HI 0x078C
753 #define SK_TXQA2_RXSTAT 0x0790
754 #define SK_TXQA2_CSUM_STARTVAL 0x0794
755 #define SK_TXQA2_CSUM_STARTPOS 0x0798
756 #define SK_TXQA2_CSUM_WRITEPOS 0x079A
757 #define SK_TXQA2_CURADDR_LO 0x07A0
758 #define SK_TXQA2_CURADDR_HI 0x07A4
759 #define SK_TXQA2_CURCNT_LO 0x07A8
760 #define SK_TXQA2_CURCNT_HI 0x07AC
761 #define SK_TXQA2_CURBYTES 0x07B0
762 #define SK_TXQA2_BMU_CSR 0x07B4
763 #define SK_TXQA2_WATERMARK 0x07B8
764 #define SK_TXQA2_FLAG 0x07BA
765 #define SK_TXQA2_TEST1 0x07BC
766 #define SK_TXQA2_TEST2 0x07C0
767 #define SK_TXQA2_TEST3 0x07C4
769 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001
770 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002
771 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004
772 #define SK_TXBMU_TX_START 0x00000010
773 #define SK_TXBMU_TX_STOP 0x00000020
774 #define SK_TXBMU_POLL_OFF 0x00000040
775 #define SK_TXBMU_POLL_ON 0x00000080
776 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100
777 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200
778 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400
779 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800
780 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000
781 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000
782 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000
783 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000
784 #define SK_TXBMU_PFI_SM_RESET 0x00010000
785 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000
786 #define SK_TXBMU_FIFO_RESET 0x00040000
787 #define SK_TXBMU_FIFO_UNRESET 0x00080000
788 #define SK_TXBMU_DESC_RESET 0x00100000
789 #define SK_TXBMU_DESC_UNRESET 0x00200000
790 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000
792 #define SK_TXBMU_ONLINE \
793 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \
794 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \
795 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \
796 SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON)
798 #define SK_TXBMU_OFFLINE \
799 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \
800 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \
801 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \
802 SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF)
804 /* Block 16 -- Receive RAMbuffer 1 */
805 #define SK_RXRB1_START 0x0800
806 #define SK_RXRB1_END 0x0804
807 #define SK_RXRB1_WR_PTR 0x0808
808 #define SK_RXRB1_RD_PTR 0x080C
809 #define SK_RXRB1_UTHR_PAUSE 0x0810
810 #define SK_RXRB1_LTHR_PAUSE 0x0814
811 #define SK_RXRB1_UTHR_HIPRIO 0x0818
812 #define SK_RXRB1_UTHR_LOPRIO 0x081C
813 #define SK_RXRB1_PKTCNT 0x0820
814 #define SK_RXRB1_LVL 0x0824
815 #define SK_RXRB1_CTLTST 0x0828
817 /* Block 17 -- Receive RAMbuffer 2 */
818 #define SK_RXRB2_START 0x0880
819 #define SK_RXRB2_END 0x0884
820 #define SK_RXRB2_WR_PTR 0x0888
821 #define SK_RXRB2_RD_PTR 0x088C
822 #define SK_RXRB2_UTHR_PAUSE 0x0890
823 #define SK_RXRB2_LTHR_PAUSE 0x0894
824 #define SK_RXRB2_UTHR_HIPRIO 0x0898
825 #define SK_RXRB2_UTHR_LOPRIO 0x089C
826 #define SK_RXRB2_PKTCNT 0x08A0
827 #define SK_RXRB2_LVL 0x08A4
828 #define SK_RXRB2_CTLTST 0x08A8
830 /* Block 20 -- Sync. Transmit RAMbuffer 1 */
831 #define SK_TXRBS1_START 0x0A00
832 #define SK_TXRBS1_END 0x0A04
833 #define SK_TXRBS1_WR_PTR 0x0A08
834 #define SK_TXRBS1_RD_PTR 0x0A0C
835 #define SK_TXRBS1_PKTCNT 0x0A20
836 #define SK_TXRBS1_LVL 0x0A24
837 #define SK_TXRBS1_CTLTST 0x0A28
839 /* Block 21 -- Async. Transmit RAMbuffer 1 */
840 #define SK_TXRBA1_START 0x0A80
841 #define SK_TXRBA1_END 0x0A84
842 #define SK_TXRBA1_WR_PTR 0x0A88
843 #define SK_TXRBA1_RD_PTR 0x0A8C
844 #define SK_TXRBA1_PKTCNT 0x0AA0
845 #define SK_TXRBA1_LVL 0x0AA4
846 #define SK_TXRBA1_CTLTST 0x0AA8
848 /* Block 22 -- Sync. Transmit RAMbuffer 2 */
849 #define SK_TXRBS2_START 0x0B00
850 #define SK_TXRBS2_END 0x0B04
851 #define SK_TXRBS2_WR_PTR 0x0B08
852 #define SK_TXRBS2_RD_PTR 0x0B0C
853 #define SK_TXRBS2_PKTCNT 0x0B20
854 #define SK_TXRBS2_LVL 0x0B24
855 #define SK_TXRBS2_CTLTST 0x0B28
857 /* Block 23 -- Async. Transmit RAMbuffer 2 */
858 #define SK_TXRBA2_START 0x0B80
859 #define SK_TXRBA2_END 0x0B84
860 #define SK_TXRBA2_WR_PTR 0x0B88
861 #define SK_TXRBA2_RD_PTR 0x0B8C
862 #define SK_TXRBA2_PKTCNT 0x0BA0
863 #define SK_TXRBA2_LVL 0x0BA4
864 #define SK_TXRBA2_CTLTST 0x0BA8
866 #define SK_RBCTL_RESET 0x00000001
867 #define SK_RBCTL_UNRESET 0x00000002
868 #define SK_RBCTL_OFF 0x00000004
869 #define SK_RBCTL_ON 0x00000008
870 #define SK_RBCTL_STORENFWD_OFF 0x00000010
871 #define SK_RBCTL_STORENFWD_ON 0x00000020
873 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */
874 #define SK_RXF1_END 0x0C00
875 #define SK_RXF1_WPTR 0x0C04
876 #define SK_RXF1_RPTR 0x0C0C
877 #define SK_RXF1_PKTCNT 0x0C10
878 #define SK_RXF1_LVL 0x0C14
879 #define SK_RXF1_MACCTL 0x0C18
880 #define SK_RXF1_CTL 0x0C1C
881 #define SK_RXLED1_CNTINIT 0x0C20
882 #define SK_RXLED1_COUNTER 0x0C24
883 #define SK_RXLED1_CTL 0x0C28
884 #define SK_RXLED1_TST 0x0C29
885 #define SK_LINK_SYNC1_CINIT 0x0C30
886 #define SK_LINK_SYNC1_COUNTER 0x0C34
887 #define SK_LINK_SYNC1_CTL 0x0C38
888 #define SK_LINK_SYNC1_TST 0x0C39
889 #define SK_LINKLED1_CTL 0x0C3C
891 #define SK_FIFO_END 0x3F
893 /* Receive MAC FIFO 1 (Yukon Only) */
894 #define SK_RXMF1_END 0x0C40
895 #define SK_RXMF1_THRESHOLD 0x0C44
896 #define SK_RXMF1_CTRL_TEST 0x0C48
897 #define SK_RXMF1_FLUSH_MASK 0x0C4C
898 #define SK_RXMF1_FLUSH_THRESHOLD 0x0C50
899 #define SK_RXMF1_WRITE_PTR 0x0C60
900 #define SK_RXMF1_WRITE_LEVEL 0x0C68
901 #define SK_RXMF1_READ_PTR 0x0C70
902 #define SK_RXMF1_READ_LEVEL 0x0C78
904 /* Receive MAC FIFO 1 Control/Test */
905 #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
906 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
907 #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
908 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */
909 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */
910 #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */
911 #define SK_RFCTL_FIFO_FLUSH_OFF 0x00000080 /* RX FIFO Flsuh mode off */
912 #define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */
913 #define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */
914 #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */
915 #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */
916 #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */
917 #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */
918 #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */
920 #define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */
922 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
923 #define SK_RXF2_END 0x0C80
924 #define SK_RXF2_WPTR 0x0C84
925 #define SK_RXF2_RPTR 0x0C8C
926 #define SK_RXF2_PKTCNT 0x0C90
927 #define SK_RXF2_LVL 0x0C94
928 #define SK_RXF2_MACCTL 0x0C98
929 #define SK_RXF2_CTL 0x0C9C
930 #define SK_RXLED2_CNTINIT 0x0CA0
931 #define SK_RXLED2_COUNTER 0x0CA4
932 #define SK_RXLED2_CTL 0x0CA8
933 #define SK_RXLED2_TST 0x0CA9
934 #define SK_LINK_SYNC2_CINIT 0x0CB0
935 #define SK_LINK_SYNC2_COUNTER 0x0CB4
936 #define SK_LINK_SYNC2_CTL 0x0CB8
937 #define SK_LINK_SYNC2_TST 0x0CB9
938 #define SK_LINKLED2_CTL 0x0CBC
940 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001
941 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002
942 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004
943 #define SK_RXMACCTL_RSTAMP_ON 0x00000008
944 #define SK_RXMACCTL_FLUSH_OFF 0x00000010
945 #define SK_RXMACCTL_FLUSH_ON 0x00000020
946 #define SK_RXMACCTL_PAUSE_OFF 0x00000040
947 #define SK_RXMACCTL_PAUSE_ON 0x00000080
948 #define SK_RXMACCTL_AFULL_OFF 0x00000100
949 #define SK_RXMACCTL_AFULL_ON 0x00000200
950 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400
951 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800
952 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000
953 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000
954 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000
955 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000
957 #define SK_RXLEDCTL_ENABLE 0x0001
958 #define SK_RXLEDCTL_COUNTER_STOP 0x0002
959 #define SK_RXLEDCTL_COUNTER_START 0x0004
961 #define SK_LINKLED_OFF 0x0001
962 #define SK_LINKLED_ON 0x0002
963 #define SK_LINKLED_LINKSYNC_OFF 0x0004
964 #define SK_LINKLED_LINKSYNC_ON 0x0008
965 #define SK_LINKLED_BLINK_OFF 0x0010
966 #define SK_LINKLED_BLINK_ON 0x0020
968 /* Block 26 -- TX MAC FIFO 1 regisrers */
969 #define SK_TXF1_END 0x0D00
970 #define SK_TXF1_WPTR 0x0D04
971 #define SK_TXF1_RPTR 0x0D0C
972 #define SK_TXF1_PKTCNT 0x0D10
973 #define SK_TXF1_LVL 0x0D14
974 #define SK_TXF1_MACCTL 0x0D18
975 #define SK_TXF1_CTL 0x0D1C
976 #define SK_TXLED1_CNTINIT 0x0D20
977 #define SK_TXLED1_COUNTER 0x0D24
978 #define SK_TXLED1_CTL 0x0D28
979 #define SK_TXLED1_TST 0x0D29
981 /* Transmit MAC FIFO 1 (Yukon Only) */
982 #define SK_TXMF1_END 0x0D40
983 #define SK_TXMF1_THRESHOLD 0x0D44
984 #define SK_TXMF1_CTRL_TEST 0x0D48
985 #define SK_TXMF1_WRITE_PTR 0x0D60
986 #define SK_TXMF1_WRITE_SHADOW 0x0D64
987 #define SK_TXMF1_WRITE_LEVEL 0x0D68
988 #define SK_TXMF1_READ_PTR 0x0D70
989 #define SK_TXMF1_RESTART_PTR 0x0D74
990 #define SK_TXMF1_READ_LEVEL 0x0D78
992 /* Transmit MAC FIFO Control/Test */
993 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
994 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
995 #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
996 #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */
997 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */
998 #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */
999 #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */
1000 #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */
1001 #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */
1002 #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */
1003 #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */
1004 #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */
1005 #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */
1007 /* Block 27 -- TX MAC FIFO 2 regisrers */
1008 #define SK_TXF2_END 0x0D80
1009 #define SK_TXF2_WPTR 0x0D84
1010 #define SK_TXF2_RPTR 0x0D8C
1011 #define SK_TXF2_PKTCNT 0x0D90
1012 #define SK_TXF2_LVL 0x0D94
1013 #define SK_TXF2_MACCTL 0x0D98
1014 #define SK_TXF2_CTL 0x0D9C
1015 #define SK_TXLED2_CNTINIT 0x0DA0
1016 #define SK_TXLED2_COUNTER 0x0DA4
1017 #define SK_TXLED2_CTL 0x0DA8
1018 #define SK_TXLED2_TST 0x0DA9
1020 #define SK_TXMACCTL_XMAC_RESET 0x00000001
1021 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002
1022 #define SK_TXMACCTL_LOOP_OFF 0x00000004
1023 #define SK_TXMACCTL_LOOP_ON 0x00000008
1024 #define SK_TXMACCTL_FLUSH_OFF 0x00000010
1025 #define SK_TXMACCTL_FLUSH_ON 0x00000020
1026 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040
1027 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080
1028 #define SK_TXMACCTL_AFULL_OFF 0x00000100
1029 #define SK_TXMACCTL_AFULL_ON 0x00000200
1030 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400
1031 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800
1032 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000
1033 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000
1034 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000
1035 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000
1037 #define SK_TXLEDCTL_ENABLE 0x0001
1038 #define SK_TXLEDCTL_COUNTER_STOP 0x0002
1039 #define SK_TXLEDCTL_COUNTER_START 0x0004
1041 #define SK_FIFO_RESET 0x00000001
1042 #define SK_FIFO_UNRESET 0x00000002
1043 #define SK_FIFO_OFF 0x00000004
1044 #define SK_FIFO_ON 0x00000008
1046 /* Block 28 -- Descriptor Poll Timer */
1047 #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */
1048 #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */
1050 #define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */
1052 #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */
1053 #define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */
1054 #define SK_DPT_TCTL_START 0x0002 /* Start Timer */
1056 #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */
1057 #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */
1058 #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */
1059 #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */
1061 /* Block 29 -- reserved */
1063 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/
1064 #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */
1065 #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */
1066 #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */
1067 #define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */
1068 #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */
1069 #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */
1070 #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */
1071 #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */
1072 #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */
1073 #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */
1074 #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */
1075 #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */
1076 #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */
1077 #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */
1078 #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */
1079 #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */
1080 #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */
1081 #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */
1082 #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */
1083 #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */
1084 #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */
1085 #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */
1086 #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */
1087 #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */
1088 #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */
1089 #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */
1090 #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */
1091 #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */
1092 #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */
1094 #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */
1095 #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */
1096 #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */
1097 #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */
1098 #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */
1099 #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */
1101 #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */
1102 #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */
1103 #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */
1104 #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */
1105 #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */
1106 #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */
1107 #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */
1108 #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */
1109 #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */
1110 #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */
1111 #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */
1112 #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */
1113 #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */
1114 #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */
1115 #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */
1116 #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */
1117 #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */
1118 #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */
1119 #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */
1120 #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */
1121 #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */
1122 #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */
1123 #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */
1125 #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
1126 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 )
1127 #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
1129 #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \
1130 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 )
1132 #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */
1133 #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */
1134 #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */
1135 #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */
1136 #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */
1137 #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */
1139 #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */
1140 #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */
1142 /* Block 31 -- reserved */
1144 /* Block 32-33 -- Pattern Ram */
1145 #define SK_WOL_PRAM 0x1000
1147 /* Block 0x22 - 0x3f -- reserved */
1149 /* Block 0x40 to 0x4F -- XMAC 1 registers */
1150 #define SK_XMAC1_BASE 0x2000
1152 /* Block 0x50 to 0x5F -- MARV 1 registers */
1153 #define SK_MARV1_BASE 0x2800
1155 /* Block 0x60 to 0x6F -- XMAC 2 registers */
1156 #define SK_XMAC2_BASE 0x3000
1158 /* Block 0x70 to 0x7F -- MARV 2 registers */
1159 #define SK_MARV2_BASE 0x3800
1161 /* Compute relative offset of an XMAC register in the XMAC window(s). */
1162 #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \
1163 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE)))
1166 #define SK_XM_READ_4(sc, reg) \
1167 ((sk_win_read_2(sc->sk_softc, \
1168 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \
1169 ((sk_win_read_2(sc->sk_softc, \
1170 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16))
1172 #define SK_XM_WRITE_4(sc, reg, val) \
1173 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \
1174 ((val) & 0xFFFF)); \
1175 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \
1176 ((val) >> 16) & 0xFFFF)
1178 #define SK_XM_READ_4(sc, reg) \
1179 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg))
1181 #define SK_XM_WRITE_4(sc, reg, val) \
1182 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))
1185 #define SK_XM_READ_2(sc, reg) \
1186 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg))
1188 #define SK_XM_WRITE_2(sc, reg, val) \
1189 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)
1191 #define SK_XM_SETBIT_4(sc, reg, x) \
1192 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))
1194 #define SK_XM_CLRBIT_4(sc, reg, x) \
1195 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))
1197 #define SK_XM_SETBIT_2(sc, reg, x) \
1198 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))
1200 #define SK_XM_CLRBIT_2(sc, reg, x) \
1201 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))
1203 /* Compute relative offset of an MARV register in the MARV window(s). */
1204 #define SK_YU_REG(sc, reg) \
1205 ((reg) + SK_MARV1_BASE + \
1206 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE)))
1208 #define SK_YU_READ_4(sc, reg) \
1209 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg)))
1211 #define SK_YU_READ_2(sc, reg) \
1212 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg)))
1214 #define SK_YU_WRITE_4(sc, reg, val) \
1215 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
1217 #define SK_YU_WRITE_2(sc, reg, val) \
1218 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
1220 #define SK_YU_SETBIT_4(sc, reg, x) \
1221 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x))
1223 #define SK_YU_CLRBIT_4(sc, reg, x) \
1224 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x))
1226 #define SK_YU_SETBIT_2(sc, reg, x) \
1227 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x))
1229 #define SK_YU_CLRBIT_2(sc, reg, x) \
1230 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x))
1233 * The default FIFO threshold on the XMAC II is 4 bytes. On
1234 * dual port NICs, this often leads to transmit underruns, so we
1235 * bump the threshold a little.
1237 #define SK_XM_TX_FIFOTHRESH 512
1239 #define SK_PCI_VENDOR_ID 0x0000
1240 #define SK_PCI_DEVICE_ID 0x0002
1241 #define SK_PCI_COMMAND 0x0004
1242 #define SK_PCI_STATUS 0x0006
1243 #define SK_PCI_REVID 0x0008
1244 #define SK_PCI_CLASSCODE 0x0009
1245 #define SK_PCI_CACHELEN 0x000C
1246 #define SK_PCI_LATENCY_TIMER 0x000D
1247 #define SK_PCI_HEADER_TYPE 0x000E
1248 #define SK_PCI_LOMEM 0x0010
1249 #define SK_PCI_LOIO 0x0014
1250 #define SK_PCI_SUBVEN_ID 0x002C
1251 #define SK_PCI_SYBSYS_ID 0x002E
1252 #define SK_PCI_BIOSROM 0x0030
1253 #define SK_PCI_INTLINE 0x003C
1254 #define SK_PCI_INTPIN 0x003D
1255 #define SK_PCI_MINGNT 0x003E
1256 #define SK_PCI_MINLAT 0x003F
1258 /* device specific PCI registers */
1259 #define SK_PCI_OURREG1 0x0040
1260 #define SK_PCI_OURREG2 0x0044
1261 #define SK_PCI_CAPID 0x0048 /* 8 bits */
1262 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */
1263 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */
1264 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */
1265 #define SK_PCI_PME_EVENT 0x004F
1267 #define SK_PSTATE_MASK 0x0003
1268 #define SK_PSTATE_D0 0x0000
1269 #define SK_PSTATE_D1 0x0001
1270 #define SK_PSTATE_D2 0x0002
1271 #define SK_PSTATE_D3 0x0003
1272 #define SK_PME_EN 0x0010
1273 #define SK_PME_STATUS 0x8000
1275 #define CSR_WRITE_4(sc, reg, val) \
1276 bus_write_4((sc)->sk_res[0], (reg), (val))
1277 #define CSR_WRITE_2(sc, reg, val) \
1278 bus_write_2((sc)->sk_res[0], (reg), (val))
1279 #define CSR_WRITE_1(sc, reg, val) \
1280 bus_write_1((sc)->sk_res[0], (reg), (val))
1282 #define CSR_READ_4(sc, reg) \
1283 bus_read_4((sc)->sk_res[0], (reg))
1284 #define CSR_READ_2(sc, reg) \
1285 bus_read_2((sc)->sk_res[0], (reg))
1286 #define CSR_READ_1(sc, reg) \
1287 bus_read_1((sc)->sk_res[0], (reg))
1292 const char *sk_name;
1295 #define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff)
1296 #define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32)
1298 #define SK_RING_ALIGN 64
1300 /* RX queue descriptor data structure */
1304 u_int32_t sk_data_lo;
1305 u_int32_t sk_data_hi;
1306 u_int32_t sk_xmac_rxstat;
1307 u_int32_t sk_timestamp;
1309 u_int32_t sk_csum_start;
1312 #define SK_OPCODE_DEFAULT 0x00550000
1313 #define SK_OPCODE_CSUM 0x00560000
1315 #define SK_RXCTL_LEN 0x0000FFFF
1316 #define SK_RXCTL_OPCODE 0x00FF0000
1317 #define SK_RXCTL_TSTAMP_VALID 0x01000000
1318 #define SK_RXCTL_STATUS_VALID 0x02000000
1319 #define SK_RXCTL_DEV0 0x04000000
1320 #define SK_RXCTL_EOF_INTR 0x08000000
1321 #define SK_RXCTL_EOB_INTR 0x10000000
1322 #define SK_RXCTL_LASTFRAG 0x20000000
1323 #define SK_RXCTL_FIRSTFRAG 0x40000000
1324 #define SK_RXCTL_OWN 0x80000000
1327 (SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG|SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
1332 u_int32_t sk_data_lo;
1333 u_int32_t sk_data_hi;
1334 u_int32_t sk_xmac_txstat;
1335 u_int32_t sk_csum_startval;
1336 u_int32_t sk_csum_start;
1340 #define SK_TXCTL_LEN 0x0000FFFF
1341 #define SK_TXCTL_OPCODE 0x00FF0000
1342 #define SK_TXCTL_SW 0x01000000
1343 #define SK_TXCTL_NOCRC 0x02000000
1344 #define SK_TXCTL_STORENFWD 0x04000000
1345 #define SK_TXCTL_EOF_INTR 0x08000000
1346 #define SK_TXCTL_EOB_INTR 0x10000000
1347 #define SK_TXCTL_LASTFRAG 0x20000000
1348 #define SK_TXCTL_FIRSTFRAG 0x40000000
1349 #define SK_TXCTL_OWN 0x80000000
1352 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN)
1354 #define SK_RXBYTES(x) ((x) & 0x0000FFFF)
1355 #define SK_TXBYTES SK_RXBYTES
1357 #define SK_TX_RING_CNT 512
1358 #define SK_RX_RING_CNT 256
1359 #define SK_JUMBO_RX_RING_CNT 256
1360 #define SK_MAXTXSEGS 32
1362 #define SK_JUMBO_FRAMELEN 9018
1363 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
1364 #define SK_MAX_FRAMELEN \
1365 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)
1366 #define SK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
1370 bus_dmamap_t tx_dmamap;
1371 STAILQ_ENTRY(sk_txdesc) tx_q;
1374 STAILQ_HEAD(sk_txdq, sk_txdesc);
1378 bus_dmamap_t rx_dmamap;
1381 struct sk_chain_data {
1382 bus_dma_tag_t sk_parent_tag;
1383 bus_dma_tag_t sk_tx_tag;
1384 struct sk_txdesc sk_txdesc[SK_TX_RING_CNT];
1385 struct sk_txdq sk_txfreeq;
1386 struct sk_txdq sk_txbusyq;
1387 bus_dma_tag_t sk_rx_tag;
1388 struct sk_rxdesc sk_rxdesc[SK_RX_RING_CNT];
1389 bus_dma_tag_t sk_tx_ring_tag;
1390 bus_dma_tag_t sk_rx_ring_tag;
1391 bus_dmamap_t sk_tx_ring_map;
1392 bus_dmamap_t sk_rx_ring_map;
1393 bus_dmamap_t sk_rx_sparemap;
1394 bus_dma_tag_t sk_jumbo_rx_tag;
1395 struct sk_rxdesc sk_jumbo_rxdesc[SK_JUMBO_RX_RING_CNT];
1396 bus_dma_tag_t sk_jumbo_rx_ring_tag;
1397 bus_dmamap_t sk_jumbo_rx_ring_map;
1398 bus_dmamap_t sk_jumbo_rx_sparemap;
1403 int sk_jumbo_rx_cons;
1406 struct sk_ring_data {
1407 struct sk_tx_desc *sk_tx_ring;
1408 bus_addr_t sk_tx_ring_paddr;
1409 struct sk_rx_desc *sk_rx_ring;
1410 bus_addr_t sk_rx_ring_paddr;
1411 struct sk_rx_desc *sk_jumbo_rx_ring;
1412 bus_addr_t sk_jumbo_rx_ring_paddr;
1415 #define SK_TX_RING_ADDR(sc, i) \
1416 ((sc)->sk_rdata.sk_tx_ring_paddr + sizeof(struct sk_tx_desc) * (i))
1417 #define SK_RX_RING_ADDR(sc, i) \
1418 ((sc)->sk_rdata.sk_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i))
1419 #define SK_JUMBO_RX_RING_ADDR(sc, i) \
1420 ((sc)->sk_rdata.sk_jumbo_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i))
1422 #define SK_TX_RING_SZ \
1423 (sizeof(struct sk_tx_desc) * SK_TX_RING_CNT)
1424 #define SK_RX_RING_SZ \
1425 (sizeof(struct sk_rx_desc) * SK_RX_RING_CNT)
1426 #define SK_JUMBO_RX_RING_SZ \
1427 (sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT)
1429 struct sk_bcom_hack {
1434 #define SK_INC(x, y) (x) = (x + 1) % y
1439 /* Softc for the GEnesis controller. */
1441 struct resource *sk_res[2]; /* I/O and IRQ resources */
1442 struct resource_spec *sk_res_spec;
1443 void *sk_intrhand; /* irq handler handle */
1448 u_int32_t sk_rboff; /* RAMbuffer offset */
1449 u_int32_t sk_ramsize; /* amount of RAM on NIC */
1450 u_int32_t sk_pmd; /* physical media type */
1451 u_int32_t sk_coppertype;
1452 u_int32_t sk_intrmask;
1456 struct sk_if_softc *sk_if[2];
1457 device_t sk_devs[2];
1458 struct mtx sk_mii_mtx;
1462 #define SK_LOCK(_sc) mtx_lock(&(_sc)->sk_mtx)
1463 #define SK_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_mtx)
1464 #define SK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sk_mtx, MA_OWNED)
1465 #define SK_IF_LOCK(_sc) SK_LOCK((_sc)->sk_softc)
1466 #define SK_IF_UNLOCK(_sc) SK_UNLOCK((_sc)->sk_softc)
1467 #define SK_IF_LOCK_ASSERT(_sc) SK_LOCK_ASSERT((_sc)->sk_softc)
1468 #define SK_IF_MII_LOCK(_sc) mtx_lock(&(_sc)->sk_softc->sk_mii_mtx)
1469 #define SK_IF_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_softc->sk_mii_mtx)
1471 /* Softc for each logical interface */
1472 struct sk_if_softc {
1473 struct ifnet *sk_ifp; /* interface info */
1476 u_int8_t sk_port; /* port # on controller */
1477 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */
1478 u_int32_t sk_rx_ramstart;
1479 u_int32_t sk_rx_ramend;
1480 u_int32_t sk_tx_ramstart;
1481 u_int32_t sk_tx_ramend;
1485 struct callout sk_tick_ch;
1486 struct callout sk_watchdog_ch;
1487 int sk_watchdog_timer;
1488 struct sk_chain_data sk_cdata;
1489 struct sk_ring_data sk_rdata;
1490 struct sk_softc *sk_softc; /* parent controller */
1491 int sk_tx_bmu; /* TX BMU register */
1493 int sk_jumbo_disable;
1496 #define SK_TIMEOUT 1000