1 /* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */
4 * SPDX-License-Identifier: BSD-4-Clause
6 * Copyright (c) 1997, 1998, 1999, 2000
7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Bill Paul.
20 * 4. Neither the name of the author nor the names of any co-contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGE.
40 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
42 * Permission to use, copy, modify, and distribute this software for any
43 * purpose with or without fee is hereby granted, provided that the above
44 * copyright notice and this permission notice appear in all copies.
46 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
47 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
48 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
49 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
50 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
51 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
52 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
55 /* Values to keep the different chip revisions apart (SK_CHIPVER). */
56 #define SK_GENESIS 0x0A
58 #define SK_YUKON_LITE 0xB1
59 #define SK_YUKON_LP 0xB2
60 #define SK_YUKON_FAMILY(x) ((x) & 0xB0)
62 /* Known revisions in SK_CONFIG. */
63 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */
64 #define SK_YUKON_LITE_REV_A1 0x3
65 #define SK_YUKON_LITE_REV_A3 0x7
68 * SysKonnect PCI vendor ID
70 #define VENDORID_SK 0x1148
73 * Marvell PCI vendor ID
75 #define VENDORID_MARVELL 0x11AB
78 * SK-NET gigabit ethernet device IDs
80 #define DEVICEID_SK_V1 0x4300
81 #define DEVICEID_SK_V2 0x4320
86 #define DEVICEID_BELKIN_5005 0x5005
91 #define VENDORID_3COM 0x10b7
94 * 3Com gigabit ethernet device ID
96 #define DEVICEID_3COM_3C940 0x1700
99 * Linksys PCI vendor ID
101 #define VENDORID_LINKSYS 0x1737
104 * Linksys gigabit ethernet device ID
106 #define DEVICEID_LINKSYS_EG1032 0x1032
109 * Linksys gigabit ethernet rev 2 sub-device ID
111 #define SUBDEVICEID_LINKSYS_EG1032_REV2 0x0015
114 * D-Link PCI vendor ID
116 #define VENDORID_DLINK 0x1186
119 * D-Link gigabit ethernet device ID
121 #define DEVICEID_DLINK_DGE530T_A1 0x4c00
122 #define DEVICEID_DLINK_DGE530T_B1 0x4b01
125 * GEnesis registers. The GEnesis chip has a 256-byte I/O window
126 * but internally it has a 16K register space. This 16K space is
127 * divided into 128-byte blocks. The first 128 bytes of the I/O
128 * window represent the first block, which is permanently mapped
129 * at the start of the window. The other 127 blocks can be mapped
130 * to the second 128 bytes of the I/O window by setting the desired
131 * block value in the RAP register in block 0. Not all of the 127
132 * blocks are actually used. Most registers are 32 bits wide, but
133 * there are a few 16-bit and 8-bit ones as well.
137 /* Start of remappable register window. */
138 #define SK_WIN_BASE 0x0080
140 /* Size of a window */
141 #define SK_WIN_LEN 0x80
143 #define SK_WIN_MASK 0x3F80
144 #define SK_REG_MASK 0x7F
146 /* Compute the window of a given register (for the RAP register) */
147 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN)
149 /* Compute the relative offset of a register within the window */
150 #define SK_REG(reg) ((reg) & SK_REG_MASK)
156 * Compute offset of port-specific register. Since there are two
157 * ports, there are two of some GEnesis modules (e.g. two sets of
158 * DMA queues, two sets of FIFO control registers, etc...). Normally,
159 * the block for port 0 is at offset 0x0 and the block for port 1 is
160 * at offset 0x80 (i.e. the next page over). However for the transmit
161 * BMUs and RAMbuffers, there are two blocks for each port: one for
162 * the sync transmit queue and one for the async queue (which we don't
163 * use). However instead of ordering them like this:
164 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2
165 * SysKonnect has instead ordered them like this:
166 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2
167 * This means that when referencing the TX BMU and RAMbuffer registers,
168 * we have to double the block offset (0x80 * 2) in order to reach the
169 * second queue. This prevents us from using the same formula
170 * (sk_port * 0x80) to compute the offsets for all of the port-specific
171 * blocks: we need an extra offset for the BMU and RAMbuffer registers.
172 * The simplest thing is to provide an extra argument to these macros:
173 * the 'skip' parameter. The 'skip' value is the number of extra pages
174 * for skip when computing the port0/port1 offsets. For most registers,
175 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1.
177 #define SK_IF_READ_4(sc_if, skip, reg) \
178 sk_win_read_4(sc_if->sk_softc, reg + \
179 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
180 #define SK_IF_READ_2(sc_if, skip, reg) \
181 sk_win_read_2(sc_if->sk_softc, reg + \
182 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
183 #define SK_IF_READ_1(sc_if, skip, reg) \
184 sk_win_read_1(sc_if->sk_softc, reg + \
185 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
187 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \
188 sk_win_write_4(sc_if->sk_softc, \
189 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
190 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \
191 sk_win_write_2(sc_if->sk_softc, \
192 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
193 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \
194 sk_win_write_1(sc_if->sk_softc, \
195 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
197 /* Block 0 registers, permanently mapped at iobase. */
198 #define SK_RAP 0x0000
199 #define SK_CSR 0x0004
200 #define SK_LED 0x0006
201 #define SK_ISR 0x0008 /* interrupt source */
202 #define SK_IMR 0x000C /* interrupt mask */
203 #define SK_IESR 0x0010 /* interrupt hardware error source */
204 #define SK_IEMR 0x0014 /* interrupt hardware error mask */
205 #define SK_ISSR 0x0018 /* special interrupt source */
206 #define SK_XM_IMR0 0x0020
207 #define SK_XM_ISR0 0x0028
208 #define SK_XM_PHYADDR0 0x0030
209 #define SK_XM_PHYDATA0 0x0034
210 #define SK_XM_IMR1 0x0040
211 #define SK_XM_ISR1 0x0048
212 #define SK_XM_PHYADDR1 0x0050
213 #define SK_XM_PHYDATA1 0x0054
214 #define SK_BMU_RX_CSR0 0x0060
215 #define SK_BMU_RX_CSR1 0x0064
216 #define SK_BMU_TXS_CSR0 0x0068
217 #define SK_BMU_TXA_CSR0 0x006C
218 #define SK_BMU_TXS_CSR1 0x0070
219 #define SK_BMU_TXA_CSR1 0x0074
221 /* SK_CSR register */
222 #define SK_CSR_SW_RESET 0x0001
223 #define SK_CSR_SW_UNRESET 0x0002
224 #define SK_CSR_MASTER_RESET 0x0004
225 #define SK_CSR_MASTER_UNRESET 0x0008
226 #define SK_CSR_MASTER_STOP 0x0010
227 #define SK_CSR_MASTER_DONE 0x0020
228 #define SK_CSR_SW_IRQ_CLEAR 0x0040
229 #define SK_CSR_SW_IRQ_SET 0x0080
230 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */
231 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */
233 /* SK_LED register */
234 #define SK_LED_GREEN_OFF 0x01
235 #define SK_LED_GREEN_ON 0x02
237 /* SK_ISR register */
238 #define SK_ISR_TX2_AS_CHECK 0x00000001
239 #define SK_ISR_TX2_AS_EOF 0x00000002
240 #define SK_ISR_TX2_AS_EOB 0x00000004
241 #define SK_ISR_TX2_S_CHECK 0x00000008
242 #define SK_ISR_TX2_S_EOF 0x00000010
243 #define SK_ISR_TX2_S_EOB 0x00000020
244 #define SK_ISR_TX1_AS_CHECK 0x00000040
245 #define SK_ISR_TX1_AS_EOF 0x00000080
246 #define SK_ISR_TX1_AS_EOB 0x00000100
247 #define SK_ISR_TX1_S_CHECK 0x00000200
248 #define SK_ISR_TX1_S_EOF 0x00000400
249 #define SK_ISR_TX1_S_EOB 0x00000800
250 #define SK_ISR_RX2_CHECK 0x00001000
251 #define SK_ISR_RX2_EOF 0x00002000
252 #define SK_ISR_RX2_EOB 0x00004000
253 #define SK_ISR_RX1_CHECK 0x00008000
254 #define SK_ISR_RX1_EOF 0x00010000
255 #define SK_ISR_RX1_EOB 0x00020000
256 #define SK_ISR_LINK2_OFLOW 0x00040000
257 #define SK_ISR_MAC2 0x00080000
258 #define SK_ISR_LINK1_OFLOW 0x00100000
259 #define SK_ISR_MAC1 0x00200000
260 #define SK_ISR_TIMER 0x00400000
261 #define SK_ISR_EXTERNAL_REG 0x00800000
262 #define SK_ISR_SW 0x01000000
263 #define SK_ISR_I2C_RDY 0x02000000
264 #define SK_ISR_TX2_TIMEO 0x04000000
265 #define SK_ISR_TX1_TIMEO 0x08000000
266 #define SK_ISR_RX2_TIMEO 0x10000000
267 #define SK_ISR_RX1_TIMEO 0x20000000
268 #define SK_ISR_RSVD 0x40000000
269 #define SK_ISR_HWERR 0x80000000
271 /* SK_IMR register */
272 #define SK_IMR_TX2_AS_CHECK 0x00000001
273 #define SK_IMR_TX2_AS_EOF 0x00000002
274 #define SK_IMR_TX2_AS_EOB 0x00000004
275 #define SK_IMR_TX2_S_CHECK 0x00000008
276 #define SK_IMR_TX2_S_EOF 0x00000010
277 #define SK_IMR_TX2_S_EOB 0x00000020
278 #define SK_IMR_TX1_AS_CHECK 0x00000040
279 #define SK_IMR_TX1_AS_EOF 0x00000080
280 #define SK_IMR_TX1_AS_EOB 0x00000100
281 #define SK_IMR_TX1_S_CHECK 0x00000200
282 #define SK_IMR_TX1_S_EOF 0x00000400
283 #define SK_IMR_TX1_S_EOB 0x00000800
284 #define SK_IMR_RX2_CHECK 0x00001000
285 #define SK_IMR_RX2_EOF 0x00002000
286 #define SK_IMR_RX2_EOB 0x00004000
287 #define SK_IMR_RX1_CHECK 0x00008000
288 #define SK_IMR_RX1_EOF 0x00010000
289 #define SK_IMR_RX1_EOB 0x00020000
290 #define SK_IMR_LINK2_OFLOW 0x00040000
291 #define SK_IMR_MAC2 0x00080000
292 #define SK_IMR_LINK1_OFLOW 0x00100000
293 #define SK_IMR_MAC1 0x00200000
294 #define SK_IMR_TIMER 0x00400000
295 #define SK_IMR_EXTERNAL_REG 0x00800000
296 #define SK_IMR_SW 0x01000000
297 #define SK_IMR_I2C_RDY 0x02000000
298 #define SK_IMR_TX2_TIMEO 0x04000000
299 #define SK_IMR_TX1_TIMEO 0x08000000
300 #define SK_IMR_RX2_TIMEO 0x10000000
301 #define SK_IMR_RX1_TIMEO 0x20000000
302 #define SK_IMR_RSVD 0x40000000
303 #define SK_IMR_HWERR 0x80000000
306 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1)
309 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2)
311 /* SK_IESR register */
312 #define SK_IESR_PAR_RX2 0x00000001
313 #define SK_IESR_PAR_RX1 0x00000002
314 #define SK_IESR_PAR_MAC2 0x00000004
315 #define SK_IESR_PAR_MAC1 0x00000008
316 #define SK_IESR_PAR_WR_RAM 0x00000010
317 #define SK_IESR_PAR_RD_RAM 0x00000020
318 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040
319 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080
320 #define SK_IESR_NO_STS_MAC2 0x00000100
321 #define SK_IESR_NO_STS_MAC1 0x00000200
322 #define SK_IESR_IRQ_STS 0x00000400
323 #define SK_IESR_MASTERERR 0x00000800
325 /* SK_IEMR register */
326 #define SK_IEMR_PAR_RX2 0x00000001
327 #define SK_IEMR_PAR_RX1 0x00000002
328 #define SK_IEMR_PAR_MAC2 0x00000004
329 #define SK_IEMR_PAR_MAC1 0x00000008
330 #define SK_IEMR_PAR_WR_RAM 0x00000010
331 #define SK_IEMR_PAR_RD_RAM 0x00000020
332 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040
333 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080
334 #define SK_IEMR_NO_STS_MAC2 0x00000100
335 #define SK_IEMR_NO_STS_MAC1 0x00000200
336 #define SK_IEMR_IRQ_STS 0x00000400
337 #define SK_IEMR_MASTERERR 0x00000800
340 #define SK_MAC0_0 0x0100
341 #define SK_MAC0_1 0x0104
342 #define SK_MAC1_0 0x0108
343 #define SK_MAC1_1 0x010C
344 #define SK_MAC2_0 0x0110
345 #define SK_MAC2_1 0x0114
346 #define SK_CONNTYPE 0x0118
347 #define SK_PMDTYPE 0x0119
348 #define SK_CONFIG 0x011A
349 #define SK_CHIPVER 0x011B
350 #define SK_EPROM0 0x011C
351 #define SK_EPROM1 0x011D /* yukon/genesis */
352 #define SK_EPROM2 0x011E /* yukon/genesis */
353 #define SK_EPROM3 0x011F
354 #define SK_EP_ADDR 0x0120
355 #define SK_EP_DATA 0x0124
356 #define SK_EP_LOADCTL 0x0128
357 #define SK_EP_LOADTST 0x0129
358 #define SK_TIMERINIT 0x0130
359 #define SK_TIMER 0x0134
360 #define SK_TIMERCTL 0x0138
361 #define SK_TIMERTST 0x0139
362 #define SK_IMTIMERINIT 0x0140
363 #define SK_IMTIMER 0x0144
364 #define SK_IMTIMERCTL 0x0148
365 #define SK_IMTIMERTST 0x0149
366 #define SK_IMMR 0x014C
367 #define SK_IHWEMR 0x0150
368 #define SK_TESTCTL1 0x0158
369 #define SK_TESTCTL2 0x0159
370 #define SK_GPIO 0x015C
371 #define SK_I2CHWCTL 0x0160
372 #define SK_I2CHWDATA 0x0164
373 #define SK_I2CHWIRQ 0x0168
374 #define SK_I2CSW 0x016C
375 #define SK_BLNKINIT 0x0170
376 #define SK_BLNKCOUNT 0x0174
377 #define SK_BLNKCTL 0x0178
378 #define SK_BLNKSTS 0x0179
379 #define SK_BLNKTST 0x017A
381 #define SK_IMCTL_STOP 0x02
382 #define SK_IMCTL_START 0x04
384 #define SK_IMTIMER_TICKS_GENESIS 53
385 #define SK_IMTIMER_TICKS_YUKON 78
386 #define SK_IM_USECS(x, t) ((x) * (t))
389 #define SK_IM_DEFAULT 100
390 #define SK_IM_MAX 10000
393 * The SK_EPROM0 register contains a byte that describes the
394 * amount of SRAM mounted on the NIC. The value also tells if
395 * the chips are 64K or 128K. This affects the RAMbuffer address
396 * offset that we need to use.
398 #define SK_RAMSIZE_512K_64 0x1
399 #define SK_RAMSIZE_1024K_128 0x2
400 #define SK_RAMSIZE_1024K_64 0x3
401 #define SK_RAMSIZE_2048K_128 0x4
403 #define SK_RBOFF_0 0x0
404 #define SK_RBOFF_80000 0x80000
407 * SK_EEPROM1 contains the PHY type, which may be XMAC for
408 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom
411 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */
412 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */
413 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */
414 #define SK_PHYTYPE_NAT 3 /* National DP83891 */
415 #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */
416 #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */
421 #define SK_PHYADDR_XMAC 0x0
422 #define SK_PHYADDR_BCOM 0x1
423 #define SK_PHYADDR_LONE 0x3
424 #define SK_PHYADDR_NAT 0x0
425 #define SK_PHYADDR_MARV 0x0
427 #define SK_CONFIG_SINGLEMAC 0x01
428 #define SK_CONFIG_DIS_DSL_CLK 0x02
430 #define SK_PMD_1000BASELX 0x4C
431 #define SK_PMD_1000BASESX 0x53
432 #define SK_PMD_1000BASECX 0x43
433 #define SK_PMD_1000BASETX 0x54
436 #define SK_GPIO_DAT0 0x00000001
437 #define SK_GPIO_DAT1 0x00000002
438 #define SK_GPIO_DAT2 0x00000004
439 #define SK_GPIO_DAT3 0x00000008
440 #define SK_GPIO_DAT4 0x00000010
441 #define SK_GPIO_DAT5 0x00000020
442 #define SK_GPIO_DAT6 0x00000040
443 #define SK_GPIO_DAT7 0x00000080
444 #define SK_GPIO_DAT8 0x00000100
445 #define SK_GPIO_DAT9 0x00000200
446 #define SK_GPIO_DIR0 0x00010000
447 #define SK_GPIO_DIR1 0x00020000
448 #define SK_GPIO_DIR2 0x00040000
449 #define SK_GPIO_DIR3 0x00080000
450 #define SK_GPIO_DIR4 0x00100000
451 #define SK_GPIO_DIR5 0x00200000
452 #define SK_GPIO_DIR6 0x00400000
453 #define SK_GPIO_DIR7 0x00800000
454 #define SK_GPIO_DIR8 0x01000000
455 #define SK_GPIO_DIR9 0x02000000
457 /* Block 3 Ram interface and MAC arbiter registers */
458 #define SK_RAMADDR 0x0180
459 #define SK_RAMDATA0 0x0184
460 #define SK_RAMDATA1 0x0188
461 #define SK_TO0 0x0190
462 #define SK_TO1 0x0191
463 #define SK_TO2 0x0192
464 #define SK_TO3 0x0193
465 #define SK_TO4 0x0194
466 #define SK_TO5 0x0195
467 #define SK_TO6 0x0196
468 #define SK_TO7 0x0197
469 #define SK_TO8 0x0198
470 #define SK_TO9 0x0199
471 #define SK_TO10 0x019A
472 #define SK_TO11 0x019B
473 #define SK_RITIMEO_TMR 0x019C
474 #define SK_RAMCTL 0x01A0
475 #define SK_RITIMER_TST 0x01A2
477 #define SK_RAMCTL_RESET 0x0001
478 #define SK_RAMCTL_UNRESET 0x0002
479 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100
480 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200
482 /* Mac arbiter registers */
483 #define SK_MINIT_RX1 0x01B0
484 #define SK_MINIT_RX2 0x01B1
485 #define SK_MINIT_TX1 0x01B2
486 #define SK_MINIT_TX2 0x01B3
487 #define SK_MTIMEO_RX1 0x01B4
488 #define SK_MTIMEO_RX2 0x01B5
489 #define SK_MTIMEO_TX1 0x01B6
490 #define SK_MTIEMO_TX2 0x01B7
491 #define SK_MACARB_CTL 0x01B8
492 #define SK_MTIMER_TST 0x01BA
493 #define SK_RCINIT_RX1 0x01C0
494 #define SK_RCINIT_RX2 0x01C1
495 #define SK_RCINIT_TX1 0x01C2
496 #define SK_RCINIT_TX2 0x01C3
497 #define SK_RCTIMEO_RX1 0x01C4
498 #define SK_RCTIMEO_RX2 0x01C5
499 #define SK_RCTIMEO_TX1 0x01C6
500 #define SK_RCTIMEO_TX2 0x01C7
501 #define SK_RECOVERY_CTL 0x01C8
502 #define SK_RCTIMER_TST 0x01CA
504 /* Packet arbiter registers */
505 #define SK_RXPA1_TINIT 0x01D0
506 #define SK_RXPA2_TINIT 0x01D4
507 #define SK_TXPA1_TINIT 0x01D8
508 #define SK_TXPA2_TINIT 0x01DC
509 #define SK_RXPA1_TIMEO 0x01E0
510 #define SK_RXPA2_TIMEO 0x01E4
511 #define SK_TXPA1_TIMEO 0x01E8
512 #define SK_TXPA2_TIMEO 0x01EC
513 #define SK_PKTARB_CTL 0x01F0
514 #define SK_PKTATB_TST 0x01F2
516 #define SK_PKTARB_TIMEOUT 0x2000
518 #define SK_PKTARBCTL_RESET 0x0001
519 #define SK_PKTARBCTL_UNRESET 0x0002
520 #define SK_PKTARBCTL_RXTO1_OFF 0x0004
521 #define SK_PKTARBCTL_RXTO1_ON 0x0008
522 #define SK_PKTARBCTL_RXTO2_OFF 0x0010
523 #define SK_PKTARBCTL_RXTO2_ON 0x0020
524 #define SK_PKTARBCTL_TXTO1_OFF 0x0040
525 #define SK_PKTARBCTL_TXTO1_ON 0x0080
526 #define SK_PKTARBCTL_TXTO2_OFF 0x0100
527 #define SK_PKTARBCTL_TXTO2_ON 0x0200
528 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400
529 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800
530 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000
531 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000
533 #define SK_MINIT_XMAC_B2 54
534 #define SK_MINIT_XMAC_C1 63
536 #define SK_MACARBCTL_RESET 0x0001
537 #define SK_MACARBCTL_UNRESET 0x0002
538 #define SK_MACARBCTL_FASTOE_OFF 0x0004
539 #define SK_MACARBCRL_FASTOE_ON 0x0008
541 #define SK_RCINIT_XMAC_B2 54
542 #define SK_RCINIT_XMAC_C1 0
544 #define SK_RECOVERYCTL_RX1_OFF 0x0001
545 #define SK_RECOVERYCTL_RX1_ON 0x0002
546 #define SK_RECOVERYCTL_RX2_OFF 0x0004
547 #define SK_RECOVERYCTL_RX2_ON 0x0008
548 #define SK_RECOVERYCTL_TX1_OFF 0x0010
549 #define SK_RECOVERYCTL_TX1_ON 0x0020
550 #define SK_RECOVERYCTL_TX2_OFF 0x0040
551 #define SK_RECOVERYCTL_TX2_ON 0x0080
553 #define SK_RECOVERY_XMAC_B2 \
554 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \
555 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON)
557 #define SK_RECOVERY_XMAC_C1 \
558 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \
559 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF)
561 /* Block 4 -- TX Arbiter MAC 1 */
562 #define SK_TXAR1_TIMERINIT 0x0200
563 #define SK_TXAR1_TIMERVAL 0x0204
564 #define SK_TXAR1_LIMITINIT 0x0208
565 #define SK_TXAR1_LIMITCNT 0x020C
566 #define SK_TXAR1_COUNTERCTL 0x0210
567 #define SK_TXAR1_COUNTERTST 0x0212
568 #define SK_TXAR1_COUNTERSTS 0x0212
570 /* Block 5 -- TX Arbiter MAC 2 */
571 #define SK_TXAR2_TIMERINIT 0x0280
572 #define SK_TXAR2_TIMERVAL 0x0284
573 #define SK_TXAR2_LIMITINIT 0x0288
574 #define SK_TXAR2_LIMITCNT 0x028C
575 #define SK_TXAR2_COUNTERCTL 0x0290
576 #define SK_TXAR2_COUNTERTST 0x0291
577 #define SK_TXAR2_COUNTERSTS 0x0292
579 #define SK_TXARCTL_OFF 0x01
580 #define SK_TXARCTL_ON 0x02
581 #define SK_TXARCTL_RATECTL_OFF 0x04
582 #define SK_TXARCTL_RATECTL_ON 0x08
583 #define SK_TXARCTL_ALLOC_OFF 0x10
584 #define SK_TXARCTL_ALLOC_ON 0x20
585 #define SK_TXARCTL_FSYNC_OFF 0x40
586 #define SK_TXARCTL_FSYNC_ON 0x80
588 /* Block 6 -- External registers */
589 #define SK_EXTREG_BASE 0x300
590 #define SK_EXTREG_END 0x37C
592 /* Block 7 -- PCI config registers */
593 #define SK_PCI_BASE 0x0380
594 #define SK_PCI_END 0x03FC
596 /* Compute offset of mirrored PCI register */
597 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE)
599 /* Block 8 -- RX queue 1 */
600 #define SK_RXQ1_BUFCNT 0x0400
601 #define SK_RXQ1_BUFCTL 0x0402
602 #define SK_RXQ1_NEXTDESC 0x0404
603 #define SK_RXQ1_RXBUF_LO 0x0408
604 #define SK_RXQ1_RXBUF_HI 0x040C
605 #define SK_RXQ1_RXSTAT 0x0410
606 #define SK_RXQ1_TIMESTAMP 0x0414
607 #define SK_RXQ1_CSUM1 0x0418
608 #define SK_RXQ1_CSUM2 0x041A
609 #define SK_RXQ1_CSUM1_START 0x041C
610 #define SK_RXQ1_CSUM2_START 0x041E
611 #define SK_RXQ1_CURADDR_LO 0x0420
612 #define SK_RXQ1_CURADDR_HI 0x0424
613 #define SK_RXQ1_CURCNT_LO 0x0428
614 #define SK_RXQ1_CURCNT_HI 0x042C
615 #define SK_RXQ1_CURBYTES 0x0430
616 #define SK_RXQ1_BMU_CSR 0x0434
617 #define SK_RXQ1_WATERMARK 0x0438
618 #define SK_RXQ1_FLAG 0x043A
619 #define SK_RXQ1_TEST1 0x043C
620 #define SK_RXQ1_TEST2 0x0440
621 #define SK_RXQ1_TEST3 0x0444
623 /* Block 9 -- RX queue 2 */
624 #define SK_RXQ2_BUFCNT 0x0480
625 #define SK_RXQ2_BUFCTL 0x0482
626 #define SK_RXQ2_NEXTDESC 0x0484
627 #define SK_RXQ2_RXBUF_LO 0x0488
628 #define SK_RXQ2_RXBUF_HI 0x048C
629 #define SK_RXQ2_RXSTAT 0x0490
630 #define SK_RXQ2_TIMESTAMP 0x0494
631 #define SK_RXQ2_CSUM1 0x0498
632 #define SK_RXQ2_CSUM2 0x049A
633 #define SK_RXQ2_CSUM1_START 0x049C
634 #define SK_RXQ2_CSUM2_START 0x049E
635 #define SK_RXQ2_CURADDR_LO 0x04A0
636 #define SK_RXQ2_CURADDR_HI 0x04A4
637 #define SK_RXQ2_CURCNT_LO 0x04A8
638 #define SK_RXQ2_CURCNT_HI 0x04AC
639 #define SK_RXQ2_CURBYTES 0x04B0
640 #define SK_RXQ2_BMU_CSR 0x04B4
641 #define SK_RXQ2_WATERMARK 0x04B8
642 #define SK_RXQ2_FLAG 0x04BA
643 #define SK_RXQ2_TEST1 0x04BC
644 #define SK_RXQ2_TEST2 0x04C0
645 #define SK_RXQ2_TEST3 0x04C4
647 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001
648 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002
649 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004
650 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008
651 #define SK_RXBMU_RX_START 0x00000010
652 #define SK_RXBMU_RX_STOP 0x00000020
653 #define SK_RXBMU_POLL_OFF 0x00000040
654 #define SK_RXBMU_POLL_ON 0x00000080
655 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100
656 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200
657 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400
658 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800
659 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000
660 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000
661 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000
662 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000
663 #define SK_RXBMU_PFI_SM_RESET 0x00010000
664 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000
665 #define SK_RXBMU_FIFO_RESET 0x00040000
666 #define SK_RXBMU_FIFO_UNRESET 0x00080000
667 #define SK_RXBMU_DESC_RESET 0x00100000
668 #define SK_RXBMU_DESC_UNRESET 0x00200000
669 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000
671 #define SK_RXBMU_ONLINE \
672 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \
673 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \
674 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \
675 SK_RXBMU_DESC_UNRESET)
677 #define SK_RXBMU_OFFLINE \
678 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \
679 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \
680 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \
683 /* Block 12 -- TX sync queue 1 */
684 #define SK_TXQS1_BUFCNT 0x0600
685 #define SK_TXQS1_BUFCTL 0x0602
686 #define SK_TXQS1_NEXTDESC 0x0604
687 #define SK_TXQS1_RXBUF_LO 0x0608
688 #define SK_TXQS1_RXBUF_HI 0x060C
689 #define SK_TXQS1_RXSTAT 0x0610
690 #define SK_TXQS1_CSUM_STARTVAL 0x0614
691 #define SK_TXQS1_CSUM_STARTPOS 0x0618
692 #define SK_TXQS1_CSUM_WRITEPOS 0x061A
693 #define SK_TXQS1_CURADDR_LO 0x0620
694 #define SK_TXQS1_CURADDR_HI 0x0624
695 #define SK_TXQS1_CURCNT_LO 0x0628
696 #define SK_TXQS1_CURCNT_HI 0x062C
697 #define SK_TXQS1_CURBYTES 0x0630
698 #define SK_TXQS1_BMU_CSR 0x0634
699 #define SK_TXQS1_WATERMARK 0x0638
700 #define SK_TXQS1_FLAG 0x063A
701 #define SK_TXQS1_TEST1 0x063C
702 #define SK_TXQS1_TEST2 0x0640
703 #define SK_TXQS1_TEST3 0x0644
705 /* Block 13 -- TX async queue 1 */
706 #define SK_TXQA1_BUFCNT 0x0680
707 #define SK_TXQA1_BUFCTL 0x0682
708 #define SK_TXQA1_NEXTDESC 0x0684
709 #define SK_TXQA1_RXBUF_LO 0x0688
710 #define SK_TXQA1_RXBUF_HI 0x068C
711 #define SK_TXQA1_RXSTAT 0x0690
712 #define SK_TXQA1_CSUM_STARTVAL 0x0694
713 #define SK_TXQA1_CSUM_STARTPOS 0x0698
714 #define SK_TXQA1_CSUM_WRITEPOS 0x069A
715 #define SK_TXQA1_CURADDR_LO 0x06A0
716 #define SK_TXQA1_CURADDR_HI 0x06A4
717 #define SK_TXQA1_CURCNT_LO 0x06A8
718 #define SK_TXQA1_CURCNT_HI 0x06AC
719 #define SK_TXQA1_CURBYTES 0x06B0
720 #define SK_TXQA1_BMU_CSR 0x06B4
721 #define SK_TXQA1_WATERMARK 0x06B8
722 #define SK_TXQA1_FLAG 0x06BA
723 #define SK_TXQA1_TEST1 0x06BC
724 #define SK_TXQA1_TEST2 0x06C0
725 #define SK_TXQA1_TEST3 0x06C4
727 /* Block 14 -- TX sync queue 2 */
728 #define SK_TXQS2_BUFCNT 0x0700
729 #define SK_TXQS2_BUFCTL 0x0702
730 #define SK_TXQS2_NEXTDESC 0x0704
731 #define SK_TXQS2_RXBUF_LO 0x0708
732 #define SK_TXQS2_RXBUF_HI 0x070C
733 #define SK_TXQS2_RXSTAT 0x0710
734 #define SK_TXQS2_CSUM_STARTVAL 0x0714
735 #define SK_TXQS2_CSUM_STARTPOS 0x0718
736 #define SK_TXQS2_CSUM_WRITEPOS 0x071A
737 #define SK_TXQS2_CURADDR_LO 0x0720
738 #define SK_TXQS2_CURADDR_HI 0x0724
739 #define SK_TXQS2_CURCNT_LO 0x0728
740 #define SK_TXQS2_CURCNT_HI 0x072C
741 #define SK_TXQS2_CURBYTES 0x0730
742 #define SK_TXQS2_BMU_CSR 0x0734
743 #define SK_TXQS2_WATERMARK 0x0738
744 #define SK_TXQS2_FLAG 0x073A
745 #define SK_TXQS2_TEST1 0x073C
746 #define SK_TXQS2_TEST2 0x0740
747 #define SK_TXQS2_TEST3 0x0744
749 /* Block 15 -- TX async queue 2 */
750 #define SK_TXQA2_BUFCNT 0x0780
751 #define SK_TXQA2_BUFCTL 0x0782
752 #define SK_TXQA2_NEXTDESC 0x0784
753 #define SK_TXQA2_RXBUF_LO 0x0788
754 #define SK_TXQA2_RXBUF_HI 0x078C
755 #define SK_TXQA2_RXSTAT 0x0790
756 #define SK_TXQA2_CSUM_STARTVAL 0x0794
757 #define SK_TXQA2_CSUM_STARTPOS 0x0798
758 #define SK_TXQA2_CSUM_WRITEPOS 0x079A
759 #define SK_TXQA2_CURADDR_LO 0x07A0
760 #define SK_TXQA2_CURADDR_HI 0x07A4
761 #define SK_TXQA2_CURCNT_LO 0x07A8
762 #define SK_TXQA2_CURCNT_HI 0x07AC
763 #define SK_TXQA2_CURBYTES 0x07B0
764 #define SK_TXQA2_BMU_CSR 0x07B4
765 #define SK_TXQA2_WATERMARK 0x07B8
766 #define SK_TXQA2_FLAG 0x07BA
767 #define SK_TXQA2_TEST1 0x07BC
768 #define SK_TXQA2_TEST2 0x07C0
769 #define SK_TXQA2_TEST3 0x07C4
771 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001
772 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002
773 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004
774 #define SK_TXBMU_TX_START 0x00000010
775 #define SK_TXBMU_TX_STOP 0x00000020
776 #define SK_TXBMU_POLL_OFF 0x00000040
777 #define SK_TXBMU_POLL_ON 0x00000080
778 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100
779 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200
780 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400
781 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800
782 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000
783 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000
784 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000
785 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000
786 #define SK_TXBMU_PFI_SM_RESET 0x00010000
787 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000
788 #define SK_TXBMU_FIFO_RESET 0x00040000
789 #define SK_TXBMU_FIFO_UNRESET 0x00080000
790 #define SK_TXBMU_DESC_RESET 0x00100000
791 #define SK_TXBMU_DESC_UNRESET 0x00200000
792 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000
794 #define SK_TXBMU_ONLINE \
795 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \
796 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \
797 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \
798 SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON)
800 #define SK_TXBMU_OFFLINE \
801 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \
802 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \
803 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \
804 SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF)
806 /* Block 16 -- Receive RAMbuffer 1 */
807 #define SK_RXRB1_START 0x0800
808 #define SK_RXRB1_END 0x0804
809 #define SK_RXRB1_WR_PTR 0x0808
810 #define SK_RXRB1_RD_PTR 0x080C
811 #define SK_RXRB1_UTHR_PAUSE 0x0810
812 #define SK_RXRB1_LTHR_PAUSE 0x0814
813 #define SK_RXRB1_UTHR_HIPRIO 0x0818
814 #define SK_RXRB1_UTHR_LOPRIO 0x081C
815 #define SK_RXRB1_PKTCNT 0x0820
816 #define SK_RXRB1_LVL 0x0824
817 #define SK_RXRB1_CTLTST 0x0828
819 /* Block 17 -- Receive RAMbuffer 2 */
820 #define SK_RXRB2_START 0x0880
821 #define SK_RXRB2_END 0x0884
822 #define SK_RXRB2_WR_PTR 0x0888
823 #define SK_RXRB2_RD_PTR 0x088C
824 #define SK_RXRB2_UTHR_PAUSE 0x0890
825 #define SK_RXRB2_LTHR_PAUSE 0x0894
826 #define SK_RXRB2_UTHR_HIPRIO 0x0898
827 #define SK_RXRB2_UTHR_LOPRIO 0x089C
828 #define SK_RXRB2_PKTCNT 0x08A0
829 #define SK_RXRB2_LVL 0x08A4
830 #define SK_RXRB2_CTLTST 0x08A8
832 /* Block 20 -- Sync. Transmit RAMbuffer 1 */
833 #define SK_TXRBS1_START 0x0A00
834 #define SK_TXRBS1_END 0x0A04
835 #define SK_TXRBS1_WR_PTR 0x0A08
836 #define SK_TXRBS1_RD_PTR 0x0A0C
837 #define SK_TXRBS1_PKTCNT 0x0A20
838 #define SK_TXRBS1_LVL 0x0A24
839 #define SK_TXRBS1_CTLTST 0x0A28
841 /* Block 21 -- Async. Transmit RAMbuffer 1 */
842 #define SK_TXRBA1_START 0x0A80
843 #define SK_TXRBA1_END 0x0A84
844 #define SK_TXRBA1_WR_PTR 0x0A88
845 #define SK_TXRBA1_RD_PTR 0x0A8C
846 #define SK_TXRBA1_PKTCNT 0x0AA0
847 #define SK_TXRBA1_LVL 0x0AA4
848 #define SK_TXRBA1_CTLTST 0x0AA8
850 /* Block 22 -- Sync. Transmit RAMbuffer 2 */
851 #define SK_TXRBS2_START 0x0B00
852 #define SK_TXRBS2_END 0x0B04
853 #define SK_TXRBS2_WR_PTR 0x0B08
854 #define SK_TXRBS2_RD_PTR 0x0B0C
855 #define SK_TXRBS2_PKTCNT 0x0B20
856 #define SK_TXRBS2_LVL 0x0B24
857 #define SK_TXRBS2_CTLTST 0x0B28
859 /* Block 23 -- Async. Transmit RAMbuffer 2 */
860 #define SK_TXRBA2_START 0x0B80
861 #define SK_TXRBA2_END 0x0B84
862 #define SK_TXRBA2_WR_PTR 0x0B88
863 #define SK_TXRBA2_RD_PTR 0x0B8C
864 #define SK_TXRBA2_PKTCNT 0x0BA0
865 #define SK_TXRBA2_LVL 0x0BA4
866 #define SK_TXRBA2_CTLTST 0x0BA8
868 #define SK_RBCTL_RESET 0x00000001
869 #define SK_RBCTL_UNRESET 0x00000002
870 #define SK_RBCTL_OFF 0x00000004
871 #define SK_RBCTL_ON 0x00000008
872 #define SK_RBCTL_STORENFWD_OFF 0x00000010
873 #define SK_RBCTL_STORENFWD_ON 0x00000020
875 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */
876 #define SK_RXF1_END 0x0C00
877 #define SK_RXF1_WPTR 0x0C04
878 #define SK_RXF1_RPTR 0x0C0C
879 #define SK_RXF1_PKTCNT 0x0C10
880 #define SK_RXF1_LVL 0x0C14
881 #define SK_RXF1_MACCTL 0x0C18
882 #define SK_RXF1_CTL 0x0C1C
883 #define SK_RXLED1_CNTINIT 0x0C20
884 #define SK_RXLED1_COUNTER 0x0C24
885 #define SK_RXLED1_CTL 0x0C28
886 #define SK_RXLED1_TST 0x0C29
887 #define SK_LINK_SYNC1_CINIT 0x0C30
888 #define SK_LINK_SYNC1_COUNTER 0x0C34
889 #define SK_LINK_SYNC1_CTL 0x0C38
890 #define SK_LINK_SYNC1_TST 0x0C39
891 #define SK_LINKLED1_CTL 0x0C3C
893 #define SK_FIFO_END 0x3F
895 /* Receive MAC FIFO 1 (Yukon Only) */
896 #define SK_RXMF1_END 0x0C40
897 #define SK_RXMF1_THRESHOLD 0x0C44
898 #define SK_RXMF1_CTRL_TEST 0x0C48
899 #define SK_RXMF1_FLUSH_MASK 0x0C4C
900 #define SK_RXMF1_FLUSH_THRESHOLD 0x0C50
901 #define SK_RXMF1_WRITE_PTR 0x0C60
902 #define SK_RXMF1_WRITE_LEVEL 0x0C68
903 #define SK_RXMF1_READ_PTR 0x0C70
904 #define SK_RXMF1_READ_LEVEL 0x0C78
906 /* Receive MAC FIFO 1 Control/Test */
907 #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
908 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
909 #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
910 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */
911 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */
912 #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */
913 #define SK_RFCTL_FIFO_FLUSH_OFF 0x00000080 /* RX FIFO Flsuh mode off */
914 #define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */
915 #define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */
916 #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */
917 #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */
918 #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */
919 #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */
920 #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */
922 #define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */
924 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
925 #define SK_RXF2_END 0x0C80
926 #define SK_RXF2_WPTR 0x0C84
927 #define SK_RXF2_RPTR 0x0C8C
928 #define SK_RXF2_PKTCNT 0x0C90
929 #define SK_RXF2_LVL 0x0C94
930 #define SK_RXF2_MACCTL 0x0C98
931 #define SK_RXF2_CTL 0x0C9C
932 #define SK_RXLED2_CNTINIT 0x0CA0
933 #define SK_RXLED2_COUNTER 0x0CA4
934 #define SK_RXLED2_CTL 0x0CA8
935 #define SK_RXLED2_TST 0x0CA9
936 #define SK_LINK_SYNC2_CINIT 0x0CB0
937 #define SK_LINK_SYNC2_COUNTER 0x0CB4
938 #define SK_LINK_SYNC2_CTL 0x0CB8
939 #define SK_LINK_SYNC2_TST 0x0CB9
940 #define SK_LINKLED2_CTL 0x0CBC
942 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001
943 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002
944 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004
945 #define SK_RXMACCTL_RSTAMP_ON 0x00000008
946 #define SK_RXMACCTL_FLUSH_OFF 0x00000010
947 #define SK_RXMACCTL_FLUSH_ON 0x00000020
948 #define SK_RXMACCTL_PAUSE_OFF 0x00000040
949 #define SK_RXMACCTL_PAUSE_ON 0x00000080
950 #define SK_RXMACCTL_AFULL_OFF 0x00000100
951 #define SK_RXMACCTL_AFULL_ON 0x00000200
952 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400
953 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800
954 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000
955 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000
956 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000
957 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000
959 #define SK_RXLEDCTL_ENABLE 0x0001
960 #define SK_RXLEDCTL_COUNTER_STOP 0x0002
961 #define SK_RXLEDCTL_COUNTER_START 0x0004
963 #define SK_LINKLED_OFF 0x0001
964 #define SK_LINKLED_ON 0x0002
965 #define SK_LINKLED_LINKSYNC_OFF 0x0004
966 #define SK_LINKLED_LINKSYNC_ON 0x0008
967 #define SK_LINKLED_BLINK_OFF 0x0010
968 #define SK_LINKLED_BLINK_ON 0x0020
970 /* Block 26 -- TX MAC FIFO 1 regisrers */
971 #define SK_TXF1_END 0x0D00
972 #define SK_TXF1_WPTR 0x0D04
973 #define SK_TXF1_RPTR 0x0D0C
974 #define SK_TXF1_PKTCNT 0x0D10
975 #define SK_TXF1_LVL 0x0D14
976 #define SK_TXF1_MACCTL 0x0D18
977 #define SK_TXF1_CTL 0x0D1C
978 #define SK_TXLED1_CNTINIT 0x0D20
979 #define SK_TXLED1_COUNTER 0x0D24
980 #define SK_TXLED1_CTL 0x0D28
981 #define SK_TXLED1_TST 0x0D29
983 /* Transmit MAC FIFO 1 (Yukon Only) */
984 #define SK_TXMF1_END 0x0D40
985 #define SK_TXMF1_THRESHOLD 0x0D44
986 #define SK_TXMF1_CTRL_TEST 0x0D48
987 #define SK_TXMF1_WRITE_PTR 0x0D60
988 #define SK_TXMF1_WRITE_SHADOW 0x0D64
989 #define SK_TXMF1_WRITE_LEVEL 0x0D68
990 #define SK_TXMF1_READ_PTR 0x0D70
991 #define SK_TXMF1_RESTART_PTR 0x0D74
992 #define SK_TXMF1_READ_LEVEL 0x0D78
994 /* Transmit MAC FIFO Control/Test */
995 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
996 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
997 #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
998 #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */
999 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */
1000 #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */
1001 #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */
1002 #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */
1003 #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */
1004 #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */
1005 #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */
1006 #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */
1007 #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */
1009 /* Block 27 -- TX MAC FIFO 2 regisrers */
1010 #define SK_TXF2_END 0x0D80
1011 #define SK_TXF2_WPTR 0x0D84
1012 #define SK_TXF2_RPTR 0x0D8C
1013 #define SK_TXF2_PKTCNT 0x0D90
1014 #define SK_TXF2_LVL 0x0D94
1015 #define SK_TXF2_MACCTL 0x0D98
1016 #define SK_TXF2_CTL 0x0D9C
1017 #define SK_TXLED2_CNTINIT 0x0DA0
1018 #define SK_TXLED2_COUNTER 0x0DA4
1019 #define SK_TXLED2_CTL 0x0DA8
1020 #define SK_TXLED2_TST 0x0DA9
1022 #define SK_TXMACCTL_XMAC_RESET 0x00000001
1023 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002
1024 #define SK_TXMACCTL_LOOP_OFF 0x00000004
1025 #define SK_TXMACCTL_LOOP_ON 0x00000008
1026 #define SK_TXMACCTL_FLUSH_OFF 0x00000010
1027 #define SK_TXMACCTL_FLUSH_ON 0x00000020
1028 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040
1029 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080
1030 #define SK_TXMACCTL_AFULL_OFF 0x00000100
1031 #define SK_TXMACCTL_AFULL_ON 0x00000200
1032 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400
1033 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800
1034 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000
1035 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000
1036 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000
1037 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000
1039 #define SK_TXLEDCTL_ENABLE 0x0001
1040 #define SK_TXLEDCTL_COUNTER_STOP 0x0002
1041 #define SK_TXLEDCTL_COUNTER_START 0x0004
1043 #define SK_FIFO_RESET 0x00000001
1044 #define SK_FIFO_UNRESET 0x00000002
1045 #define SK_FIFO_OFF 0x00000004
1046 #define SK_FIFO_ON 0x00000008
1048 /* Block 28 -- Descriptor Poll Timer */
1049 #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */
1050 #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */
1052 #define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */
1054 #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */
1055 #define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */
1056 #define SK_DPT_TCTL_START 0x0002 /* Start Timer */
1058 #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */
1059 #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */
1060 #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */
1061 #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */
1063 /* Block 29 -- reserved */
1065 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/
1066 #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */
1067 #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */
1068 #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */
1069 #define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */
1070 #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */
1071 #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */
1072 #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */
1073 #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */
1074 #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */
1075 #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */
1076 #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */
1077 #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */
1078 #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */
1079 #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */
1080 #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */
1081 #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */
1082 #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */
1083 #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */
1084 #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */
1085 #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */
1086 #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */
1087 #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */
1088 #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */
1089 #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */
1090 #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */
1091 #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */
1092 #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */
1093 #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */
1094 #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */
1096 #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */
1097 #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */
1098 #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */
1099 #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */
1100 #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */
1101 #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */
1103 #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */
1104 #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */
1105 #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */
1106 #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */
1107 #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */
1108 #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */
1109 #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */
1110 #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */
1111 #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */
1112 #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */
1113 #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */
1114 #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */
1115 #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */
1116 #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */
1117 #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */
1118 #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */
1119 #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */
1120 #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */
1121 #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */
1122 #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */
1123 #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */
1124 #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */
1125 #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */
1127 #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
1128 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 )
1129 #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
1131 #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \
1132 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 )
1134 #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */
1135 #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */
1136 #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */
1137 #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */
1138 #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */
1139 #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */
1141 #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */
1142 #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */
1144 /* Block 31 -- reserved */
1146 /* Block 32-33 -- Pattern Ram */
1147 #define SK_WOL_PRAM 0x1000
1149 /* Block 0x22 - 0x3f -- reserved */
1151 /* Block 0x40 to 0x4F -- XMAC 1 registers */
1152 #define SK_XMAC1_BASE 0x2000
1154 /* Block 0x50 to 0x5F -- MARV 1 registers */
1155 #define SK_MARV1_BASE 0x2800
1157 /* Block 0x60 to 0x6F -- XMAC 2 registers */
1158 #define SK_XMAC2_BASE 0x3000
1160 /* Block 0x70 to 0x7F -- MARV 2 registers */
1161 #define SK_MARV2_BASE 0x3800
1163 /* Compute relative offset of an XMAC register in the XMAC window(s). */
1164 #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \
1165 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE)))
1168 #define SK_XM_READ_4(sc, reg) \
1169 ((sk_win_read_2(sc->sk_softc, \
1170 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \
1171 ((sk_win_read_2(sc->sk_softc, \
1172 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16))
1174 #define SK_XM_WRITE_4(sc, reg, val) \
1175 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \
1176 ((val) & 0xFFFF)); \
1177 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \
1178 ((val) >> 16) & 0xFFFF)
1180 #define SK_XM_READ_4(sc, reg) \
1181 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg))
1183 #define SK_XM_WRITE_4(sc, reg, val) \
1184 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))
1187 #define SK_XM_READ_2(sc, reg) \
1188 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg))
1190 #define SK_XM_WRITE_2(sc, reg, val) \
1191 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)
1193 #define SK_XM_SETBIT_4(sc, reg, x) \
1194 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))
1196 #define SK_XM_CLRBIT_4(sc, reg, x) \
1197 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))
1199 #define SK_XM_SETBIT_2(sc, reg, x) \
1200 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))
1202 #define SK_XM_CLRBIT_2(sc, reg, x) \
1203 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))
1205 /* Compute relative offset of an MARV register in the MARV window(s). */
1206 #define SK_YU_REG(sc, reg) \
1207 ((reg) + SK_MARV1_BASE + \
1208 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE)))
1210 #define SK_YU_READ_4(sc, reg) \
1211 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg)))
1213 #define SK_YU_READ_2(sc, reg) \
1214 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg)))
1216 #define SK_YU_WRITE_4(sc, reg, val) \
1217 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
1219 #define SK_YU_WRITE_2(sc, reg, val) \
1220 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
1222 #define SK_YU_SETBIT_4(sc, reg, x) \
1223 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x))
1225 #define SK_YU_CLRBIT_4(sc, reg, x) \
1226 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x))
1228 #define SK_YU_SETBIT_2(sc, reg, x) \
1229 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x))
1231 #define SK_YU_CLRBIT_2(sc, reg, x) \
1232 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x))
1235 * The default FIFO threshold on the XMAC II is 4 bytes. On
1236 * dual port NICs, this often leads to transmit underruns, so we
1237 * bump the threshold a little.
1239 #define SK_XM_TX_FIFOTHRESH 512
1241 #define SK_PCI_VENDOR_ID 0x0000
1242 #define SK_PCI_DEVICE_ID 0x0002
1243 #define SK_PCI_COMMAND 0x0004
1244 #define SK_PCI_STATUS 0x0006
1245 #define SK_PCI_REVID 0x0008
1246 #define SK_PCI_CLASSCODE 0x0009
1247 #define SK_PCI_CACHELEN 0x000C
1248 #define SK_PCI_LATENCY_TIMER 0x000D
1249 #define SK_PCI_HEADER_TYPE 0x000E
1250 #define SK_PCI_LOMEM 0x0010
1251 #define SK_PCI_LOIO 0x0014
1252 #define SK_PCI_SUBVEN_ID 0x002C
1253 #define SK_PCI_SYBSYS_ID 0x002E
1254 #define SK_PCI_BIOSROM 0x0030
1255 #define SK_PCI_INTLINE 0x003C
1256 #define SK_PCI_INTPIN 0x003D
1257 #define SK_PCI_MINGNT 0x003E
1258 #define SK_PCI_MINLAT 0x003F
1260 /* device specific PCI registers */
1261 #define SK_PCI_OURREG1 0x0040
1262 #define SK_PCI_OURREG2 0x0044
1263 #define SK_PCI_CAPID 0x0048 /* 8 bits */
1264 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */
1265 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */
1266 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */
1267 #define SK_PCI_PME_EVENT 0x004F
1269 #define SK_PSTATE_MASK 0x0003
1270 #define SK_PSTATE_D0 0x0000
1271 #define SK_PSTATE_D1 0x0001
1272 #define SK_PSTATE_D2 0x0002
1273 #define SK_PSTATE_D3 0x0003
1274 #define SK_PME_EN 0x0010
1275 #define SK_PME_STATUS 0x8000
1277 #define CSR_WRITE_4(sc, reg, val) \
1278 bus_write_4((sc)->sk_res[0], (reg), (val))
1279 #define CSR_WRITE_2(sc, reg, val) \
1280 bus_write_2((sc)->sk_res[0], (reg), (val))
1281 #define CSR_WRITE_1(sc, reg, val) \
1282 bus_write_1((sc)->sk_res[0], (reg), (val))
1284 #define CSR_READ_4(sc, reg) \
1285 bus_read_4((sc)->sk_res[0], (reg))
1286 #define CSR_READ_2(sc, reg) \
1287 bus_read_2((sc)->sk_res[0], (reg))
1288 #define CSR_READ_1(sc, reg) \
1289 bus_read_1((sc)->sk_res[0], (reg))
1294 const char *sk_name;
1297 #define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff)
1298 #define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32)
1300 #define SK_RING_ALIGN 64
1302 /* RX queue descriptor data structure */
1306 u_int32_t sk_data_lo;
1307 u_int32_t sk_data_hi;
1308 u_int32_t sk_xmac_rxstat;
1309 u_int32_t sk_timestamp;
1311 u_int32_t sk_csum_start;
1314 #define SK_OPCODE_DEFAULT 0x00550000
1315 #define SK_OPCODE_CSUM 0x00560000
1317 #define SK_RXCTL_LEN 0x0000FFFF
1318 #define SK_RXCTL_OPCODE 0x00FF0000
1319 #define SK_RXCTL_TSTAMP_VALID 0x01000000
1320 #define SK_RXCTL_STATUS_VALID 0x02000000
1321 #define SK_RXCTL_DEV0 0x04000000
1322 #define SK_RXCTL_EOF_INTR 0x08000000
1323 #define SK_RXCTL_EOB_INTR 0x10000000
1324 #define SK_RXCTL_LASTFRAG 0x20000000
1325 #define SK_RXCTL_FIRSTFRAG 0x40000000
1326 #define SK_RXCTL_OWN 0x80000000
1329 (SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG|SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
1334 u_int32_t sk_data_lo;
1335 u_int32_t sk_data_hi;
1336 u_int32_t sk_xmac_txstat;
1337 u_int32_t sk_csum_startval;
1338 u_int32_t sk_csum_start;
1342 #define SK_TXCTL_LEN 0x0000FFFF
1343 #define SK_TXCTL_OPCODE 0x00FF0000
1344 #define SK_TXCTL_SW 0x01000000
1345 #define SK_TXCTL_NOCRC 0x02000000
1346 #define SK_TXCTL_STORENFWD 0x04000000
1347 #define SK_TXCTL_EOF_INTR 0x08000000
1348 #define SK_TXCTL_EOB_INTR 0x10000000
1349 #define SK_TXCTL_LASTFRAG 0x20000000
1350 #define SK_TXCTL_FIRSTFRAG 0x40000000
1351 #define SK_TXCTL_OWN 0x80000000
1354 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN)
1356 #define SK_RXBYTES(x) ((x) & 0x0000FFFF)
1357 #define SK_TXBYTES SK_RXBYTES
1359 #define SK_TX_RING_CNT 512
1360 #define SK_RX_RING_CNT 256
1361 #define SK_JUMBO_RX_RING_CNT 256
1362 #define SK_MAXTXSEGS 32
1364 #define SK_JUMBO_FRAMELEN 9018
1365 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
1366 #define SK_MAX_FRAMELEN \
1367 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)
1368 #define SK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
1372 bus_dmamap_t tx_dmamap;
1373 STAILQ_ENTRY(sk_txdesc) tx_q;
1376 STAILQ_HEAD(sk_txdq, sk_txdesc);
1380 bus_dmamap_t rx_dmamap;
1383 struct sk_chain_data {
1384 bus_dma_tag_t sk_parent_tag;
1385 bus_dma_tag_t sk_tx_tag;
1386 struct sk_txdesc sk_txdesc[SK_TX_RING_CNT];
1387 struct sk_txdq sk_txfreeq;
1388 struct sk_txdq sk_txbusyq;
1389 bus_dma_tag_t sk_rx_tag;
1390 struct sk_rxdesc sk_rxdesc[SK_RX_RING_CNT];
1391 bus_dma_tag_t sk_tx_ring_tag;
1392 bus_dma_tag_t sk_rx_ring_tag;
1393 bus_dmamap_t sk_tx_ring_map;
1394 bus_dmamap_t sk_rx_ring_map;
1395 bus_dmamap_t sk_rx_sparemap;
1396 bus_dma_tag_t sk_jumbo_rx_tag;
1397 struct sk_rxdesc sk_jumbo_rxdesc[SK_JUMBO_RX_RING_CNT];
1398 bus_dma_tag_t sk_jumbo_rx_ring_tag;
1399 bus_dmamap_t sk_jumbo_rx_ring_map;
1400 bus_dmamap_t sk_jumbo_rx_sparemap;
1405 int sk_jumbo_rx_cons;
1408 struct sk_ring_data {
1409 struct sk_tx_desc *sk_tx_ring;
1410 bus_addr_t sk_tx_ring_paddr;
1411 struct sk_rx_desc *sk_rx_ring;
1412 bus_addr_t sk_rx_ring_paddr;
1413 struct sk_rx_desc *sk_jumbo_rx_ring;
1414 bus_addr_t sk_jumbo_rx_ring_paddr;
1417 #define SK_TX_RING_ADDR(sc, i) \
1418 ((sc)->sk_rdata.sk_tx_ring_paddr + sizeof(struct sk_tx_desc) * (i))
1419 #define SK_RX_RING_ADDR(sc, i) \
1420 ((sc)->sk_rdata.sk_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i))
1421 #define SK_JUMBO_RX_RING_ADDR(sc, i) \
1422 ((sc)->sk_rdata.sk_jumbo_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i))
1424 #define SK_TX_RING_SZ \
1425 (sizeof(struct sk_tx_desc) * SK_TX_RING_CNT)
1426 #define SK_RX_RING_SZ \
1427 (sizeof(struct sk_rx_desc) * SK_RX_RING_CNT)
1428 #define SK_JUMBO_RX_RING_SZ \
1429 (sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT)
1431 struct sk_bcom_hack {
1436 #define SK_INC(x, y) (x) = (x + 1) % y
1441 /* Softc for the GEnesis controller. */
1443 struct resource *sk_res[2]; /* I/O and IRQ resources */
1444 struct resource_spec *sk_res_spec;
1445 void *sk_intrhand; /* irq handler handle */
1450 u_int32_t sk_rboff; /* RAMbuffer offset */
1451 u_int32_t sk_ramsize; /* amount of RAM on NIC */
1452 u_int32_t sk_pmd; /* physical media type */
1453 u_int32_t sk_coppertype;
1454 u_int32_t sk_intrmask;
1458 struct sk_if_softc *sk_if[2];
1459 device_t sk_devs[2];
1460 struct mtx sk_mii_mtx;
1464 #define SK_LOCK(_sc) mtx_lock(&(_sc)->sk_mtx)
1465 #define SK_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_mtx)
1466 #define SK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sk_mtx, MA_OWNED)
1467 #define SK_IF_LOCK(_sc) SK_LOCK((_sc)->sk_softc)
1468 #define SK_IF_UNLOCK(_sc) SK_UNLOCK((_sc)->sk_softc)
1469 #define SK_IF_LOCK_ASSERT(_sc) SK_LOCK_ASSERT((_sc)->sk_softc)
1470 #define SK_IF_MII_LOCK(_sc) mtx_lock(&(_sc)->sk_softc->sk_mii_mtx)
1471 #define SK_IF_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_softc->sk_mii_mtx)
1473 /* Softc for each logical interface */
1474 struct sk_if_softc {
1475 struct ifnet *sk_ifp; /* interface info */
1478 u_int8_t sk_port; /* port # on controller */
1479 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */
1480 u_int32_t sk_rx_ramstart;
1481 u_int32_t sk_rx_ramend;
1482 u_int32_t sk_tx_ramstart;
1483 u_int32_t sk_tx_ramend;
1487 struct callout sk_tick_ch;
1488 struct callout sk_watchdog_ch;
1489 int sk_watchdog_timer;
1490 struct sk_chain_data sk_cdata;
1491 struct sk_ring_data sk_rdata;
1492 struct sk_softc *sk_softc; /* parent controller */
1493 int sk_tx_bmu; /* TX BMU register */
1495 int sk_jumbo_disable;
1498 #define SK_TIMEOUT 1000