sys/dev/smartpqi/smartpqi_defines.h

   1 /*-
   2  * Copyright 2016-2021 Microchip Technology, Inc. and/or its subsidiaries.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /* $FreeBSD$ */
  27
  28 #ifndef _PQI_DEFINES_H
  29 #define _PQI_DEFINES_H
  30
  31 #define PQI_STATUS_FAILURE              -1
  32 #define PQI_STATUS_TIMEOUT              -2
  33 #define PQI_STATUS_QFULL                -3
  34 #define PQI_STATUS_SUCCESS              0
  35
  36 /* Maximum timeout for internal command completion */
  37 #define TIMEOUT_INFINITE                ((uint32_t) (-1))
  38 #define PQISRC_CMD_TIMEOUT              TIMEOUT_INFINITE
  39 #define PQISRC_PASSTHROUGH_CMD_TIMEOUT  PQISRC_CMD_TIMEOUT
  40 /* Delay in milli seconds */
  41 #define PQISRC_TMF_TIMEOUT              (OS_TMF_TIMEOUT_SEC * 1000)
  42 /* Delay in micro seconds */
  43 #define PQISRC_PENDING_IO_TIMEOUT_USEC  30000000 /* 30 seconds */
  44
  45 /* If want to disable atomic operations on device active io, then set to zero */
  46 #define PQISRC_DEVICE_IO_COUNTER        1
  47
  48 #define INVALID_ELEM                    0xffff
  49 #ifndef MIN
  50 #define MIN(a,b)                        ((a) < (b) ? (a) : (b))
  51 #endif
  52
  53 #ifndef MAX
  54 #define MAX(a,b)                        ((a) > (b) ? (a) : (b))
  55 #endif
  56
  57 #define PQISRC_ROUNDUP(x, y)            (((x) + (y) - 1) / (y) * (y))
  58 #define PQISRC_DIV_ROUND_UP(x, y)       (((x) + (y) - 1) / (y))
  59
  60 #define ALIGN_BOUNDARY(a, n)    {       \
  61                 if (a % n)      \
  62                         a = a + (n - a % n);    \
  63         }
  64
  65 /* Busy wait timeout on a condition */
  66 #define COND_BUSYWAIT(cond, timeout /* in millisecond */) { \
  67                 if (!(cond)) { \
  68                         while (timeout) { \
  69                                 OS_BUSYWAIT(1000); \
  70                                 if (cond) \
  71                                         break; \
  72                                 timeout--; \
  73                         } \
  74                 } \
  75         }
  76
  77 /* Wait timeout on a condition*/
  78 #define COND_WAIT(cond, timeout /* in millisecond */) { \
  79                 if (!(cond)) { \
  80                         while (timeout) { \
  81                                 OS_SLEEP(1000); \
  82                                 if (cond) \
  83                                         break; \
  84                                 timeout--; \
  85                         } \
  86                 } \
  87         }
  88
  89 #define FILL_QUEUE_ARRAY_ADDR(q,virt,dma) {     \
  90                         q->array_virt_addr = virt;      \
  91                         q->array_dma_addr = dma;        \
  92                 }
  93
  94 #define true    1
  95 #define false   0
  96
  97 enum INTR_TYPE {
  98         LOCK_INTR,
  99         LOCK_SLEEP
 100 };
 101
 102 #define LOCKNAME_SIZE           32
 103
 104 #define INTR_TYPE_NONE          0x0
 105 #define INTR_TYPE_FIXED         0x1
 106 #define INTR_TYPE_MSI           0x2
 107 #define INTR_TYPE_MSIX          0x4
 108 #define SIS_ENABLE_MSIX         0x40
 109 #define SIS_ENABLE_INTX         0x80
 110 #define PQISRC_LEGACY_INTX_MASK 0x1
 111
 112 #define DMA_TO_VIRT(mem)        ((mem)->virt_addr)
 113 #define DMA_PHYS_LOW(mem)       (((mem)->dma_addr)  & 0x00000000ffffffff)
 114 #define DMA_PHYS_HIGH(mem)      ((((mem)->dma_addr) & 0xffffffff00000000) >> 32)
 115
 116
 117 typedef enum REQUEST_STATUS {
 118         REQUEST_SUCCESS = 0,
 119         REQUEST_PENDING = -1,
 120         REQUEST_FAILED = -2,
 121 }REQUEST_STATUS_T;
 122 typedef enum IO_PATH {
 123         AIO_PATH,
 124         RAID_PATH
 125 }IO_PATH_T;
 126
 127 typedef enum device_type
 128 {
 129         DISK_DEVICE,
 130         TAPE_DEVICE,
 131         ROM_DEVICE = 5,
 132         SES_DEVICE,
 133         CONTROLLER_DEVICE,
 134         MEDIUM_CHANGER_DEVICE,
 135         RAID_DEVICE = 0x0c,
 136         ENCLOSURE_DEVICE,
 137         ZBC_DEVICE = 0x14
 138 } device_type_t;
 139
 140 typedef enum controller_state {
 141         PQI_UP_RUNNING,
 142         PQI_BUS_RESET,
 143 }controller_state_t;
 144
 145
 146 #define PQISRC_MAX_MSIX_SUPPORTED               64
 147
 148 /* SIS Specific */
 149 #define PQISRC_INIT_STRUCT_REVISION             9
 150 #define PQISRC_SECTOR_SIZE                      512
 151 #define PQISRC_BLK_SIZE                         PQISRC_SECTOR_SIZE
 152 #define PQISRC_DEFAULT_DMA_ALIGN                4
 153 #define PQISRC_DMA_ALIGN_MASK                   (PQISRC_DEFAULT_DMA_ALIGN - 1)
 154 #define PQISRC_ERR_BUF_DMA_ALIGN                32
 155 #define PQISRC_ERR_BUF_ELEM_SIZE                MAX(sizeof(raid_path_error_info_elem_t),sizeof(aio_path_error_info_elem_t))
 156 #define PQISRC_INIT_STRUCT_DMA_ALIGN            16
 157
 158 #define SIS_CMD_GET_ADAPTER_PROPERTIES          0x19
 159 #define SIS_CMD_GET_COMM_PREFERRED_SETTINGS     0x26
 160 #define SIS_CMD_GET_PQI_CAPABILITIES            0x3000
 161 #define SIS_CMD_INIT_BASE_STRUCT_ADDRESS        0x1b
 162
 163 #define SIS_SUPPORT_EXT_OPT                     0x00800000
 164 #define SIS_SUPPORT_PQI                         0x00000004
 165 #define SIS_SUPPORT_PQI_RESET_QUIESCE           0x00000008
 166
 167 #define SIS_PQI_RESET_QUIESCE                   0x1000000
 168
 169 #define SIS_STATUS_OK_TIMEOUT                   120000  /* in milli sec, 5 sec */
 170
 171 #define SIS_CMD_COMPLETE_TIMEOUT                30000  /* in milli sec, 30 secs */
 172 #define SIS_POLL_START_WAIT_TIME                20000  /* in micro sec, 20 milli sec */
 173 #define SIS_DB_BIT_CLEAR_TIMEOUT_CNT            120000  /* 500usec * 120000 = 60 sec */
 174
 175 #define SIS_ENABLE_TIMEOUT                      3000
 176 #define REENABLE_SIS                            0x1
 177 #define TRIGGER_NMI_SIS                         0x800000
 178 /*SIS Register status defines */
 179
 180 #define PQI_CTRL_KERNEL_UP_AND_RUNNING          0x80
 181 #define PQI_CTRL_KERNEL_PANIC                   0x100
 182
 183 #define SIS_CTL_TO_HOST_DB_DISABLE_ALL          0xFFFFFFFF
 184 #define SIS_CTL_TO_HOST_DB_CLEAR                0x00001000
 185 #define SIS_CMD_SUBMIT                          0x00000200  /* Bit 9 */
 186 #define SIS_CMD_COMPLETE                        0x00001000  /* Bit 12 */
 187 #define SIS_CMD_STATUS_SUCCESS                  0x1
 188
 189 /* PQI specific */
 190
 191 /* defines */
 192 #define PQISRC_PQI_REG_OFFSET                           0x4000
 193 #define PQISRC_MAX_OUTSTANDING_REQ                      4096
 194 #define PQISRC_MAX_ADMIN_IB_QUEUE_ELEM_NUM              16
 195 #define PQISRC_MAX_ADMIN_OB_QUEUE_ELEM_NUM              16
 196
 197
 198
 199 #define PQI_MIN_OP_IB_QUEUE_ID                  1
 200 #define PQI_OP_EVENT_QUEUE_ID                   1
 201 #define PQI_MIN_OP_OB_QUEUE_ID                  2
 202
 203 #define PQISRC_MAX_SUPPORTED_OP_IB_Q            128
 204 #define PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q       (PQISRC_MAX_SUPPORTED_OP_IB_Q / 2)
 205 #define PQISRC_MAX_SUPPORTED_OP_AIO_IB_Q        (PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q)
 206 #define PQISRC_MAX_OP_IB_QUEUE_ELEM_NUM         (PQISRC_MAX_OUTSTANDING_REQ / PQISRC_MAX_SUPPORTED_OP_IB_Q)
 207 #define PQISRC_MAX_OP_OB_QUEUE_ELEM_NUM         PQISRC_MAX_OUTSTANDING_REQ
 208 #define PQISRC_MIN_OP_OB_QUEUE_ELEM_NUM         2
 209 #define PQISRC_MAX_SUPPORTED_OP_OB_Q            64
 210 #define PQISRC_OP_MAX_IBQ_ELEM_SIZE             8 /* 8 * 16  = 128 bytes */
 211 #define PQISRC_OP_MIN_IBQ_ELEM_SIZE             2 /* 2 * 16  = 32 bytes */
 212 #define PQISRC_OP_OBQ_ELEM_SIZE                 1 /* 16 bytes */
 213 #define PQISRC_ADMIN_IBQ_ELEM_SIZE              2 /* 2 * 16  = 32 bytes */
 214 #define PQISRC_INTR_COALSC_GRAN                 0
 215 #define PQISRC_PROTO_BIT_MASK                   0
 216 #define PQISRC_SGL_SUPPORTED_BIT_MASK           0
 217
 218 #define PQISRC_NUM_EVENT_Q_ELEM                 32
 219 #define PQISRC_EVENT_Q_ELEM_SIZE                32
 220
 221 /* PQI Registers state status */
 222
 223 #define PQI_RESET_ACTION_RESET                  0x1
 224 #define PQI_RESET_ACTION_COMPLETED              0x2
 225 #define PQI_RESET_TYPE_NO_RESET                 0x0
 226 #define PQI_RESET_TYPE_SOFT_RESET               0x1
 227 #define PQI_RESET_TYPE_FIRM_RESET               0x2
 228 #define PQI_RESET_TYPE_HARD_RESET               0x3
 229
 230 #define PQI_RESET_POLL_INTERVAL                 100000 /*100 msec*/
 231
 232 enum pqisrc_ctrl_mode{
 233         CTRL_SIS_MODE = 0,
 234         CTRL_PQI_MODE
 235 };
 236
 237 /* PQI device performing internal initialization (e.g., POST). */
 238 #define PQI_DEV_STATE_POWER_ON_AND_RESET        0x0
 239 /* Upon entry to this state PQI device initialization begins. */
 240 #define PQI_DEV_STATE_PQI_STATUS_AVAILABLE      0x1
 241 /* PQI device Standard registers are available to the driver. */
 242 #define PQI_DEV_STATE_ALL_REGISTERS_READY       0x2
 243 /* PQI device is initialized and ready to process any PCI transactions. */
 244 #define PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY    0x3
 245 /* The PQI Device Error register indicates the error. */
 246 #define PQI_DEV_STATE_ERROR                     0x4
 247
 248 #define PQI_DEV_STATE_AT_INIT                   ( PQI_DEV_STATE_PQI_STATUS_AVAILABLE | \
 249                                                   PQI_DEV_STATE_ALL_REGISTERS_READY | \
 250                                                   PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY )
 251
 252 #define PQISRC_PQI_DEVICE_SIGNATURE             "PQI DREG"
 253 #define PQI_ADMINQ_ELEM_ARRAY_ALIGN             64
 254 #define PQI_ADMINQ_CI_PI_ALIGN                  64
 255 #define PQI_OPQ_ELEM_ARRAY_ALIGN                64
 256 #define PQI_OPQ_CI_PI_ALIGN                             4
 257 #define PQI_ADDR_ALIGN_MASK_64                  0x3F /* lsb 6 bits */
 258 #define PQI_ADDR_ALIGN_MASK_4                   0x3  /* lsb 2 bits */
 259
 260 #define PQISRC_PQIMODE_READY_TIMEOUT            (30 * 1000 ) /* 30 secs */
 261 #define PQISRC_MODE_READY_POLL_INTERVAL         1000 /* 1 msec */
 262
 263 #define PRINT_PQI_SIGNATURE(sign)               { int i = 0; \
 264                                                   char si[9]; \
 265                                                   for(i=0;i<8;i++) \
 266                                                         si[i] = *((char *)&(sign)+i); \
 267                                                   si[i] = '\0'; \
 268                                                   DBG_INFO("Signature is %s",si); \
 269                                                 }
 270 #define PQI_CONF_TABLE_MAX_LEN          ((uint16_t)~0)
 271 #define PQI_CONF_TABLE_SIGNATURE        "CFGTABLE"
 272
 273 /* PQI configuration table section IDs */
 274 #define PQI_CONF_TABLE_ALL_SECTIONS                     (-1)
 275 #define PQI_CONF_TABLE_SECTION_GENERAL_INFO             0
 276 #define PQI_CONF_TABLE_SECTION_FIRMWARE_FEATURES        1
 277 #define PQI_CONF_TABLE_SECTION_FIRMWARE_ERRATA          2
 278 #define PQI_CONF_TABLE_SECTION_DEBUG                    3
 279 #define PQI_CONF_TABLE_SECTION_HEARTBEAT                4
 280
 281
 282 #define PQI_FIRMWARE_FEATURE_OFA                        0
 283 #define PQI_FIRMWARE_FEATURE_SMP                        1
 284 #define PQI_FIRMWARE_FEATURE_MAX_KNOWN                  2
 285 #define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_0            3
 286 #define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_1_10         4
 287 #define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_5_50         5
 288 #define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_6_60         6
 289 #define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_0           7
 290 #define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_1_10        8
 291 #define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_5_50        9
 292 #define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_6_60        10
 293 #define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE       11
 294 #define PQI_FIRMWARE_FEATURE_SATA_WWN_FOR_DEV_UNIQUE_ID 12
 295 #define PQI_FIRMWARE_FEATURE_TIMEOUT_IN_RAID_IU_SUPPORT 13
 296 #define PQI_FIRMWARE_FEATURE_TIMEOUT_IN_TMF_IU_SUPPORT  14
 297 #define PQI_FIRMWARE_FEATURE_MAXIMUM                    14
 298
 299 #define CTRLR_HEARTBEAT_CNT(softs)              \
 300         LE_64(PCI_MEM_GET64(softs, softs->heartbeat_counter_abs_addr, softs->heartbeat_counter_off))
 301 #define PQI_HEARTBEAT_TIMEOUT_SEC               (10) /* 10 sec interval */
 302 #define PQI_HOST_WELLNESS_TIMEOUT_SEC           (24*3600)
 303
 304  /* pqi-2r00a table 36 */
 305 #define PQI_ADMIN_QUEUE_MSIX_DISABLE    (0x80000000)
 306 #define PQI_ADMIN_QUEUE_MSIX_ENABLE             (0 << 31)
 307
 308 #define PQI_ADMIN_QUEUE_CONF_FUNC_CREATE_Q_PAIR 0x01
 309 #define PQI_ADMIN_QUEUE_CONF_FUNC_DEL_Q_PAIR    0x02
 310 #define PQI_ADMIN_QUEUE_CONF_FUNC_STATUS_IDLE   0x00
 311 #define PQISRC_ADMIN_QUEUE_CREATE_TIMEOUT       1000  /* in miLLI sec, 1 sec, 100 ms is standard */
 312 #define PQISRC_ADMIN_QUEUE_DELETE_TIMEOUT       100  /* 100 ms is standard */
 313 #define PQISRC_ADMIN_CMD_RESP_TIMEOUT           3000 /* 3 sec  */
 314 #define PQISRC_RAIDPATH_CMD_TIMEOUT             30000 /* 30 sec */
 315
 316 #define REPORT_PQI_DEV_CAP_DATA_BUF_SIZE        sizeof(pqi_dev_cap_t)
 317 #define REPORT_MANUFACTURER_INFO_DATA_BUF_SIZE  0x80   /* Data buffer size specified in bytes 0-1 of data buffer.  128 bytes. */
 318 /* PQI IUs */
 319 /* Admin IU request length not including header. */
 320 #define PQI_STANDARD_IU_LENGTH                  0x003C  /* 60 bytes. */
 321 #define PQI_IU_TYPE_GENERAL_ADMIN_REQUEST       0x60
 322 #define PQI_IU_TYPE_GENERAL_ADMIN_RESPONSE      0xe0
 323
 324 /* PQI / Vendor specific IU */
 325 #define PQI_FUNCTION_REPORT_DEV_CAP                             0x00
 326 #define PQI_REQUEST_IU_RAID_TASK_MANAGEMENT                     0x13
 327 #define PQI_IU_TYPE_RAID_PATH_IO_REQUEST                        0x14
 328 #define PQI_IU_TYPE_AIO_PATH_IO_REQUEST                         0x15
 329 #define PQI_REQUEST_IU_AIO_TASK_MANAGEMENT                      0x16
 330 #define PQI_REQUEST_IU_GENERAL_ADMIN                            0x60
 331 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG               0x72
 332 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG                  0x73
 333 #define PQI_REQUEST_IU_VENDOR_GENERAL                           0x75
 334 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT                      0x81
 335 #define PQI_RESPONSE_IU_TASK_MANAGEMENT                         0x93
 336 #define PQI_RESPONSE_IU_GENERAL_ADMIN                           0xe0
 337
 338 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS                    0xf0
 339 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS                     0xf1
 340 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR                      0xf2
 341 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR                       0xf3
 342 #define PQI_RESPONSE_IU_AIO_PATH_IS_OFF                         0xf4
 343 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT                 0xf6
 344 #define PQI_RESPONSE_IU_VENDOR_GENERAL                          0xf7
 345 #define PQI_REQUEST_HEADER_LENGTH                               4
 346 #define PQI_FUNCTION_CREATE_OPERATIONAL_IQ                      0x10
 347 #define PQI_FUNCTION_CREATE_OPERATIONAL_OQ                      0x11
 348 #define PQI_FUNCTION_DELETE_OPERATIONAL_IQ                      0x12
 349 #define PQI_FUNCTION_DELETE_OPERATIONAL_OQ                      0x13
 350 #define PQI_FUNCTION_CHANGE_OPERATIONAL_IQ_PROP                 0x14
 351 #define PQI_CHANGE_OP_IQ_PROP_ASSIGN_AIO                        1
 352
 353 #define PQI_DEFAULT_IB_QUEUE                            0
 354 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE          0
 355
 356 #define PQI_VENDOR_RESPONSE_IU_SUCCESS                  0
 357 #define PQI_VENDOR_RESPONSE_IU_UNSUCCESS                1
 358 #define PQI_VENDOR_RESPONSE_IU_INVALID_PARAM            2
 359 #define PQI_VENDOR_RESPONSE_IU_INSUFF_RESRC             3
 360
 361 /* Interface macros */
 362
 363 #define GET_FW_STATUS(softs) \
 364         (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad3_fw_status, LEGACY_SIS_OMR))
 365
 366 #define SIS_IS_KERNEL_PANIC(softs) \
 367         (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_PANIC)
 368
 369 #define SIS_IS_KERNEL_UP(softs) \
 370         (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_UP_AND_RUNNING)
 371
 372 #define PQI_GET_CTRL_MODE(softs) \
 373         (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0))
 374
 375 #define PQI_SAVE_CTRL_MODE(softs, mode) \
 376         PCI_MEM_PUT32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0, mode)
 377
 378 #define PQISRC_MAX_TARGETID             1024
 379 #define PQISRC_MAX_TARGETLUN            64
 380
 381 /* Vendor specific IU Type for Event config Cmds */
 382 #define PQI_REQUEST_IU_REPORT_EVENT_CONFIG      0x72
 383 #define PQI_REQUEST_IU_SET_EVENT_CONFIG         0x73
 384 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
 385
 386 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT      0x81
 387 #define PQI_MANAGEMENT_CMD_RESP_TIMEOUT         3000
 388 #define PQISRC_EVENT_ACK_RESP_TIMEOUT           1000
 389
 390
 391 /* Supported Event types by controller */
 392
 393 #define PQI_NUM_SUPPORTED_EVENTS                6
 394
 395 #define PQI_EVENT_TYPE_HOTPLUG                  0x1
 396 #define PQI_EVENT_TYPE_HARDWARE                 0x2
 397 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE          0x4
 398 #define PQI_EVENT_TYPE_LOGICAL_DEVICE           0x5
 399 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE         0xfd
 400 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE        0xfe
 401
 402 /* for indexing into the pending_events[] field of struct pqisrc_softstate */
 403 #define PQI_EVENT_HOTPLUG                       0
 404 #define PQI_EVENT_HARDWARE                      1
 405 #define PQI_EVENT_PHYSICAL_DEVICE               2
 406 #define PQI_EVENT_LOGICAL_DEVICE                3
 407 #define PQI_EVENT_AIO_STATE_CHANGE              4
 408 #define PQI_EVENT_AIO_CONFIG_CHANGE             5
 409
 410
 411
 412 /* Device flags */
 413 #define PQISRC_DFLAG_VALID                      (1 << 0)
 414 #define PQISRC_DFLAG_CONFIGURING                (1 << 1)
 415
 416 #define MAX_EMBEDDED_SG_IN_FIRST_IU             4
 417 #define MAX_EMBEDDED_SG_IN_IU                   8
 418 #define SG_FLAG_LAST                            0x40000000
 419 #define SG_FLAG_CHAIN                           0x80000000
 420
 421 #define IN_PQI_RESET(softs)     (softs->ctlr_state & PQI_BUS_RESET)
 422 #define DEV_GONE(dev)           (!dev || (dev->invalid == true))
 423 #define IS_AIO_PATH(dev)        (dev->aio_enabled)
 424 #define IS_RAID_PATH(dev)       (!dev->aio_enabled)
 425
 426 #define DEVICE_RESET(dvp)       (dvp->reset_in_progress)
 427
 428 /* SOP data direction flags */
 429 #define SOP_DATA_DIR_NONE               0x00
 430 #define SOP_DATA_DIR_FROM_DEVICE        0x01
 431 #define SOP_DATA_DIR_TO_DEVICE          0x02
 432 #define SOP_DATA_DIR_BIDIRECTIONAL      0x03
 433 #define SOP_PARTIAL_DATA_BUFFER         0x04
 434
 435 #define PQISRC_DMA_VALID                (1 << 0)
 436 #define PQISRC_CMD_NO_INTR              (1 << 1)
 437
 438 #define SOP_TASK_ATTRIBUTE_SIMPLE               0
 439 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE        1
 440 #define SOP_TASK_ATTRIBUTE_ORDERED              2
 441 #define SOP_TASK_ATTRIBUTE_ACA                  4
 442
 443 #define SOP_TASK_MANAGEMENT_FUNCTION_COMPLETE           0x0
 444 #define SOP_TASK_MANAGEMENT_FUNCTION_REJECTED           0x4
 445 #define SOP_TASK_MANAGEMENT_FUNCTION_FAILED             0x5
 446 #define SOP_TASK_MANAGEMENT_FUNCTION_SUCCEEDED          0x8
 447 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK         0x01
 448 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK_SET     0x02
 449 #define SOP_TASK_MANAGEMENT_LUN_RESET                   0x8
 450
 451
 452 /* Additional CDB bytes  */
 453 #define PQI_ADDITIONAL_CDB_BYTES_0              0       /* 16 byte CDB */
 454 #define PQI_ADDITIONAL_CDB_BYTES_4              1       /* 20 byte CDB */
 455 #define PQI_ADDITIONAL_CDB_BYTES_8              2       /* 24 byte CDB */
 456 #define PQI_ADDITIONAL_CDB_BYTES_12             3       /* 28 byte CDB */
 457 #define PQI_ADDITIONAL_CDB_BYTES_16             4       /* 32 byte CDB */
 458
 459 #define PQI_PROTOCOL_SOP                        0x0
 460
 461 #define PQI_AIO_STATUS_GOOD                     0x0
 462 #define PQI_AIO_STATUS_CHECK_CONDITION          0x2
 463 #define PQI_AIO_STATUS_CONDITION_MET            0x4
 464 #define PQI_AIO_STATUS_DEVICE_BUSY              0x8
 465 #define PQI_AIO_STATUS_INT_GOOD                 0x10
 466 #define PQI_AIO_STATUS_INT_COND_MET             0x14
 467 #define PQI_AIO_STATUS_RESERV_CONFLICT          0x18
 468 #define PQI_AIO_STATUS_CMD_TERMINATED           0x22
 469 #define PQI_AIO_STATUS_QUEUE_FULL               0x28
 470 #define PQI_AIO_STATUS_TASK_ABORTED             0x40
 471 #define PQI_AIO_STATUS_UNDERRUN                 0x51
 472 #define PQI_AIO_STATUS_OVERRUN                  0x75
 473 /* Status when Target Failure */
 474 #define PQI_AIO_STATUS_IO_ERROR                 0x1
 475 #define PQI_AIO_STATUS_IO_ABORTED               0x2
 476 #define PQI_AIO_STATUS_IO_NO_DEVICE             0x3
 477 #define PQI_AIO_STATUS_INVALID_DEVICE           0x4
 478 #define PQI_AIO_STATUS_AIO_PATH_DISABLED        0xe
 479
 480 /* Service Response */
 481 #define PQI_AIO_SERV_RESPONSE_COMPLETE                  0
 482 #define PQI_AIO_SERV_RESPONSE_FAILURE                   1
 483 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE              2
 484 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED             3
 485 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED              4
 486 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN         5
 487
 488 #define PQI_TMF_WAIT_DELAY                      10000000        /* 10 seconds */
 489
 490 #define PQI_RAID_STATUS_GOOD                    PQI_AIO_STATUS_GOOD
 491 #define PQI_RAID_STATUS_CHECK_CONDITION         PQI_AIO_STATUS_CHECK_CONDITION
 492 #define PQI_RAID_STATUS_CONDITION_MET           PQI_AIO_STATUS_CONDITION_MET
 493 #define PQI_RAID_STATUS_DEVICE_BUSY             PQI_AIO_STATUS_DEVICE_BUSY
 494 #define PQI_RAID_STATUS_INT_GOOD                PQI_AIO_STATUS_INT_GOOD
 495 #define PQI_RAID_STATUS_INT_COND_MET            PQI_AIO_STATUS_INT_COND_MET
 496 #define PQI_RAID_STATUS_RESERV_CONFLICT         PQI_AIO_STATUS_RESERV_CONFLICT
 497 #define PQI_RAID_STATUS_CMD_TERMINATED          PQI_AIO_STATUS_CMD_TERMINATED
 498 #define PQI_RAID_STATUS_QUEUE_FULL              PQI_AIO_STATUS_QUEUE_FULL
 499 #define PQI_RAID_STATUS_TASK_ABORTED            PQI_AIO_STATUS_TASK_ABORTED
 500 #define PQI_RAID_STATUS_UNDERRUN                PQI_AIO_STATUS_UNDERRUN
 501 #define PQI_RAID_STATUS_OVERRUN                 PQI_AIO_STATUS_OVERRUN
 502
 503 /* VPD inquiry pages */
 504 #define SCSI_VPD_SUPPORTED_PAGES        0x0             /* standard page */
 505 #define SCSI_VPD_DEVICE_ID              0x83    /* standard page */
 506 #define SA_VPD_PHYS_DEVICE_ID           0xc0    /* vendor-specific page */
 507 #define SA_VPD_LV_DEVICE_GEOMETRY       0xc1    /* vendor-specific page */
 508 #define SA_VPD_LV_IOACCEL_STATUS        0xc2    /* vendor-specific page */
 509 #define SA_VPD_LV_STATUS                0xc3    /* vendor-specific page */
 510
 511 #define VPD_PAGE        (1 << 8)
 512
 513
 514 /* logical volume states */
 515 #define SA_LV_OK                                        0x0
 516 #define SA_LV_FAILED                                    0x1
 517 #define SA_LV_NOT_CONFIGURED                            0x2
 518 #define SA_LV_DEGRADED                                  0x3
 519 #define SA_LV_READY_FOR_RECOVERY                        0x4
 520 #define SA_LV_UNDERGOING_RECOVERY                       0x5
 521 #define SA_LV_WRONG_PHYSICAL_DRIVE_REPLACED             0x6
 522 #define SA_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM         0x7
 523 #define SA_LV_HARDWARE_OVERHEATING                      0x8
 524 #define SA_LV_HARDWARE_HAS_OVERHEATED                   0x9
 525 #define SA_LV_UNDERGOING_EXPANSION                      0xA
 526 #define SA_LV_NOT_AVAILABLE                             0xb
 527 #define SA_LV_QUEUED_FOR_EXPANSION                      0xc
 528 #define SA_LV_DISABLED_SCSI_ID_CONFLICT                 0xd
 529 #define SA_LV_EJECTED                                   0xe
 530 #define SA_LV_UNDERGOING_ERASE                          0xf
 531 #define SA_LV_UNDERGOING_RPI                            0x12
 532 #define SA_LV_PENDING_RPI                               0x13
 533 #define SA_LV_ENCRYPTED_NO_KEY                          0x14
 534 #define SA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER      0x15
 535 #define SA_LV_UNDERGOING_ENCRYPTION                     0x16
 536 #define SA_LV_UNDERGOING_ENCRYPTION_REKEYING            0x17
 537 #define SA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER     0x18
 538 #define SA_LV_PENDING_ENCRYPTION                        0x19
 539 #define SA_LV_PENDING_ENCRYPTION_REKEYING               0x1a
 540 #define SA_LV_STATUS_VPD_UNSUPPORTED                    0xff
 541
 542
 543 /* constants for flags field of ciss_vpd_logical_volume_status */
 544 #define SA_LV_FLAGS_NO_HOST_IO  0x1     /* volume not available for */
 545
 546 /*
 547  * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands
 548  */
 549 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH       27
 550
 551 /* 0 = no limit */
 552 #define PQI_LOGICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH        0
 553 #define PQI_LOG_EXT_QUEUE_DEPTH_ENABLED                 0x20
 554 #define PQI_LOG_EXT_QUEUE_ENABLE                        0x56
 555 #define MAX_RAW_M256_QDEPTH                             32512
 556 #define MAX_RAW_M16_QDEPTH                              2032
 557 #define PQI_PTRAID_UPDATE_ON_RESCAN_LUNS                0x80000000
 558
 559 #define RAID_CTLR_LUNID         "\0\0\0\0\0\0\0\0"
 560
 561 #define SA_CACHE_FLUSH          0x1
 562 #define PQISRC_INQUIRY_TIMEOUT 30
 563 #define SA_INQUIRY              0x12
 564 #define SA_REPORT_LOG           0xc2    /* Report Logical LUNs */
 565 #define SA_REPORT_PHYS          0xc3    /* Report Physical LUNs */
 566 #define SA_CISS_READ            0xc0
 567 #define SA_GET_RAID_MAP         0xc8
 568
 569 #define SCSI_SENSE_RESPONSE_70      0x70
 570 #define SCSI_SENSE_RESPONSE_71      0x71
 571 #define SCSI_SENSE_RESPONSE_72      0x72
 572 #define SCSI_SENSE_RESPONSE_73      0x73
 573
 574 #define SA_REPORT_LOG_EXTENDED  0x1
 575 #define SA_REPORT_PHYS_EXTENDED 0x2
 576
 577 #define SA_CACHE_FLUSH_BUF_LEN  4
 578
 579 #define GET_SCSI_SNO(cmd)       (cmd->cmdId.serialNumber)
 580
 581 #define REPORT_LUN_DEV_FLAG_AIO_ENABLED 0x8
 582 #define PQI_MAX_TRANSFER_SIZE   (4 * 1024U * 1024U)
 583 #define RAID_MAP_MAX_ENTRIES    1024
 584 #define RAID_MAP_ENCRYPTION_ENABLED     0x1
 585 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH       27
 586
 587 #define ASC_LUN_NOT_READY                               0x4
 588 #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS           0x4
 589 #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ         0x2
 590
 591
 592 #define OBDR_SIG_OFFSET         43
 593 #define OBDR_TAPE_SIG           "$DR-10"
 594 #define OBDR_SIG_LEN            (sizeof(OBDR_TAPE_SIG) - 1)
 595 #define OBDR_TAPE_INQ_SIZE      (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
 596
 597
 598 #define IOACCEL_STATUS_BYTE     4
 599 #define OFFLOAD_CONFIGURED_BIT  0x1
 600 #define OFFLOAD_ENABLED_BIT     0x2
 601
 602 #define PQI_RAID_DATA_IN_OUT_GOOD                                    0x0
 603 #define PQI_RAID_DATA_IN_OUT_UNDERFLOW                               0x1
 604 #define PQI_RAID_DATA_IN_OUT_BUFFER_ERROR                            0x40
 605 #define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW                         0x41
 606 #define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA         0x42
 607 #define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE                  0x43
 608 #define PQI_RAID_DATA_IN_OUT_PCIE_FABRIC_ERROR                       0x60
 609 #define PQI_RAID_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT                 0x61
 610 #define PQI_RAID_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED           0x62
 611 #define PQI_RAID_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ               0x63
 612 #define PQI_RAID_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED                  0x64
 613 #define PQI_RAID_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST                0x65
 614 #define PQI_RAID_DATA_IN_OUT_PCIE_ACS_VIOLATION                      0x66
 615 #define PQI_RAID_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED                 0x67
 616 #define PQI_RAID_DATA_IN_OUT_ERROR                                   0xf0
 617 #define PQI_RAID_DATA_IN_OUT_PROTOCOL_ERROR                          0xf1
 618 #define PQI_RAID_DATA_IN_OUT_HARDWARE_ERROR                          0xf2
 619 #define PQI_RAID_DATA_IN_OUT_UNSOLICITED_ABORT                       0xf3
 620 #define PQI_RAID_DATA_IN_OUT_ABORTED                                 0xf4
 621 #define PQI_RAID_DATA_IN_OUT_TIMEOUT                                 0xf5
 622
 623
 624 #define PQI_PHYSICAL_DEVICE_BUS         0
 625 #define PQI_RAID_VOLUME_BUS             1
 626 #define PQI_HBA_BUS                     2
 627 #define PQI_EXTERNAL_RAID_VOLUME_BUS    3
 628 #define PQI_MAX_BUS                     PQI_EXTERNAL_RAID_VOLUME_BUS
 629
 630 #define TEST_UNIT_READY         0x00
 631 #define SCSI_VPD_HEADER_LENGTH  64
 632
 633
 634 #define PQI_MAX_MULTILUN        256
 635 #define PQI_MAX_LOGICALS        64
 636 #define PQI_MAX_PHYSICALS       1024
 637 #define PQI_MAX_DEVICES         (PQI_MAX_LOGICALS + PQI_MAX_PHYSICALS + 1) /* 1 for controller device entry */
 638 #define PQI_MAX_EXT_TARGETS     32
 639
 640 #define PQI_CTLR_INDEX          (PQI_MAX_DEVICES - 1)
 641 #define PQI_PD_INDEX(t)         (t + PQI_MAX_LOGICALS)
 642
 643 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 644 #define MAX_TARGET_DEVICES 1024
 645
 646 #define PQI_NO_MEM      2
 647
 648 typedef enum pqisrc_device_status {
 649         DEVICE_NOT_FOUND,
 650         DEVICE_CHANGED,
 651         DEVICE_UNCHANGED,
 652 } device_status_t;
 653
 654 #define SA_RAID_0                       0
 655 #define SA_RAID_4                       1
 656 #define SA_RAID_1                       2       /* also used for RAID 10 */
 657 #define SA_RAID_5                       3       /* also used for RAID 50 */
 658 #define SA_RAID_51                      4
 659 #define SA_RAID_6                       5       /* also used for RAID 60 */
 660 #define SA_RAID_ADM                     6       /* also used for RAID 1+0 ADM */
 661 #define SA_RAID_MAX                     SA_RAID_ADM
 662 #define SA_RAID_UNKNOWN                 0xff
 663
 664 #define BIT0 (1 << 0)
 665 #define BIT1 (1 << 1)
 666 #define BIT2 (1 << 2)
 667 #define BIT3 (1 << 3)
 668
 669 #define BITS_PER_BYTE   8
 670 /* BMIC commands */
 671 #define BMIC_IDENTIFY_CONTROLLER                0x11
 672 #define BMIC_IDENTIFY_PHYSICAL_DEVICE           0x15
 673 #define BMIC_READ                               0x26
 674 #define BMIC_WRITE                              0x27
 675 #define BMIC_SENSE_CONTROLLER_PARAMETERS        0x64
 676 #define BMIC_SENSE_SUBSYSTEM_INFORMATION        0x66
 677 #define BMIC_CACHE_FLUSH                        0xc2
 678 #define BMIC_FLASH_FIRMWARE                     0xf7
 679 #define BMIC_WRITE_HOST_WELLNESS                0xa5
 680 #define BMIC_SET_DIAGS_OPTIONS                  0xf4
 681 #define BMIC_SENSE_DIAGS_OPTIONS                0xf5
 682
 683
 684 #define MASKED_DEVICE(lunid)                    ((lunid)[3] & 0xC0)
 685 #define BMIC_GET_LEVEL_2_BUS(lunid)             ((lunid)[7] & 0x3F)
 686 #define BMIC_GET_LEVEL_TWO_TARGET(lunid)        ((lunid)[6])
 687 #define BMIC_GET_DRIVE_NUMBER(lunid)            \
 688         (((BMIC_GET_LEVEL_2_BUS((lunid)) - 1) << 8) +   \
 689         BMIC_GET_LEVEL_TWO_TARGET((lunid)))
 690 #define NON_DISK_PHYS_DEV(rle)                  \
 691         (((reportlun_ext_entry_t *)(rle))->device_flags & 0x1)
 692
 693 #define NO_TIMEOUT              ((unsigned long) -1)
 694
 695 #define BMIC_DEVICE_TYPE_SATA   0x1
 696
 697 /* No of IO slots required for internal requests */
 698 #define PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS     3
 699 #define PQI_RESERVED_IO_SLOTS_TMF               1
 700 #define PQI_RESERVED_IO_SLOTS_CNT               (PQI_NUM_SUPPORTED_EVENTS + \
 701                                                 PQI_RESERVED_IO_SLOTS_TMF + \
 702                                                 PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS)
 703
 704 /* Defines for print flags */
 705 #define PRINT_FLAG_HDR_COLUMN                                   0x0001
 706
 707
 708 static inline uint16_t GET_LE16(const uint8_t *p)
 709 {
 710         return p[0] | p[1] << 8;
 711 }
 712
 713 static inline uint32_t GET_LE32(const uint8_t *p)
 714 {
 715         return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
 716 }
 717
 718 static inline uint64_t GET_LE64(const uint8_t *p)
 719 {
 720         return (((uint64_t)GET_LE32(p + 4) << 32) |
 721                 GET_LE32(p));
 722 }
 723
 724 static inline uint16_t GET_BE16(const uint8_t *p)
 725 {
 726         return p[0] << 8 | p[1];
 727 }
 728
 729 static inline uint32_t GET_BE32(const uint8_t *p)
 730 {
 731         return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3];
 732 }
 733
 734 static inline uint64_t GET_BE64(const uint8_t *p)
 735 {
 736         return (((uint64_t)GET_BE32(p) << 32) |
 737                GET_BE32(p + 4));
 738 }
 739
 740 static inline void PUT_BE16(uint16_t val, uint8_t *p)
 741 {
 742         *p++ = val >> 8;
 743         *p++ = val;
 744 }
 745
 746 static inline void PUT_BE32(uint32_t val, uint8_t *p)
 747 {
 748         PUT_BE16(val >> 16, p);
 749         PUT_BE16(val, p + 2);
 750 }
 751
 752 static inline void PUT_BE64(uint64_t val, uint8_t *p)
 753 {
 754         PUT_BE32(val >> 32, p);
 755         PUT_BE32(val, p + 4);
 756 }
 757
 758 #define OS_FREEBSD
 759 #define SIS_POLL_WAIT
 760
 761 #define OS_ATTRIBUTE_PACKED         __attribute__((__packed__))
 762 #define OS_ATTRIBUTE_ALIGNED(n)     __attribute__((aligned(n)))
 763
 764
 765 /* Management Interface */
 766 #define CCISS_IOC_MAGIC         'C'
 767 #define SMARTPQI_IOCTL_BASE     'M'
 768 #define CCISS_GETDRIVVER       _IOWR(SMARTPQI_IOCTL_BASE, 0, driver_info)
 769 #define CCISS_GETPCIINFO       _IOWR(SMARTPQI_IOCTL_BASE, 1, pqi_pci_info_t)
 770 #define SMARTPQI_PASS_THRU     _IOWR(SMARTPQI_IOCTL_BASE, 2, IOCTL_Command_struct)
 771 #define CCISS_PASSTHRU         _IOWR('C', 210, IOCTL_Command_struct)
 772 #define CCISS_REGNEWD          _IO(CCISS_IOC_MAGIC, 14)
 773
 774 /*IOCTL  pci_info structure */
 775 typedef struct pqi_pci_info
 776 {
 777        unsigned char   bus;
 778        unsigned char   dev_fn;
 779        unsigned short  domain;
 780        uint32_t        board_id;
 781        uint32_t        chip_id;
 782 }pqi_pci_info_t;
 783
 784 typedef struct _driver_info
 785 {
 786         unsigned char   major_version;
 787         unsigned long   minor_version;
 788         unsigned char   release_version;
 789         unsigned long   build_revision;
 790         unsigned long   max_targets;
 791         unsigned long   max_io;
 792         unsigned long   max_transfer_length;
 793 }driver_info, *pdriver_info;
 794
 795 typedef uint8_t *passthru_buf_type_t;
 796
 797
 798 #define PQISRC_OS_VERSION       1
 799 #define PQISRC_FEATURE_VERSION  4014
 800 #define PQISRC_PATCH_VERSION    0
 801 #define PQISRC_BUILD_VERSION    105
 802
 803 #define STR(s)                          # s
 804 #define PQISRC_VERSION(a, b, c, d)      STR(a.b.c.d)
 805 #define PQISRC_DRIVER_VERSION           PQISRC_VERSION(PQISRC_OS_VERSION, \
 806                                         PQISRC_FEATURE_VERSION, \
 807                                         PQISRC_PATCH_VERSION, \
 808                                         PQISRC_BUILD_VERSION)
 809
 810 /* End Management interface */
 811
 812 #ifdef ASSERT
 813 #undef ASSERT
 814 #endif
 815
 816 /*
 817 *os_atomic64_cas--
 818 *
 819 *Atomically read, compare, and conditionally write.
 820 *i.e. compare and swap.
 821 *retval True    On Success
 822 *retval False   On Failure
 823 *
 824 */
 825 static inline boolean_t
 826 os_atomic64_cas(volatile uint64_t* var, uint64_t old_val, uint64_t new_val)
 827 {
 828         return (atomic_cmpset_64(var, old_val, new_val));
 829 }
 830
 831 #define ASSERT(cond) {\
 832                 if (!(cond)) { \
 833                         printf("Assertion failed at file %s line %d\n",__FILE__,__LINE__);      \
 834                 }       \
 835                 }
 836
 837 /* Atomic */
 838 typedef volatile uint64_t       OS_ATOMIC64_T;
 839 #define OS_ATOMIC64_READ(p)     atomic_load_acq_64(p)
 840 #define OS_ATOMIC64_INIT(p,val) atomic_store_rel_64(p, val)
 841
 842 /* 64-bit post atomic increment and decrement operations on value in pointer.*/
 843 #define OS_ATOMIC64_DEC(p)      (atomic_fetchadd_64(p, -1) - 1)
 844 #define OS_ATOMIC64_INC(p)      (atomic_fetchadd_64(p, 1) + 1)
 845
 846
 847 #define PQI_MAX_MSIX            64      /* vectors */
 848 #define PQI_MSI_CTX_SIZE        sizeof(pqi_intr_ctx)+1
 849 #define IS_POLLING_REQUIRED(softs)      if (cold) {\
 850                                         pqisrc_process_event_intr_src(softs, 0);\
 851                                         pqisrc_process_response_queue(softs, 1);\
 852                                 }
 853
 854 #define OS_GET_TASK_ATTR(rcb)           os_get_task_attr(rcb)
 855 #define OS_FW_HEARTBEAT_TIMER_INTERVAL (5)
 856
 857 typedef struct PCI_ACC_HANDLE {
 858         bus_space_tag_t         pqi_btag;
 859         bus_space_handle_t      pqi_bhandle;
 860 } PCI_ACC_HANDLE_T;
 861
 862 /*
 863  * Legacy SIS Register definitions for the Adaptec PMC SRC/SRCv/smartraid adapters.
 864  */
 865 /* accessible via BAR0 */
 866 #define LEGACY_SIS_IOAR         0x18    /* IOA->host interrupt register */
 867 #define LEGACY_SIS_IDBR         0x20    /* inbound doorbell register */
 868 #define LEGACY_SIS_IISR         0x24    /* inbound interrupt status register */
 869 #define LEGACY_SIS_OIMR         0x34    /* outbound interrupt mask register */
 870 #define LEGACY_SIS_ODBR_R       0x9c    /* outbound doorbell register read */
 871 #define LEGACY_SIS_ODBR_C       0xa0    /* outbound doorbell register clear */
 872
 873 #define LEGACY_SIS_SCR0         0xb0    /* scratchpad 0 */
 874 #define LEGACY_SIS_OMR          0xbc    /* outbound message register */
 875 #define LEGACY_SIS_IQUE64_L     0xc0    /* inbound queue address 64-bit (low) */
 876 #define LEGACY_SIS_IQUE64_H     0xc4    /* inbound queue address 64-bit (high)*/
 877 #define LEGACY_SIS_ODBR_MSI     0xc8    /* MSI register for sync./AIF */
 878 #define LEGACY_SIS_IQN_L        0xd0    /* inbound queue native mode (low) */
 879 #define LEGACY_SIS_IQN_H        0xd4    /* inbound queue native mode (high)*/
 880 #define LEGACY_SIS_MAILBOX      0x7fc60 /* mailbox (20 bytes) */
 881 #define LEGACY_SIS_SRCV_MAILBOX 0x1000  /* mailbox (20 bytes) */
 882 #define LEGACY_SIS_SRCV_OFFSET_MAILBOX_7  0x101C   /* mailbox 7 register offset */
 883
 884
 885 #define LEGACY_SIS_ODR_SHIFT    12      /* outbound doorbell shift */
 886 #define LEGACY_SIS_IDR_SHIFT    9       /* inbound doorbell shift */
 887
 888
 889 /*
 890  * PQI Register definitions for the smartraid adapters
 891  */
 892 /* accessible via BAR0 */
 893 #define PQI_SIGNATURE                  0x4000
 894 #define PQI_ADMINQ_CONFIG              0x4008
 895 #define PQI_ADMINQ_CAP                 0x4010
 896 #define PQI_LEGACY_INTR_STATUS         0x4018
 897 #define PQI_LEGACY_INTR_MASK_SET       0x401C
 898 #define PQI_LEGACY_INTR_MASK_CLR       0x4020
 899 #define PQI_DEV_STATUS                 0x4040
 900 #define PQI_ADMIN_IBQ_PI_OFFSET        0x4048
 901 #define PQI_ADMIN_OBQ_CI_OFFSET        0x4050
 902 #define PQI_ADMIN_IBQ_ELEM_ARRAY_ADDR  0x4058
 903 #define PQI_ADMIN_OBQ_ELEM_ARRAY_ADDR  0x4060
 904 #define PQI_ADMIN_IBQ_CI_ADDR          0x4068
 905 #define PQI_ADMIN_OBQ_PI_ADDR          0x4070
 906 #define PQI_ADMINQ_PARAM               0x4078
 907 #define PQI_DEV_ERR                    0x4080
 908 #define PQI_DEV_ERR_DETAILS            0x4088
 909 #define PQI_DEV_RESET                  0x4090
 910 #define PQI_POWER_ACTION               0x4094
 911
 912 /* Busy wait micro seconds */
 913 #define OS_BUSYWAIT(x) DELAY(x)
 914 #define OS_SLEEP(timeout)       \
 915         DELAY(timeout);
 916
 917 /* TMF request timeout is 600 Sec */
 918 #define OS_TMF_TIMEOUT_SEC              (10 * 60)
 919
 920 #define LE_16(x) htole16(x)
 921 #define LE_32(x) htole32(x)
 922 #define LE_64(x) htole64(x)
 923 #define BE_16(x) htobe16(x)
 924 #define BE_32(x) htobe32(x)
 925 #define BE_64(x) htobe64(x)
 926
 927 #define PQI_HWIF_SRCV           0
 928 #define PQI_HWIF_UNKNOWN        -1
 929
 930
 931 #define SMART_STATE_SUSPEND             (1<<0)
 932 #define SMART_STATE_UNUSED0             (1<<1)
 933 #define SMART_STATE_INTERRUPTS_ON       (1<<2)
 934 #define SMART_STATE_AIF_SLEEPER         (1<<3)
 935 #define SMART_STATE_RESET               (1<<4)
 936
 937 #define PQI_FLAG_BUSY                   (1<<0)
 938 #define PQI_MSI_ENABLED                 (1<<1)
 939 #define PQI_SIM_REGISTERED              (1<<2)
 940 #define PQI_MTX_INIT                    (1<<3)
 941
 942
 943 #define PQI_CMD_MAPPED                  (1<<2)
 944
 945 /* Interrupt context to get oq_id */
 946 typedef struct pqi_intr_ctx {
 947         int      oq_id;
 948         device_t pqi_dev;
 949 }pqi_intr_ctx_t;
 950
 951 typedef uint8_t os_dev_info_t;
 952
 953 typedef struct OS_SPECIFIC {
 954         device_t                pqi_dev;
 955         struct resource         *pqi_regs_res0; /* reg. if. window */
 956         int                     pqi_regs_rid0;          /* resource ID */
 957         bus_dma_tag_t           pqi_parent_dmat;        /* parent DMA tag */
 958         bus_dma_tag_t           pqi_buffer_dmat;
 959
 960         /* controller hardware interface */
 961         int                     pqi_hwif;
 962         struct resource         *pqi_irq[PQI_MAX_MSIX];  /* interrupt */
 963         int                     pqi_irq_rid[PQI_MAX_MSIX];
 964         void                    *intrcookie[PQI_MAX_MSIX];
 965         bool                    intr_registered[PQI_MAX_MSIX];
 966         bool                    msi_enabled;            /* MSI/MSI-X enabled */
 967         pqi_intr_ctx_t          *msi_ctx;
 968         int                     oq_id;
 969         int                     pqi_state;
 970         uint32_t                pqi_flags;
 971         struct mtx              cam_lock;
 972         struct mtx              map_lock;
 973         int                     mtx_init;
 974         int                     sim_registered;
 975         struct cam_devq         *devq;
 976         struct cam_sim          *sim;
 977         struct cam_path         *path;
 978         struct task             event_task;
 979         struct cdev             *cdev;
 980         struct callout          wellness_periodic;      /* periodic event handling */
 981         struct callout          heartbeat_timeout_id;   /* heart beat event handling */
 982 } OS_SPECIFIC_T;
 983
 984 typedef bus_addr_t dma_addr_t;
 985
 986
 987 /* Register access macros */
 988 #define PCI_MEM_GET32( _softs, _absaddr, _offset ) \
 989         bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \
 990         _softs->pci_mem_handle.pqi_bhandle, _offset)
 991
 992
 993 #if defined(__i386__)
 994 #define PCI_MEM_GET64( _softs, _absaddr, _offset ) ({ \
 995         (uint64_t)bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \
 996         _softs->pci_mem_handle.pqi_bhandle, _offset) + \
 997         ((uint64_t)bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \
 998         _softs->pci_mem_handle.pqi_bhandle, _offset + 4) << 32); \
 999         })
1000 #else
1001 #define PCI_MEM_GET64(_softs, _absaddr, _offset ) \
1002         bus_space_read_8(_softs->pci_mem_handle.pqi_btag, \
1003         _softs->pci_mem_handle.pqi_bhandle, _offset)
1004 #endif
1005
1006 #define PCI_MEM_PUT32( _softs, _absaddr, _offset, _val ) \
1007         bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \
1008         _softs->pci_mem_handle.pqi_bhandle, _offset, _val)
1009
1010 #if defined(__i386__)
1011 #define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \
1012         bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \
1013                         _softs->pci_mem_handle.pqi_bhandle, _offset, _val); \
1014         bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \
1015                 _softs->pci_mem_handle.pqi_bhandle, _offset + 4, _val >> 32);
1016 #else
1017 #define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \
1018         bus_space_write_8(_softs->pci_mem_handle.pqi_btag, \
1019                 _softs->pci_mem_handle.pqi_bhandle, _offset, _val)
1020 #endif
1021
1022
1023 #define PCI_MEM_GET_BUF(_softs, _absaddr, _offset, buf, size) \
1024         bus_space_read_region_1(_softs->pci_mem_handle.pqi_btag,\
1025         _softs->pci_mem_handle.pqi_bhandle, _offset, buf, size)
1026
1027 /* Lock */
1028 typedef struct mtx OS_LOCK_T;
1029 typedef struct sema OS_SEMA_LOCK_T;
1030
1031 #define OS_PQILOCK_T OS_LOCK_T
1032
1033 #define OS_ACQUIRE_SPINLOCK(_lock) mtx_lock_spin(_lock)
1034 #define OS_RELEASE_SPINLOCK(_lock) mtx_unlock_spin(_lock)
1035
1036 #define OS_INIT_PQILOCK(_softs,_lock,_lockname) os_init_spinlock(_softs,_lock,_lockname)
1037 #define OS_UNINIT_PQILOCK(_lock) os_uninit_spinlock(_lock)
1038
1039 #define PQI_LOCK(_lock) OS_ACQUIRE_SPINLOCK(_lock)
1040 #define PQI_UNLOCK(_lock) OS_RELEASE_SPINLOCK(_lock)
1041
1042 #define OS_GET_CDBP(rcb) \
1043         ((rcb->cm_ccb->ccb_h.flags & CAM_CDB_POINTER) ? rcb->cm_ccb->csio.cdb_io.cdb_ptr : rcb->cm_ccb->csio.cdb_io.cdb_bytes)
1044 #define GET_SCSI_BUFFLEN(rcb)   (rcb->cm_ccb->csio.dxfer_len)
1045 #define IS_OS_SCSICMD(rcb)      (rcb && !rcb->tm_req && rcb->cm_ccb)
1046
1047 #define OS_GET_IO_QINDEX(softs,rcb)     curcpu % softs->num_op_obq
1048 #define OS_GET_IO_RESP_QID(softs,rcb)   (softs->op_ob_q[(OS_GET_IO_QINDEX(softs,rcb))].q_id)
1049 #define OS_GET_IO_REQ_QINDEX(softs,rcb) OS_GET_IO_QINDEX(softs,rcb)
1050 #define OS_GET_TMF_RESP_QID             OS_GET_IO_RESP_QID
1051 #define OS_GET_TMF_REQ_QINDEX           OS_GET_IO_REQ_QINDEX
1052
1053 /* check request type */
1054 #define is_internal_req(rcb)    (!(rcb->cm_ccb))
1055
1056 #define os_io_memcpy(dest, src, len)    memcpy(dest, src, len)
1057
1058 /* sg elements addr, len, flags */
1059 #define OS_GET_IO_SG_COUNT(rcb)         rcb->nseg
1060 #define OS_GET_IO_SG_ADDR(rcb,i)        rcb->sgt[i].addr
1061 #define OS_GET_IO_SG_LEN(rcb,i)         rcb->sgt[i].len
1062
1063 /* scsi commands used in pqilib for RAID bypass*/
1064 #define SCMD_READ_6     READ_6
1065 #define SCMD_WRITE_6    WRITE_6
1066 #define SCMD_READ_10    READ_10
1067 #define SCMD_WRITE_10   WRITE_10
1068 #define SCMD_READ_12    READ_12
1069 #define SCMD_WRITE_12   WRITE_12
1070 #define SCMD_READ_16    READ_16
1071 #define SCMD_WRITE_16   WRITE_16
1072
1073 /* FreeBSD status macros */
1074 #define BSD_SUCCESS     0
1075
1076
1077 /* Debug facility */
1078
1079 #define PQISRC_LOG_LEVEL  0x60
1080
1081 static int logging_level  = PQISRC_LOG_LEVEL;
1082
1083 #define PQISRC_FLAGS_MASK               0x0000ffff
1084 #define PQISRC_FLAGS_INIT               0x00000001
1085 #define PQISRC_FLAGS_INFO               0x00000002
1086 #define PQISRC_FLAGS_FUNC               0x00000004
1087 #define PQISRC_FLAGS_TRACEIO            0x00000008
1088 #define PQISRC_FLAGS_DISC               0x00000010
1089 #define PQISRC_FLAGS_WARN               0x00000020
1090 #define PQISRC_FLAGS_ERROR              0x00000040
1091 #define PQISRC_FLAGS_NOTE               0x00000080
1092
1093
1094 #define DBG_INIT(fmt,args...)                                           \
1095                 do {                                                    \
1096                         if (logging_level & PQISRC_FLAGS_INIT) {        \
1097                                 printf("[INIT]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args);                     \
1098                         }                                               \
1099                 }while(0);
1100
1101 #define DBG_INFO(fmt,args...)                                           \
1102                 do {                                                    \
1103                         if (logging_level & PQISRC_FLAGS_INFO) {        \
1104                                 printf("[INFO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args);                     \
1105                         }                                               \
1106                 }while(0);
1107
1108 #define DBG_FUNC(fmt,args...)                                           \
1109                 do {                                                    \
1110                         if (logging_level & PQISRC_FLAGS_FUNC) {        \
1111                                 printf("[FUNC]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args);                     \
1112                         }                                               \
1113                 }while(0);
1114
1115 #define DBG_TRACEIO(fmt,args...)                                        \
1116                 do {                                                    \
1117                         if (logging_level & PQISRC_FLAGS_TRACEIO) {     \
1118                                 printf("[TRACEIO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args);                  \
1119                         }                                               \
1120                 }while(0);
1121
1122 #define DBG_DISC(fmt,args...)                                           \
1123                 do {                                                    \
1124                         if (logging_level & PQISRC_FLAGS_DISC) {        \
1125                                 printf("[DISC]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args);                     \
1126                         }                                               \
1127                 }while(0);
1128
1129 #define DBG_WARN(fmt,args...)                                           \
1130                 do {                                                    \
1131                         if (logging_level & PQISRC_FLAGS_WARN) {        \
1132                                 printf("[WARN]:[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args);\
1133                         }                                               \
1134                 }while(0);
1135
1136 #define DBG_ERR(fmt,args...)                                            \
1137                 do {                                                    \
1138                         if (logging_level & PQISRC_FLAGS_ERROR) {       \
1139                                 printf("[ERROR]::[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args); \
1140                         }                                               \
1141                 }while(0);
1142 #define DBG_IO(fmt,args...)                                             \
1143                 do {                                                    \
1144                         if (logging_level & PQISRC_FLAGS_TRACEIO) {     \
1145                                 printf("[IO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args);                       \
1146                         }                                               \
1147                 }while(0);
1148
1149 #define DBG_ERR_BTL(device,fmt,args...)                                         \
1150                 do {                                                    \
1151                         if (logging_level & PQISRC_FLAGS_ERROR) {       \
1152                                 printf("[ERROR]::[%u:%u.%u][%u,%u,%u][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args); \
1153                         }                                               \
1154                 }while(0);
1155
1156 #define DBG_WARN_BTL(device,fmt,args...)                                                \
1157                 do {                                                    \
1158                         if (logging_level & PQISRC_FLAGS_WARN) {        \
1159                                 printf("[WARN]:[%u:%u.%u][%u,%u,%u][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args);\
1160                         }                                               \
1161                 }while(0);
1162
1163 #define DBG_NOTE(fmt,args...)                                           \
1164                 do {                                                    \
1165                         if (logging_level & PQISRC_FLAGS_NOTE) {        \
1166                                 printf("[INFO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args);                     \
1167                         }                                               \
1168                 }while(0);
1169
1170 #endif /* _PQI_DEFINES_H */