2 * Copyright (c) 2018 Microsemi Corporation.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _PQI_DEFINES_H
30 #define _PQI_DEFINES_H
32 #define PQI_STATUS_FAILURE -1
33 #define PQI_STATUS_TIMEOUT -2
34 #define PQI_STATUS_QFULL -3
35 #define PQI_STATUS_SUCCESS 0
37 #define PQISRC_CMD_TIMEOUT_CNT 1200000 /* 500usec * 1200000 = 5 min */
38 #define PQI_CMND_COMPLETE_TMO 1000 /* in millisecond */
40 #define INVALID_ELEM 0xffff
42 #define MIN(a,b) ((a) < (b) ? (a) : (b))
46 #define MAX(a,b) ((a) > (b) ? (a) : (b))
49 #define PQISRC_ROUNDUP(x, y) (((x) + (y) - 1) / (y) * (y))
50 #define PQISRC_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
52 #define ALIGN_BOUNDARY(a, n) { \
54 a = a + (n - a % n); \
57 /* Busy wait timeout on a condition */
58 #define COND_BUSYWAIT(cond, timeout /* in millisecond */) { \
69 /* Wait timeout on a condition*/
70 #define COND_WAIT(cond, timeout /* in millisecond */) { \
81 #define FILL_QUEUE_ARRAY_ADDR(q,virt,dma) { \
82 q->array_virt_addr = virt; \
83 q->array_dma_addr = dma; \
94 #define LOCKNAME_SIZE 32
96 #define INTR_TYPE_NONE 0x0
97 #define INTR_TYPE_FIXED 0x1
98 #define INTR_TYPE_MSI 0x2
99 #define INTR_TYPE_MSIX 0x4
100 #define SIS_ENABLE_MSIX 0x40
101 #define SIS_ENABLE_INTX 0x80
102 #define PQISRC_LEGACY_INTX_MASK 0x1
104 #define DMA_TO_VIRT(mem) ((mem)->virt_addr)
105 #define DMA_PHYS_LOW(mem) (((mem)->dma_addr) & 0x00000000ffffffff)
106 #define DMA_PHYS_HIGH(mem) ((((mem)->dma_addr) & 0xffffffff00000000) >> 32)
109 typedef enum REQUEST_STATUS {
111 REQUEST_PENDING = -1,
115 typedef enum IO_PATH {
120 typedef enum device_type
127 MEDIUM_CHANGER_DEVICE,
133 typedef enum controller_state {
139 #define PQISRC_MAX_MSIX_SUPPORTED 64
142 #define PQISRC_INIT_STRUCT_REVISION 9
143 #define PQISRC_SECTOR_SIZE 512
144 #define PQISRC_BLK_SIZE PQISRC_SECTOR_SIZE
145 #define PQISRC_DEFAULT_DMA_ALIGN 4
146 #define PQISRC_DMA_ALIGN_MASK (PQISRC_DEFAULT_DMA_ALIGN - 1)
147 #define PQISRC_ERR_BUF_DMA_ALIGN 32
148 #define PQISRC_ERR_BUF_ELEM_SIZE MAX(sizeof(raid_path_error_info_elem_t),sizeof(aio_path_error_info_elem_t))
149 #define PQISRC_INIT_STRUCT_DMA_ALIGN 16
151 #define SIS_CMD_GET_ADAPTER_PROPERTIES 0x19
152 #define SIS_CMD_GET_COMM_PREFERRED_SETTINGS 0x26
153 #define SIS_CMD_GET_PQI_CAPABILITIES 0x3000
154 #define SIS_CMD_INIT_BASE_STRUCT_ADDRESS 0x1b
156 #define SIS_SUPPORT_EXT_OPT 0x00800000
157 #define SIS_SUPPORT_PQI 0x00000004
158 #define SIS_SUPPORT_PQI_RESET_QUIESCE 0x00000008
160 #define SIS_PQI_RESET_QUIESCE 0x1000000
162 #define SIS_STATUS_OK_TIMEOUT 120000 /* in milli sec, 5 sec */
164 #define SIS_CMD_COMPLETE_TIMEOUT 30000 /* in milli sec, 30 secs */
165 #define SIS_POLL_START_WAIT_TIME 20000 /* in micro sec, 20 milli sec */
166 #define SIS_DB_BIT_CLEAR_TIMEOUT_CNT 120000 /* 500usec * 120000 = 60 sec */
168 #define SIS_ENABLE_TIMEOUT 3000
169 #define REENABLE_SIS 0x1
170 #define TRIGGER_NMI_SIS 0x800000
171 /*SIS Register status defines */
173 #define PQI_CTRL_KERNEL_UP_AND_RUNNING 0x80
174 #define PQI_CTRL_KERNEL_PANIC 0x100
176 #define SIS_CTL_TO_HOST_DB_DISABLE_ALL 0xFFFFFFFF
177 #define SIS_CTL_TO_HOST_DB_CLEAR 0x00001000
178 #define SIS_CMD_SUBMIT 0x00000200 /* Bit 9 */
179 #define SIS_CMD_COMPLETE 0x00001000 /* Bit 12 */
180 #define SIS_CMD_STATUS_SUCCESS 0x1
185 #define PQISRC_PQI_REG_OFFSET 0x4000
186 #define PQISRC_MAX_OUTSTANDING_REQ 4096
187 #define PQISRC_MAX_ADMIN_IB_QUEUE_ELEM_NUM 16
188 #define PQISRC_MAX_ADMIN_OB_QUEUE_ELEM_NUM 16
192 #define PQI_MIN_OP_IB_QUEUE_ID 1
193 #define PQI_OP_EVENT_QUEUE_ID 1
194 #define PQI_MIN_OP_OB_QUEUE_ID 2
196 #define PQISRC_MAX_SUPPORTED_OP_IB_Q 128
197 #define PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q (PQISRC_MAX_SUPPORTED_OP_IB_Q / 2)
198 #define PQISRC_MAX_SUPPORTED_OP_AIO_IB_Q (PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q)
199 #define PQISRC_MAX_OP_IB_QUEUE_ELEM_NUM (PQISRC_MAX_OUTSTANDING_REQ / PQISRC_MAX_SUPPORTED_OP_IB_Q)
200 #define PQISRC_MAX_OP_OB_QUEUE_ELEM_NUM PQISRC_MAX_OUTSTANDING_REQ
201 #define PQISRC_MIN_OP_OB_QUEUE_ELEM_NUM 2
202 #define PQISRC_MAX_SUPPORTED_OP_OB_Q 64
203 #define PQISRC_OP_MAX_IBQ_ELEM_SIZE 8 /* 8 * 16 = 128 bytes */
204 #define PQISRC_OP_MIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */
205 #define PQISRC_OP_OBQ_ELEM_SIZE 1 /* 16 bytes */
206 #define PQISRC_ADMIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */
207 #define PQISRC_INTR_COALSC_GRAN 0
208 #define PQISRC_PROTO_BIT_MASK 0
209 #define PQISRC_SGL_SUPPORTED_BIT_MASK 0
211 #define PQISRC_NUM_EVENT_Q_ELEM 32
212 #define PQISRC_EVENT_Q_ELEM_SIZE 32
214 /* PQI Registers state status */
216 #define PQI_RESET_ACTION_RESET 0x1
217 #define PQI_RESET_ACTION_COMPLETED 0x2
218 #define PQI_RESET_TYPE_NO_RESET 0x0
219 #define PQI_RESET_TYPE_SOFT_RESET 0x1
220 #define PQI_RESET_TYPE_FIRM_RESET 0x2
221 #define PQI_RESET_TYPE_HARD_RESET 0x3
223 #define PQI_RESET_POLL_INTERVAL 100000 /*100 msec*/
225 enum pqisrc_ctrl_mode{
230 /* PQI device performing internal initialization (e.g., POST). */
231 #define PQI_DEV_STATE_POWER_ON_AND_RESET 0x0
232 /* Upon entry to this state PQI device initialization begins. */
233 #define PQI_DEV_STATE_PQI_STATUS_AVAILABLE 0x1
234 /* PQI device Standard registers are available to the driver. */
235 #define PQI_DEV_STATE_ALL_REGISTERS_READY 0x2
236 /* PQI device is initialized and ready to process any PCI transactions. */
237 #define PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY 0x3
238 /* The PQI Device Error register indicates the error. */
239 #define PQI_DEV_STATE_ERROR 0x4
241 #define PQI_DEV_STATE_AT_INIT ( PQI_DEV_STATE_PQI_STATUS_AVAILABLE | \
242 PQI_DEV_STATE_ALL_REGISTERS_READY | \
243 PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY )
245 #define PQISRC_PQI_DEVICE_SIGNATURE "PQI DREG"
246 #define PQI_ADMINQ_ELEM_ARRAY_ALIGN 64
247 #define PQI_ADMINQ_CI_PI_ALIGN 64
248 #define PQI_OPQ_ELEM_ARRAY_ALIGN 64
249 #define PQI_OPQ_CI_PI_ALIGN 4
250 #define PQI_ADDR_ALIGN_MASK_64 0x3F /* lsb 6 bits */
251 #define PQI_ADDR_ALIGN_MASK_4 0x3 /* lsb 2 bits */
253 #define PQISRC_PQIMODE_READY_TIMEOUT (30 * 1000 ) /* 30 secs */
254 #define PQISRC_MODE_READY_POLL_INTERVAL 1000 /* 1 msec */
256 #define PRINT_PQI_SIGNATURE(sign) { int i = 0; \
259 si[i] = *((char *)&(sign)+i); \
261 DBG_INFO("Signature is %s",si); \
263 #define PQI_CONF_TABLE_MAX_LEN ((uint16_t)~0)
264 #define PQI_CONF_TABLE_SIGNATURE "CFGTABLE"
266 /* PQI configuration table section IDs */
267 #define PQI_CONF_TABLE_SECTION_GENERAL_INFO 0
268 #define PQI_CONF_TABLE_SECTION_FIRMWARE_FEATURES 1
269 #define PQI_CONF_TABLE_SECTION_FIRMWARE_ERRATA 2
270 #define PQI_CONF_TABLE_SECTION_DEBUG 3
271 #define PQI_CONF_TABLE_SECTION_HEARTBEAT 4
273 #define CTRLR_HEARTBEAT_CNT(softs) LE_64(PCI_MEM_GET64(softs, softs->heartbeat_counter_abs_addr, softs->heartbeat_counter_off))
274 #define PQI_NEW_HEARTBEAT_MECHANISM(softs) 1
276 /* pqi-2r00a table 36 */
277 #define PQI_ADMIN_QUEUE_MSIX_DISABLE (0x80000000)
278 #define PQI_ADMIN_QUEUE_MSIX_ENABLE (0 << 31)
280 #define PQI_ADMIN_QUEUE_CONF_FUNC_CREATE_Q_PAIR 0x01
281 #define PQI_ADMIN_QUEUE_CONF_FUNC_DEL_Q_PAIR 0x02
282 #define PQI_ADMIN_QUEUE_CONF_FUNC_STATUS_IDLE 0x00
283 #define PQISRC_ADMIN_QUEUE_CREATE_TIMEOUT 1000 /* in miLLI sec, 1 sec, 100 ms is standard */
284 #define PQISRC_ADMIN_QUEUE_DELETE_TIMEOUT 100 /* 100 ms is standard */
285 #define PQISRC_ADMIN_CMD_RESP_TIMEOUT 3000 /* 3 sec */
286 #define PQISRC_RAIDPATH_CMD_TIMEOUT 30000 /* 30 sec */
288 #define REPORT_PQI_DEV_CAP_DATA_BUF_SIZE sizeof(pqi_dev_cap_t)
289 #define REPORT_MANUFACTURER_INFO_DATA_BUF_SIZE 0x80 /* Data buffer size specified in bytes 0-1 of data buffer. 128 bytes. */
291 /* Admin IU request length not including header. */
292 #define PQI_STANDARD_IU_LENGTH 0x003C /* 60 bytes. */
293 #define PQI_IU_TYPE_GENERAL_ADMIN_REQUEST 0x60
294 #define PQI_IU_TYPE_GENERAL_ADMIN_RESPONSE 0xe0
296 /* PQI / Vendor specific IU */
297 #define PQI_FUNCTION_REPORT_DEV_CAP 0x00
298 #define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13
299 #define PQI_IU_TYPE_RAID_PATH_IO_REQUEST 0x14
300 #define PQI_IU_TYPE_AIO_PATH_IO_REQUEST 0x15
301 #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60
302 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72
303 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73
304 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
305 #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93
306 #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0
308 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0
309 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1
310 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2
311 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3
312 #define PQI_RESPONSE_IU_AIO_PATH_IS_OFF 0xf4
313 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
314 #define PQI_REQUEST_HEADER_LENGTH 4
315 #define PQI_FUNCTION_CREATE_OPERATIONAL_IQ 0x10
316 #define PQI_FUNCTION_CREATE_OPERATIONAL_OQ 0x11
317 #define PQI_FUNCTION_DELETE_OPERATIONAL_IQ 0x12
318 #define PQI_FUNCTION_DELETE_OPERATIONAL_OQ 0x13
319 #define PQI_FUNCTION_CHANGE_OPERATIONAL_IQ_PROP 0x14
320 #define PQI_CHANGE_OP_IQ_PROP_ASSIGN_AIO 1
322 #define PQI_DEFAULT_IB_QUEUE 0
323 /* Interface macros */
325 #define GET_FW_STATUS(softs) \
326 (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad3_fw_status, LEGACY_SIS_OMR))
328 #define SIS_IS_KERNEL_PANIC(softs) \
329 (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_PANIC)
331 #define SIS_IS_KERNEL_UP(softs) \
332 (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_UP_AND_RUNNING)
334 #define PQI_GET_CTRL_MODE(softs) \
335 (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0))
337 #define PQI_SAVE_CTRL_MODE(softs, mode) \
338 PCI_MEM_PUT32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0, mode)
340 #define PQISRC_MAX_TARGETID 1024
341 #define PQISRC_MAX_TARGETLUN 64
343 /* Vendor specific IU Type for Event config Cmds */
344 #define PQI_REQUEST_IU_REPORT_EVENT_CONFIG 0x72
345 #define PQI_REQUEST_IU_SET_EVENT_CONFIG 0x73
346 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
347 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
348 #define PQI_MANAGEMENT_CMD_RESP_TIMEOUT 3000
349 #define PQISRC_EVENT_ACK_RESP_TIMEOUT 1000
352 /* Supported Event types by controller */
353 #define PQI_NUM_SUPPORTED_EVENTS 7
355 #define PQI_EVENT_TYPE_HOTPLUG 0x1
356 #define PQI_EVENT_TYPE_HARDWARE 0x2
357 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4
358 #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5
359 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd
360 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe
361 #define PQI_EVENT_TYPE_HEARTBEAT 0xff
363 /* for indexing into the pending_events[] field of struct pqisrc_softstate */
364 #define PQI_EVENT_HEARTBEAT 0
365 #define PQI_EVENT_HOTPLUG 1
366 #define PQI_EVENT_HARDWARE 2
367 #define PQI_EVENT_PHYSICAL_DEVICE 3
368 #define PQI_EVENT_LOGICAL_DEVICE 4
369 #define PQI_EVENT_AIO_STATE_CHANGE 5
370 #define PQI_EVENT_AIO_CONFIG_CHANGE 6
372 #define PQI_MAX_HEARTBEAT_REQUESTS 5
376 #define PQISRC_DFLAG_VALID (1 << 0)
377 #define PQISRC_DFLAG_CONFIGURING (1 << 1)
379 #define MAX_EMBEDDED_SG_IN_FIRST_IU 4
380 #define MAX_EMBEDDED_SG_IN_IU 8
381 #define SG_FLAG_LAST 0x40000000
382 #define SG_FLAG_CHAIN 0x80000000
384 #define IN_PQI_RESET(softs) (softs->ctlr_state & PQI_BUS_RESET)
385 #define DEV_GONE(dev) (!dev || (dev->invalid == true))
386 #define IS_AIO_PATH(dev) (dev->aio_enabled)
387 #define IS_RAID_PATH(dev) (!dev->aio_enabled)
389 #define DEV_RESET(dvp) (dvp->reset_in_progress)
391 /* SOP data direction flags */
392 #define SOP_DATA_DIR_NONE 0x00
393 #define SOP_DATA_DIR_FROM_DEVICE 0x01
394 #define SOP_DATA_DIR_TO_DEVICE 0x02
395 #define SOP_DATA_DIR_BIDIRECTIONAL 0x03
396 #define SOP_PARTIAL_DATA_BUFFER 0x04
398 #define PQISRC_DMA_VALID (1 << 0)
399 #define PQISRC_CMD_NO_INTR (1 << 1)
401 #define SOP_TASK_ATTRIBUTE_SIMPLE 0
402 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1
403 #define SOP_TASK_ATTRIBUTE_ORDERED 2
404 #define SOP_TASK_ATTRIBUTE_ACA 4
406 #define SOP_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0
407 #define SOP_TASK_MANAGEMENT_FUNCTION_REJECTED 0x4
408 #define SOP_TASK_MANAGEMENT_FUNCTION_FAILED 0x5
409 #define SOP_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8
410 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK 0x01
411 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK_SET 0x02
412 #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8
415 /* Additional CDB bytes */
416 #define PQI_ADDITIONAL_CDB_BYTES_0 0 /* 16 byte CDB */
417 #define PQI_ADDITIONAL_CDB_BYTES_4 1 /* 20 byte CDB */
418 #define PQI_ADDITIONAL_CDB_BYTES_8 2 /* 24 byte CDB */
419 #define PQI_ADDITIONAL_CDB_BYTES_12 3 /* 28 byte CDB */
420 #define PQI_ADDITIONAL_CDB_BYTES_16 4 /* 32 byte CDB */
422 #define PQI_PROTOCOL_SOP 0x0
424 #define PQI_AIO_STATUS_GOOD 0x0
425 #define PQI_AIO_STATUS_CHECK_CONDITION 0x2
426 #define PQI_AIO_STATUS_CONDITION_MET 0x4
427 #define PQI_AIO_STATUS_DEVICE_BUSY 0x8
428 #define PQI_AIO_STATUS_INT_GOOD 0x10
429 #define PQI_AIO_STATUS_INT_COND_MET 0x14
430 #define PQI_AIO_STATUS_RESERV_CONFLICT 0x18
431 #define PQI_AIO_STATUS_CMD_TERMINATED 0x22
432 #define PQI_AIO_STATUS_QUEUE_FULL 0x28
433 #define PQI_AIO_STATUS_TASK_ABORTED 0x40
434 #define PQI_AIO_STATUS_UNDERRUN 0x51
435 #define PQI_AIO_STATUS_OVERRUN 0x75
436 /* Status when Target Failure */
437 #define PQI_AIO_STATUS_IO_ERROR 0x1
438 #define PQI_AIO_STATUS_IO_ABORTED 0x2
439 #define PQI_AIO_STATUS_IO_NO_DEVICE 0x3
440 #define PQI_AIO_STATUS_INVALID_DEVICE 0x4
441 #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe
443 /* Service Response */
444 #define PQI_AIO_SERV_RESPONSE_COMPLETE 0
445 #define PQI_AIO_SERV_RESPONSE_FAILURE 1
446 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2
447 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3
448 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4
449 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5
451 #define PQI_TMF_WAIT_DELAY 10000000 /* 10 seconds */
453 #define PQI_RAID_STATUS_GOOD PQI_AIO_STATUS_GOOD
454 #define PQI_RAID_STATUS_CHECK_CONDITION PQI_AIO_STATUS_CHECK_CONDITION
455 #define PQI_RAID_STATUS_CONDITION_MET PQI_AIO_STATUS_CONDITION_MET
456 #define PQI_RAID_STATUS_DEVICE_BUSY PQI_AIO_STATUS_DEVICE_BUSY
457 #define PQI_RAID_STATUS_INT_GOOD PQI_AIO_STATUS_INT_GOOD
458 #define PQI_RAID_STATUS_INT_COND_MET PQI_AIO_STATUS_INT_COND_MET
459 #define PQI_RAID_STATUS_RESERV_CONFLICT PQI_AIO_STATUS_RESERV_CONFLICT
460 #define PQI_RAID_STATUS_CMD_TERMINATED PQI_AIO_STATUS_CMD_TERMINATED
461 #define PQI_RAID_STATUS_QUEUE_FULL PQI_AIO_STATUS_QUEUE_FULL
462 #define PQI_RAID_STATUS_TASK_ABORTED PQI_AIO_STATUS_TASK_ABORTED
463 #define PQI_RAID_STATUS_UNDERRUN PQI_AIO_STATUS_UNDERRUN
464 #define PQI_RAID_STATUS_OVERRUN PQI_AIO_STATUS_OVERRUN
466 /* VPD inquiry pages */
467 #define SCSI_VPD_SUPPORTED_PAGES 0x0 /* standard page */
468 #define SCSI_VPD_DEVICE_ID 0x83 /* standard page */
469 #define SA_VPD_PHYS_DEVICE_ID 0xc0 /* vendor-specific page */
470 #define SA_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */
471 #define SA_VPD_LV_IOACCEL_STATUS 0xc2 /* vendor-specific page */
472 #define SA_VPD_LV_STATUS 0xc3 /* vendor-specific page */
474 #define VPD_PAGE (1 << 8)
477 /* logical volume states */
479 #define SA_LV_NOT_AVAILABLE 0xb
480 #define SA_LV_UNDERGOING_ERASE 0xf
481 #define SA_LV_UNDERGOING_RPI 0x12
482 #define SA_LV_PENDING_RPI 0x13
483 #define SA_LV_ENCRYPTED_NO_KEY 0x14
484 #define SA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15
485 #define SA_LV_UNDERGOING_ENCRYPTION 0x16
486 #define SA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17
487 #define SA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18
488 #define SA_LV_PENDING_ENCRYPTION 0x19
489 #define SA_LV_PENDING_ENCRYPTION_REKEYING 0x1a
490 #define SA_LV_STATUS_VPD_UNSUPPORTED 0xff
493 * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands
495 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27
498 #define PQI_LOGICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 0
502 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
504 #define SA_CACHE_FLUSH 0x1
505 #define SA_INQUIRY 0x12
506 #define SA_REPORT_LOG 0xc2 /* Report Logical LUNs */
507 #define SA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
508 #define SA_CISS_READ 0xc0
509 #define SA_GET_RAID_MAP 0xc8
511 #define SA_REPORT_LOG_EXTENDED 0x1
512 #define SA_REPORT_PHYS_EXTENDED 0x2
514 #define SA_CACHE_FLUSH_BUF_LEN 4
516 #define REPORT_LUN_DEV_FLAG_AIO_ENABLED 0x8
517 #define PQI_MAX_TRANSFER_SIZE (4 * 1024U * 1024U)
518 #define RAID_MAP_MAX_ENTRIES 1024
519 #define RAID_MAP_ENCRYPTION_ENABLED 0x1
520 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27
522 #define ASC_LUN_NOT_READY 0x4
523 #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x4
524 #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x2
527 #define OBDR_SIG_OFFSET 43
528 #define OBDR_TAPE_SIG "$DR-10"
529 #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
530 #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
533 #define IOACCEL_STATUS_BYTE 4
534 #define OFFLOAD_CONFIGURED_BIT 0x1
535 #define OFFLOAD_ENABLED_BIT 0x2
537 #define PQI_RAID_DATA_IN_OUT_GOOD 0x0
538 #define PQI_RAID_DATA_IN_OUT_UNDERFLOW 0x1
539 #define PQI_RAID_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3
540 #define PQI_RAID_DATA_IN_OUT_ABORTED 0xf4
542 #define PQI_PHYSICAL_DEVICE_BUS 0
543 #define PQI_RAID_VOLUME_BUS 1
544 #define PQI_HBA_BUS 2
545 #define PQI_EXTERNAL_RAID_VOLUME_BUS 3
546 #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS
548 #define TEST_UNIT_READY 0x00
549 #define SCSI_VPD_HEADER_LENGTH 64
552 #define PQI_MAX_MULTILUN 256
553 #define PQI_MAX_LOGICALS 64
554 #define PQI_MAX_PHYSICALS 1024
555 #define PQI_MAX_DEVICES (PQI_MAX_LOGICALS + PQI_MAX_PHYSICALS + 1) /* 1 for controller device entry */
556 #define PQI_MAX_EXT_TARGETS 32
558 #define PQI_CTLR_INDEX (PQI_MAX_DEVICES - 1)
559 #define PQI_PD_INDEX(t) (t + PQI_MAX_LOGICALS)
561 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
562 #define MAX_TARGET_DEVICES 1024
566 typedef enum pqisrc_device_status {
574 #define SA_RAID_1 2 /* also used for RAID 10 */
575 #define SA_RAID_5 3 /* also used for RAID 50 */
577 #define SA_RAID_6 5 /* also used for RAID 60 */
578 #define SA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
579 #define SA_RAID_MAX SA_RAID_ADM
580 #define SA_RAID_UNKNOWN 0xff
583 #define BMIC_IDENTIFY_CONTROLLER 0x11
584 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
585 #define BMIC_READ 0x26
586 #define BMIC_WRITE 0x27
587 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
588 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
589 #define BMIC_CACHE_FLUSH 0xc2
590 #define BMIC_FLASH_FIRMWARE 0xf7
591 #define BMIC_WRITE_HOST_WELLNESS 0xa5
594 #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xC0)
595 #define BMIC_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3F)
596 #define BMIC_GET_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
597 #define BMIC_GET_DRIVE_NUMBER(lunid) \
598 (((BMIC_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \
599 BMIC_GET_LEVEL_TWO_TARGET((lunid)))
600 #define NON_DISK_PHYS_DEV(rle) \
601 (((reportlun_ext_entry_t *)(rle))->device_flags & 0x1)
603 #define NO_TIMEOUT ((unsigned long) -1)
605 #define BMIC_DEVICE_TYPE_SATA 0x1
607 /* No of IO slots required for internal requests */
608 #define PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS 3
609 #define PQI_RESERVED_IO_SLOTS_TMF 1
610 #define PQI_RESERVED_IO_SLOTS_CNT (PQI_NUM_SUPPORTED_EVENTS + \
611 PQI_RESERVED_IO_SLOTS_TMF + \
612 PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS)
614 static inline uint16_t GET_LE16(const uint8_t *p)
616 return p[0] | p[1] << 8;
619 static inline uint32_t GET_LE32(const uint8_t *p)
621 return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
624 static inline uint64_t GET_LE64(const uint8_t *p)
626 return (((uint64_t)GET_LE32(p + 4) << 32) |
630 static inline uint16_t GET_BE16(const uint8_t *p)
632 return p[0] << 8 | p[1];
635 static inline uint32_t GET_BE32(const uint8_t *p)
637 return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3];
640 static inline uint64_t GET_BE64(const uint8_t *p)
642 return (((uint64_t)GET_BE32(p) << 32) |
646 static inline void PUT_BE16(uint16_t val, uint8_t *p)
652 static inline void PUT_BE32(uint32_t val, uint8_t *p)
654 PUT_BE16(val >> 16, p);
655 PUT_BE16(val, p + 2);
658 static inline void PUT_BE64(uint64_t val, uint8_t *p)
660 PUT_BE32(val >> 32, p);
661 PUT_BE32(val, p + 4);
666 #define SIS_POLL_WAIT
668 #define OS_ATTRIBUTE_PACKED __attribute__((__packed__))
669 #define OS_ATTRIBUTE_ALIGNED(n) __attribute__((aligned(n)))
672 /* Management Interface */
673 #define CCISS_IOC_MAGIC 'C'
674 #define SMARTPQI_IOCTL_BASE 'M'
675 #define CCISS_GETDRIVVER _IOWR(SMARTPQI_IOCTL_BASE, 0, driver_info)
676 #define CCISS_GETPCIINFO _IOWR(SMARTPQI_IOCTL_BASE, 1, pqi_pci_info_t)
677 #define SMARTPQI_PASS_THRU _IOWR(SMARTPQI_IOCTL_BASE, 2, IOCTL_Command_struct)
678 #define CCISS_PASSTHRU _IOWR('C', 210, IOCTL_Command_struct)
679 #define CCISS_REGNEWD _IO(CCISS_IOC_MAGIC, 14)
681 /*IOCTL pci_info structure */
682 typedef struct pqi_pci_info
685 unsigned char dev_fn;
686 unsigned short domain;
691 typedef struct _driver_info
693 unsigned char major_version;
694 unsigned char minor_version;
695 unsigned char release_version;
696 unsigned long build_revision;
697 unsigned long max_targets;
698 unsigned long max_io;
699 unsigned long max_transfer_length;
700 }driver_info, *pdriver_info;
702 typedef uint8_t *passthru_buf_type_t;
705 #define PQISRC_DRIVER_MAJOR 1
706 #define PQISRC_DRIVER_MINOR 0
707 #define PQISRC_DRIVER_RELEASE 3
708 #define PQISRC_DRIVER_REVISION 239
711 #define PQISRC_VERSION(a, b, c, d) STR(a.b.c-d)
712 #define PQISRC_DRIVER_VERSION PQISRC_VERSION(PQISRC_DRIVER_MAJOR, \
713 PQISRC_DRIVER_MINOR, \
714 PQISRC_DRIVER_RELEASE, \
715 PQISRC_DRIVER_REVISION)
717 /* End Management interface */
723 #define ASSERT(cond) {\
725 printf("Assertion failed at file %s line %d\n",__FILE__,__LINE__); \
730 #define PQI_MAX_MSIX 64 /* vectors */
731 #define PQI_MSI_CTX_SIZE sizeof(pqi_intr_ctx)+1
732 #define IS_POLLING_REQUIRED(softs) if (cold) {\
733 pqisrc_process_event_intr_src(softs, 0);\
734 pqisrc_process_response_queue(softs, 1);\
737 #define OS_GET_TASK_ATTR(rcb) os_get_task_attr(rcb)
738 #define OS_FW_HEARTBEAT_TIMER_INTERVAL (5)
740 typedef struct PCI_ACC_HANDLE {
741 bus_space_tag_t pqi_btag;
742 bus_space_handle_t pqi_bhandle;
746 * Legacy SIS Register definitions for the Adaptec PMC SRC/SRCv/smartraid adapters.
748 /* accessible via BAR0 */
749 #define LEGACY_SIS_IOAR 0x18 /* IOA->host interrupt register */
750 #define LEGACY_SIS_IDBR 0x20 /* inbound doorbell register */
751 #define LEGACY_SIS_IISR 0x24 /* inbound interrupt status register */
752 #define LEGACY_SIS_OIMR 0x34 /* outbound interrupt mask register */
753 #define LEGACY_SIS_ODBR_R 0x9c /* outbound doorbell register read */
754 #define LEGACY_SIS_ODBR_C 0xa0 /* outbound doorbell register clear */
756 #define LEGACY_SIS_SCR0 0xb0 /* scratchpad 0 */
757 #define LEGACY_SIS_OMR 0xbc /* outbound message register */
758 #define LEGACY_SIS_IQUE64_L 0xc0 /* inbound queue address 64-bit (low) */
759 #define LEGACY_SIS_IQUE64_H 0xc4 /* inbound queue address 64-bit (high)*/
760 #define LEGACY_SIS_ODBR_MSI 0xc8 /* MSI register for sync./AIF */
761 #define LEGACY_SIS_IQN_L 0xd0 /* inbound queue native mode (low) */
762 #define LEGACY_SIS_IQN_H 0xd4 /* inbound queue native mode (high)*/
763 #define LEGACY_SIS_MAILBOX 0x7fc60 /* mailbox (20 bytes) */
764 #define LEGACY_SIS_SRCV_MAILBOX 0x1000 /* mailbox (20 bytes) */
766 #define LEGACY_SIS_ODR_SHIFT 12 /* outbound doorbell shift */
767 #define LEGACY_SIS_IDR_SHIFT 9 /* inbound doorbell shift */
771 * PQI Register definitions for the smartraid adapters
773 /* accessible via BAR0 */
774 #define PQI_SIGNATURE 0x4000
775 #define PQI_ADMINQ_CONFIG 0x4008
776 #define PQI_ADMINQ_CAP 0x4010
777 #define PQI_LEGACY_INTR_STATUS 0x4018
778 #define PQI_LEGACY_INTR_MASK_SET 0x401C
779 #define PQI_LEGACY_INTR_MASK_CLR 0x4020
780 #define PQI_DEV_STATUS 0x4040
781 #define PQI_ADMIN_IBQ_PI_OFFSET 0x4048
782 #define PQI_ADMIN_OBQ_CI_OFFSET 0x4050
783 #define PQI_ADMIN_IBQ_ELEM_ARRAY_ADDR 0x4058
784 #define PQI_ADMIN_OBQ_ELEM_ARRAY_ADDR 0x4060
785 #define PQI_ADMIN_IBQ_CI_ADDR 0x4068
786 #define PQI_ADMIN_OBQ_PI_ADDR 0x4070
787 #define PQI_ADMINQ_PARAM 0x4078
788 #define PQI_DEV_ERR 0x4080
789 #define PQI_DEV_ERR_DETAILS 0x4088
790 #define PQI_DEV_RESET 0x4090
791 #define PQI_POWER_ACTION 0x4094
793 /* Busy wait micro seconds */
794 #define OS_BUSYWAIT(x) DELAY(x)
795 #define OS_SLEEP(timeout) \
798 #define OS_HOST_WELLNESS_TIMEOUT (24 * 3600)
801 #define LE_16(x) htole16(x)
802 #define LE_32(x) htole32(x)
803 #define LE_64(x) htole64(x)
804 #define BE_16(x) htobe16(x)
805 #define BE_32(x) htobe32(x)
806 #define BE_64(x) htobe64(x)
808 #define PQI_HWIF_SRCV 0
809 #define PQI_HWIF_UNKNOWN -1
812 #define SMART_STATE_SUSPEND (1<<0)
813 #define SMART_STATE_UNUSED0 (1<<1)
814 #define SMART_STATE_INTERRUPTS_ON (1<<2)
815 #define SMART_STATE_AIF_SLEEPER (1<<3)
816 #define SMART_STATE_RESET (1<<4)
818 #define PQI_FLAG_BUSY (1<<0)
819 #define PQI_MSI_ENABLED (1<<1)
820 #define PQI_SIM_REGISTERED (1<<2)
821 #define PQI_MTX_INIT (1<<3)
824 #define PQI_CMD_MAPPED (1<<2)
826 /* Interrupt context to get oq_id */
827 typedef struct pqi_intr_ctx {
832 typedef uint8_t os_dev_info_t;
834 typedef struct OS_SPECIFIC {
836 struct resource *pqi_regs_res0; /* reg. if. window */
837 int pqi_regs_rid0; /* resource ID */
838 bus_dma_tag_t pqi_parent_dmat; /* parent DMA tag */
839 bus_dma_tag_t pqi_buffer_dmat;
841 /* controller hardware interface */
843 struct resource *pqi_irq[PQI_MAX_MSIX]; /* interrupt */
844 int pqi_irq_rid[PQI_MAX_MSIX];
845 void *intrcookie[PQI_MAX_MSIX];
846 bool intr_registered[PQI_MAX_MSIX];
847 bool msi_enabled; /* MSI/MSI-X enabled */
848 pqi_intr_ctx_t *msi_ctx;
856 struct cam_devq *devq;
858 struct cam_path *path;
859 struct task event_task;
861 struct callout_handle wellness_periodic; /* periodic event handling */
862 struct callout_handle heartbeat_timeout_id; /* heart beat event handling */
866 typedef bus_addr_t dma_addr_t;
869 typedef volatile uint64_t OS_ATOMIC64_T;
870 #define OS_ATOMIC64_SET(_softs, target, val) atomic_set_long(&(_softs)->target, val)
871 #define OS_ATOMIC64_READ(_softs, target) atomic_load_acq_64(&(_softs)->target)
872 #define OS_ATOMIC64_INC(_softs, target) atomic_add_64(&(_softs)->target, 1)
874 /* Register access macros */
875 #define PCI_MEM_GET32( _softs, _absaddr, _offset ) \
876 bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \
877 _softs->pci_mem_handle.pqi_bhandle, _offset)
879 #define PCI_MEM_GET64( _softs, _absaddr, _offset ) \
880 bus_space_read_8(_softs->pci_mem_handle.pqi_btag, \
881 _softs->pci_mem_handle.pqi_bhandle, _offset)
883 #define PCI_MEM_PUT32( _softs, _absaddr, _offset, _val ) \
884 bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \
885 _softs->pci_mem_handle.pqi_bhandle, _offset, _val)
887 #define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \
888 bus_space_write_8(_softs->pci_mem_handle.pqi_btag, \
889 _softs->pci_mem_handle.pqi_bhandle, _offset, _val)
891 #define PCI_MEM_GET_BUF(_softs, _absaddr, _offset, buf, size) \
892 bus_space_read_region_1(_softs->pci_mem_handle.pqi_btag,\
893 _softs->pci_mem_handle.pqi_bhandle, _offset, buf, size)
896 typedef struct mtx OS_LOCK_T;
897 typedef struct sema OS_SEMA_LOCK_T;
899 #define OS_PQILOCK_T OS_LOCK_T
901 #define OS_ACQUIRE_SPINLOCK(_lock) mtx_lock_spin(_lock)
902 #define OS_RELEASE_SPINLOCK(_lock) mtx_unlock_spin(_lock)
904 #define OS_INIT_PQILOCK(_softs,_lock,_lockname) os_init_spinlock(_softs,_lock,_lockname)
905 #define OS_UNINIT_PQILOCK(_lock) os_uninit_spinlock(_lock)
907 #define PQI_LOCK(_lock) OS_ACQUIRE_SPINLOCK(_lock)
908 #define PQI_UNLOCK(_lock) OS_RELEASE_SPINLOCK(_lock)
910 #define OS_GET_CDBP(rcb) ((rcb->cm_ccb->ccb_h.flags & CAM_CDB_POINTER) ? rcb->cm_ccb->csio.cdb_io.cdb_ptr : rcb->cm_ccb->csio.cdb_io.cdb_bytes)
911 #define GET_SCSI_BUFFLEN(rcb) (rcb->cm_ccb->csio.dxfer_len)
913 #define OS_GET_IO_QINDEX(softs,rcb) curcpu % softs->num_op_obq
914 #define OS_GET_IO_RESP_QID(softs,rcb) (softs->op_ob_q[(OS_GET_IO_QINDEX(softs,rcb))].q_id)
915 #define OS_GET_IO_REQ_QINDEX(softs,rcb) OS_GET_IO_QINDEX(softs,rcb)
916 #define OS_GET_TMF_RESP_QID OS_GET_IO_RESP_QID
917 #define OS_GET_TMF_REQ_QINDEX OS_GET_IO_REQ_QINDEX
919 /* check request type */
920 #define is_internal_req(rcb) (!(rcb)->cm_ccb)
922 /* sg elements addr, len, flags */
923 #define OS_GET_IO_SG_COUNT(rcb) rcb->nseg
924 #define OS_GET_IO_SG_ADDR(rcb,i) rcb->sgt[i].addr
925 #define OS_GET_IO_SG_LEN(rcb,i) rcb->sgt[i].len
927 /* scsi commands used in pqilib for RAID bypass*/
928 #define SCMD_READ_6 READ_6
929 #define SCMD_WRITE_6 WRITE_6
930 #define SCMD_READ_10 READ_10
931 #define SCMD_WRITE_10 WRITE_10
932 #define SCMD_READ_12 READ_12
933 #define SCMD_WRITE_12 WRITE_12
934 #define SCMD_READ_16 READ_16
935 #define SCMD_WRITE_16 WRITE_16
939 #define PQISRC_LOG_LEVEL 0x60
941 static int logging_level = PQISRC_LOG_LEVEL;
943 #define PQISRC_FLAGS_MASK 0x0000ffff
944 #define PQISRC_FLAGS_INIT 0x00000001
945 #define PQISRC_FLAGS_INFO 0x00000002
946 #define PQISRC_FLAGS_FUNC 0x00000004
947 #define PQISRC_FLAGS_TRACEIO 0x00000008
948 #define PQISRC_FLAGS_DISC 0x00000010
949 #define PQISRC_FLAGS_WARN 0x00000020
950 #define PQISRC_FLAGS_ERROR 0x00000040
953 #define DBG_INIT(fmt,args...) \
955 if (logging_level & PQISRC_FLAGS_INIT) { \
956 printf("[INIT]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
960 #define DBG_INFO(fmt,args...) \
962 if (logging_level & PQISRC_FLAGS_INFO) { \
963 printf("[INFO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
967 #define DBG_FUNC(fmt,args...) \
969 if (logging_level & PQISRC_FLAGS_FUNC) { \
970 printf("[FUNC]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
974 #define DBG_TRACEIO(fmt,args...) \
976 if (logging_level & PQISRC_FLAGS_TRACEIO) { \
977 printf("[TRACEIO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
981 #define DBG_DISC(fmt,args...) \
983 if (logging_level & PQISRC_FLAGS_DISC) { \
984 printf("[DISC]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
988 #define DBG_WARN(fmt,args...) \
990 if (logging_level & PQISRC_FLAGS_WARN) { \
991 printf("[WARN]:[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args);\
995 #define DBG_ERR(fmt,args...) \
997 if (logging_level & PQISRC_FLAGS_ERROR) { \
998 printf("[ERROR]::[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args); \
1001 #define DBG_IO(fmt,args...) \
1003 if (logging_level & PQISRC_FLAGS_TRACEIO) { \
1004 printf("[IO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
1008 #define DBG_ERR_BTL(device,fmt,args...) \
1010 if (logging_level & PQISRC_FLAGS_ERROR) { \
1011 printf("[ERROR]::[%u:%u.%u][%u,%u,%u][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args); \
1015 #define DBG_WARN_BTL(device,fmt,args...) \
1017 if (logging_level & PQISRC_FLAGS_WARN) { \
1018 printf("[WARN]:[%u:%u.%u][%u,%u,%u][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args);\
1022 #endif // _PQI_DEFINES_H