2 * Copyright (c) 2018 Microsemi Corporation.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include "smartpqi_includes.h"
32 * Submit an admin IU to the adapter.
33 * Add interrupt support, if required
35 int pqisrc_submit_admin_req(pqisrc_softstate_t *softs,
36 gen_adm_req_iu_t *req, gen_adm_resp_iu_t *resp)
38 int ret = PQI_STATUS_SUCCESS;
39 ob_queue_t *ob_q = &softs->admin_ob_queue;
40 ib_queue_t *ib_q = &softs->admin_ib_queue;
41 int tmo = PQISRC_ADMIN_CMD_RESP_TIMEOUT;
46 PQI_IU_TYPE_GENERAL_ADMIN_REQUEST;
47 req->header.comp_feature = 0x00;
48 req->header.iu_length = PQI_STANDARD_IU_LENGTH;
53 req->req_id = pqisrc_get_tag(&softs->taglist);
54 if (INVALID_ELEM == req->req_id) {
55 DBG_ERR("Tag not available0x%x\n",(uint16_t)req->req_id);
56 ret = PQI_STATUS_FAILURE;
59 softs->rcb[req->req_id].tag = req->req_id;
61 /* Submit the command to the admin ib queue */
62 ret = pqisrc_submit_cmnd(softs, ib_q, req);
63 if (ret != PQI_STATUS_SUCCESS) {
64 DBG_ERR("Unable to submit command\n");
68 /* Wait for completion */
69 COND_WAIT((*(ob_q->pi_virt_addr) != ob_q->ci_local), tmo);
71 DBG_ERR("Admin cmd timeout\n");
72 DBG_ERR("tmo : %d\n",tmo); \
73 ret = PQI_STATUS_TIMEOUT;
77 /* Copy the response */
78 memcpy(resp, ob_q->array_virt_addr + (ob_q->ci_local * ob_q->elem_size),
79 sizeof(gen_adm_resp_iu_t));
82 ob_q->ci_local = (ob_q->ci_local + 1 ) % ob_q->num_elem;
83 PCI_MEM_PUT32(softs, ob_q->ci_register_abs,
84 ob_q->ci_register_offset, LE_32(ob_q->ci_local));
86 /* Validate the response data */
87 ASSERT(req->fn_code == resp->fn_code);
88 ASSERT(resp->header.iu_type == PQI_IU_TYPE_GENERAL_ADMIN_RESPONSE);
93 os_reset_rcb(&softs->rcb[req->req_id]);
94 pqisrc_put_tag(&softs->taglist,req->req_id);
98 os_reset_rcb(&softs->rcb[req->req_id]);
99 pqisrc_put_tag(&softs->taglist,req->req_id);
101 DBG_FUNC("failed OUT : %d\n", ret);
106 * Get the administration queue config parameters.
108 void pqisrc_get_admin_queue_config(pqisrc_softstate_t *softs)
112 val = LE_64(PCI_MEM_GET64(softs, &softs->pqi_reg->pqi_dev_adminq_cap, PQI_ADMINQ_CAP));
114 /* pqi_cap = (struct pqi_dev_adminq_cap *)&val;*/
115 softs->admin_ib_queue.num_elem = val & 0xFF;
116 softs->admin_ob_queue.num_elem = (val & 0xFF00) >> 8;
117 /* Note : size in unit of 16 byte s*/
118 softs->admin_ib_queue.elem_size = ((val & 0xFF0000) >> 16) * 16;
119 softs->admin_ob_queue.elem_size = ((val & 0xFF000000) >> 24) * 16;
121 DBG_FUNC(" softs->admin_ib_queue.num_elem : %d\n",
122 softs->admin_ib_queue.num_elem);
123 DBG_FUNC(" softs->admin_ib_queue.elem_size : %d\n",
124 softs->admin_ib_queue.elem_size);
128 * Decide the no of elements in admin ib and ob queues.
130 void pqisrc_decide_admin_queue_config(pqisrc_softstate_t *softs)
132 /* Determine num elements in Admin IBQ */
133 softs->admin_ib_queue.num_elem = MIN(softs->admin_ib_queue.num_elem,
134 PQISRC_MAX_ADMIN_IB_QUEUE_ELEM_NUM);
136 /* Determine num elements in Admin OBQ */
137 softs->admin_ob_queue.num_elem = MIN(softs->admin_ob_queue.num_elem,
138 PQISRC_MAX_ADMIN_OB_QUEUE_ELEM_NUM);
142 * Allocate DMA memory for admin queue and initialize.
144 int pqisrc_allocate_and_init_adminq(pqisrc_softstate_t *softs)
146 uint32_t ib_array_size = 0;
147 uint32_t ob_array_size = 0;
148 uint32_t alloc_size = 0;
149 char *virt_addr = NULL;
150 dma_addr_t dma_addr = 0;
151 int ret = PQI_STATUS_SUCCESS;
153 ib_array_size = (softs->admin_ib_queue.num_elem *
154 softs->admin_ib_queue.elem_size);
156 ob_array_size = (softs->admin_ob_queue.num_elem *
157 softs->admin_ob_queue.elem_size);
159 alloc_size = ib_array_size + ob_array_size +
160 2 * sizeof(uint32_t) + PQI_ADDR_ALIGN_MASK_64 + 1; /* for IB CI and OB PI */
161 /* Allocate memory for Admin Q */
162 softs->admin_queue_dma_mem.tag = "admin_queue";
163 softs->admin_queue_dma_mem.size = alloc_size;
164 softs->admin_queue_dma_mem.align = PQI_ADMINQ_ELEM_ARRAY_ALIGN;
165 ret = os_dma_mem_alloc(softs, &softs->admin_queue_dma_mem);
167 DBG_ERR("Failed to Allocate Admin Q ret : %d\n", ret);
171 /* Setup the address */
172 virt_addr = softs->admin_queue_dma_mem.virt_addr;
173 dma_addr = softs->admin_queue_dma_mem.dma_addr;
176 softs->admin_ib_queue.q_id = 0;
177 softs->admin_ib_queue.array_virt_addr = virt_addr;
178 softs->admin_ib_queue.array_dma_addr = dma_addr;
179 softs->admin_ib_queue.pi_local = 0;
181 softs->admin_ob_queue.q_id = 0;
182 softs->admin_ob_queue.array_virt_addr = virt_addr + ib_array_size;
183 softs->admin_ob_queue.array_dma_addr = dma_addr + ib_array_size;
184 softs->admin_ob_queue.ci_local = 0;
187 softs->admin_ib_queue.ci_virt_addr =
188 (uint32_t*)((uint8_t*)softs->admin_ob_queue.array_virt_addr
190 softs->admin_ib_queue.ci_dma_addr =
191 (dma_addr_t)((uint8_t*)softs->admin_ob_queue.array_dma_addr +
195 softs->admin_ob_queue.pi_virt_addr =
196 (uint32_t*)((uint8_t*)(softs->admin_ib_queue.ci_virt_addr) +
197 PQI_ADDR_ALIGN_MASK_64 + 1);
198 softs->admin_ob_queue.pi_dma_addr =
199 (dma_addr_t)((uint8_t*)(softs->admin_ib_queue.ci_dma_addr) +
200 PQI_ADDR_ALIGN_MASK_64 + 1);
202 DBG_INIT("softs->admin_ib_queue.ci_dma_addr : %p,softs->admin_ob_queue.pi_dma_addr :%p\n",
203 (void*)softs->admin_ib_queue.ci_dma_addr, (void*)softs->admin_ob_queue.pi_dma_addr );
205 /* Verify alignment */
206 ASSERT(!(softs->admin_ib_queue.array_dma_addr &
207 PQI_ADDR_ALIGN_MASK_64));
208 ASSERT(!(softs->admin_ib_queue.ci_dma_addr &
209 PQI_ADDR_ALIGN_MASK_64));
210 ASSERT(!(softs->admin_ob_queue.array_dma_addr &
211 PQI_ADDR_ALIGN_MASK_64));
212 ASSERT(!(softs->admin_ob_queue.pi_dma_addr &
213 PQI_ADDR_ALIGN_MASK_64));
219 DBG_FUNC("failed OUT\n");
220 return PQI_STATUS_FAILURE;
224 * Subroutine used to create (or) delete the admin queue requested.
226 int pqisrc_create_delete_adminq(pqisrc_softstate_t *softs,
230 int ret = PQI_STATUS_SUCCESS;
232 /* Create Admin Q pair writing to Admin Q config function reg */
234 PCI_MEM_PUT64(softs, &softs->pqi_reg->admin_q_config, PQI_ADMINQ_CONFIG, LE_64(cmd));
236 if (cmd == PQI_ADMIN_QUEUE_CONF_FUNC_CREATE_Q_PAIR)
237 tmo = PQISRC_ADMIN_QUEUE_CREATE_TIMEOUT;
239 tmo = PQISRC_ADMIN_QUEUE_DELETE_TIMEOUT;
241 /* Wait for completion */
242 COND_WAIT((PCI_MEM_GET64(softs, &softs->pqi_reg->admin_q_config, PQI_ADMINQ_CONFIG) ==
243 PQI_ADMIN_QUEUE_CONF_FUNC_STATUS_IDLE), tmo);
245 DBG_ERR("Unable to create/delete admin queue pair\n");
246 ret = PQI_STATUS_TIMEOUT;
253 * Debug admin queue configuration params.
255 void pqisrc_print_adminq_config(pqisrc_softstate_t *softs)
257 DBG_INFO(" softs->admin_ib_queue.array_dma_addr : %p\n",
258 (void*)softs->admin_ib_queue.array_dma_addr);
259 DBG_INFO(" softs->admin_ib_queue.array_virt_addr : %p\n",
260 (void*)softs->admin_ib_queue.array_virt_addr);
261 DBG_INFO(" softs->admin_ib_queue.num_elem : %d\n",
262 softs->admin_ib_queue.num_elem);
263 DBG_INFO(" softs->admin_ib_queue.elem_size : %d\n",
264 softs->admin_ib_queue.elem_size);
265 DBG_INFO(" softs->admin_ob_queue.array_dma_addr : %p\n",
266 (void*)softs->admin_ob_queue.array_dma_addr);
267 DBG_INFO(" softs->admin_ob_queue.array_virt_addr : %p\n",
268 (void*)softs->admin_ob_queue.array_virt_addr);
269 DBG_INFO(" softs->admin_ob_queue.num_elem : %d\n",
270 softs->admin_ob_queue.num_elem);
271 DBG_INFO(" softs->admin_ob_queue.elem_size : %d\n",
272 softs->admin_ob_queue.elem_size);
273 DBG_INFO(" softs->admin_ib_queue.pi_register_abs : %p\n",
274 (void*)softs->admin_ib_queue.pi_register_abs);
275 DBG_INFO(" softs->admin_ob_queue.ci_register_abs : %p\n",
276 (void*)softs->admin_ob_queue.ci_register_abs);
280 * Function used to create an admin queue.
282 int pqisrc_create_admin_queue(pqisrc_softstate_t *softs)
284 int ret = PQI_STATUS_SUCCESS;
285 uint32_t admin_q_param = 0;
289 /* Get admin queue details - pqi2-r00a - table 24 */
290 pqisrc_get_admin_queue_config(softs);
292 /* Decide admin Q config */
293 pqisrc_decide_admin_queue_config(softs);
295 /* Allocate and init Admin Q pair */
296 ret = pqisrc_allocate_and_init_adminq(softs);
298 DBG_ERR("Failed to Allocate Admin Q ret : %d\n", ret);
302 /* Write IB Q element array address */
303 PCI_MEM_PUT64(softs, &softs->pqi_reg->admin_ibq_elem_array_addr,
304 PQI_ADMIN_IBQ_ELEM_ARRAY_ADDR, LE_64(softs->admin_ib_queue.array_dma_addr));
306 /* Write OB Q element array address */
307 PCI_MEM_PUT64(softs, &softs->pqi_reg->admin_obq_elem_array_addr,
308 PQI_ADMIN_OBQ_ELEM_ARRAY_ADDR, LE_64(softs->admin_ob_queue.array_dma_addr));
310 /* Write IB Q CI address */
311 PCI_MEM_PUT64(softs, &softs->pqi_reg->admin_ibq_ci_addr,
312 PQI_ADMIN_IBQ_CI_ADDR, LE_64(softs->admin_ib_queue.ci_dma_addr));
314 /* Write OB Q PI address */
315 PCI_MEM_PUT64(softs, &softs->pqi_reg->admin_obq_pi_addr,
316 PQI_ADMIN_OBQ_PI_ADDR, LE_64(softs->admin_ob_queue.pi_dma_addr));
318 /* Write Admin Q params pqi-r200a table 36 */
320 admin_q_param = softs->admin_ib_queue.num_elem |
321 (softs->admin_ob_queue.num_elem << 8)|
322 PQI_ADMIN_QUEUE_MSIX_DISABLE;
324 PCI_MEM_PUT32(softs, &softs->pqi_reg->admin_q_param,
325 PQI_ADMINQ_PARAM, LE_32(admin_q_param));
327 /* Submit cmd to create Admin Q pair */
328 ret = pqisrc_create_delete_adminq(softs,
329 PQI_ADMIN_QUEUE_CONF_FUNC_CREATE_Q_PAIR);
331 DBG_ERR("Failed to Allocate Admin Q ret : %d\n", ret);
335 /* Admin queue created, get ci,pi offset */
336 softs->admin_ib_queue.pi_register_offset =(PQISRC_PQI_REG_OFFSET +
337 PCI_MEM_GET64(softs, &softs->pqi_reg->admin_ibq_pi_offset, PQI_ADMIN_IBQ_PI_OFFSET));
339 softs->admin_ib_queue.pi_register_abs =(uint32_t *)(softs->pci_mem_base_vaddr +
340 softs->admin_ib_queue.pi_register_offset);
342 softs->admin_ob_queue.ci_register_offset = (PQISRC_PQI_REG_OFFSET +
343 PCI_MEM_GET64(softs, &softs->pqi_reg->admin_obq_ci_offset, PQI_ADMIN_OBQ_CI_OFFSET));
345 softs->admin_ob_queue.ci_register_abs = (uint32_t *)(softs->pci_mem_base_vaddr +
346 softs->admin_ob_queue.ci_register_offset);
348 os_strlcpy(softs->admin_ib_queue.lockname, "admin_ibqlock", LOCKNAME_SIZE);
350 ret =OS_INIT_PQILOCK(softs, &softs->admin_ib_queue.lock,
351 softs->admin_ib_queue.lockname);
353 DBG_ERR("Admin spinlock initialization failed\n");
354 softs->admin_ib_queue.lockcreated = false;
357 softs->admin_ib_queue.lockcreated = true;
359 /* Print admin q config details */
360 pqisrc_print_adminq_config(softs);
367 os_dma_mem_free(softs, &softs->admin_queue_dma_mem);
369 DBG_FUNC("failed OUT\n");
374 * Subroutine used to delete an operational queue.
376 int pqisrc_delete_op_queue(pqisrc_softstate_t *softs,
377 uint32_t q_id, boolean_t ibq)
379 int ret = PQI_STATUS_SUCCESS;
380 /* Firmware doesn't support this now */
383 gen_adm_req_iu_t admin_req;
384 gen_adm_resp_iu_t admin_resp;
386 memset(&admin_req, 0, sizeof(admin_req));
387 memset(&admin_resp, 0, sizeof(admin_resp));
391 admin_req.req_type.create_op_iq.qid = q_id;
394 admin_req.fn_code = PQI_FUNCTION_DELETE_OPERATIONAL_IQ;
396 admin_req.fn_code = PQI_FUNCTION_DELETE_OPERATIONAL_OQ;
398 ret = pqisrc_submit_admin_req(softs, &admin_req, &admin_resp);
406 * Function used to destroy the event queue.
408 void pqisrc_destroy_event_queue(pqisrc_softstate_t *softs)
412 if (softs->event_q.created == true) {
413 int ret = PQI_STATUS_SUCCESS;
414 ret = pqisrc_delete_op_queue(softs, softs->event_q.q_id, false);
416 DBG_ERR("Failed to Delete Event Q %d\n", softs->event_q.q_id);
418 softs->event_q.created = false;
421 /* Free the memory */
422 os_dma_mem_free(softs, &softs->event_q_dma_mem);
428 * Function used to destroy operational ib queues.
430 void pqisrc_destroy_op_ib_queues(pqisrc_softstate_t *softs)
432 int ret = PQI_STATUS_SUCCESS;
433 ib_queue_t *op_ib_q = NULL;
438 for (i = 0; i < softs->num_op_raid_ibq; i++) {
440 op_ib_q = &softs->op_raid_ib_q[i];
441 if (op_ib_q->created == true) {
442 ret = pqisrc_delete_op_queue(softs, op_ib_q->q_id, true);
444 DBG_ERR("Failed to Delete Raid IB Q %d\n",op_ib_q->q_id);
446 op_ib_q->created = false;
449 if(op_ib_q->lockcreated==true){
450 OS_UNINIT_PQILOCK(&op_ib_q->lock);
451 op_ib_q->lockcreated = false;
455 op_ib_q = &softs->op_aio_ib_q[i];
456 if (op_ib_q->created == true) {
457 ret = pqisrc_delete_op_queue(softs, op_ib_q->q_id, true);
459 DBG_ERR("Failed to Delete AIO IB Q %d\n",op_ib_q->q_id);
461 op_ib_q->created = false;
464 if(op_ib_q->lockcreated==true){
465 OS_UNINIT_PQILOCK(&op_ib_q->lock);
466 op_ib_q->lockcreated = false;
470 /* Free the memory */
471 os_dma_mem_free(softs, &softs->op_ibq_dma_mem);
476 * Function used to destroy operational ob queues.
478 void pqisrc_destroy_op_ob_queues(pqisrc_softstate_t *softs)
480 int ret = PQI_STATUS_SUCCESS;
485 for (i = 0; i < softs->num_op_obq; i++) {
486 ob_queue_t *op_ob_q = NULL;
487 op_ob_q = &softs->op_ob_q[i];
488 if (op_ob_q->created == true) {
489 ret = pqisrc_delete_op_queue(softs, op_ob_q->q_id, false);
491 DBG_ERR("Failed to Delete OB Q %d\n",op_ob_q->q_id);
493 op_ob_q->created = false;
497 /* Free the memory */
498 os_dma_mem_free(softs, &softs->op_obq_dma_mem);
503 * Function used to destroy an admin queue.
505 int pqisrc_destroy_admin_queue(pqisrc_softstate_t *softs)
507 int ret = PQI_STATUS_SUCCESS;
511 ret = pqisrc_create_delete_adminq(softs,
512 PQI_ADMIN_QUEUE_CONF_FUNC_DEL_Q_PAIR);
514 os_dma_mem_free(softs, &softs->admin_queue_dma_mem);
521 * Function used to change operational ib queue properties.
523 int pqisrc_change_op_ibq_queue_prop(pqisrc_softstate_t *softs,
524 ib_queue_t *op_ib_q, uint32_t prop)
526 int ret = PQI_STATUS_SUCCESS;
527 gen_adm_req_iu_t admin_req;
528 gen_adm_resp_iu_t admin_resp;
530 memset(&admin_req, 0, sizeof(admin_req));
531 memset(&admin_resp, 0, sizeof(admin_resp));
535 admin_req.fn_code = PQI_FUNCTION_CHANGE_OPERATIONAL_IQ_PROP;
536 admin_req.req_type.change_op_iq_prop.qid = op_ib_q->q_id;
537 admin_req.req_type.change_op_iq_prop.vend_specific = prop;
539 ret = pqisrc_submit_admin_req(softs, &admin_req, &admin_resp);
546 * Function used to create an operational ob queue.
548 int pqisrc_create_op_obq(pqisrc_softstate_t *softs,
551 int ret = PQI_STATUS_SUCCESS;
552 gen_adm_req_iu_t admin_req;
553 gen_adm_resp_iu_t admin_resp;
557 memset(&admin_req, 0, sizeof(admin_req));
558 memset(&admin_resp, 0, sizeof(admin_resp));
560 admin_req.fn_code = PQI_FUNCTION_CREATE_OPERATIONAL_OQ;
561 admin_req.req_type.create_op_oq.qid = op_ob_q->q_id;
562 admin_req.req_type.create_op_oq.intr_msg_num = op_ob_q->intr_msg_num;
563 admin_req.req_type.create_op_oq.elem_arr_addr = op_ob_q->array_dma_addr;
564 admin_req.req_type.create_op_oq.ob_pi_addr = op_ob_q->pi_dma_addr;
565 admin_req.req_type.create_op_oq.num_elem = op_ob_q->num_elem;
566 admin_req.req_type.create_op_oq.elem_len = op_ob_q->elem_size / 16;
568 DBG_INFO("admin_req.req_type.create_op_oq.qid : %x\n",admin_req.req_type.create_op_oq.qid);
569 DBG_INFO("admin_req.req_type.create_op_oq.intr_msg_num : %x\n", admin_req.req_type.create_op_oq.intr_msg_num );
571 ret = pqisrc_submit_admin_req(softs, &admin_req, &admin_resp);
572 if( PQI_STATUS_SUCCESS == ret) {
573 op_ob_q->ci_register_offset = (PQISRC_PQI_REG_OFFSET +
574 admin_resp.resp_type.create_op_oq.ci_offset);
575 op_ob_q->ci_register_abs = (uint32_t *)(softs->pci_mem_base_vaddr +
576 op_ob_q->ci_register_offset);
579 DBG_WARN("Error Status Descriptors\n");
580 for(i = 0; i < 4;i++)
581 DBG_WARN(" %x ",admin_resp.resp_type.create_op_oq.status_desc[i]);
584 DBG_FUNC("OUT ret : %d\n", ret);
590 * Function used to create an operational ib queue.
592 int pqisrc_create_op_ibq(pqisrc_softstate_t *softs,
595 int ret = PQI_STATUS_SUCCESS;
596 gen_adm_req_iu_t admin_req;
597 gen_adm_resp_iu_t admin_resp;
601 memset(&admin_req, 0, sizeof(admin_req));
602 memset(&admin_resp, 0, sizeof(admin_resp));
604 admin_req.fn_code = PQI_FUNCTION_CREATE_OPERATIONAL_IQ;
605 admin_req.req_type.create_op_iq.qid = op_ib_q->q_id;
606 admin_req.req_type.create_op_iq.elem_arr_addr = op_ib_q->array_dma_addr;
607 admin_req.req_type.create_op_iq.iq_ci_addr = op_ib_q->ci_dma_addr;
608 admin_req.req_type.create_op_iq.num_elem = op_ib_q->num_elem;
609 admin_req.req_type.create_op_iq.elem_len = op_ib_q->elem_size / 16;
611 ret = pqisrc_submit_admin_req(softs, &admin_req, &admin_resp);
613 if( PQI_STATUS_SUCCESS == ret) {
614 op_ib_q->pi_register_offset =(PQISRC_PQI_REG_OFFSET +
615 admin_resp.resp_type.create_op_iq.pi_offset);
617 op_ib_q->pi_register_abs =(uint32_t *)(softs->pci_mem_base_vaddr +
618 op_ib_q->pi_register_offset);
621 DBG_WARN("Error Status Decsriptors\n");
622 for(i = 0; i < 4;i++)
623 DBG_WARN(" %x ",admin_resp.resp_type.create_op_iq.status_desc[i]);
626 DBG_FUNC("OUT ret : %d\n", ret);
631 * subroutine used to create an operational ib queue for AIO.
633 int pqisrc_create_op_aio_ibq(pqisrc_softstate_t *softs,
634 ib_queue_t *op_aio_ib_q)
636 int ret = PQI_STATUS_SUCCESS;
640 ret = pqisrc_create_op_ibq(softs,op_aio_ib_q);
641 if ( PQI_STATUS_SUCCESS == ret)
642 ret = pqisrc_change_op_ibq_queue_prop(softs,
643 op_aio_ib_q, PQI_CHANGE_OP_IQ_PROP_ASSIGN_AIO);
645 DBG_FUNC("OUT ret : %d\n", ret);
650 * subroutine used to create an operational ib queue for RAID.
652 int pqisrc_create_op_raid_ibq(pqisrc_softstate_t *softs,
653 ib_queue_t *op_raid_ib_q)
655 int ret = PQI_STATUS_SUCCESS;
659 ret = pqisrc_create_op_ibq(softs,op_raid_ib_q);
666 * Allocate and create an event queue to process supported events.
668 int pqisrc_alloc_and_create_event_queue(pqisrc_softstate_t *softs)
670 int ret = PQI_STATUS_SUCCESS;
671 uint32_t alloc_size = 0;
673 char *virt_addr = NULL;
674 dma_addr_t dma_addr = 0;
675 uint32_t event_q_pi_dma_start_offset = 0;
676 uint32_t event_q_pi_virt_start_offset = 0;
677 char *event_q_pi_virt_start_addr = NULL;
678 ob_queue_t *event_q = NULL;
683 * Calculate memory requirements.
684 * If event queue is shared for IO response, number of
685 * elements in event queue depends on num elements in OP OB Q
686 * also. Since event queue element size (32) is more than IO
687 * response size , event queue element size need not be checked
688 * for queue size calculation.
690 #ifdef SHARE_EVENT_QUEUE_FOR_IO
691 num_elem = MIN(softs->num_elem_per_op_obq, PQISRC_NUM_EVENT_Q_ELEM);
693 num_elem = PQISRC_NUM_EVENT_Q_ELEM;
696 alloc_size = num_elem * PQISRC_EVENT_Q_ELEM_SIZE;
697 event_q_pi_dma_start_offset = alloc_size;
698 event_q_pi_virt_start_offset = alloc_size;
699 alloc_size += sizeof(uint32_t); /*For IBQ CI*/
701 /* Allocate memory for event queues */
702 softs->event_q_dma_mem.tag = "event_queue";
703 softs->event_q_dma_mem.size = alloc_size;
704 softs->event_q_dma_mem.align = PQI_OPQ_ELEM_ARRAY_ALIGN;
705 ret = os_dma_mem_alloc(softs, &softs->event_q_dma_mem);
707 DBG_ERR("Failed to Allocate Event Q ret : %d\n"
712 /* Set up the address */
713 virt_addr = softs->event_q_dma_mem.virt_addr;
714 dma_addr = softs->event_q_dma_mem.dma_addr;
715 event_q_pi_dma_start_offset += dma_addr;
716 event_q_pi_virt_start_addr = virt_addr + event_q_pi_virt_start_offset;
718 event_q = &softs->event_q;
719 ASSERT(!(dma_addr & PQI_ADDR_ALIGN_MASK_64));
720 FILL_QUEUE_ARRAY_ADDR(event_q,virt_addr,dma_addr);
721 event_q->q_id = PQI_OP_EVENT_QUEUE_ID;
722 event_q->num_elem = num_elem;
723 event_q->elem_size = PQISRC_EVENT_Q_ELEM_SIZE;
724 event_q->pi_dma_addr = event_q_pi_dma_start_offset;
725 event_q->pi_virt_addr = (uint32_t *)event_q_pi_virt_start_addr;
726 event_q->intr_msg_num = 0; /* vector zero for event */
727 ASSERT(!(event_q->pi_dma_addr & PQI_ADDR_ALIGN_MASK_4));
729 ret = pqisrc_create_op_obq(softs,event_q);
731 DBG_ERR("Failed to Create EventQ %d\n",event_q->q_id);
734 event_q->created = true;
740 pqisrc_destroy_event_queue(softs);
742 DBG_FUNC("OUT failed %d\n", ret);
743 return PQI_STATUS_FAILURE;
747 * Allocate DMA memory and create operational ib queues.
749 int pqisrc_alloc_and_create_ib_queues(pqisrc_softstate_t *softs)
751 int ret = PQI_STATUS_SUCCESS;
752 uint32_t alloc_size = 0;
753 char *virt_addr = NULL;
754 dma_addr_t dma_addr = 0;
755 uint32_t ibq_size = 0;
756 uint32_t ib_ci_dma_start_offset = 0;
757 char *ib_ci_virt_start_addr = NULL;
758 uint32_t ib_ci_virt_start_offset = 0;
759 uint32_t ibq_id = PQI_MIN_OP_IB_QUEUE_ID;
760 ib_queue_t *op_ib_q = NULL;
761 uint32_t num_op_ibq = softs->num_op_raid_ibq +
762 softs->num_op_aio_ibq;
767 /* Calculate memory requirements */
768 ibq_size = softs->num_elem_per_op_ibq * softs->ibq_elem_size;
769 alloc_size = num_op_ibq * ibq_size;
770 /* CI indexes starts after Queue element array */
771 ib_ci_dma_start_offset = alloc_size;
772 ib_ci_virt_start_offset = alloc_size;
773 alloc_size += num_op_ibq * sizeof(uint32_t); /*For IBQ CI*/
775 /* Allocate memory for IB queues */
776 softs->op_ibq_dma_mem.tag = "op_ib_queue";
777 softs->op_ibq_dma_mem.size = alloc_size;
778 softs->op_ibq_dma_mem.align = PQI_OPQ_ELEM_ARRAY_ALIGN;
779 ret = os_dma_mem_alloc(softs, &softs->op_ibq_dma_mem);
781 DBG_ERR("Failed to Allocate Operational IBQ memory ret : %d\n",
786 /* Set up the address */
787 virt_addr = softs->op_ibq_dma_mem.virt_addr;
788 dma_addr = softs->op_ibq_dma_mem.dma_addr;
789 ib_ci_dma_start_offset += dma_addr;
790 ib_ci_virt_start_addr = virt_addr + ib_ci_virt_start_offset;
792 ASSERT(softs->num_op_raid_ibq == softs->num_op_aio_ibq);
794 for (i = 0; i < softs->num_op_raid_ibq; i++) {
796 op_ib_q = &softs->op_raid_ib_q[i];
797 ASSERT(!(dma_addr & PQI_ADDR_ALIGN_MASK_64));
798 FILL_QUEUE_ARRAY_ADDR(op_ib_q,virt_addr,dma_addr);
799 op_ib_q->q_id = ibq_id++;
801 snprintf(op_ib_q->lockname, LOCKNAME_SIZE, "raid_ibqlock%d", i);
802 ret = OS_INIT_PQILOCK(softs, &op_ib_q->lock, op_ib_q->lockname);
804 DBG_ERR("raid_ibqlock %d init failed\n", i);
805 op_ib_q->lockcreated = false;
808 op_ib_q->lockcreated = true;
809 op_ib_q->num_elem = softs->num_elem_per_op_ibq;
810 op_ib_q->elem_size = softs->ibq_elem_size;
811 op_ib_q->ci_dma_addr = ib_ci_dma_start_offset +
812 (2 * i * sizeof(uint32_t));
813 op_ib_q->ci_virt_addr = (uint32_t*)(ib_ci_virt_start_addr +
814 (2 * i * sizeof(uint32_t)));
815 ASSERT(!(op_ib_q->ci_dma_addr & PQI_ADDR_ALIGN_MASK_4));
816 ret = pqisrc_create_op_raid_ibq(softs, op_ib_q);
818 DBG_ERR("[ %s ] Failed to Create OP Raid IBQ %d\n",
819 __func__, op_ib_q->q_id);
822 op_ib_q->created = true;
825 virt_addr += ibq_size;
826 dma_addr += ibq_size;
827 op_ib_q = &softs->op_aio_ib_q[i];
828 ASSERT(!(dma_addr & PQI_ADDR_ALIGN_MASK_64));
829 FILL_QUEUE_ARRAY_ADDR(op_ib_q,virt_addr,dma_addr);
830 op_ib_q->q_id = ibq_id++;
831 snprintf(op_ib_q->lockname, LOCKNAME_SIZE, "aio_ibqlock%d", i);
832 ret = OS_INIT_PQILOCK(softs, &op_ib_q->lock, op_ib_q->lockname);
834 DBG_ERR("aio_ibqlock %d init failed\n", i);
835 op_ib_q->lockcreated = false;
838 op_ib_q->lockcreated = true;
839 op_ib_q->num_elem = softs->num_elem_per_op_ibq;
840 op_ib_q->elem_size = softs->ibq_elem_size;
841 op_ib_q->ci_dma_addr = ib_ci_dma_start_offset +
842 (((2 * i) + 1) * sizeof(uint32_t));
843 op_ib_q->ci_virt_addr = (uint32_t*)(ib_ci_virt_start_addr +
844 (((2 * i) + 1) * sizeof(uint32_t)));
845 ASSERT(!(op_ib_q->ci_dma_addr & PQI_ADDR_ALIGN_MASK_4));
846 ret = pqisrc_create_op_aio_ibq(softs, op_ib_q);
848 DBG_ERR("Failed to Create OP AIO IBQ %d\n",op_ib_q->q_id);
851 op_ib_q->created = true;
853 virt_addr += ibq_size;
854 dma_addr += ibq_size;
862 pqisrc_destroy_op_ib_queues(softs);
864 DBG_FUNC("OUT failed %d\n", ret);
865 return PQI_STATUS_FAILURE;
869 * Allocate DMA memory and create operational ob queues.
871 int pqisrc_alloc_and_create_ob_queues(pqisrc_softstate_t *softs)
873 int ret = PQI_STATUS_SUCCESS;
874 uint32_t alloc_size = 0;
875 char *virt_addr = NULL;
876 dma_addr_t dma_addr = 0;
877 uint32_t obq_size = 0;
878 uint32_t ob_pi_dma_start_offset = 0;
879 uint32_t ob_pi_virt_start_offset = 0;
880 char *ob_pi_virt_start_addr = NULL;
881 uint32_t obq_id = PQI_MIN_OP_OB_QUEUE_ID;
882 ob_queue_t *op_ob_q = NULL;
883 uint32_t num_op_obq = softs->num_op_obq;
889 * OB Q element array should be 64 byte aligned.
890 * So the number of elements in OB Q should be multiple
891 * of 4, so that OB Queue element size (16) * num elements
892 * will be multiple of 64.
895 ALIGN_BOUNDARY(softs->num_elem_per_op_obq, 4);
896 obq_size = softs->num_elem_per_op_obq * softs->obq_elem_size;
897 alloc_size += num_op_obq * obq_size;
898 /* PI indexes starts after Queue element array */
899 ob_pi_dma_start_offset = alloc_size;
900 ob_pi_virt_start_offset = alloc_size;
901 alloc_size += num_op_obq * sizeof(uint32_t); /*For OBQ PI*/
903 /* Allocate memory for OB queues */
904 softs->op_obq_dma_mem.tag = "op_ob_queue";
905 softs->op_obq_dma_mem.size = alloc_size;
906 softs->op_obq_dma_mem.align = PQI_OPQ_ELEM_ARRAY_ALIGN;
907 ret = os_dma_mem_alloc(softs, &softs->op_obq_dma_mem);
909 DBG_ERR("Failed to Allocate Operational OBQ memory ret : %d\n",
914 /* Set up the address */
915 virt_addr = softs->op_obq_dma_mem.virt_addr;
916 dma_addr = softs->op_obq_dma_mem.dma_addr;
917 ob_pi_dma_start_offset += dma_addr;
918 ob_pi_virt_start_addr = virt_addr + ob_pi_virt_start_offset;
920 DBG_INFO("softs->num_op_obq %d\n",softs->num_op_obq);
922 for (i = 0; i < softs->num_op_obq; i++) {
923 op_ob_q = &softs->op_ob_q[i];
924 ASSERT(!(dma_addr & PQI_ADDR_ALIGN_MASK_64));
925 FILL_QUEUE_ARRAY_ADDR(op_ob_q,virt_addr,dma_addr);
926 op_ob_q->q_id = obq_id++;
927 if(softs->share_opq_and_eventq == true)
928 op_ob_q->intr_msg_num = i;
930 op_ob_q->intr_msg_num = i + 1; /* msg num zero for event */
931 op_ob_q->num_elem = softs->num_elem_per_op_obq;
932 op_ob_q->elem_size = softs->obq_elem_size;
933 op_ob_q->pi_dma_addr = ob_pi_dma_start_offset +
934 (i * sizeof(uint32_t));
935 op_ob_q->pi_virt_addr = (uint32_t*)(ob_pi_virt_start_addr +
936 (i * sizeof(uint32_t)));
937 ASSERT(!(op_ob_q->pi_dma_addr & PQI_ADDR_ALIGN_MASK_4));
939 ret = pqisrc_create_op_obq(softs,op_ob_q);
941 DBG_ERR("Failed to Create OP OBQ %d\n",op_ob_q->q_id);
944 op_ob_q->created = true;
945 virt_addr += obq_size;
946 dma_addr += obq_size;
953 pqisrc_destroy_op_ob_queues(softs);
955 DBG_FUNC("OUT failed %d\n", ret);
956 return PQI_STATUS_FAILURE;
960 * Function used to create operational queues for the adapter.
962 int pqisrc_create_op_queues(pqisrc_softstate_t *softs)
964 int ret = PQI_STATUS_SUCCESS;
968 /* Create Operational IB queues */
969 ret = pqisrc_alloc_and_create_ib_queues(softs);
972 /* Create Operational OB queues */
973 ret = pqisrc_alloc_and_create_ob_queues(softs);
977 /* Create Event queue */
978 ret = pqisrc_alloc_and_create_event_queue(softs);
985 pqisrc_destroy_op_ob_queues(softs);
987 pqisrc_destroy_op_ib_queues(softs);
989 DBG_FUNC("OUT failed %d\n", ret);
990 return PQI_STATUS_FAILURE;