2 * Copyright (c) 2018 Microsemi Corporation.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include "smartpqi_includes.h"
32 void sis_disable_msix(pqisrc_softstate_t *softs)
38 db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
40 db_reg &= ~SIS_ENABLE_MSIX;
41 PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
42 LEGACY_SIS_IDBR, db_reg);
47 void sis_enable_intx(pqisrc_softstate_t *softs)
53 db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
55 db_reg |= SIS_ENABLE_INTX;
56 PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
57 LEGACY_SIS_IDBR, db_reg);
58 if (pqisrc_sis_wait_for_db_bit_to_clear(softs,SIS_ENABLE_INTX)
59 != PQI_STATUS_SUCCESS) {
60 DBG_ERR("Failed to wait for enable intx db bit to clear\n");
65 void sis_disable_intx(pqisrc_softstate_t *softs)
71 db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
73 db_reg &= ~SIS_ENABLE_INTX;
74 PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
75 LEGACY_SIS_IDBR, db_reg);
80 void sis_disable_interrupt(pqisrc_softstate_t *softs)
84 switch(softs->intr_type) {
86 pqisrc_configure_legacy_intx(softs,false);
87 sis_disable_intx(softs);
91 sis_disable_msix(softs);
94 DBG_ERR("Inerrupt mode none!\n");
101 /* Trigger a NMI as part of taking controller offline procedure */
102 void pqisrc_trigger_nmi_sis(pqisrc_softstate_t *softs)
107 PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
108 LEGACY_SIS_IDBR, LE_32(TRIGGER_NMI_SIS));
112 /* Switch the adapter back to SIS mode during uninitialization */
113 int pqisrc_reenable_sis(pqisrc_softstate_t *softs)
115 int ret = PQI_STATUS_SUCCESS;
116 uint32_t timeout = SIS_ENABLE_TIMEOUT;
120 PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
121 LEGACY_SIS_IDBR, LE_32(REENABLE_SIS));
123 COND_WAIT(((PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R) &
124 REENABLE_SIS) == 0), timeout)
126 DBG_WARN(" [ %s ] failed to re enable sis\n",__func__);
127 ret = PQI_STATUS_TIMEOUT;
134 /* Validate the FW status PQI_CTRL_KERNEL_UP_AND_RUNNING */
135 int pqisrc_check_fw_status(pqisrc_softstate_t *softs)
137 int ret = PQI_STATUS_SUCCESS;
138 uint32_t timeout = SIS_STATUS_OK_TIMEOUT;
143 COND_WAIT((GET_FW_STATUS(softs) &
144 PQI_CTRL_KERNEL_UP_AND_RUNNING), timeout);
146 DBG_ERR("FW check status timedout\n");
147 ret = PQI_STATUS_TIMEOUT;
154 /* Function used to submit a SIS command to the adapter */
155 static int pqisrc_send_sis_cmd(pqisrc_softstate_t *softs,
158 int ret = PQI_STATUS_SUCCESS;
160 uint32_t timeout = SIS_CMD_COMPLETE_TIMEOUT;
167 /* Copy Command to mailbox */
168 for (i = 0; i < 6; i++)
169 PCI_MEM_PUT32(softs, &softs->ioa_reg->mb[i],
170 LEGACY_SIS_SRCV_MAILBOX+i*4, LE_32(mb[i]));
172 PCI_MEM_PUT32(softs, &softs->ioa_reg->ioa_to_host_db_clr,
173 LEGACY_SIS_ODBR_R, LE_32(0x1000));
175 /* Submit the command */
176 PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
177 LEGACY_SIS_IDBR, LE_32(SIS_CMD_SUBMIT));
180 /* Wait for 20 milli sec to poll */
181 OS_BUSYWAIT(SIS_POLL_START_WAIT_TIME);
184 val = PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R);
186 DBG_FUNC("val : %x\n",val);
187 /* Spin waiting for the command to complete */
188 COND_WAIT((PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R) &
189 SIS_CMD_COMPLETE), timeout);
191 DBG_ERR("Sync command %x, timedout\n", mb[0]);
192 ret = PQI_STATUS_TIMEOUT;
195 /* Check command status */
196 mb[0] = LE_32(PCI_MEM_GET32(softs, &softs->ioa_reg->mb[0], LEGACY_SIS_SRCV_MAILBOX));
198 if (mb[0] != SIS_CMD_STATUS_SUCCESS) {
199 DBG_ERR("SIS cmd failed with status = 0x%x\n",
201 ret = PQI_STATUS_FAILURE;
205 /* Copy the mailbox back */
206 for (i = 1; i < 6; i++)
207 mb[i] = LE_32(PCI_MEM_GET32(softs, &softs->ioa_reg->mb[i], LEGACY_SIS_SRCV_MAILBOX+i*4));
213 DBG_FUNC("OUT failed\n");
217 /* First SIS command for the adapter to check PQI support */
218 int pqisrc_get_adapter_properties(pqisrc_softstate_t *softs,
219 uint32_t *prop, uint32_t *ext_prop)
221 int ret = PQI_STATUS_SUCCESS;
222 uint32_t mb[6] = {0};
226 mb[0] = SIS_CMD_GET_ADAPTER_PROPERTIES;
227 ret = pqisrc_send_sis_cmd(softs, mb);
229 DBG_INIT("GET_PROPERTIES prop = %x, ext_prop = %x\n",
239 /* Second SIS command to the adapter GET_COMM_PREFERRED_SETTINGS */
240 int pqisrc_get_preferred_settings(pqisrc_softstate_t *softs)
242 int ret = PQI_STATUS_SUCCESS;
243 uint32_t mb[6] = {0};
247 mb[0] = SIS_CMD_GET_COMM_PREFERRED_SETTINGS;
248 ret = pqisrc_send_sis_cmd(softs, mb);
250 /* 31:16 maximum command size in KB */
251 softs->pref_settings.max_cmd_size = mb[1] >> 16;
252 /* 15:00: Maximum FIB size in bytes */
253 softs->pref_settings.max_fib_size = mb[1] & 0x0000FFFF;
254 DBG_INIT("cmd size = %x, fib size = %x\n",
255 softs->pref_settings.max_cmd_size,
256 softs->pref_settings.max_fib_size);
263 /* Get supported PQI capabilities from the adapter */
264 int pqisrc_get_sis_pqi_cap(pqisrc_softstate_t *softs)
266 int ret = PQI_STATUS_SUCCESS;
267 uint32_t mb[6] = {0};
271 mb[0] = SIS_CMD_GET_PQI_CAPABILITIES;
272 ret = pqisrc_send_sis_cmd(softs, mb);
274 softs->pqi_cap.max_sg_elem = mb[1];
275 softs->pqi_cap.max_transfer_size = mb[2];
276 softs->pqi_cap.max_outstanding_io = mb[3];
277 softs->pqi_cap.conf_tab_off = mb[4];
278 softs->pqi_cap.conf_tab_sz = mb[5];
280 DBG_INIT("max_sg_elem = %x\n",
281 softs->pqi_cap.max_sg_elem);
282 DBG_INIT("max_transfer_size = %x\n",
283 softs->pqi_cap.max_transfer_size);
284 DBG_INIT("max_outstanding_io = %x\n",
285 softs->pqi_cap.max_outstanding_io);
292 /* Send INIT STRUCT BASE ADDR - one of the SIS command */
293 int pqisrc_init_struct_base(pqisrc_softstate_t *softs)
295 int ret = PQI_STATUS_SUCCESS;
296 uint32_t elem_size = 0;
297 uint32_t num_elem = 0;
298 struct dma_mem init_struct_mem = {0};
299 struct init_base_struct *init_struct = NULL;
300 uint32_t mb[6] = {0};
304 /* Allocate init struct */
305 memset(&init_struct_mem, 0, sizeof(struct dma_mem));
306 init_struct_mem.size = sizeof(struct init_base_struct);
307 init_struct_mem.align = PQISRC_INIT_STRUCT_DMA_ALIGN;
308 init_struct_mem.tag = "init_struct";
309 ret = os_dma_mem_alloc(softs, &init_struct_mem);
311 DBG_ERR("Failed to Allocate error buffer ret : %d\n",
316 /* Calculate error buffer size */
317 /* The valid tag values are from 1, 2, ..., softs->max_outstanding_io
318 * The rcb and error buffer will be accessed by using the tag as index
319 * As 0 tag index is not used, we need to allocate one extra.
321 num_elem = softs->pqi_cap.max_outstanding_io + 1;
322 elem_size = PQISRC_ERR_BUF_ELEM_SIZE;
323 softs->err_buf_dma_mem.size = num_elem * elem_size;
325 /* Allocate error buffer */
326 softs->err_buf_dma_mem.align = PQISRC_ERR_BUF_DMA_ALIGN;
327 softs->err_buf_dma_mem.tag = "error_buffer";
328 ret = os_dma_mem_alloc(softs, &softs->err_buf_dma_mem);
330 DBG_ERR("Failed to Allocate error buffer ret : %d\n",
332 goto err_error_buf_alloc;
335 /* Fill init struct */
336 init_struct = (struct init_base_struct *)DMA_TO_VIRT(&init_struct_mem);
337 init_struct->revision = PQISRC_INIT_STRUCT_REVISION;
338 init_struct->flags = 0;
339 init_struct->err_buf_paddr_l = DMA_PHYS_LOW(&softs->err_buf_dma_mem);
340 init_struct->err_buf_paddr_h = DMA_PHYS_HIGH(&softs->err_buf_dma_mem);
341 init_struct->err_buf_elem_len = elem_size;
342 init_struct->err_buf_num_elem = num_elem;
344 mb[0] = SIS_CMD_INIT_BASE_STRUCT_ADDRESS;
345 mb[1] = DMA_PHYS_LOW(&init_struct_mem);
346 mb[2] = DMA_PHYS_HIGH(&init_struct_mem);
347 mb[3] = init_struct_mem.size;
349 ret = pqisrc_send_sis_cmd(softs, mb);
354 os_dma_mem_free(softs, &init_struct_mem);
358 os_dma_mem_free(softs, &softs->err_buf_dma_mem);
360 os_dma_mem_free(softs, &init_struct_mem);
362 DBG_FUNC("OUT failed %d\n", ret);
363 return PQI_STATUS_FAILURE;
367 * SIS initialization of the adapter in a sequence of
368 * - GET_ADAPTER_PROPERTIES
369 * - GET_COMM_PREFERRED_SETTINGS
370 * - GET_PQI_CAPABILITIES
371 * - INIT_STRUCT_BASE ADDR
373 int pqisrc_sis_init(pqisrc_softstate_t *softs)
375 int ret = PQI_STATUS_SUCCESS;
377 uint32_t ext_prop = 0;
381 ret = pqisrc_force_sis(softs);
383 DBG_ERR("Failed to switch back the adapter to SIS mode!\n");
387 /* Check FW status ready */
388 ret = pqisrc_check_fw_status(softs);
390 DBG_ERR("PQI Controller is not ready !!!\n");
394 /* Check For PQI support(19h) */
395 ret = pqisrc_get_adapter_properties(softs, &prop, &ext_prop);
397 DBG_ERR("Failed to get adapter properties\n");
400 if (!((prop & SIS_SUPPORT_EXT_OPT) &&
401 (ext_prop & SIS_SUPPORT_PQI))) {
402 DBG_ERR("PQI Mode Not Supported\n");
403 ret = PQI_STATUS_FAILURE;
407 softs->pqi_reset_quiesce_allowed = false;
408 if (ext_prop & SIS_SUPPORT_PQI_RESET_QUIESCE)
409 softs->pqi_reset_quiesce_allowed = true;
411 /* Send GET_COMM_PREFERRED_SETTINGS (26h) */
412 ret = pqisrc_get_preferred_settings(softs);
414 DBG_ERR("Failed to get adapter pref settings\n");
418 /* Get PQI settings , 3000h*/
419 ret = pqisrc_get_sis_pqi_cap(softs);
421 DBG_ERR("Failed to get PQI Capabilities\n");
425 /* Init struct base addr */
426 ret = pqisrc_init_struct_base(softs);
428 DBG_ERR("Failed to set init struct base addr\n");
436 DBG_FUNC("OUT failed\n");
440 /* Deallocate the resources used during SIS initialization */
441 void pqisrc_sis_uninit(pqisrc_softstate_t *softs)
445 os_dma_mem_free(softs, &softs->err_buf_dma_mem);
446 os_resource_free(softs);
452 int pqisrc_sis_wait_for_db_bit_to_clear(pqisrc_softstate_t *softs, uint32_t bit)
454 int rcode = PQI_STATUS_SUCCESS;
456 uint32_t loop_cnt = 0;
461 db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
463 if ((db_reg & bit) == 0)
465 if (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_PANIC) {
466 DBG_ERR("controller kernel panic\n");
467 rcode = PQI_STATUS_FAILURE;
470 if (loop_cnt++ == SIS_DB_BIT_CLEAR_TIMEOUT_CNT) {
471 DBG_ERR("door-bell reg bit 0x%x not cleared\n", bit);
472 rcode = PQI_STATUS_TIMEOUT;