2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Benno Rice. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * Driver for SMSC LAN91C111, may work for older variants.
34 #ifdef HAVE_KERNEL_OPTION_HEADERS
35 #include "opt_device_polling.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/errno.h>
41 #include <sys/kernel.h>
42 #include <sys/sockio.h>
43 #include <sys/malloc.h>
45 #include <sys/queue.h>
46 #include <sys/socket.h>
47 #include <sys/syslog.h>
48 #include <sys/taskqueue.h>
50 #include <sys/module.h>
53 #include <machine/bus.h>
54 #include <machine/resource.h>
57 #include <net/ethernet.h>
59 #include <net/if_var.h>
60 #include <net/if_arp.h>
61 #include <net/if_dl.h>
62 #include <net/if_types.h>
63 #include <net/if_mib.h>
64 #include <net/if_media.h>
67 #include <netinet/in.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/in_var.h>
70 #include <netinet/ip.h>
74 #include <net/bpfdesc.h>
76 #include <dev/smc/if_smcreg.h>
77 #include <dev/smc/if_smcvar.h>
79 #include <dev/mii/mii.h>
80 #include <dev/mii/mii_bitbang.h>
81 #include <dev/mii/miivar.h>
83 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx)
84 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx)
85 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED)
87 #define SMC_INTR_PRIORITY 0
88 #define SMC_RX_PRIORITY 5
89 #define SMC_TX_PRIORITY 10
91 devclass_t smc_devclass;
93 static const char *smc_chip_ids[16] = {
95 /* 3 */ "SMSC LAN91C90 or LAN91C92",
96 /* 4 */ "SMSC LAN91C94",
97 /* 5 */ "SMSC LAN91C95",
98 /* 6 */ "SMSC LAN91C96",
99 /* 7 */ "SMSC LAN91C100",
100 /* 8 */ "SMSC LAN91C100FD",
101 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD",
106 static void smc_init(void *);
107 static void smc_start(struct ifnet *);
108 static void smc_stop(struct smc_softc *);
109 static int smc_ioctl(struct ifnet *, u_long, caddr_t);
111 static void smc_init_locked(struct smc_softc *);
112 static void smc_start_locked(struct ifnet *);
113 static void smc_reset(struct smc_softc *);
114 static int smc_mii_ifmedia_upd(struct ifnet *);
115 static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *);
116 static void smc_mii_tick(void *);
117 static void smc_mii_mediachg(struct smc_softc *);
118 static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long);
120 static void smc_task_intr(void *, int);
121 static void smc_task_rx(void *, int);
122 static void smc_task_tx(void *, int);
124 static driver_filter_t smc_intr;
125 static callout_func_t smc_watchdog;
126 #ifdef DEVICE_POLLING
127 static poll_handler_t smc_poll;
133 static uint32_t smc_mii_bitbang_read(device_t);
134 static void smc_mii_bitbang_write(device_t, uint32_t);
136 static const struct mii_bitbang_ops smc_mii_bitbang_ops = {
137 smc_mii_bitbang_read,
138 smc_mii_bitbang_write,
140 MGMT_MDO, /* MII_BIT_MDO */
141 MGMT_MDI, /* MII_BIT_MDI */
142 MGMT_MCLK, /* MII_BIT_MDC */
143 MGMT_MDOE, /* MII_BIT_DIR_HOST_PHY */
144 0, /* MII_BIT_DIR_PHY_HOST */
149 smc_select_bank(struct smc_softc *sc, uint16_t bank)
152 bus_barrier(sc->smc_reg, BSR, 2,
153 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
154 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK);
155 bus_barrier(sc->smc_reg, BSR, 2,
156 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
159 /* Never call this when not in bank 2. */
161 smc_mmu_wait(struct smc_softc *sc)
164 KASSERT((bus_read_2(sc->smc_reg, BSR) &
165 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2",
166 device_get_nameunit(sc->smc_dev)));
167 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY)
171 static __inline uint8_t
172 smc_read_1(struct smc_softc *sc, bus_size_t offset)
175 return (bus_read_1(sc->smc_reg, offset));
179 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val)
182 bus_write_1(sc->smc_reg, offset, val);
185 static __inline uint16_t
186 smc_read_2(struct smc_softc *sc, bus_size_t offset)
189 return (bus_read_2(sc->smc_reg, offset));
193 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val)
196 bus_write_2(sc->smc_reg, offset, val);
200 smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
204 bus_read_multi_2(sc->smc_reg, offset, datap, count);
208 smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
212 bus_write_multi_2(sc->smc_reg, offset, datap, count);
216 smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length,
220 bus_barrier(sc->smc_reg, offset, length, flags);
224 smc_probe(device_t dev)
226 int rid, type, error;
228 struct smc_softc *sc;
229 struct resource *reg;
231 sc = device_get_softc(dev);
233 type = SYS_RES_IOPORT;
237 type = SYS_RES_MEMORY;
239 reg = bus_alloc_resource_anywhere(dev, type, &rid, 16, RF_ACTIVE);
243 "could not allocate I/O resource for probe\n");
247 /* Check for the identification value in the BSR. */
248 val = bus_read_2(reg, BSR);
249 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
251 device_printf(dev, "identification value not in BSR\n");
257 * Try switching banks and make sure we still get the identification
260 bus_write_2(reg, BSR, 0);
261 val = bus_read_2(reg, BSR);
262 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
265 "identification value not in BSR after write\n");
272 bus_write_2(reg, BSR, 1);
273 val = bus_read_2(reg, BAR);
274 val = BAR_ADDRESS(val);
275 if (rman_get_start(reg) != val) {
277 device_printf(dev, "BAR address %x does not match "
278 "I/O resource address %lx\n", val,
279 rman_get_start(reg));
285 /* Compare REV against known chip revisions. */
286 bus_write_2(reg, BSR, 3);
287 val = bus_read_2(reg, REV);
288 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
289 if (smc_chip_ids[val] == NULL) {
291 device_printf(dev, "Unknown chip revision: %d\n", val);
296 device_set_desc(dev, smc_chip_ids[val]);
299 bus_release_resource(dev, type, rid, reg);
304 smc_attach(device_t dev)
308 u_char eaddr[ETHER_ADDR_LEN];
309 struct smc_softc *sc;
312 sc = device_get_softc(dev);
317 ifp = sc->smc_ifp = if_alloc(IFT_ETHER);
323 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
325 /* Set up watchdog callout. */
326 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0);
328 type = SYS_RES_IOPORT;
330 type = SYS_RES_MEMORY;
333 sc->smc_reg = bus_alloc_resource_anywhere(dev, type, &sc->smc_reg_rid,
335 if (sc->smc_reg == NULL) {
340 sc->smc_irq = bus_alloc_resource_anywhere(dev, SYS_RES_IRQ,
341 &sc->smc_irq_rid, 1, RF_ACTIVE | RF_SHAREABLE);
342 if (sc->smc_irq == NULL) {
351 smc_select_bank(sc, 3);
352 val = smc_read_2(sc, REV);
353 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
354 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT;
356 device_printf(dev, "revision %x\n", sc->smc_rev);
358 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx,
359 CALLOUT_RETURNUNLOCKED);
360 if (sc->smc_chip >= REV_CHIP_91110FD) {
361 (void)mii_attach(dev, &sc->smc_miibus, ifp,
362 smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK,
363 MII_PHY_ANY, MII_OFFSET_ANY, 0);
364 if (sc->smc_miibus != NULL) {
365 sc->smc_mii_tick = smc_mii_tick;
366 sc->smc_mii_mediachg = smc_mii_mediachg;
367 sc->smc_mii_mediaioctl = smc_mii_mediaioctl;
371 smc_select_bank(sc, 1);
372 eaddr[0] = smc_read_1(sc, IAR0);
373 eaddr[1] = smc_read_1(sc, IAR1);
374 eaddr[2] = smc_read_1(sc, IAR2);
375 eaddr[3] = smc_read_1(sc, IAR3);
376 eaddr[4] = smc_read_1(sc, IAR4);
377 eaddr[5] = smc_read_1(sc, IAR5);
379 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
381 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
382 ifp->if_init = smc_init;
383 ifp->if_ioctl = smc_ioctl;
384 ifp->if_start = smc_start;
385 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
386 IFQ_SET_READY(&ifp->if_snd);
388 ifp->if_capabilities = ifp->if_capenable = 0;
390 #ifdef DEVICE_POLLING
391 ifp->if_capabilities |= IFCAP_POLLING;
394 ether_ifattach(ifp, eaddr);
396 /* Set up taskqueue */
397 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp);
398 NET_TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp);
399 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp);
400 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT,
401 taskqueue_thread_enqueue, &sc->smc_tq);
402 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq",
403 device_get_nameunit(sc->smc_dev));
405 /* Mask all interrupts. */
407 smc_write_1(sc, MSK, 0);
409 /* Wire up interrupt */
410 error = bus_setup_intr(dev, sc->smc_irq,
411 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih);
422 smc_detach(device_t dev)
425 struct smc_softc *sc;
427 sc = device_get_softc(dev);
432 if (sc->smc_ifp != NULL) {
433 ether_ifdetach(sc->smc_ifp);
436 callout_drain(&sc->smc_watchdog);
437 callout_drain(&sc->smc_mii_tick_ch);
439 #ifdef DEVICE_POLLING
440 if (sc->smc_ifp->if_capenable & IFCAP_POLLING)
441 ether_poll_deregister(sc->smc_ifp);
444 if (sc->smc_ih != NULL)
445 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih);
447 if (sc->smc_tq != NULL) {
448 taskqueue_drain(sc->smc_tq, &sc->smc_intr);
449 taskqueue_drain(sc->smc_tq, &sc->smc_rx);
450 taskqueue_drain(sc->smc_tq, &sc->smc_tx);
451 taskqueue_free(sc->smc_tq);
455 if (sc->smc_ifp != NULL) {
456 if_free(sc->smc_ifp);
459 if (sc->smc_miibus != NULL) {
460 device_delete_child(sc->smc_dev, sc->smc_miibus);
461 bus_generic_detach(sc->smc_dev);
464 if (sc->smc_reg != NULL) {
465 type = SYS_RES_IOPORT;
467 type = SYS_RES_MEMORY;
469 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid,
473 if (sc->smc_irq != NULL)
474 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid,
477 if (mtx_initialized(&sc->smc_mtx))
478 mtx_destroy(&sc->smc_mtx);
484 smc_start(struct ifnet *ifp)
486 struct smc_softc *sc;
490 smc_start_locked(ifp);
495 smc_start_locked(struct ifnet *ifp)
497 struct smc_softc *sc;
499 u_int len, npages, spin_count;
502 SMC_ASSERT_LOCKED(sc);
504 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
506 if (IFQ_IS_EMPTY(&ifp->if_snd))
510 * Grab the next packet. If it's too big, drop it.
512 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
513 len = m_length(m, NULL);
515 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) {
516 if_printf(ifp, "large packet discarded\n");
517 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
519 return; /* XXX readcheck? */
523 * Flag that we're busy.
525 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
529 * Work out how many 256 byte "pages" we need. We have to include the
530 * control data for the packet in this calculation.
532 npages = (len + PKT_CTRL_DATA_LEN) >> 8;
539 smc_select_bank(sc, 2);
541 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages);
544 * Spin briefly to see if the allocation succeeds.
546 spin_count = TX_ALLOC_WAIT_TIME;
548 if (smc_read_1(sc, IST) & ALLOC_INT) {
549 smc_write_1(sc, ACK, ALLOC_INT);
552 } while (--spin_count);
555 * If the allocation is taking too long, unmask the alloc interrupt
558 if (spin_count == 0) {
559 sc->smc_mask |= ALLOC_INT;
560 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
561 smc_write_1(sc, MSK, sc->smc_mask);
565 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
569 smc_task_tx(void *context, int pending)
572 struct smc_softc *sc;
579 ifp = (struct ifnet *)context;
584 if (sc->smc_pending == NULL) {
589 m = m0 = sc->smc_pending;
590 sc->smc_pending = NULL;
591 smc_select_bank(sc, 2);
594 * Check the allocation result.
596 packet = smc_read_1(sc, ARR);
599 * If the allocation failed, requeue the packet and retry.
601 if (packet & ARR_FAILED) {
602 IFQ_DRV_PREPEND(&ifp->if_snd, m);
603 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
604 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
605 smc_start_locked(ifp);
611 * Tell the device to write to our packet number.
613 smc_write_1(sc, PNR, packet);
614 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR);
617 * Tell the device how long the packet is (including control data).
619 len = m_length(m, 0);
620 len += PKT_CTRL_DATA_LEN;
621 smc_write_2(sc, DATA0, 0);
622 smc_write_2(sc, DATA0, len);
625 * Push the data out to the device.
629 for (; m != NULL; m = m->m_next) {
630 data = mtod(m, uint8_t *);
631 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2);
636 * Push out the control byte and and the odd byte if needed.
638 if ((len & 1) != 0 && data != NULL)
639 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]);
641 smc_write_2(sc, DATA0, 0);
644 * Unmask the TX empty interrupt.
646 sc->smc_mask |= TX_EMPTY_INT;
647 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
648 smc_write_1(sc, MSK, sc->smc_mask);
651 * Enqueue the packet.
654 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE);
655 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc);
660 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
661 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
668 * See if there's anything else to do.
674 smc_task_rx(void *context, int pending)
676 u_int packet, status, len;
679 struct smc_softc *sc;
680 struct mbuf *m, *mhead, *mtail;
683 ifp = (struct ifnet *)context;
685 mhead = mtail = NULL;
689 packet = smc_read_1(sc, FIFO_RX);
690 while ((packet & FIFO_EMPTY) == 0) {
692 * Grab an mbuf and attach a cluster.
694 MGETHDR(m, M_NOWAIT, MT_DATA);
698 if (!(MCLGET(m, M_NOWAIT))) {
704 * Point to the start of the packet.
706 smc_select_bank(sc, 2);
707 smc_write_1(sc, PNR, packet);
708 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
711 * Grab status and packet length.
713 status = smc_read_2(sc, DATA0);
714 len = smc_read_2(sc, DATA0) & RX_LEN_MASK;
716 if (status & RX_ODDFRM)
722 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) {
724 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
725 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
731 * Set the mbuf up the way we want it.
733 m->m_pkthdr.rcvif = ifp;
734 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */
735 m_adj(m, ETHER_ALIGN);
738 * Pull the packet out of the device. Make sure we're in the
739 * right bank first as things may have changed while we were
740 * allocating our mbuf.
742 smc_select_bank(sc, 2);
743 smc_write_1(sc, PNR, packet);
744 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
745 data = mtod(m, uint8_t *);
746 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1);
749 *data = smc_read_1(sc, DATA0);
753 * Tell the device we're done.
756 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
768 packet = smc_read_1(sc, FIFO_RX);
771 sc->smc_mask |= RCV_INT;
772 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
773 smc_write_1(sc, MSK, sc->smc_mask);
777 while (mhead != NULL) {
779 mhead = mhead->m_next;
781 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
782 (*ifp->if_input)(ifp, m);
786 #ifdef DEVICE_POLLING
788 smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
790 struct smc_softc *sc;
795 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
801 if (cmd == POLL_AND_CHECK_STATUS)
802 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
808 smc_intr(void *context)
810 struct smc_softc *sc;
813 sc = (struct smc_softc *)context;
816 * Save current bank and restore later in this function
818 curbank = (smc_read_2(sc, BSR) & BSR_BANK_MASK);
821 * Block interrupts in order to let smc_task_intr to kick in
823 smc_select_bank(sc, 2);
824 smc_write_1(sc, MSK, 0);
827 smc_select_bank(sc, curbank);
829 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
830 return (FILTER_HANDLED);
834 smc_task_intr(void *context, int pending)
836 struct smc_softc *sc;
838 u_int status, packet, counter, tcr;
841 ifp = (struct ifnet *)context;
846 smc_select_bank(sc, 2);
849 * Find out what interrupts are flagged.
851 status = smc_read_1(sc, IST) & sc->smc_mask;
856 if (status & TX_INT) {
858 * Kill off the packet if there is one and re-enable transmit.
860 packet = smc_read_1(sc, FIFO_TX);
861 if ((packet & FIFO_EMPTY) == 0) {
862 callout_stop(&sc->smc_watchdog);
863 smc_select_bank(sc, 2);
864 smc_write_1(sc, PNR, packet);
865 smc_write_2(sc, PTR, 0 | PTR_READ |
867 smc_select_bank(sc, 0);
868 tcr = smc_read_2(sc, EPHSR);
870 if ((tcr & EPHSR_TX_SUC) == 0)
871 device_printf(sc->smc_dev,
874 smc_select_bank(sc, 2);
876 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT);
878 smc_select_bank(sc, 0);
879 tcr = smc_read_2(sc, TCR);
880 tcr |= TCR_TXENA | TCR_PAD_EN;
881 smc_write_2(sc, TCR, tcr);
882 smc_select_bank(sc, 2);
883 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
889 smc_write_1(sc, ACK, TX_INT);
895 if (status & RCV_INT) {
896 smc_write_1(sc, ACK, RCV_INT);
897 sc->smc_mask &= ~RCV_INT;
898 taskqueue_enqueue(sc->smc_tq, &sc->smc_rx);
904 if (status & ALLOC_INT) {
905 smc_write_1(sc, ACK, ALLOC_INT);
906 sc->smc_mask &= ~ALLOC_INT;
907 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
913 if (status & RX_OVRN_INT) {
914 smc_write_1(sc, ACK, RX_OVRN_INT);
915 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
921 if (status & TX_EMPTY_INT) {
922 smc_write_1(sc, ACK, TX_EMPTY_INT);
923 sc->smc_mask &= ~TX_EMPTY_INT;
924 callout_stop(&sc->smc_watchdog);
927 * Update collision stats.
929 smc_select_bank(sc, 0);
930 counter = smc_read_2(sc, ECR);
931 smc_select_bank(sc, 2);
932 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
933 ((counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT) +
934 ((counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT));
937 * See if there are any packets to transmit.
939 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
943 * Update the interrupt mask.
945 smc_select_bank(sc, 2);
946 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
947 smc_write_1(sc, MSK, sc->smc_mask);
953 smc_mii_bitbang_read(device_t dev)
955 struct smc_softc *sc;
958 sc = device_get_softc(dev);
960 SMC_ASSERT_LOCKED(sc);
961 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
962 ("%s: smc_mii_bitbang_read called with bank %d (!= 3)",
963 device_get_nameunit(sc->smc_dev),
964 smc_read_2(sc, BSR) & BSR_BANK_MASK));
966 val = smc_read_2(sc, MGMT);
967 smc_barrier(sc, MGMT, 2,
968 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
974 smc_mii_bitbang_write(device_t dev, uint32_t val)
976 struct smc_softc *sc;
978 sc = device_get_softc(dev);
980 SMC_ASSERT_LOCKED(sc);
981 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
982 ("%s: smc_mii_bitbang_write called with bank %d (!= 3)",
983 device_get_nameunit(sc->smc_dev),
984 smc_read_2(sc, BSR) & BSR_BANK_MASK));
986 smc_write_2(sc, MGMT, val);
987 smc_barrier(sc, MGMT, 2,
988 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
992 smc_miibus_readreg(device_t dev, int phy, int reg)
994 struct smc_softc *sc;
997 sc = device_get_softc(dev);
1001 smc_select_bank(sc, 3);
1003 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg);
1010 smc_miibus_writereg(device_t dev, int phy, int reg, int data)
1012 struct smc_softc *sc;
1014 sc = device_get_softc(dev);
1018 smc_select_bank(sc, 3);
1020 mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data);
1027 smc_miibus_statchg(device_t dev)
1029 struct smc_softc *sc;
1030 struct mii_data *mii;
1033 sc = device_get_softc(dev);
1034 mii = device_get_softc(sc->smc_miibus);
1038 smc_select_bank(sc, 0);
1039 tcr = smc_read_2(sc, TCR);
1041 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1046 smc_write_2(sc, TCR, tcr);
1052 smc_mii_ifmedia_upd(struct ifnet *ifp)
1054 struct smc_softc *sc;
1055 struct mii_data *mii;
1058 if (sc->smc_miibus == NULL)
1061 mii = device_get_softc(sc->smc_miibus);
1062 return (mii_mediachg(mii));
1066 smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1068 struct smc_softc *sc;
1069 struct mii_data *mii;
1072 if (sc->smc_miibus == NULL)
1075 mii = device_get_softc(sc->smc_miibus);
1077 ifmr->ifm_active = mii->mii_media_active;
1078 ifmr->ifm_status = mii->mii_media_status;
1082 smc_mii_tick(void *context)
1084 struct smc_softc *sc;
1086 sc = (struct smc_softc *)context;
1088 if (sc->smc_miibus == NULL)
1093 mii_tick(device_get_softc(sc->smc_miibus));
1094 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc);
1098 smc_mii_mediachg(struct smc_softc *sc)
1101 if (sc->smc_miibus == NULL)
1103 mii_mediachg(device_get_softc(sc->smc_miibus));
1107 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command)
1109 struct mii_data *mii;
1111 if (sc->smc_miibus == NULL)
1114 mii = device_get_softc(sc->smc_miibus);
1115 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command));
1119 smc_reset(struct smc_softc *sc)
1123 SMC_ASSERT_LOCKED(sc);
1125 smc_select_bank(sc, 2);
1128 * Mask all interrupts.
1130 smc_write_1(sc, MSK, 0);
1133 * Tell the device to reset.
1135 smc_select_bank(sc, 0);
1136 smc_write_2(sc, RCR, RCR_SOFT_RST);
1139 * Set up the configuration register.
1141 smc_select_bank(sc, 1);
1142 smc_write_2(sc, CR, CR_EPH_POWER_EN);
1146 * Turn off transmit and receive.
1148 smc_select_bank(sc, 0);
1149 smc_write_2(sc, TCR, 0);
1150 smc_write_2(sc, RCR, 0);
1153 * Set up the control register.
1155 smc_select_bank(sc, 1);
1156 ctr = smc_read_2(sc, CTR);
1157 ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE;
1158 smc_write_2(sc, CTR, ctr);
1163 smc_select_bank(sc, 2);
1165 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET);
1169 smc_enable(struct smc_softc *sc)
1173 SMC_ASSERT_LOCKED(sc);
1177 * Set up the receive/PHY control register.
1179 smc_select_bank(sc, 0);
1180 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT)
1181 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT));
1184 * Set up the transmit and receive control registers.
1186 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN);
1187 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC);
1190 * Set up the interrupt mask.
1192 smc_select_bank(sc, 2);
1193 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT;
1194 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1195 smc_write_1(sc, MSK, sc->smc_mask);
1199 smc_stop(struct smc_softc *sc)
1202 SMC_ASSERT_LOCKED(sc);
1205 * Turn off callouts.
1207 callout_stop(&sc->smc_watchdog);
1208 callout_stop(&sc->smc_mii_tick_ch);
1211 * Mask all interrupts.
1213 smc_select_bank(sc, 2);
1215 smc_write_1(sc, MSK, 0);
1216 #ifdef DEVICE_POLLING
1217 ether_poll_deregister(sc->smc_ifp);
1218 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING;
1222 * Disable transmit and receive.
1224 smc_select_bank(sc, 0);
1225 smc_write_2(sc, TCR, 0);
1226 smc_write_2(sc, RCR, 0);
1228 sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1232 smc_watchdog(void *arg)
1234 struct smc_softc *sc;
1236 sc = (struct smc_softc *)arg;
1237 device_printf(sc->smc_dev, "watchdog timeout\n");
1238 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
1242 smc_init(void *context)
1244 struct smc_softc *sc;
1246 sc = (struct smc_softc *)context;
1248 smc_init_locked(sc);
1253 smc_init_locked(struct smc_softc *sc)
1257 SMC_ASSERT_LOCKED(sc);
1259 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1265 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1266 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1268 smc_start_locked(ifp);
1270 if (sc->smc_mii_tick != NULL)
1271 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc);
1273 #ifdef DEVICE_POLLING
1275 ether_poll_register(smc_poll, ifp);
1277 ifp->if_capenable |= IFCAP_POLLING;
1282 smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1284 struct smc_softc *sc;
1292 if ((ifp->if_flags & IFF_UP) == 0 &&
1293 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1299 if (sc->smc_mii_mediachg != NULL)
1300 sc->smc_mii_mediachg(sc);
1316 if (sc->smc_mii_mediaioctl == NULL) {
1320 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd);
1324 error = ether_ioctl(ifp, cmd, data);