sys/dev/smc/if_smc.c

   1 /*-
   2  * Copyright (c) 2008 Benno Rice.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  19  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  20  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  */
  24
  25 #include <sys/cdefs.h>
  26 __FBSDID("$FreeBSD$");
  27
  28 /*
  29  * Driver for SMSC LAN91C111, may work for older variants.
  30  */
  31
  32 #ifdef HAVE_KERNEL_OPTION_HEADERS
  33 #include "opt_device_polling.h"
  34 #endif
  35
  36 #include <sys/param.h>
  37 #include <sys/systm.h>
  38 #include <sys/errno.h>
  39 #include <sys/kernel.h>
  40 #include <sys/sockio.h>
  41 #include <sys/malloc.h>
  42 #include <sys/mbuf.h>
  43 #include <sys/queue.h>
  44 #include <sys/socket.h>
  45 #include <sys/syslog.h>
  46 #include <sys/taskqueue.h>
  47
  48 #include <sys/module.h>
  49 #include <sys/bus.h>
  50
  51 #include <machine/bus.h>
  52 #include <machine/resource.h>
  53 #include <sys/rman.h>
  54
  55 #include <net/ethernet.h>
  56 #include <net/if.h>
  57 #include <net/if_arp.h>
  58 #include <net/if_dl.h>
  59 #include <net/if_types.h>
  60 #include <net/if_mib.h>
  61 #include <net/if_media.h>
  62
  63 #ifdef INET
  64 #include <netinet/in.h>
  65 #include <netinet/in_systm.h>
  66 #include <netinet/in_var.h>
  67 #include <netinet/ip.h>
  68 #endif
  69
  70 #include <net/bpf.h>
  71 #include <net/bpfdesc.h>
  72
  73 #include <dev/smc/if_smcreg.h>
  74 #include <dev/smc/if_smcvar.h>
  75
  76 #include <dev/mii/mii.h>
  77 #include <dev/mii/miivar.h>
  78
  79 #define SMC_LOCK(sc)            mtx_lock(&(sc)->smc_mtx)
  80 #define SMC_UNLOCK(sc)          mtx_unlock(&(sc)->smc_mtx)
  81 #define SMC_ASSERT_LOCKED(sc)   mtx_assert(&(sc)->smc_mtx, MA_OWNED)
  82
  83 #define SMC_INTR_PRIORITY       0
  84 #define SMC_RX_PRIORITY         5
  85 #define SMC_TX_PRIORITY         10
  86
  87 devclass_t      smc_devclass;
  88
  89 static const char *smc_chip_ids[16] = {
  90         NULL, NULL, NULL,
  91         /* 3 */ "SMSC LAN91C90 or LAN91C92",
  92         /* 4 */ "SMSC LAN91C94",
  93         /* 5 */ "SMSC LAN91C95",
  94         /* 6 */ "SMSC LAN91C96",
  95         /* 7 */ "SMSC LAN91C100",
  96         /* 8 */ "SMSC LAN91C100FD",
  97         /* 9 */ "SMSC LAN91C110FD or LAN91C111FD",
  98         NULL, NULL, NULL,
  99         NULL, NULL, NULL
 100 };
 101
 102 static void     smc_init(void *);
 103 static void     smc_start(struct ifnet *);
 104 static void     smc_stop(struct smc_softc *);
 105 static int      smc_ioctl(struct ifnet *, u_long, caddr_t);
 106
 107 static void     smc_init_locked(struct smc_softc *);
 108 static void     smc_start_locked(struct ifnet *);
 109 static void     smc_reset(struct smc_softc *);
 110 static int      smc_mii_ifmedia_upd(struct ifnet *);
 111 static void     smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 112 static void     smc_mii_tick(void *);
 113 static void     smc_mii_mediachg(struct smc_softc *);
 114 static int      smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long);
 115
 116 static void     smc_task_intr(void *, int);
 117 static void     smc_task_rx(void *, int);
 118 static void     smc_task_tx(void *, int);
 119
 120 static driver_filter_t  smc_intr;
 121 static timeout_t        smc_watchdog;
 122 #ifdef DEVICE_POLLING
 123 static poll_handler_t   smc_poll;
 124 #endif
 125
 126 static __inline void
 127 smc_select_bank(struct smc_softc *sc, uint16_t bank)
 128 {
 129
 130         bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK);
 131 }
 132
 133 /* Never call this when not in bank 2. */
 134 static __inline void
 135 smc_mmu_wait(struct smc_softc *sc)
 136 {
 137
 138         KASSERT((bus_read_2(sc->smc_reg, BSR) &
 139             BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2",
 140             device_get_nameunit(sc->smc_dev)));
 141         while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY)
 142                 ;
 143 }
 144
 145 static __inline uint8_t
 146 smc_read_1(struct smc_softc *sc, bus_addr_t offset)
 147 {
 148
 149         return (bus_read_1(sc->smc_reg, offset));
 150 }
 151
 152 static __inline void
 153 smc_write_1(struct smc_softc *sc, bus_addr_t offset, uint8_t val)
 154 {
 155
 156         bus_write_1(sc->smc_reg, offset, val);
 157 }
 158
 159 static __inline uint16_t
 160 smc_read_2(struct smc_softc *sc, bus_addr_t offset)
 161 {
 162
 163         return (bus_read_2(sc->smc_reg, offset));
 164 }
 165
 166 static __inline void
 167 smc_write_2(struct smc_softc *sc, bus_addr_t offset, uint16_t val)
 168 {
 169
 170         bus_write_2(sc->smc_reg, offset, val);
 171 }
 172
 173 static __inline void
 174 smc_read_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap,
 175     bus_size_t count)
 176 {
 177
 178         bus_read_multi_2(sc->smc_reg, offset, datap, count);
 179 }
 180
 181 static __inline void
 182 smc_write_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap,
 183     bus_size_t count)
 184 {
 185
 186         bus_write_multi_2(sc->smc_reg, offset, datap, count);
 187 }
 188
 189 int
 190 smc_probe(device_t dev)
 191 {
 192         int                     rid, type, error;
 193         uint16_t                val;
 194         struct smc_softc        *sc;
 195         struct resource         *reg;
 196
 197         sc = device_get_softc(dev);
 198         rid = 0;
 199         type = SYS_RES_IOPORT;
 200         error = 0;
 201
 202         if (sc->smc_usemem)
 203                 type = SYS_RES_MEMORY;
 204
 205         reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE);
 206         if (reg == NULL) {
 207                 if (bootverbose)
 208                         device_printf(dev,
 209                             "could not allocate I/O resource for probe\n");
 210                 return (ENXIO);
 211         }
 212
 213         /* Check for the identification value in the BSR. */
 214         val = bus_read_2(reg, BSR);
 215         if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
 216                 if (bootverbose)
 217                         device_printf(dev, "identification value not in BSR\n");
 218                 error = ENXIO;
 219                 goto done;
 220         }
 221
 222         /*
 223          * Try switching banks and make sure we still get the identification
 224          * value.
 225          */
 226         bus_write_2(reg, BSR, 0);
 227         val = bus_read_2(reg, BSR);
 228         if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
 229                 if (bootverbose)
 230                         device_printf(dev,
 231                             "identification value not in BSR after write\n");
 232                 error = ENXIO;
 233                 goto done;
 234         }
 235
 236 #if 0
 237         /* Check the BAR. */
 238         bus_write_2(reg, BSR, 1);
 239         val = bus_read_2(reg, BAR);
 240         val = BAR_ADDRESS(val);
 241         if (rman_get_start(reg) != val) {
 242                 if (bootverbose)
 243                         device_printf(dev, "BAR address %x does not match "
 244                             "I/O resource address %lx\n", val,
 245                             rman_get_start(reg));
 246                 error = ENXIO;
 247                 goto done;
 248         }
 249 #endif
 250
 251         /* Compare REV against known chip revisions. */
 252         bus_write_2(reg, BSR, 3);
 253         val = bus_read_2(reg, REV);
 254         val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
 255         if (smc_chip_ids[val] == NULL) {
 256                 if (bootverbose)
 257                         device_printf(dev, "Unknown chip revision: %d\n", val);
 258                 error = ENXIO;
 259                 goto done;
 260         }
 261
 262         device_set_desc(dev, smc_chip_ids[val]);
 263
 264 done:
 265         bus_release_resource(dev, type, rid, reg);
 266         return (error);
 267 }
 268
 269 int
 270 smc_attach(device_t dev)
 271 {
 272         int                     type, error;
 273         uint16_t                val;
 274         u_char                  eaddr[ETHER_ADDR_LEN];
 275         struct smc_softc        *sc;
 276         struct ifnet            *ifp;
 277
 278         sc = device_get_softc(dev);
 279         error = 0;
 280
 281         sc->smc_dev = dev;
 282         sc->smc_shutdown = 0;
 283
 284         /* Set up watchdog callout. */
 285         callout_init(&sc->smc_watchdog, 1);
 286
 287         ifp = sc->smc_ifp = if_alloc(IFT_ETHER);
 288         if (ifp == NULL) {
 289                 error = ENOSPC;
 290                 goto done;
 291         }
 292
 293         mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
 294
 295         type = SYS_RES_IOPORT;
 296         if (sc->smc_usemem)
 297                 type = SYS_RES_MEMORY;
 298
 299         sc->smc_reg_rid = 0;
 300         sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0,
 301             16, RF_ACTIVE);
 302         if (sc->smc_reg == NULL) {
 303                 error = ENXIO;
 304                 goto done;
 305         }
 306
 307         sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0,
 308             ~0, 1, RF_ACTIVE | RF_SHAREABLE);
 309         if (sc->smc_irq == NULL) {
 310                 error = ENXIO;
 311                 goto done;
 312         }
 313
 314         SMC_LOCK(sc);
 315         smc_reset(sc);
 316         SMC_UNLOCK(sc);
 317
 318         smc_select_bank(sc, 3);
 319         val = smc_read_2(sc, REV);
 320         sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
 321         sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT;
 322         if (bootverbose)
 323                 device_printf(dev, "revision %x\n", sc->smc_rev);
 324
 325         callout_init(&sc->smc_mii_tick_ch, 1);
 326         if (sc->smc_chip >= REV_CHIP_91110FD) {
 327                 mii_phy_probe(dev, &sc->smc_miibus, smc_mii_ifmedia_upd,
 328                     smc_mii_ifmedia_sts);
 329                 if (sc->smc_miibus != NULL) {
 330                         sc->smc_mii_tick = smc_mii_tick;
 331                         sc->smc_mii_mediachg = smc_mii_mediachg;
 332                         sc->smc_mii_mediaioctl = smc_mii_mediaioctl;
 333                 }
 334         }
 335
 336         smc_select_bank(sc, 1);
 337         eaddr[0] = smc_read_1(sc, IAR0);
 338         eaddr[1] = smc_read_1(sc, IAR1);
 339         eaddr[2] = smc_read_1(sc, IAR2);
 340         eaddr[3] = smc_read_1(sc, IAR3);
 341         eaddr[4] = smc_read_1(sc, IAR4);
 342         eaddr[5] = smc_read_1(sc, IAR5);
 343
 344         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 345         ifp->if_softc = sc;
 346         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 347         ifp->if_init = smc_init;
 348         ifp->if_ioctl = smc_ioctl;
 349         ifp->if_start = smc_start;
 350         IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
 351         IFQ_SET_READY(&ifp->if_snd);
 352
 353         ifp->if_capabilities = ifp->if_capenable = 0;
 354
 355 #ifdef DEVICE_POLLING
 356         ifp->if_capabilities |= IFCAP_POLLING;
 357 #endif
 358
 359         ether_ifattach(ifp, eaddr);
 360
 361         /* Set up taskqueue */
 362         TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp);
 363         TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp);
 364         TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp);
 365         sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT,
 366             taskqueue_thread_enqueue, &sc->smc_tq);
 367         taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq",
 368             device_get_nameunit(sc->smc_dev));
 369
 370         /* Mask all interrupts. */
 371         sc->smc_mask = 0;
 372         smc_write_1(sc, MSK, 0);
 373
 374         /* Wire up interrupt */
 375         error = bus_setup_intr(dev, sc->smc_irq,
 376             INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih);
 377         if (error != 0)
 378                 goto done;
 379
 380 done:
 381         if (error != 0)
 382                 smc_detach(dev);
 383         return (error);
 384 }
 385
 386 int
 387 smc_detach(device_t dev)
 388 {
 389         int                     type;
 390         struct smc_softc        *sc;
 391
 392         sc = device_get_softc(dev);
 393         SMC_LOCK(sc);
 394         sc->smc_shutdown = 1;
 395         smc_stop(sc);
 396         SMC_UNLOCK(sc);
 397
 398         if (sc->smc_tq != NULL) {
 399                 taskqueue_drain(sc->smc_tq, &sc->smc_intr);
 400                 taskqueue_drain(sc->smc_tq, &sc->smc_rx);
 401                 taskqueue_drain(sc->smc_tq, &sc->smc_tx);
 402                 taskqueue_free(sc->smc_tq);
 403                 sc->smc_tq = NULL;
 404         }
 405
 406 #ifdef DEVICE_POLLING
 407         if (sc->smc_ifp->if_capenable & IFCAP_POLLING)
 408                 ether_poll_deregister(sc->smc_ifp);
 409 #endif
 410
 411         if (sc->smc_ih != NULL)
 412                 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih);
 413
 414         if (sc->smc_ifp != NULL) {
 415                 ether_ifdetach(sc->smc_ifp);
 416                 if_free(sc->smc_ifp);
 417         }
 418
 419         if (sc->smc_miibus != NULL) {
 420                 callout_stop(&sc->smc_mii_tick_ch);
 421                 device_delete_child(sc->smc_dev, sc->smc_miibus);
 422                 bus_generic_detach(sc->smc_dev);
 423         }
 424
 425         if (sc->smc_reg != NULL) {
 426                 type = SYS_RES_IOPORT;
 427                 if (sc->smc_usemem)
 428                         type = SYS_RES_MEMORY;
 429
 430                 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid,
 431                     sc->smc_reg);
 432         }
 433
 434         if (sc->smc_irq != NULL)
 435                 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid,
 436                    sc->smc_irq);
 437
 438         if (mtx_initialized(&sc->smc_mtx))
 439                 mtx_destroy(&sc->smc_mtx);
 440
 441         return (0);
 442 }
 443
 444 static void
 445 smc_start(struct ifnet *ifp)
 446 {
 447         struct smc_softc        *sc;
 448
 449         sc = ifp->if_softc;
 450         SMC_LOCK(sc);
 451         smc_start_locked(ifp);
 452         SMC_UNLOCK(sc);
 453 }
 454
 455 static void
 456 smc_start_locked(struct ifnet *ifp)
 457 {
 458         struct smc_softc        *sc;
 459         struct mbuf             *m;
 460         u_int                   len, npages, spin_count;
 461
 462         sc = ifp->if_softc;
 463         SMC_ASSERT_LOCKED(sc);
 464
 465         if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
 466                 return;
 467         if (IFQ_IS_EMPTY(&ifp->if_snd))
 468                 return;
 469
 470         /*
 471          * Grab the next packet.  If it's too big, drop it.
 472          */
 473         IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
 474         len = m_length(m, NULL);
 475         len += (len & 1);
 476         if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) {
 477                 if_printf(ifp, "large packet discarded\n");
 478                 ++ifp->if_oerrors;
 479                 m_freem(m);
 480                 return; /* XXX readcheck? */
 481         }
 482
 483         /*
 484          * Flag that we're busy.
 485          */
 486         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 487         sc->smc_pending = m;
 488
 489         /*
 490          * Work out how many 256 byte "pages" we need.  We have to include the
 491          * control data for the packet in this calculation.
 492          */
 493         npages = (len * PKT_CTRL_DATA_LEN) >> 8;
 494         if (npages == 0)
 495                 npages = 1;
 496
 497         /*
 498          * Request memory.
 499          */
 500         smc_select_bank(sc, 2);
 501         smc_mmu_wait(sc);
 502         smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages);
 503
 504         /*
 505          * Spin briefly to see if the allocation succeeds.
 506          */
 507         spin_count = TX_ALLOC_WAIT_TIME;
 508         do {
 509                 if (smc_read_1(sc, IST) & ALLOC_INT) {
 510                         smc_write_1(sc, ACK, ALLOC_INT);
 511                         break;
 512                 }
 513         } while (--spin_count);
 514
 515         /*
 516          * If the allocation is taking too long, unmask the alloc interrupt
 517          * and wait.
 518          */
 519         if (spin_count == 0) {
 520                 sc->smc_mask |= ALLOC_INT;
 521                 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 522                         smc_write_1(sc, MSK, sc->smc_mask);
 523                 return;
 524         }
 525
 526         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 527 }
 528
 529 static void
 530 smc_task_tx(void *context, int pending)
 531 {
 532         struct ifnet            *ifp;
 533         struct smc_softc        *sc;
 534         struct mbuf             *m, *m0;
 535         u_int                   packet, len;
 536         uint8_t                 *data;
 537
 538         (void)pending;
 539         ifp = (struct ifnet *)context;
 540         sc = ifp->if_softc;
 541
 542         SMC_LOCK(sc);
 543         if (sc->smc_shutdown == 1) {
 544                 SMC_UNLOCK(sc);
 545                 return;
 546         }
 547
 548         if (sc->smc_pending == NULL) {
 549                 SMC_UNLOCK(sc);
 550                 goto next_packet;
 551         }
 552
 553         m = m0 = sc->smc_pending;
 554         sc->smc_pending = NULL;
 555         smc_select_bank(sc, 2);
 556
 557         /*
 558          * Check the allocation result.
 559          */
 560         packet = smc_read_1(sc, ARR);
 561
 562         /*
 563          * If the allocation failed, requeue the packet and retry.
 564          */
 565         if (packet & ARR_FAILED) {
 566                 IFQ_DRV_PREPEND(&ifp->if_snd, m);
 567                 ++ifp->if_oerrors;
 568                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 569                 smc_start_locked(ifp);
 570                 SMC_UNLOCK(sc);
 571                 return;
 572         }
 573
 574         /*
 575          * Tell the device to write to our packet number.
 576          */
 577         smc_write_1(sc, PNR, packet);
 578         smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR);
 579
 580         /*
 581          * Tell the device how long the packet is (including control data).
 582          */
 583         len = m_length(m, 0);
 584         len += PKT_CTRL_DATA_LEN;
 585         smc_write_2(sc, DATA0, 0);
 586         smc_write_2(sc, DATA0, len);
 587
 588         /*
 589          * Push the data out to the device.
 590          */
 591         data = NULL;
 592         for (; m != NULL; m = m->m_next) {
 593                 data = mtod(m, uint8_t *);
 594                 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2);
 595         }
 596
 597         /*
 598          * Push out the control byte and and the odd byte if needed.
 599          */
 600         if ((len & 1) != 0 && data != NULL)
 601                 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[m->m_len - 1]);
 602         else
 603                 smc_write_2(sc, DATA0, 0);
 604
 605         /*
 606          * Unmask the TX empty interrupt.
 607          */
 608         sc->smc_mask |= TX_EMPTY_INT;
 609         if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 610                 smc_write_1(sc, MSK, sc->smc_mask);
 611
 612         /*
 613          * Enqueue the packet.
 614          */
 615         smc_mmu_wait(sc);
 616         smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE);
 617         callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc);
 618
 619         /*
 620          * Finish up.
 621          */
 622         ifp->if_opackets++;
 623         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 624         SMC_UNLOCK(sc);
 625         BPF_MTAP(ifp, m0);
 626         m_freem(m0);
 627
 628 next_packet:
 629         /*
 630          * See if there's anything else to do.
 631          */
 632         smc_start(ifp);
 633 }
 634
 635 static void
 636 smc_task_rx(void *context, int pending)
 637 {
 638         u_int                   packet, status, len;
 639         uint8_t                 *data;
 640         struct ifnet            *ifp;
 641         struct smc_softc        *sc;
 642         struct mbuf             *m, *mhead, *mtail;
 643
 644         (void)pending;
 645         ifp = (struct ifnet *)context;
 646         sc = ifp->if_softc;
 647         mhead = mtail = NULL;
 648
 649         SMC_LOCK(sc);
 650         if (sc->smc_shutdown == 1) {
 651                 SMC_UNLOCK(sc);
 652                 return;
 653         }
 654
 655         packet = smc_read_1(sc, FIFO_RX);
 656         while ((packet & FIFO_EMPTY) == 0) {
 657                 /*
 658                  * Grab an mbuf and attach a cluster.
 659                  */
 660                 MGETHDR(m, M_DONTWAIT, MT_DATA);
 661                 if (m == NULL) {
 662                         break;
 663                 }
 664                 MCLGET(m, M_DONTWAIT);
 665                 if ((m->m_flags & M_EXT) == 0) {
 666                         m_freem(m);
 667                         break;
 668                 }
 669
 670                 /*
 671                  * Point to the start of the packet.
 672                  */
 673                 smc_select_bank(sc, 2);
 674                 smc_write_1(sc, PNR, packet);
 675                 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
 676
 677                 /*
 678                  * Grab status and packet length.
 679                  */
 680                 status = smc_read_2(sc, DATA0);
 681                 len = smc_read_2(sc, DATA0) & RX_LEN_MASK;
 682                 len -= 6;
 683                 if (status & RX_ODDFRM)
 684                         len += 1;
 685
 686                 /*
 687                  * Check for errors.
 688                  */
 689                 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) {
 690                         smc_mmu_wait(sc);
 691                         smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
 692                         ifp->if_ierrors++;
 693                         m_freem(m);
 694                         break;
 695                 }
 696
 697                 /*
 698                  * Set the mbuf up the way we want it.
 699                  */
 700                 m->m_pkthdr.rcvif = ifp;
 701                 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */
 702                 m_adj(m, ETHER_ALIGN);
 703
 704                 /*
 705                  * Pull the packet out of the device.  Make sure we're in the
 706                  * right bank first as things may have changed while we were
 707                  * allocating our mbuf.
 708                  */
 709                 smc_select_bank(sc, 2);
 710                 smc_write_1(sc, PNR, packet);
 711                 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
 712                 data = mtod(m, uint8_t *);
 713                 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1);
 714                 if (len & 1) {
 715                         data += len & ~1;
 716                         *data = smc_read_1(sc, DATA0);
 717                 }
 718
 719                 /*
 720                  * Tell the device we're done.
 721                  */
 722                 smc_mmu_wait(sc);
 723                 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
 724                 if (m == NULL) {
 725                         break;
 726                 }
 727
 728                 if (mhead == NULL) {
 729                         mhead = mtail = m;
 730                         m->m_next = NULL;
 731                 } else {
 732                         mtail->m_next = m;
 733                         mtail = m;
 734                 }
 735                 packet = smc_read_1(sc, FIFO_RX);
 736         }
 737
 738         sc->smc_mask |= RCV_INT;
 739         if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 740                 smc_write_1(sc, MSK, sc->smc_mask);
 741
 742         SMC_UNLOCK(sc);
 743
 744         while (mhead != NULL) {
 745                 m = mhead;
 746                 mhead = mhead->m_next;
 747                 m->m_next = NULL;
 748                 ifp->if_ipackets++;
 749                 (*ifp->if_input)(ifp, m);
 750         }
 751 }
 752
 753 #ifdef DEVICE_POLLING
 754 static void
 755 smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
 756 {
 757         struct smc_softc        *sc;
 758
 759         sc = ifp->if_softc;
 760
 761         SMC_LOCK(sc);
 762         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
 763                 SMC_UNLOCK(sc);
 764                 return;
 765         }
 766         SMC_UNLOCK(sc);
 767
 768         if (cmd == POLL_AND_CHECK_STATUS)
 769                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
 770 }
 771 #endif
 772
 773 static int
 774 smc_intr(void *context)
 775 {
 776         struct smc_softc        *sc;
 777
 778         sc = (struct smc_softc *)context;
 779         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
 780         return (FILTER_HANDLED);
 781 }
 782
 783 static void
 784 smc_task_intr(void *context, int pending)
 785 {
 786         struct smc_softc        *sc;
 787         struct ifnet            *ifp;
 788         u_int                   status, packet, counter, tcr;
 789
 790         (void)pending;
 791         ifp = (struct ifnet *)context;
 792         sc = ifp->if_softc;
 793
 794         SMC_LOCK(sc);
 795         if (sc->smc_shutdown == 1) {
 796                 SMC_UNLOCK(sc);
 797                 return;
 798         }
 799
 800         smc_select_bank(sc, 2);
 801
 802         /*
 803          * Get the current mask, and then block all interrupts while we're
 804          * working.
 805          */
 806         if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 807                 smc_write_1(sc, MSK, 0);
 808
 809         /*
 810          * Find out what interrupts are flagged.
 811          */
 812         status = smc_read_1(sc, IST) & sc->smc_mask;
 813
 814         /*
 815          * Transmit error
 816          */
 817         if (status & TX_INT) {
 818                 /*
 819                  * Kill off the packet if there is one and re-enable transmit.
 820                  */
 821                 packet = smc_read_1(sc, FIFO_TX);
 822                 if ((packet & FIFO_EMPTY) == 0) {
 823                         smc_write_1(sc, PNR, packet);
 824                         smc_write_2(sc, PTR, 0 | PTR_READ |
 825                             PTR_AUTO_INCR);
 826                         tcr = smc_read_2(sc, DATA0);
 827                         if ((tcr & EPHSR_TX_SUC) == 0)
 828                                 device_printf(sc->smc_dev,
 829                                     "bad packet\n");
 830                         smc_mmu_wait(sc);
 831                         smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT);
 832
 833                         smc_select_bank(sc, 0);
 834                         tcr = smc_read_2(sc, TCR);
 835                         tcr |= TCR_TXENA | TCR_PAD_EN;
 836                         smc_write_2(sc, TCR, tcr);
 837                         smc_select_bank(sc, 2);
 838                         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 839                 }
 840
 841                 /*
 842                  * Ack the interrupt.
 843                  */
 844                 smc_write_1(sc, ACK, TX_INT);
 845         }
 846
 847         /*
 848          * Receive
 849          */
 850         if (status & RCV_INT) {
 851                 smc_write_1(sc, ACK, RCV_INT);
 852                 sc->smc_mask &= ~RCV_INT;
 853                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx);
 854         }
 855
 856         /*
 857          * Allocation
 858          */
 859         if (status & ALLOC_INT) {
 860                 smc_write_1(sc, ACK, ALLOC_INT);
 861                 sc->smc_mask &= ~ALLOC_INT;
 862                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 863         }
 864
 865         /*
 866          * Receive overrun
 867          */
 868         if (status & RX_OVRN_INT) {
 869                 smc_write_1(sc, ACK, RX_OVRN_INT);
 870                 ifp->if_ierrors++;
 871         }
 872
 873         /*
 874          * Transmit empty
 875          */
 876         if (status & TX_EMPTY_INT) {
 877                 smc_write_1(sc, ACK, TX_EMPTY_INT);
 878                 sc->smc_mask &= ~TX_EMPTY_INT;
 879                 callout_stop(&sc->smc_watchdog);
 880
 881                 /*
 882                  * Update collision stats.
 883                  */
 884                 smc_select_bank(sc, 0);
 885                 counter = smc_read_2(sc, ECR);
 886                 smc_select_bank(sc, 2);
 887                 ifp->if_collisions +=
 888                     (counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT;
 889                 ifp->if_collisions +=
 890                     (counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT;
 891
 892                 /*
 893                  * See if there are any packets to transmit.
 894                  */
 895                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 896         }
 897
 898         /*
 899          * Update the interrupt mask.
 900          */
 901         if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 902                 smc_write_1(sc, MSK, sc->smc_mask);
 903
 904         SMC_UNLOCK(sc);
 905 }
 906
 907 static u_int
 908 smc_mii_readbits(struct smc_softc *sc, int nbits)
 909 {
 910         u_int   mgmt, mask, val;
 911
 912         SMC_ASSERT_LOCKED(sc);
 913         KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
 914             ("%s: smc_mii_readbits called with bank %d (!= 3)",
 915             device_get_nameunit(sc->smc_dev),
 916             smc_read_2(sc, BSR) & BSR_BANK_MASK));
 917
 918         /*
 919          * Set up the MGMT (aka MII) register.
 920          */
 921         mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO);
 922         smc_write_2(sc, MGMT, mgmt);
 923
 924         /*
 925          * Read the bits in.
 926          */
 927         for (mask = 1 << (nbits - 1), val = 0; mask; mask >>= 1) {
 928                 if (smc_read_2(sc, MGMT) & MGMT_MDI)
 929                         val |= mask;
 930
 931                 smc_write_2(sc, MGMT, mgmt);
 932                 DELAY(1);
 933                 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK);
 934                 DELAY(1);
 935         }
 936
 937         return (val);
 938 }
 939
 940 static void
 941 smc_mii_writebits(struct smc_softc *sc, u_int val, int nbits)
 942 {
 943         u_int   mgmt, mask;
 944
 945         SMC_ASSERT_LOCKED(sc);
 946         KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
 947             ("%s: smc_mii_writebits called with bank %d (!= 3)",
 948             device_get_nameunit(sc->smc_dev),
 949             smc_read_2(sc, BSR) & BSR_BANK_MASK));
 950
 951         /*
 952          * Set up the MGMT (aka MII) register).
 953          */
 954         mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO);
 955         mgmt |= MGMT_MDOE;
 956
 957         /*
 958          * Push the bits out.
 959          */
 960         for (mask = 1 << (nbits - 1); mask; mask >>= 1) {
 961                 if (val & mask)
 962                         mgmt |= MGMT_MDO;
 963                 else
 964                         mgmt &= ~MGMT_MDO;
 965
 966                 smc_write_2(sc, MGMT, mgmt);
 967                 DELAY(1);
 968                 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK);
 969                 DELAY(1);
 970         }
 971 }
 972
 973 int
 974 smc_miibus_readreg(device_t dev, int phy, int reg)
 975 {
 976         struct smc_softc        *sc;
 977         int                     val;
 978
 979         sc = device_get_softc(dev);
 980
 981         SMC_LOCK(sc);
 982
 983         smc_select_bank(sc, 3);
 984
 985         /*
 986          * Send out the idle pattern.
 987          */
 988         smc_mii_writebits(sc, 0xffffffff, 32);
 989
 990         /*
 991          * Start code + read opcode + phy address + phy register
 992          */
 993         smc_mii_writebits(sc, 6 << 10 | phy << 5 | reg, 14);
 994
 995         /*
 996          * Turnaround + data
 997          */
 998         val = smc_mii_readbits(sc, 18);
 999
1000         /*
1001          * Reset the MDIO interface.
1002          */
1003         smc_write_2(sc, MGMT,
1004             smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO));
1005
1006         SMC_UNLOCK(sc);
1007         return (val);
1008 }
1009
1010 void
1011 smc_miibus_writereg(device_t dev, int phy, int reg, int data)
1012 {
1013         struct smc_softc        *sc;
1014
1015         sc = device_get_softc(dev);
1016
1017         SMC_LOCK(sc);
1018
1019         smc_select_bank(sc, 3);
1020
1021         /*
1022          * Send idle pattern.
1023          */
1024         smc_mii_writebits(sc, 0xffffffff, 32);
1025
1026         /*
1027          * Start code + write opcode + phy address + phy register + turnaround
1028          * + data.
1029          */
1030         smc_mii_writebits(sc, 5 << 28 | phy << 23 | reg << 18 | 2 << 16 | data,
1031             32);
1032
1033         /*
1034          * Reset MDIO interface.
1035          */
1036         smc_write_2(sc, MGMT,
1037             smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO));
1038
1039         SMC_UNLOCK(sc);
1040 }
1041
1042 void
1043 smc_miibus_statchg(device_t dev)
1044 {
1045         struct smc_softc        *sc;
1046         struct mii_data         *mii;
1047         uint16_t                tcr;
1048
1049         sc = device_get_softc(dev);
1050         mii = device_get_softc(sc->smc_miibus);
1051
1052         SMC_LOCK(sc);
1053
1054         smc_select_bank(sc, 0);
1055         tcr = smc_read_2(sc, TCR);
1056
1057         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1058                 tcr |= TCR_SWFDUP;
1059         else
1060                 tcr &= ~TCR_SWFDUP;
1061
1062         smc_write_2(sc, TCR, tcr);
1063
1064         SMC_UNLOCK(sc);
1065 }
1066
1067 static int
1068 smc_mii_ifmedia_upd(struct ifnet *ifp)
1069 {
1070         struct smc_softc        *sc;
1071         struct mii_data         *mii;
1072
1073         sc = ifp->if_softc;
1074         if (sc->smc_miibus == NULL)
1075                 return (ENXIO);
1076
1077         mii = device_get_softc(sc->smc_miibus);
1078         return (mii_mediachg(mii));
1079 }
1080
1081 static void
1082 smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1083 {
1084         struct smc_softc        *sc;
1085         struct mii_data         *mii;
1086
1087         sc = ifp->if_softc;
1088         if (sc->smc_miibus == NULL)
1089                 return;
1090
1091         mii = device_get_softc(sc->smc_miibus);
1092         mii_pollstat(mii);
1093         ifmr->ifm_active = mii->mii_media_active;
1094         ifmr->ifm_status = mii->mii_media_status;
1095 }
1096
1097 static void
1098 smc_mii_tick(void *context)
1099 {
1100         struct smc_softc        *sc;
1101
1102         sc = (struct smc_softc *)context;
1103
1104         if (sc->smc_miibus == NULL)
1105                 return;
1106
1107         mii_tick(device_get_softc(sc->smc_miibus));
1108         callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc);
1109 }
1110
1111 static void
1112 smc_mii_mediachg(struct smc_softc *sc)
1113 {
1114
1115         if (sc->smc_miibus == NULL)
1116                 return;
1117         mii_mediachg(device_get_softc(sc->smc_miibus));
1118 }
1119
1120 static int
1121 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command)
1122 {
1123         struct mii_data *mii;
1124
1125         if (sc->smc_miibus == NULL)
1126                 return (EINVAL);
1127
1128         mii = device_get_softc(sc->smc_miibus);
1129         return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command));
1130 }
1131
1132 static void
1133 smc_reset(struct smc_softc *sc)
1134 {
1135         u_int   ctr;
1136
1137         SMC_ASSERT_LOCKED(sc);
1138
1139         smc_select_bank(sc, 2);
1140
1141         /*
1142          * Mask all interrupts.
1143          */
1144         smc_write_1(sc, MSK, 0);
1145
1146         /*
1147          * Tell the device to reset.
1148          */
1149         smc_select_bank(sc, 0);
1150         smc_write_2(sc, RCR, RCR_SOFT_RST);
1151
1152         /*
1153          * Set up the configuration register.
1154          */
1155         smc_select_bank(sc, 1);
1156         smc_write_2(sc, CR, CR_EPH_POWER_EN);
1157         DELAY(1);
1158
1159         /*
1160          * Turn off transmit and receive.
1161          */
1162         smc_select_bank(sc, 0);
1163         smc_write_2(sc, TCR, 0);
1164         smc_write_2(sc, RCR, 0);
1165
1166         /*
1167          * Set up the control register.
1168          */
1169         smc_select_bank(sc, 1);
1170         ctr = smc_read_2(sc, CTR);
1171         ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE;
1172         smc_write_2(sc, CTR, ctr);
1173
1174         /*
1175          * Reset the MMU.
1176          */
1177         smc_select_bank(sc, 2);
1178         smc_mmu_wait(sc);
1179         smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET);
1180 }
1181
1182 static void
1183 smc_enable(struct smc_softc *sc)
1184 {
1185         struct ifnet            *ifp;
1186
1187         SMC_ASSERT_LOCKED(sc);
1188         ifp = sc->smc_ifp;
1189
1190         /*
1191          * Set up the receive/PHY control register.
1192          */
1193         smc_select_bank(sc, 0);
1194         smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT)
1195             | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT));
1196
1197         /*
1198          * Set up the transmit and receive control registers.
1199          */
1200         smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN);
1201         smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC);
1202
1203         /*
1204          * Set up the interrupt mask.
1205          */
1206         smc_select_bank(sc, 2);
1207         sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT;
1208         if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1209                 smc_write_1(sc, MSK, sc->smc_mask);
1210 }
1211
1212 static void
1213 smc_stop(struct smc_softc *sc)
1214 {
1215
1216         SMC_ASSERT_LOCKED(sc);
1217
1218         /*
1219          * Turn off watchdog.
1220          */
1221         callout_stop(&sc->smc_watchdog);
1222
1223         /*
1224          * Mask all interrupts.
1225          */
1226         smc_select_bank(sc, 2);
1227         sc->smc_mask = 0;
1228         smc_write_1(sc, MSK, 0);
1229 #ifdef DEVICE_POLLING
1230         ether_poll_deregister(sc->smc_ifp);
1231         sc->smc_ifp->if_capenable &= ~IFCAP_POLLING;
1232 #endif
1233
1234         /*
1235          * Disable transmit and receive.
1236          */
1237         smc_select_bank(sc, 0);
1238         smc_write_2(sc, TCR, 0);
1239         smc_write_2(sc, RCR, 0);
1240
1241         sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1242 }
1243
1244 static void
1245 smc_watchdog(void *arg)
1246 {
1247         struct smc_softc        *sc;
1248
1249         sc = (struct smc_softc *)arg;
1250         SMC_LOCK(sc);
1251         if (sc->smc_shutdown == 1) {
1252                 SMC_UNLOCK(sc);
1253                 return;
1254         }
1255         SMC_UNLOCK(sc);
1256         device_printf(sc->smc_dev, "watchdog timeout\n");
1257         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
1258 }
1259
1260 static void
1261 smc_init(void *context)
1262 {
1263         struct smc_softc        *sc;
1264
1265         sc = (struct smc_softc *)context;
1266         SMC_LOCK(sc);
1267         smc_init_locked(sc);
1268         SMC_UNLOCK(sc);
1269 }
1270
1271 static void
1272 smc_init_locked(struct smc_softc *sc)
1273 {
1274         struct ifnet    *ifp;
1275
1276         ifp = sc->smc_ifp;
1277
1278         SMC_ASSERT_LOCKED(sc);
1279
1280         smc_reset(sc);
1281         smc_enable(sc);
1282
1283         ifp->if_drv_flags |= IFF_DRV_RUNNING;
1284         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1285
1286         smc_start_locked(ifp);
1287
1288         if (sc->smc_mii_tick != NULL)
1289                 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc);
1290
1291 #ifdef DEVICE_POLLING
1292         SMC_UNLOCK(sc);
1293         ether_poll_register(smc_poll, ifp);
1294         SMC_LOCK(sc);
1295         ifp->if_capenable |= IFCAP_POLLING;
1296 #endif
1297 }
1298
1299 static int
1300 smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1301 {
1302         struct smc_softc        *sc;
1303         int                     error;
1304
1305         sc = ifp->if_softc;
1306         error = 0;
1307
1308         switch (cmd) {
1309         case SIOCSIFFLAGS:
1310                 if ((ifp->if_flags & IFF_UP) == 0 &&
1311                     (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1312                         SMC_LOCK(sc);
1313                         smc_stop(sc);
1314                         SMC_UNLOCK(sc);
1315                 } else {
1316                         smc_init(sc);
1317                         if (sc->smc_mii_mediachg != NULL)
1318                                 sc->smc_mii_mediachg(sc);
1319                 }
1320                 break;
1321
1322         case SIOCADDMULTI:
1323         case SIOCDELMULTI:
1324                 /* XXX
1325                 SMC_LOCK(sc);
1326                 smc_setmcast(sc);
1327                 SMC_UNLOCK(sc);
1328                 */
1329                 error = EINVAL;
1330                 break;
1331
1332         case SIOCGIFMEDIA:
1333         case SIOCSIFMEDIA:
1334                 if (sc->smc_mii_mediaioctl == NULL) {
1335                         error = EINVAL;
1336                         break;
1337                 }
1338                 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd);
1339                 break;
1340
1341         default:
1342                 error = ether_ioctl(ifp, cmd, data);
1343                 break;
1344         }
1345
1346         return (error);
1347 }