sys/dev/smc/if_smc.c

   1 /*-
   2  * Copyright (c) 2008 Benno Rice.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  19  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  20  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  */
  24
  25 #include <sys/cdefs.h>
  26 __FBSDID("$FreeBSD$");
  27
  28 /*
  29  * Driver for SMSC LAN91C111, may work for older variants.
  30  */
  31
  32 #ifdef HAVE_KERNEL_OPTION_HEADERS
  33 #include "opt_device_polling.h"
  34 #endif
  35
  36 #include <sys/param.h>
  37 #include <sys/systm.h>
  38 #include <sys/errno.h>
  39 #include <sys/kernel.h>
  40 #include <sys/sockio.h>
  41 #include <sys/malloc.h>
  42 #include <sys/mbuf.h>
  43 #include <sys/queue.h>
  44 #include <sys/socket.h>
  45 #include <sys/syslog.h>
  46 #include <sys/taskqueue.h>
  47
  48 #include <sys/module.h>
  49 #include <sys/bus.h>
  50
  51 #include <machine/bus.h>
  52 #include <machine/resource.h>
  53 #include <sys/rman.h>
  54
  55 #include <net/ethernet.h>
  56 #include <net/if.h>
  57 #include <net/if_arp.h>
  58 #include <net/if_dl.h>
  59 #include <net/if_types.h>
  60 #include <net/if_mib.h>
  61 #include <net/if_media.h>
  62
  63 #ifdef INET
  64 #include <netinet/in.h>
  65 #include <netinet/in_systm.h>
  66 #include <netinet/in_var.h>
  67 #include <netinet/ip.h>
  68 #endif
  69
  70 #include <net/bpf.h>
  71 #include <net/bpfdesc.h>
  72
  73 #include <dev/smc/if_smcreg.h>
  74 #include <dev/smc/if_smcvar.h>
  75
  76 #include <dev/mii/mii.h>
  77 #include <dev/mii/miivar.h>
  78
  79 #define SMC_LOCK(sc)            mtx_lock(&(sc)->smc_mtx)
  80 #define SMC_UNLOCK(sc)          mtx_unlock(&(sc)->smc_mtx)
  81 #define SMC_ASSERT_LOCKED(sc)   mtx_assert(&(sc)->smc_mtx, MA_OWNED)
  82
  83 #define SMC_INTR_PRIORITY       0
  84 #define SMC_RX_PRIORITY         5
  85 #define SMC_TX_PRIORITY         10
  86
  87 devclass_t      smc_devclass;
  88
  89 static const char *smc_chip_ids[16] = {
  90         NULL, NULL, NULL,
  91         /* 3 */ "SMSC LAN91C90 or LAN91C92",
  92         /* 4 */ "SMSC LAN91C94",
  93         /* 5 */ "SMSC LAN91C95",
  94         /* 6 */ "SMSC LAN91C96",
  95         /* 7 */ "SMSC LAN91C100",
  96         /* 8 */ "SMSC LAN91C100FD",
  97         /* 9 */ "SMSC LAN91C110FD or LAN91C111FD",
  98         NULL, NULL, NULL,
  99         NULL, NULL, NULL
 100 };
 101
 102 static void     smc_init(void *);
 103 static void     smc_start(struct ifnet *);
 104 static void     smc_stop(struct smc_softc *);
 105 static int      smc_ioctl(struct ifnet *, u_long, caddr_t);
 106
 107 static void     smc_init_locked(struct smc_softc *);
 108 static void     smc_start_locked(struct ifnet *);
 109 static void     smc_reset(struct smc_softc *);
 110 static int      smc_mii_ifmedia_upd(struct ifnet *);
 111 static void     smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 112 static void     smc_mii_tick(void *);
 113 static void     smc_mii_mediachg(struct smc_softc *);
 114 static int      smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long);
 115
 116 static void     smc_task_intr(void *, int);
 117 static void     smc_task_rx(void *, int);
 118 static void     smc_task_tx(void *, int);
 119
 120 static driver_filter_t  smc_intr;
 121 static timeout_t        smc_watchdog;
 122 #ifdef DEVICE_POLLING
 123 static poll_handler_t   smc_poll;
 124 #endif
 125
 126 static __inline void
 127 smc_select_bank(struct smc_softc *sc, uint16_t bank)
 128 {
 129
 130         bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK);
 131 }
 132
 133 /* Never call this when not in bank 2. */
 134 static __inline void
 135 smc_mmu_wait(struct smc_softc *sc)
 136 {
 137
 138         KASSERT((bus_read_2(sc->smc_reg, BSR) &
 139             BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2",
 140             device_get_nameunit(sc->smc_dev)));
 141         while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY)
 142                 ;
 143 }
 144
 145 static __inline uint8_t
 146 smc_read_1(struct smc_softc *sc, bus_addr_t offset)
 147 {
 148
 149         return (bus_read_1(sc->smc_reg, offset));
 150 }
 151
 152 static __inline void
 153 smc_write_1(struct smc_softc *sc, bus_addr_t offset, uint8_t val)
 154 {
 155
 156         bus_write_1(sc->smc_reg, offset, val);
 157 }
 158
 159 static __inline uint16_t
 160 smc_read_2(struct smc_softc *sc, bus_addr_t offset)
 161 {
 162
 163         return (bus_read_2(sc->smc_reg, offset));
 164 }
 165
 166 static __inline void
 167 smc_write_2(struct smc_softc *sc, bus_addr_t offset, uint16_t val)
 168 {
 169
 170         bus_write_2(sc->smc_reg, offset, val);
 171 }
 172
 173 static __inline void
 174 smc_read_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap,
 175     bus_size_t count)
 176 {
 177
 178         bus_read_multi_2(sc->smc_reg, offset, datap, count);
 179 }
 180
 181 static __inline void
 182 smc_write_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap,
 183     bus_size_t count)
 184 {
 185
 186         bus_write_multi_2(sc->smc_reg, offset, datap, count);
 187 }
 188
 189 int
 190 smc_probe(device_t dev)
 191 {
 192         int                     rid, type, error;
 193         uint16_t                val;
 194         struct smc_softc        *sc;
 195         struct resource         *reg;
 196
 197         sc = device_get_softc(dev);
 198         rid = 0;
 199         type = SYS_RES_IOPORT;
 200         error = 0;
 201
 202         if (sc->smc_usemem)
 203                 type = SYS_RES_MEMORY;
 204
 205         reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE);
 206         if (reg == NULL) {
 207                 if (bootverbose)
 208                         device_printf(dev,
 209                             "could not allocate I/O resource for probe\n");
 210                 return (ENXIO);
 211         }
 212
 213         /* Check for the identification value in the BSR. */
 214         val = bus_read_2(reg, BSR);
 215         if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
 216                 if (bootverbose)
 217                         device_printf(dev, "identification value not in BSR\n");
 218                 error = ENXIO;
 219                 goto done;
 220         }
 221
 222         /*
 223          * Try switching banks and make sure we still get the identification
 224          * value.
 225          */
 226         bus_write_2(reg, BSR, 0);
 227         val = bus_read_2(reg, BSR);
 228         if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
 229                 if (bootverbose)
 230                         device_printf(dev,
 231                             "identification value not in BSR after write\n");
 232                 error = ENXIO;
 233                 goto done;
 234         }
 235
 236 #if 0
 237         /* Check the BAR. */
 238         bus_write_2(reg, BSR, 1);
 239         val = bus_read_2(reg, BAR);
 240         val = BAR_ADDRESS(val);
 241         if (rman_get_start(reg) != val) {
 242                 if (bootverbose)
 243                         device_printf(dev, "BAR address %x does not match "
 244                             "I/O resource address %lx\n", val,
 245                             rman_get_start(reg));
 246                 error = ENXIO;
 247                 goto done;
 248         }
 249 #endif
 250
 251         /* Compare REV against known chip revisions. */
 252         bus_write_2(reg, BSR, 3);
 253         val = bus_read_2(reg, REV);
 254         val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
 255         if (smc_chip_ids[val] == NULL) {
 256                 if (bootverbose)
 257                         device_printf(dev, "Unknown chip revision: %d\n", val);
 258                 error = ENXIO;
 259                 goto done;
 260         }
 261
 262         device_set_desc(dev, smc_chip_ids[val]);
 263
 264 done:
 265         bus_release_resource(dev, type, rid, reg);
 266         return (error);
 267 }
 268
 269 int
 270 smc_attach(device_t dev)
 271 {
 272         int                     type, error;
 273         uint16_t                val;
 274         u_char                  eaddr[ETHER_ADDR_LEN];
 275         struct smc_softc        *sc;
 276         struct ifnet            *ifp;
 277
 278         sc = device_get_softc(dev);
 279         error = 0;
 280
 281         sc->smc_dev = dev;
 282
 283         ifp = sc->smc_ifp = if_alloc(IFT_ETHER);
 284         if (ifp == NULL) {
 285                 error = ENOSPC;
 286                 goto done;
 287         }
 288
 289         mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
 290
 291         /* Set up watchdog callout. */
 292         callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0);
 293
 294         type = SYS_RES_IOPORT;
 295         if (sc->smc_usemem)
 296                 type = SYS_RES_MEMORY;
 297
 298         sc->smc_reg_rid = 0;
 299         sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0,
 300             16, RF_ACTIVE);
 301         if (sc->smc_reg == NULL) {
 302                 error = ENXIO;
 303                 goto done;
 304         }
 305
 306         sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0,
 307             ~0, 1, RF_ACTIVE | RF_SHAREABLE);
 308         if (sc->smc_irq == NULL) {
 309                 error = ENXIO;
 310                 goto done;
 311         }
 312
 313         SMC_LOCK(sc);
 314         smc_reset(sc);
 315         SMC_UNLOCK(sc);
 316
 317         smc_select_bank(sc, 3);
 318         val = smc_read_2(sc, REV);
 319         sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
 320         sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT;
 321         if (bootverbose)
 322                 device_printf(dev, "revision %x\n", sc->smc_rev);
 323
 324         callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx,
 325             CALLOUT_RETURNUNLOCKED);
 326         if (sc->smc_chip >= REV_CHIP_91110FD) {
 327                 mii_phy_probe(dev, &sc->smc_miibus, smc_mii_ifmedia_upd,
 328                     smc_mii_ifmedia_sts);
 329                 if (sc->smc_miibus != NULL) {
 330                         sc->smc_mii_tick = smc_mii_tick;
 331                         sc->smc_mii_mediachg = smc_mii_mediachg;
 332                         sc->smc_mii_mediaioctl = smc_mii_mediaioctl;
 333                 }
 334         }
 335
 336         smc_select_bank(sc, 1);
 337         eaddr[0] = smc_read_1(sc, IAR0);
 338         eaddr[1] = smc_read_1(sc, IAR1);
 339         eaddr[2] = smc_read_1(sc, IAR2);
 340         eaddr[3] = smc_read_1(sc, IAR3);
 341         eaddr[4] = smc_read_1(sc, IAR4);
 342         eaddr[5] = smc_read_1(sc, IAR5);
 343
 344         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 345         ifp->if_softc = sc;
 346         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 347         ifp->if_init = smc_init;
 348         ifp->if_ioctl = smc_ioctl;
 349         ifp->if_start = smc_start;
 350         IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
 351         IFQ_SET_READY(&ifp->if_snd);
 352
 353         ifp->if_capabilities = ifp->if_capenable = 0;
 354
 355 #ifdef DEVICE_POLLING
 356         ifp->if_capabilities |= IFCAP_POLLING;
 357 #endif
 358
 359         ether_ifattach(ifp, eaddr);
 360
 361         /* Set up taskqueue */
 362         TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp);
 363         TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp);
 364         TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp);
 365         sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT,
 366             taskqueue_thread_enqueue, &sc->smc_tq);
 367         taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq",
 368             device_get_nameunit(sc->smc_dev));
 369
 370         /* Mask all interrupts. */
 371         sc->smc_mask = 0;
 372         smc_write_1(sc, MSK, 0);
 373
 374         /* Wire up interrupt */
 375         error = bus_setup_intr(dev, sc->smc_irq,
 376             INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih);
 377         if (error != 0)
 378                 goto done;
 379
 380 done:
 381         if (error != 0)
 382                 smc_detach(dev);
 383         return (error);
 384 }
 385
 386 int
 387 smc_detach(device_t dev)
 388 {
 389         int                     type;
 390         struct smc_softc        *sc;
 391
 392         sc = device_get_softc(dev);
 393         SMC_LOCK(sc);
 394         smc_stop(sc);
 395         SMC_UNLOCK(sc);
 396
 397 #ifdef DEVICE_POLLING
 398         if (sc->smc_ifp->if_capenable & IFCAP_POLLING)
 399                 ether_poll_deregister(sc->smc_ifp);
 400 #endif
 401
 402         if (sc->smc_ih != NULL)
 403                 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih);
 404
 405         if (sc->smc_tq != NULL) {
 406                 taskqueue_drain(sc->smc_tq, &sc->smc_intr);
 407                 taskqueue_drain(sc->smc_tq, &sc->smc_rx);
 408                 taskqueue_drain(sc->smc_tq, &sc->smc_tx);
 409                 taskqueue_free(sc->smc_tq);
 410                 sc->smc_tq = NULL;
 411         }
 412
 413
 414         if (sc->smc_ifp != NULL) {
 415                 ether_ifdetach(sc->smc_ifp);
 416                 if_free(sc->smc_ifp);
 417         }
 418
 419         if (sc->smc_miibus != NULL) {
 420                 device_delete_child(sc->smc_dev, sc->smc_miibus);
 421                 bus_generic_detach(sc->smc_dev);
 422         }
 423
 424         if (sc->smc_reg != NULL) {
 425                 type = SYS_RES_IOPORT;
 426                 if (sc->smc_usemem)
 427                         type = SYS_RES_MEMORY;
 428
 429                 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid,
 430                     sc->smc_reg);
 431         }
 432
 433         if (sc->smc_irq != NULL)
 434                 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid,
 435                    sc->smc_irq);
 436
 437         if (mtx_initialized(&sc->smc_mtx))
 438                 mtx_destroy(&sc->smc_mtx);
 439
 440         return (0);
 441 }
 442
 443 static void
 444 smc_start(struct ifnet *ifp)
 445 {
 446         struct smc_softc        *sc;
 447
 448         sc = ifp->if_softc;
 449         SMC_LOCK(sc);
 450         smc_start_locked(ifp);
 451         SMC_UNLOCK(sc);
 452 }
 453
 454 static void
 455 smc_start_locked(struct ifnet *ifp)
 456 {
 457         struct smc_softc        *sc;
 458         struct mbuf             *m;
 459         u_int                   len, npages, spin_count;
 460
 461         sc = ifp->if_softc;
 462         SMC_ASSERT_LOCKED(sc);
 463
 464         if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
 465                 return;
 466         if (IFQ_IS_EMPTY(&ifp->if_snd))
 467                 return;
 468
 469         /*
 470          * Grab the next packet.  If it's too big, drop it.
 471          */
 472         IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
 473         len = m_length(m, NULL);
 474         len += (len & 1);
 475         if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) {
 476                 if_printf(ifp, "large packet discarded\n");
 477                 ++ifp->if_oerrors;
 478                 m_freem(m);
 479                 return; /* XXX readcheck? */
 480         }
 481
 482         /*
 483          * Flag that we're busy.
 484          */
 485         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 486         sc->smc_pending = m;
 487
 488         /*
 489          * Work out how many 256 byte "pages" we need.  We have to include the
 490          * control data for the packet in this calculation.
 491          */
 492         npages = (len * PKT_CTRL_DATA_LEN) >> 8;
 493         if (npages == 0)
 494                 npages = 1;
 495
 496         /*
 497          * Request memory.
 498          */
 499         smc_select_bank(sc, 2);
 500         smc_mmu_wait(sc);
 501         smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages);
 502
 503         /*
 504          * Spin briefly to see if the allocation succeeds.
 505          */
 506         spin_count = TX_ALLOC_WAIT_TIME;
 507         do {
 508                 if (smc_read_1(sc, IST) & ALLOC_INT) {
 509                         smc_write_1(sc, ACK, ALLOC_INT);
 510                         break;
 511                 }
 512         } while (--spin_count);
 513
 514         /*
 515          * If the allocation is taking too long, unmask the alloc interrupt
 516          * and wait.
 517          */
 518         if (spin_count == 0) {
 519                 sc->smc_mask |= ALLOC_INT;
 520                 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 521                         smc_write_1(sc, MSK, sc->smc_mask);
 522                 return;
 523         }
 524
 525         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 526 }
 527
 528 static void
 529 smc_task_tx(void *context, int pending)
 530 {
 531         struct ifnet            *ifp;
 532         struct smc_softc        *sc;
 533         struct mbuf             *m, *m0;
 534         u_int                   packet, len;
 535         uint8_t                 *data;
 536
 537         (void)pending;
 538         ifp = (struct ifnet *)context;
 539         sc = ifp->if_softc;
 540
 541         SMC_LOCK(sc);
 542
 543         if (sc->smc_pending == NULL) {
 544                 SMC_UNLOCK(sc);
 545                 goto next_packet;
 546         }
 547
 548         m = m0 = sc->smc_pending;
 549         sc->smc_pending = NULL;
 550         smc_select_bank(sc, 2);
 551
 552         /*
 553          * Check the allocation result.
 554          */
 555         packet = smc_read_1(sc, ARR);
 556
 557         /*
 558          * If the allocation failed, requeue the packet and retry.
 559          */
 560         if (packet & ARR_FAILED) {
 561                 IFQ_DRV_PREPEND(&ifp->if_snd, m);
 562                 ++ifp->if_oerrors;
 563                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 564                 smc_start_locked(ifp);
 565                 SMC_UNLOCK(sc);
 566                 return;
 567         }
 568
 569         /*
 570          * Tell the device to write to our packet number.
 571          */
 572         smc_write_1(sc, PNR, packet);
 573         smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR);
 574
 575         /*
 576          * Tell the device how long the packet is (including control data).
 577          */
 578         len = m_length(m, 0);
 579         len += PKT_CTRL_DATA_LEN;
 580         smc_write_2(sc, DATA0, 0);
 581         smc_write_2(sc, DATA0, len);
 582
 583         /*
 584          * Push the data out to the device.
 585          */
 586         data = NULL;
 587         for (; m != NULL; m = m->m_next) {
 588                 data = mtod(m, uint8_t *);
 589                 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2);
 590         }
 591
 592         /*
 593          * Push out the control byte and and the odd byte if needed.
 594          */
 595         if ((len & 1) != 0 && data != NULL)
 596                 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[m->m_len - 1]);
 597         else
 598                 smc_write_2(sc, DATA0, 0);
 599
 600         /*
 601          * Unmask the TX empty interrupt.
 602          */
 603         sc->smc_mask |= TX_EMPTY_INT;
 604         if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 605                 smc_write_1(sc, MSK, sc->smc_mask);
 606
 607         /*
 608          * Enqueue the packet.
 609          */
 610         smc_mmu_wait(sc);
 611         smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE);
 612         callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc);
 613
 614         /*
 615          * Finish up.
 616          */
 617         ifp->if_opackets++;
 618         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 619         SMC_UNLOCK(sc);
 620         BPF_MTAP(ifp, m0);
 621         m_freem(m0);
 622
 623 next_packet:
 624         /*
 625          * See if there's anything else to do.
 626          */
 627         smc_start(ifp);
 628 }
 629
 630 static void
 631 smc_task_rx(void *context, int pending)
 632 {
 633         u_int                   packet, status, len;
 634         uint8_t                 *data;
 635         struct ifnet            *ifp;
 636         struct smc_softc        *sc;
 637         struct mbuf             *m, *mhead, *mtail;
 638
 639         (void)pending;
 640         ifp = (struct ifnet *)context;
 641         sc = ifp->if_softc;
 642         mhead = mtail = NULL;
 643
 644         SMC_LOCK(sc);
 645
 646         packet = smc_read_1(sc, FIFO_RX);
 647         while ((packet & FIFO_EMPTY) == 0) {
 648                 /*
 649                  * Grab an mbuf and attach a cluster.
 650                  */
 651                 MGETHDR(m, M_DONTWAIT, MT_DATA);
 652                 if (m == NULL) {
 653                         break;
 654                 }
 655                 MCLGET(m, M_DONTWAIT);
 656                 if ((m->m_flags & M_EXT) == 0) {
 657                         m_freem(m);
 658                         break;
 659                 }
 660
 661                 /*
 662                  * Point to the start of the packet.
 663                  */
 664                 smc_select_bank(sc, 2);
 665                 smc_write_1(sc, PNR, packet);
 666                 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
 667
 668                 /*
 669                  * Grab status and packet length.
 670                  */
 671                 status = smc_read_2(sc, DATA0);
 672                 len = smc_read_2(sc, DATA0) & RX_LEN_MASK;
 673                 len -= 6;
 674                 if (status & RX_ODDFRM)
 675                         len += 1;
 676
 677                 /*
 678                  * Check for errors.
 679                  */
 680                 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) {
 681                         smc_mmu_wait(sc);
 682                         smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
 683                         ifp->if_ierrors++;
 684                         m_freem(m);
 685                         break;
 686                 }
 687
 688                 /*
 689                  * Set the mbuf up the way we want it.
 690                  */
 691                 m->m_pkthdr.rcvif = ifp;
 692                 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */
 693                 m_adj(m, ETHER_ALIGN);
 694
 695                 /*
 696                  * Pull the packet out of the device.  Make sure we're in the
 697                  * right bank first as things may have changed while we were
 698                  * allocating our mbuf.
 699                  */
 700                 smc_select_bank(sc, 2);
 701                 smc_write_1(sc, PNR, packet);
 702                 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
 703                 data = mtod(m, uint8_t *);
 704                 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1);
 705                 if (len & 1) {
 706                         data += len & ~1;
 707                         *data = smc_read_1(sc, DATA0);
 708                 }
 709
 710                 /*
 711                  * Tell the device we're done.
 712                  */
 713                 smc_mmu_wait(sc);
 714                 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
 715                 if (m == NULL) {
 716                         break;
 717                 }
 718
 719                 if (mhead == NULL) {
 720                         mhead = mtail = m;
 721                         m->m_next = NULL;
 722                 } else {
 723                         mtail->m_next = m;
 724                         mtail = m;
 725                 }
 726                 packet = smc_read_1(sc, FIFO_RX);
 727         }
 728
 729         sc->smc_mask |= RCV_INT;
 730         if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 731                 smc_write_1(sc, MSK, sc->smc_mask);
 732
 733         SMC_UNLOCK(sc);
 734
 735         while (mhead != NULL) {
 736                 m = mhead;
 737                 mhead = mhead->m_next;
 738                 m->m_next = NULL;
 739                 ifp->if_ipackets++;
 740                 (*ifp->if_input)(ifp, m);
 741         }
 742 }
 743
 744 #ifdef DEVICE_POLLING
 745 static void
 746 smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
 747 {
 748         struct smc_softc        *sc;
 749
 750         sc = ifp->if_softc;
 751
 752         SMC_LOCK(sc);
 753         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
 754                 SMC_UNLOCK(sc);
 755                 return;
 756         }
 757         SMC_UNLOCK(sc);
 758
 759         if (cmd == POLL_AND_CHECK_STATUS)
 760                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
 761 }
 762 #endif
 763
 764 static int
 765 smc_intr(void *context)
 766 {
 767         struct smc_softc        *sc;
 768
 769         sc = (struct smc_softc *)context;
 770         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
 771         return (FILTER_HANDLED);
 772 }
 773
 774 static void
 775 smc_task_intr(void *context, int pending)
 776 {
 777         struct smc_softc        *sc;
 778         struct ifnet            *ifp;
 779         u_int                   status, packet, counter, tcr;
 780
 781         (void)pending;
 782         ifp = (struct ifnet *)context;
 783         sc = ifp->if_softc;
 784
 785         SMC_LOCK(sc);
 786
 787         smc_select_bank(sc, 2);
 788
 789         /*
 790          * Get the current mask, and then block all interrupts while we're
 791          * working.
 792          */
 793         if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 794                 smc_write_1(sc, MSK, 0);
 795
 796         /*
 797          * Find out what interrupts are flagged.
 798          */
 799         status = smc_read_1(sc, IST) & sc->smc_mask;
 800
 801         /*
 802          * Transmit error
 803          */
 804         if (status & TX_INT) {
 805                 /*
 806                  * Kill off the packet if there is one and re-enable transmit.
 807                  */
 808                 packet = smc_read_1(sc, FIFO_TX);
 809                 if ((packet & FIFO_EMPTY) == 0) {
 810                         smc_write_1(sc, PNR, packet);
 811                         smc_write_2(sc, PTR, 0 | PTR_READ |
 812                             PTR_AUTO_INCR);
 813                         tcr = smc_read_2(sc, DATA0);
 814                         if ((tcr & EPHSR_TX_SUC) == 0)
 815                                 device_printf(sc->smc_dev,
 816                                     "bad packet\n");
 817                         smc_mmu_wait(sc);
 818                         smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT);
 819
 820                         smc_select_bank(sc, 0);
 821                         tcr = smc_read_2(sc, TCR);
 822                         tcr |= TCR_TXENA | TCR_PAD_EN;
 823                         smc_write_2(sc, TCR, tcr);
 824                         smc_select_bank(sc, 2);
 825                         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 826                 }
 827
 828                 /*
 829                  * Ack the interrupt.
 830                  */
 831                 smc_write_1(sc, ACK, TX_INT);
 832         }
 833
 834         /*
 835          * Receive
 836          */
 837         if (status & RCV_INT) {
 838                 smc_write_1(sc, ACK, RCV_INT);
 839                 sc->smc_mask &= ~RCV_INT;
 840                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx);
 841         }
 842
 843         /*
 844          * Allocation
 845          */
 846         if (status & ALLOC_INT) {
 847                 smc_write_1(sc, ACK, ALLOC_INT);
 848                 sc->smc_mask &= ~ALLOC_INT;
 849                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 850         }
 851
 852         /*
 853          * Receive overrun
 854          */
 855         if (status & RX_OVRN_INT) {
 856                 smc_write_1(sc, ACK, RX_OVRN_INT);
 857                 ifp->if_ierrors++;
 858         }
 859
 860         /*
 861          * Transmit empty
 862          */
 863         if (status & TX_EMPTY_INT) {
 864                 smc_write_1(sc, ACK, TX_EMPTY_INT);
 865                 sc->smc_mask &= ~TX_EMPTY_INT;
 866                 callout_stop(&sc->smc_watchdog);
 867
 868                 /*
 869                  * Update collision stats.
 870                  */
 871                 smc_select_bank(sc, 0);
 872                 counter = smc_read_2(sc, ECR);
 873                 smc_select_bank(sc, 2);
 874                 ifp->if_collisions +=
 875                     (counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT;
 876                 ifp->if_collisions +=
 877                     (counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT;
 878
 879                 /*
 880                  * See if there are any packets to transmit.
 881                  */
 882                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 883         }
 884
 885         /*
 886          * Update the interrupt mask.
 887          */
 888         if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 889                 smc_write_1(sc, MSK, sc->smc_mask);
 890
 891         SMC_UNLOCK(sc);
 892 }
 893
 894 static u_int
 895 smc_mii_readbits(struct smc_softc *sc, int nbits)
 896 {
 897         u_int   mgmt, mask, val;
 898
 899         SMC_ASSERT_LOCKED(sc);
 900         KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
 901             ("%s: smc_mii_readbits called with bank %d (!= 3)",
 902             device_get_nameunit(sc->smc_dev),
 903             smc_read_2(sc, BSR) & BSR_BANK_MASK));
 904
 905         /*
 906          * Set up the MGMT (aka MII) register.
 907          */
 908         mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO);
 909         smc_write_2(sc, MGMT, mgmt);
 910
 911         /*
 912          * Read the bits in.
 913          */
 914         for (mask = 1 << (nbits - 1), val = 0; mask; mask >>= 1) {
 915                 if (smc_read_2(sc, MGMT) & MGMT_MDI)
 916                         val |= mask;
 917
 918                 smc_write_2(sc, MGMT, mgmt);
 919                 DELAY(1);
 920                 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK);
 921                 DELAY(1);
 922         }
 923
 924         return (val);
 925 }
 926
 927 static void
 928 smc_mii_writebits(struct smc_softc *sc, u_int val, int nbits)
 929 {
 930         u_int   mgmt, mask;
 931
 932         SMC_ASSERT_LOCKED(sc);
 933         KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
 934             ("%s: smc_mii_writebits called with bank %d (!= 3)",
 935             device_get_nameunit(sc->smc_dev),
 936             smc_read_2(sc, BSR) & BSR_BANK_MASK));
 937
 938         /*
 939          * Set up the MGMT (aka MII) register).
 940          */
 941         mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO);
 942         mgmt |= MGMT_MDOE;
 943
 944         /*
 945          * Push the bits out.
 946          */
 947         for (mask = 1 << (nbits - 1); mask; mask >>= 1) {
 948                 if (val & mask)
 949                         mgmt |= MGMT_MDO;
 950                 else
 951                         mgmt &= ~MGMT_MDO;
 952
 953                 smc_write_2(sc, MGMT, mgmt);
 954                 DELAY(1);
 955                 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK);
 956                 DELAY(1);
 957         }
 958 }
 959
 960 int
 961 smc_miibus_readreg(device_t dev, int phy, int reg)
 962 {
 963         struct smc_softc        *sc;
 964         int                     val;
 965
 966         sc = device_get_softc(dev);
 967
 968         SMC_LOCK(sc);
 969
 970         smc_select_bank(sc, 3);
 971
 972         /*
 973          * Send out the idle pattern.
 974          */
 975         smc_mii_writebits(sc, 0xffffffff, 32);
 976
 977         /*
 978          * Start code + read opcode + phy address + phy register
 979          */
 980         smc_mii_writebits(sc, 6 << 10 | phy << 5 | reg, 14);
 981
 982         /*
 983          * Turnaround + data
 984          */
 985         val = smc_mii_readbits(sc, 18);
 986
 987         /*
 988          * Reset the MDIO interface.
 989          */
 990         smc_write_2(sc, MGMT,
 991             smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO));
 992
 993         SMC_UNLOCK(sc);
 994         return (val);
 995 }
 996
 997 void
 998 smc_miibus_writereg(device_t dev, int phy, int reg, int data)
 999 {
1000         struct smc_softc        *sc;
1001
1002         sc = device_get_softc(dev);
1003
1004         SMC_LOCK(sc);
1005
1006         smc_select_bank(sc, 3);
1007
1008         /*
1009          * Send idle pattern.
1010          */
1011         smc_mii_writebits(sc, 0xffffffff, 32);
1012
1013         /*
1014          * Start code + write opcode + phy address + phy register + turnaround
1015          * + data.
1016          */
1017         smc_mii_writebits(sc, 5 << 28 | phy << 23 | reg << 18 | 2 << 16 | data,
1018             32);
1019
1020         /*
1021          * Reset MDIO interface.
1022          */
1023         smc_write_2(sc, MGMT,
1024             smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO));
1025
1026         SMC_UNLOCK(sc);
1027 }
1028
1029 void
1030 smc_miibus_statchg(device_t dev)
1031 {
1032         struct smc_softc        *sc;
1033         struct mii_data         *mii;
1034         uint16_t                tcr;
1035
1036         sc = device_get_softc(dev);
1037         mii = device_get_softc(sc->smc_miibus);
1038
1039         SMC_LOCK(sc);
1040
1041         smc_select_bank(sc, 0);
1042         tcr = smc_read_2(sc, TCR);
1043
1044         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1045                 tcr |= TCR_SWFDUP;
1046         else
1047                 tcr &= ~TCR_SWFDUP;
1048
1049         smc_write_2(sc, TCR, tcr);
1050
1051         SMC_UNLOCK(sc);
1052 }
1053
1054 static int
1055 smc_mii_ifmedia_upd(struct ifnet *ifp)
1056 {
1057         struct smc_softc        *sc;
1058         struct mii_data         *mii;
1059
1060         sc = ifp->if_softc;
1061         if (sc->smc_miibus == NULL)
1062                 return (ENXIO);
1063
1064         mii = device_get_softc(sc->smc_miibus);
1065         return (mii_mediachg(mii));
1066 }
1067
1068 static void
1069 smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1070 {
1071         struct smc_softc        *sc;
1072         struct mii_data         *mii;
1073
1074         sc = ifp->if_softc;
1075         if (sc->smc_miibus == NULL)
1076                 return;
1077
1078         mii = device_get_softc(sc->smc_miibus);
1079         mii_pollstat(mii);
1080         ifmr->ifm_active = mii->mii_media_active;
1081         ifmr->ifm_status = mii->mii_media_status;
1082 }
1083
1084 static void
1085 smc_mii_tick(void *context)
1086 {
1087         struct smc_softc        *sc;
1088
1089         sc = (struct smc_softc *)context;
1090
1091         if (sc->smc_miibus == NULL)
1092                 return;
1093
1094         SMC_UNLOCK(sc);
1095
1096         mii_tick(device_get_softc(sc->smc_miibus));
1097         callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc);
1098 }
1099
1100 static void
1101 smc_mii_mediachg(struct smc_softc *sc)
1102 {
1103
1104         if (sc->smc_miibus == NULL)
1105                 return;
1106         mii_mediachg(device_get_softc(sc->smc_miibus));
1107 }
1108
1109 static int
1110 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command)
1111 {
1112         struct mii_data *mii;
1113
1114         if (sc->smc_miibus == NULL)
1115                 return (EINVAL);
1116
1117         mii = device_get_softc(sc->smc_miibus);
1118         return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command));
1119 }
1120
1121 static void
1122 smc_reset(struct smc_softc *sc)
1123 {
1124         u_int   ctr;
1125
1126         SMC_ASSERT_LOCKED(sc);
1127
1128         smc_select_bank(sc, 2);
1129
1130         /*
1131          * Mask all interrupts.
1132          */
1133         smc_write_1(sc, MSK, 0);
1134
1135         /*
1136          * Tell the device to reset.
1137          */
1138         smc_select_bank(sc, 0);
1139         smc_write_2(sc, RCR, RCR_SOFT_RST);
1140
1141         /*
1142          * Set up the configuration register.
1143          */
1144         smc_select_bank(sc, 1);
1145         smc_write_2(sc, CR, CR_EPH_POWER_EN);
1146         DELAY(1);
1147
1148         /*
1149          * Turn off transmit and receive.
1150          */
1151         smc_select_bank(sc, 0);
1152         smc_write_2(sc, TCR, 0);
1153         smc_write_2(sc, RCR, 0);
1154
1155         /*
1156          * Set up the control register.
1157          */
1158         smc_select_bank(sc, 1);
1159         ctr = smc_read_2(sc, CTR);
1160         ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE;
1161         smc_write_2(sc, CTR, ctr);
1162
1163         /*
1164          * Reset the MMU.
1165          */
1166         smc_select_bank(sc, 2);
1167         smc_mmu_wait(sc);
1168         smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET);
1169 }
1170
1171 static void
1172 smc_enable(struct smc_softc *sc)
1173 {
1174         struct ifnet            *ifp;
1175
1176         SMC_ASSERT_LOCKED(sc);
1177         ifp = sc->smc_ifp;
1178
1179         /*
1180          * Set up the receive/PHY control register.
1181          */
1182         smc_select_bank(sc, 0);
1183         smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT)
1184             | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT));
1185
1186         /*
1187          * Set up the transmit and receive control registers.
1188          */
1189         smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN);
1190         smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC);
1191
1192         /*
1193          * Set up the interrupt mask.
1194          */
1195         smc_select_bank(sc, 2);
1196         sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT;
1197         if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1198                 smc_write_1(sc, MSK, sc->smc_mask);
1199 }
1200
1201 static void
1202 smc_stop(struct smc_softc *sc)
1203 {
1204
1205         SMC_ASSERT_LOCKED(sc);
1206
1207         /*
1208          * Turn off callouts.
1209          */
1210         callout_stop(&sc->smc_watchdog);
1211         callout_stop(&sc->smc_mii_tick_ch);
1212
1213         /*
1214          * Mask all interrupts.
1215          */
1216         smc_select_bank(sc, 2);
1217         sc->smc_mask = 0;
1218         smc_write_1(sc, MSK, 0);
1219 #ifdef DEVICE_POLLING
1220         ether_poll_deregister(sc->smc_ifp);
1221         sc->smc_ifp->if_capenable &= ~IFCAP_POLLING;
1222 #endif
1223
1224         /*
1225          * Disable transmit and receive.
1226          */
1227         smc_select_bank(sc, 0);
1228         smc_write_2(sc, TCR, 0);
1229         smc_write_2(sc, RCR, 0);
1230
1231         sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1232 }
1233
1234 static void
1235 smc_watchdog(void *arg)
1236 {
1237         struct smc_softc        *sc;
1238
1239         sc = (struct smc_softc *)arg;
1240         device_printf(sc->smc_dev, "watchdog timeout\n");
1241         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
1242 }
1243
1244 static void
1245 smc_init(void *context)
1246 {
1247         struct smc_softc        *sc;
1248
1249         sc = (struct smc_softc *)context;
1250         SMC_LOCK(sc);
1251         smc_init_locked(sc);
1252         SMC_UNLOCK(sc);
1253 }
1254
1255 static void
1256 smc_init_locked(struct smc_softc *sc)
1257 {
1258         struct ifnet    *ifp;
1259
1260         ifp = sc->smc_ifp;
1261
1262         SMC_ASSERT_LOCKED(sc);
1263
1264         smc_reset(sc);
1265         smc_enable(sc);
1266
1267         ifp->if_drv_flags |= IFF_DRV_RUNNING;
1268         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1269
1270         smc_start_locked(ifp);
1271
1272         if (sc->smc_mii_tick != NULL)
1273                 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc);
1274
1275 #ifdef DEVICE_POLLING
1276         SMC_UNLOCK(sc);
1277         ether_poll_register(smc_poll, ifp);
1278         SMC_LOCK(sc);
1279         ifp->if_capenable |= IFCAP_POLLING;
1280 #endif
1281 }
1282
1283 static int
1284 smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1285 {
1286         struct smc_softc        *sc;
1287         int                     error;
1288
1289         sc = ifp->if_softc;
1290         error = 0;
1291
1292         switch (cmd) {
1293         case SIOCSIFFLAGS:
1294                 if ((ifp->if_flags & IFF_UP) == 0 &&
1295                     (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1296                         SMC_LOCK(sc);
1297                         smc_stop(sc);
1298                         SMC_UNLOCK(sc);
1299                 } else {
1300                         smc_init(sc);
1301                         if (sc->smc_mii_mediachg != NULL)
1302                                 sc->smc_mii_mediachg(sc);
1303                 }
1304                 break;
1305
1306         case SIOCADDMULTI:
1307         case SIOCDELMULTI:
1308                 /* XXX
1309                 SMC_LOCK(sc);
1310                 smc_setmcast(sc);
1311                 SMC_UNLOCK(sc);
1312                 */
1313                 error = EINVAL;
1314                 break;
1315
1316         case SIOCGIFMEDIA:
1317         case SIOCSIFMEDIA:
1318                 if (sc->smc_mii_mediaioctl == NULL) {
1319                         error = EINVAL;
1320                         break;
1321                 }
1322                 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd);
1323                 break;
1324
1325         default:
1326                 error = ether_ioctl(ifp, cmd, data);
1327                 break;
1328         }
1329
1330         return (error);
1331 }