sys/dev/smc/if_smc.c

   1 /*-
   2  * Copyright (c) 2008 Benno Rice.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  19  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  20  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  */
  24
  25 #include <sys/cdefs.h>
  26 __FBSDID("$FreeBSD$");
  27
  28 /*
  29  * Driver for SMSC LAN91C111, may work for older variants.
  30  */
  31
  32 #ifdef HAVE_KERNEL_OPTION_HEADERS
  33 #include "opt_device_polling.h"
  34 #endif
  35
  36 #include <sys/param.h>
  37 #include <sys/systm.h>
  38 #include <sys/errno.h>
  39 #include <sys/kernel.h>
  40 #include <sys/sockio.h>
  41 #include <sys/malloc.h>
  42 #include <sys/mbuf.h>
  43 #include <sys/queue.h>
  44 #include <sys/socket.h>
  45 #include <sys/syslog.h>
  46 #include <sys/taskqueue.h>
  47
  48 #include <sys/module.h>
  49 #include <sys/bus.h>
  50
  51 #include <machine/bus.h>
  52 #include <machine/resource.h>
  53 #include <sys/rman.h>
  54
  55 #include <net/ethernet.h>
  56 #include <net/if.h>
  57 #include <net/if_var.h>
  58 #include <net/if_arp.h>
  59 #include <net/if_dl.h>
  60 #include <net/if_types.h>
  61 #include <net/if_mib.h>
  62 #include <net/if_media.h>
  63
  64 #ifdef INET
  65 #include <netinet/in.h>
  66 #include <netinet/in_systm.h>
  67 #include <netinet/in_var.h>
  68 #include <netinet/ip.h>
  69 #endif
  70
  71 #include <net/bpf.h>
  72 #include <net/bpfdesc.h>
  73
  74 #include <dev/smc/if_smcreg.h>
  75 #include <dev/smc/if_smcvar.h>
  76
  77 #include <dev/mii/mii.h>
  78 #include <dev/mii/mii_bitbang.h>
  79 #include <dev/mii/miivar.h>
  80
  81 #define SMC_LOCK(sc)            mtx_lock(&(sc)->smc_mtx)
  82 #define SMC_UNLOCK(sc)          mtx_unlock(&(sc)->smc_mtx)
  83 #define SMC_ASSERT_LOCKED(sc)   mtx_assert(&(sc)->smc_mtx, MA_OWNED)
  84
  85 #define SMC_INTR_PRIORITY       0
  86 #define SMC_RX_PRIORITY         5
  87 #define SMC_TX_PRIORITY         10
  88
  89 devclass_t      smc_devclass;
  90
  91 static const char *smc_chip_ids[16] = {
  92         NULL, NULL, NULL,
  93         /* 3 */ "SMSC LAN91C90 or LAN91C92",
  94         /* 4 */ "SMSC LAN91C94",
  95         /* 5 */ "SMSC LAN91C95",
  96         /* 6 */ "SMSC LAN91C96",
  97         /* 7 */ "SMSC LAN91C100",
  98         /* 8 */ "SMSC LAN91C100FD",
  99         /* 9 */ "SMSC LAN91C110FD or LAN91C111FD",
 100         NULL, NULL, NULL,
 101         NULL, NULL, NULL
 102 };
 103
 104 static void     smc_init(void *);
 105 static void     smc_start(struct ifnet *);
 106 static void     smc_stop(struct smc_softc *);
 107 static int      smc_ioctl(struct ifnet *, u_long, caddr_t);
 108
 109 static void     smc_init_locked(struct smc_softc *);
 110 static void     smc_start_locked(struct ifnet *);
 111 static void     smc_reset(struct smc_softc *);
 112 static int      smc_mii_ifmedia_upd(struct ifnet *);
 113 static void     smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 114 static void     smc_mii_tick(void *);
 115 static void     smc_mii_mediachg(struct smc_softc *);
 116 static int      smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long);
 117
 118 static void     smc_task_intr(void *, int);
 119 static void     smc_task_rx(void *, int);
 120 static void     smc_task_tx(void *, int);
 121
 122 static driver_filter_t  smc_intr;
 123 static timeout_t        smc_watchdog;
 124 #ifdef DEVICE_POLLING
 125 static poll_handler_t   smc_poll;
 126 #endif
 127
 128 /*
 129  * MII bit-bang glue
 130  */
 131 static uint32_t smc_mii_bitbang_read(device_t);
 132 static void smc_mii_bitbang_write(device_t, uint32_t);
 133
 134 static const struct mii_bitbang_ops smc_mii_bitbang_ops = {
 135         smc_mii_bitbang_read,
 136         smc_mii_bitbang_write,
 137         {
 138                 MGMT_MDO,       /* MII_BIT_MDO */
 139                 MGMT_MDI,       /* MII_BIT_MDI */
 140                 MGMT_MCLK,      /* MII_BIT_MDC */
 141                 MGMT_MDOE,      /* MII_BIT_DIR_HOST_PHY */
 142                 0,              /* MII_BIT_DIR_PHY_HOST */
 143         }
 144 };
 145
 146 static __inline void
 147 smc_select_bank(struct smc_softc *sc, uint16_t bank)
 148 {
 149
 150         bus_barrier(sc->smc_reg, BSR, 2,
 151             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 152         bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK);
 153         bus_barrier(sc->smc_reg, BSR, 2,
 154             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 155 }
 156
 157 /* Never call this when not in bank 2. */
 158 static __inline void
 159 smc_mmu_wait(struct smc_softc *sc)
 160 {
 161
 162         KASSERT((bus_read_2(sc->smc_reg, BSR) &
 163             BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2",
 164             device_get_nameunit(sc->smc_dev)));
 165         while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY)
 166                 ;
 167 }
 168
 169 static __inline uint8_t
 170 smc_read_1(struct smc_softc *sc, bus_size_t offset)
 171 {
 172
 173         return (bus_read_1(sc->smc_reg, offset));
 174 }
 175
 176 static __inline void
 177 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val)
 178 {
 179
 180         bus_write_1(sc->smc_reg, offset, val);
 181 }
 182
 183 static __inline uint16_t
 184 smc_read_2(struct smc_softc *sc, bus_size_t offset)
 185 {
 186
 187         return (bus_read_2(sc->smc_reg, offset));
 188 }
 189
 190 static __inline void
 191 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val)
 192 {
 193
 194         bus_write_2(sc->smc_reg, offset, val);
 195 }
 196
 197 static __inline void
 198 smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
 199     bus_size_t count)
 200 {
 201
 202         bus_read_multi_2(sc->smc_reg, offset, datap, count);
 203 }
 204
 205 static __inline void
 206 smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
 207     bus_size_t count)
 208 {
 209
 210         bus_write_multi_2(sc->smc_reg, offset, datap, count);
 211 }
 212
 213 static __inline void
 214 smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length,
 215     int flags)
 216 {
 217
 218         bus_barrier(sc->smc_reg, offset, length, flags);
 219 }
 220
 221 int
 222 smc_probe(device_t dev)
 223 {
 224         int                     rid, type, error;
 225         uint16_t                val;
 226         struct smc_softc        *sc;
 227         struct resource         *reg;
 228
 229         sc = device_get_softc(dev);
 230         rid = 0;
 231         type = SYS_RES_IOPORT;
 232         error = 0;
 233
 234         if (sc->smc_usemem)
 235                 type = SYS_RES_MEMORY;
 236
 237         reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE);
 238         if (reg == NULL) {
 239                 if (bootverbose)
 240                         device_printf(dev,
 241                             "could not allocate I/O resource for probe\n");
 242                 return (ENXIO);
 243         }
 244
 245         /* Check for the identification value in the BSR. */
 246         val = bus_read_2(reg, BSR);
 247         if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
 248                 if (bootverbose)
 249                         device_printf(dev, "identification value not in BSR\n");
 250                 error = ENXIO;
 251                 goto done;
 252         }
 253
 254         /*
 255          * Try switching banks and make sure we still get the identification
 256          * value.
 257          */
 258         bus_write_2(reg, BSR, 0);
 259         val = bus_read_2(reg, BSR);
 260         if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
 261                 if (bootverbose)
 262                         device_printf(dev,
 263                             "identification value not in BSR after write\n");
 264                 error = ENXIO;
 265                 goto done;
 266         }
 267
 268 #if 0
 269         /* Check the BAR. */
 270         bus_write_2(reg, BSR, 1);
 271         val = bus_read_2(reg, BAR);
 272         val = BAR_ADDRESS(val);
 273         if (rman_get_start(reg) != val) {
 274                 if (bootverbose)
 275                         device_printf(dev, "BAR address %x does not match "
 276                             "I/O resource address %lx\n", val,
 277                             rman_get_start(reg));
 278                 error = ENXIO;
 279                 goto done;
 280         }
 281 #endif
 282
 283         /* Compare REV against known chip revisions. */
 284         bus_write_2(reg, BSR, 3);
 285         val = bus_read_2(reg, REV);
 286         val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
 287         if (smc_chip_ids[val] == NULL) {
 288                 if (bootverbose)
 289                         device_printf(dev, "Unknown chip revision: %d\n", val);
 290                 error = ENXIO;
 291                 goto done;
 292         }
 293
 294         device_set_desc(dev, smc_chip_ids[val]);
 295
 296 done:
 297         bus_release_resource(dev, type, rid, reg);
 298         return (error);
 299 }
 300
 301 int
 302 smc_attach(device_t dev)
 303 {
 304         int                     type, error;
 305         uint16_t                val;
 306         u_char                  eaddr[ETHER_ADDR_LEN];
 307         struct smc_softc        *sc;
 308         struct ifnet            *ifp;
 309
 310         sc = device_get_softc(dev);
 311         error = 0;
 312
 313         sc->smc_dev = dev;
 314
 315         ifp = sc->smc_ifp = if_alloc(IFT_ETHER);
 316         if (ifp == NULL) {
 317                 error = ENOSPC;
 318                 goto done;
 319         }
 320
 321         mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
 322
 323         /* Set up watchdog callout. */
 324         callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0);
 325
 326         type = SYS_RES_IOPORT;
 327         if (sc->smc_usemem)
 328                 type = SYS_RES_MEMORY;
 329
 330         sc->smc_reg_rid = 0;
 331         sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0,
 332             16, RF_ACTIVE);
 333         if (sc->smc_reg == NULL) {
 334                 error = ENXIO;
 335                 goto done;
 336         }
 337
 338         sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0,
 339             ~0, 1, RF_ACTIVE | RF_SHAREABLE);
 340         if (sc->smc_irq == NULL) {
 341                 error = ENXIO;
 342                 goto done;
 343         }
 344
 345         SMC_LOCK(sc);
 346         smc_reset(sc);
 347         SMC_UNLOCK(sc);
 348
 349         smc_select_bank(sc, 3);
 350         val = smc_read_2(sc, REV);
 351         sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
 352         sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT;
 353         if (bootverbose)
 354                 device_printf(dev, "revision %x\n", sc->smc_rev);
 355
 356         callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx,
 357             CALLOUT_RETURNUNLOCKED);
 358         if (sc->smc_chip >= REV_CHIP_91110FD) {
 359                 (void)mii_attach(dev, &sc->smc_miibus, ifp,
 360                     smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK,
 361                     MII_PHY_ANY, MII_OFFSET_ANY, 0);
 362                 if (sc->smc_miibus != NULL) {
 363                         sc->smc_mii_tick = smc_mii_tick;
 364                         sc->smc_mii_mediachg = smc_mii_mediachg;
 365                         sc->smc_mii_mediaioctl = smc_mii_mediaioctl;
 366                 }
 367         }
 368
 369         smc_select_bank(sc, 1);
 370         eaddr[0] = smc_read_1(sc, IAR0);
 371         eaddr[1] = smc_read_1(sc, IAR1);
 372         eaddr[2] = smc_read_1(sc, IAR2);
 373         eaddr[3] = smc_read_1(sc, IAR3);
 374         eaddr[4] = smc_read_1(sc, IAR4);
 375         eaddr[5] = smc_read_1(sc, IAR5);
 376
 377         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 378         ifp->if_softc = sc;
 379         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 380         ifp->if_init = smc_init;
 381         ifp->if_ioctl = smc_ioctl;
 382         ifp->if_start = smc_start;
 383         IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
 384         IFQ_SET_READY(&ifp->if_snd);
 385
 386         ifp->if_capabilities = ifp->if_capenable = 0;
 387
 388 #ifdef DEVICE_POLLING
 389         ifp->if_capabilities |= IFCAP_POLLING;
 390 #endif
 391
 392         ether_ifattach(ifp, eaddr);
 393
 394         /* Set up taskqueue */
 395         TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp);
 396         TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp);
 397         TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp);
 398         sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT,
 399             taskqueue_thread_enqueue, &sc->smc_tq);
 400         taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq",
 401             device_get_nameunit(sc->smc_dev));
 402
 403         /* Mask all interrupts. */
 404         sc->smc_mask = 0;
 405         smc_write_1(sc, MSK, 0);
 406
 407         /* Wire up interrupt */
 408         error = bus_setup_intr(dev, sc->smc_irq,
 409             INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih);
 410         if (error != 0)
 411                 goto done;
 412
 413 done:
 414         if (error != 0)
 415                 smc_detach(dev);
 416         return (error);
 417 }
 418
 419 int
 420 smc_detach(device_t dev)
 421 {
 422         int                     type;
 423         struct smc_softc        *sc;
 424
 425         sc = device_get_softc(dev);
 426         SMC_LOCK(sc);
 427         smc_stop(sc);
 428         SMC_UNLOCK(sc);
 429
 430         if (sc->smc_ifp != NULL) {
 431                 ether_ifdetach(sc->smc_ifp);
 432         }
 433
 434         callout_drain(&sc->smc_watchdog);
 435         callout_drain(&sc->smc_mii_tick_ch);
 436
 437 #ifdef DEVICE_POLLING
 438         if (sc->smc_ifp->if_capenable & IFCAP_POLLING)
 439                 ether_poll_deregister(sc->smc_ifp);
 440 #endif
 441
 442         if (sc->smc_ih != NULL)
 443                 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih);
 444
 445         if (sc->smc_tq != NULL) {
 446                 taskqueue_drain(sc->smc_tq, &sc->smc_intr);
 447                 taskqueue_drain(sc->smc_tq, &sc->smc_rx);
 448                 taskqueue_drain(sc->smc_tq, &sc->smc_tx);
 449                 taskqueue_free(sc->smc_tq);
 450                 sc->smc_tq = NULL;
 451         }
 452
 453         if (sc->smc_ifp != NULL) {
 454                 if_free(sc->smc_ifp);
 455         }
 456
 457         if (sc->smc_miibus != NULL) {
 458                 device_delete_child(sc->smc_dev, sc->smc_miibus);
 459                 bus_generic_detach(sc->smc_dev);
 460         }
 461
 462         if (sc->smc_reg != NULL) {
 463                 type = SYS_RES_IOPORT;
 464                 if (sc->smc_usemem)
 465                         type = SYS_RES_MEMORY;
 466
 467                 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid,
 468                     sc->smc_reg);
 469         }
 470
 471         if (sc->smc_irq != NULL)
 472                 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid,
 473                    sc->smc_irq);
 474
 475         if (mtx_initialized(&sc->smc_mtx))
 476                 mtx_destroy(&sc->smc_mtx);
 477
 478         return (0);
 479 }
 480
 481 static void
 482 smc_start(struct ifnet *ifp)
 483 {
 484         struct smc_softc        *sc;
 485
 486         sc = ifp->if_softc;
 487         SMC_LOCK(sc);
 488         smc_start_locked(ifp);
 489         SMC_UNLOCK(sc);
 490 }
 491
 492 static void
 493 smc_start_locked(struct ifnet *ifp)
 494 {
 495         struct smc_softc        *sc;
 496         struct mbuf             *m;
 497         u_int                   len, npages, spin_count;
 498
 499         sc = ifp->if_softc;
 500         SMC_ASSERT_LOCKED(sc);
 501
 502         if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
 503                 return;
 504         if (IFQ_IS_EMPTY(&ifp->if_snd))
 505                 return;
 506
 507         /*
 508          * Grab the next packet.  If it's too big, drop it.
 509          */
 510         IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
 511         len = m_length(m, NULL);
 512         len += (len & 1);
 513         if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) {
 514                 if_printf(ifp, "large packet discarded\n");
 515                 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
 516                 m_freem(m);
 517                 return; /* XXX readcheck? */
 518         }
 519
 520         /*
 521          * Flag that we're busy.
 522          */
 523         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 524         sc->smc_pending = m;
 525
 526         /*
 527          * Work out how many 256 byte "pages" we need.  We have to include the
 528          * control data for the packet in this calculation.
 529          */
 530         npages = (len * PKT_CTRL_DATA_LEN) >> 8;
 531         if (npages == 0)
 532                 npages = 1;
 533
 534         /*
 535          * Request memory.
 536          */
 537         smc_select_bank(sc, 2);
 538         smc_mmu_wait(sc);
 539         smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages);
 540
 541         /*
 542          * Spin briefly to see if the allocation succeeds.
 543          */
 544         spin_count = TX_ALLOC_WAIT_TIME;
 545         do {
 546                 if (smc_read_1(sc, IST) & ALLOC_INT) {
 547                         smc_write_1(sc, ACK, ALLOC_INT);
 548                         break;
 549                 }
 550         } while (--spin_count);
 551
 552         /*
 553          * If the allocation is taking too long, unmask the alloc interrupt
 554          * and wait.
 555          */
 556         if (spin_count == 0) {
 557                 sc->smc_mask |= ALLOC_INT;
 558                 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 559                         smc_write_1(sc, MSK, sc->smc_mask);
 560                 return;
 561         }
 562
 563         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 564 }
 565
 566 static void
 567 smc_task_tx(void *context, int pending)
 568 {
 569         struct ifnet            *ifp;
 570         struct smc_softc        *sc;
 571         struct mbuf             *m, *m0;
 572         u_int                   packet, len;
 573         int                     last_len;
 574         uint8_t                 *data;
 575
 576         (void)pending;
 577         ifp = (struct ifnet *)context;
 578         sc = ifp->if_softc;
 579
 580         SMC_LOCK(sc);
 581
 582         if (sc->smc_pending == NULL) {
 583                 SMC_UNLOCK(sc);
 584                 goto next_packet;
 585         }
 586
 587         m = m0 = sc->smc_pending;
 588         sc->smc_pending = NULL;
 589         smc_select_bank(sc, 2);
 590
 591         /*
 592          * Check the allocation result.
 593          */
 594         packet = smc_read_1(sc, ARR);
 595
 596         /*
 597          * If the allocation failed, requeue the packet and retry.
 598          */
 599         if (packet & ARR_FAILED) {
 600                 IFQ_DRV_PREPEND(&ifp->if_snd, m);
 601                 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
 602                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 603                 smc_start_locked(ifp);
 604                 SMC_UNLOCK(sc);
 605                 return;
 606         }
 607
 608         /*
 609          * Tell the device to write to our packet number.
 610          */
 611         smc_write_1(sc, PNR, packet);
 612         smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR);
 613
 614         /*
 615          * Tell the device how long the packet is (including control data).
 616          */
 617         len = m_length(m, 0);
 618         len += PKT_CTRL_DATA_LEN;
 619         smc_write_2(sc, DATA0, 0);
 620         smc_write_2(sc, DATA0, len);
 621
 622         /*
 623          * Push the data out to the device.
 624          */
 625         data = NULL;
 626         last_len = 0;
 627         for (; m != NULL; m = m->m_next) {
 628                 data = mtod(m, uint8_t *);
 629                 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2);
 630                 last_len = m->m_len;
 631         }
 632
 633         /*
 634          * Push out the control byte and and the odd byte if needed.
 635          */
 636         if ((len & 1) != 0 && data != NULL)
 637                 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]);
 638         else
 639                 smc_write_2(sc, DATA0, 0);
 640
 641         /*
 642          * Unmask the TX empty interrupt.
 643          */
 644         sc->smc_mask |= TX_EMPTY_INT;
 645         if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 646                 smc_write_1(sc, MSK, sc->smc_mask);
 647
 648         /*
 649          * Enqueue the packet.
 650          */
 651         smc_mmu_wait(sc);
 652         smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE);
 653         callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc);
 654
 655         /*
 656          * Finish up.
 657          */
 658         if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
 659         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 660         SMC_UNLOCK(sc);
 661         BPF_MTAP(ifp, m0);
 662         m_freem(m0);
 663
 664 next_packet:
 665         /*
 666          * See if there's anything else to do.
 667          */
 668         smc_start(ifp);
 669 }
 670
 671 static void
 672 smc_task_rx(void *context, int pending)
 673 {
 674         u_int                   packet, status, len;
 675         uint8_t                 *data;
 676         struct ifnet            *ifp;
 677         struct smc_softc        *sc;
 678         struct mbuf             *m, *mhead, *mtail;
 679
 680         (void)pending;
 681         ifp = (struct ifnet *)context;
 682         sc = ifp->if_softc;
 683         mhead = mtail = NULL;
 684
 685         SMC_LOCK(sc);
 686
 687         packet = smc_read_1(sc, FIFO_RX);
 688         while ((packet & FIFO_EMPTY) == 0) {
 689                 /*
 690                  * Grab an mbuf and attach a cluster.
 691                  */
 692                 MGETHDR(m, M_NOWAIT, MT_DATA);
 693                 if (m == NULL) {
 694                         break;
 695                 }
 696                 MCLGET(m, M_NOWAIT);
 697                 if ((m->m_flags & M_EXT) == 0) {
 698                         m_freem(m);
 699                         break;
 700                 }
 701
 702                 /*
 703                  * Point to the start of the packet.
 704                  */
 705                 smc_select_bank(sc, 2);
 706                 smc_write_1(sc, PNR, packet);
 707                 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
 708
 709                 /*
 710                  * Grab status and packet length.
 711                  */
 712                 status = smc_read_2(sc, DATA0);
 713                 len = smc_read_2(sc, DATA0) & RX_LEN_MASK;
 714                 len -= 6;
 715                 if (status & RX_ODDFRM)
 716                         len += 1;
 717
 718                 /*
 719                  * Check for errors.
 720                  */
 721                 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) {
 722                         smc_mmu_wait(sc);
 723                         smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
 724                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 725                         m_freem(m);
 726                         break;
 727                 }
 728
 729                 /*
 730                  * Set the mbuf up the way we want it.
 731                  */
 732                 m->m_pkthdr.rcvif = ifp;
 733                 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */
 734                 m_adj(m, ETHER_ALIGN);
 735
 736                 /*
 737                  * Pull the packet out of the device.  Make sure we're in the
 738                  * right bank first as things may have changed while we were
 739                  * allocating our mbuf.
 740                  */
 741                 smc_select_bank(sc, 2);
 742                 smc_write_1(sc, PNR, packet);
 743                 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
 744                 data = mtod(m, uint8_t *);
 745                 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1);
 746                 if (len & 1) {
 747                         data += len & ~1;
 748                         *data = smc_read_1(sc, DATA0);
 749                 }
 750
 751                 /*
 752                  * Tell the device we're done.
 753                  */
 754                 smc_mmu_wait(sc);
 755                 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
 756                 if (m == NULL) {
 757                         break;
 758                 }
 759
 760                 if (mhead == NULL) {
 761                         mhead = mtail = m;
 762                         m->m_next = NULL;
 763                 } else {
 764                         mtail->m_next = m;
 765                         mtail = m;
 766                 }
 767                 packet = smc_read_1(sc, FIFO_RX);
 768         }
 769
 770         sc->smc_mask |= RCV_INT;
 771         if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 772                 smc_write_1(sc, MSK, sc->smc_mask);
 773
 774         SMC_UNLOCK(sc);
 775
 776         while (mhead != NULL) {
 777                 m = mhead;
 778                 mhead = mhead->m_next;
 779                 m->m_next = NULL;
 780                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
 781                 (*ifp->if_input)(ifp, m);
 782         }
 783 }
 784
 785 #ifdef DEVICE_POLLING
 786 static void
 787 smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
 788 {
 789         struct smc_softc        *sc;
 790
 791         sc = ifp->if_softc;
 792
 793         SMC_LOCK(sc);
 794         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
 795                 SMC_UNLOCK(sc);
 796                 return;
 797         }
 798         SMC_UNLOCK(sc);
 799
 800         if (cmd == POLL_AND_CHECK_STATUS)
 801                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
 802 }
 803 #endif
 804
 805 static int
 806 smc_intr(void *context)
 807 {
 808         struct smc_softc        *sc;
 809
 810         sc = (struct smc_softc *)context;
 811         /*
 812          * Block interrupts in order to let smc_task_intr to kick in
 813          */
 814         smc_write_1(sc, MSK, 0);
 815         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
 816         return (FILTER_HANDLED);
 817 }
 818
 819 static void
 820 smc_task_intr(void *context, int pending)
 821 {
 822         struct smc_softc        *sc;
 823         struct ifnet            *ifp;
 824         u_int                   status, packet, counter, tcr;
 825
 826         (void)pending;
 827         ifp = (struct ifnet *)context;
 828         sc = ifp->if_softc;
 829
 830         SMC_LOCK(sc);
 831
 832         smc_select_bank(sc, 2);
 833
 834         /*
 835          * Find out what interrupts are flagged.
 836          */
 837         status = smc_read_1(sc, IST) & sc->smc_mask;
 838
 839         /*
 840          * Transmit error
 841          */
 842         if (status & TX_INT) {
 843                 /*
 844                  * Kill off the packet if there is one and re-enable transmit.
 845                  */
 846                 packet = smc_read_1(sc, FIFO_TX);
 847                 if ((packet & FIFO_EMPTY) == 0) {
 848                         smc_write_1(sc, PNR, packet);
 849                         smc_write_2(sc, PTR, 0 | PTR_READ |
 850                             PTR_AUTO_INCR);
 851                         tcr = smc_read_2(sc, DATA0);
 852                         if ((tcr & EPHSR_TX_SUC) == 0)
 853                                 device_printf(sc->smc_dev,
 854                                     "bad packet\n");
 855                         smc_mmu_wait(sc);
 856                         smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT);
 857
 858                         smc_select_bank(sc, 0);
 859                         tcr = smc_read_2(sc, TCR);
 860                         tcr |= TCR_TXENA | TCR_PAD_EN;
 861                         smc_write_2(sc, TCR, tcr);
 862                         smc_select_bank(sc, 2);
 863                         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 864                 }
 865
 866                 /*
 867                  * Ack the interrupt.
 868                  */
 869                 smc_write_1(sc, ACK, TX_INT);
 870         }
 871
 872         /*
 873          * Receive
 874          */
 875         if (status & RCV_INT) {
 876                 smc_write_1(sc, ACK, RCV_INT);
 877                 sc->smc_mask &= ~RCV_INT;
 878                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx);
 879         }
 880
 881         /*
 882          * Allocation
 883          */
 884         if (status & ALLOC_INT) {
 885                 smc_write_1(sc, ACK, ALLOC_INT);
 886                 sc->smc_mask &= ~ALLOC_INT;
 887                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 888         }
 889
 890         /*
 891          * Receive overrun
 892          */
 893         if (status & RX_OVRN_INT) {
 894                 smc_write_1(sc, ACK, RX_OVRN_INT);
 895                 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 896         }
 897
 898         /*
 899          * Transmit empty
 900          */
 901         if (status & TX_EMPTY_INT) {
 902                 smc_write_1(sc, ACK, TX_EMPTY_INT);
 903                 sc->smc_mask &= ~TX_EMPTY_INT;
 904                 callout_stop(&sc->smc_watchdog);
 905
 906                 /*
 907                  * Update collision stats.
 908                  */
 909                 smc_select_bank(sc, 0);
 910                 counter = smc_read_2(sc, ECR);
 911                 smc_select_bank(sc, 2);
 912                 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
 913                     ((counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT) +
 914                     ((counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT));
 915
 916                 /*
 917                  * See if there are any packets to transmit.
 918                  */
 919                 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
 920         }
 921
 922         /*
 923          * Update the interrupt mask.
 924          */
 925         if ((ifp->if_capenable & IFCAP_POLLING) == 0)
 926                 smc_write_1(sc, MSK, sc->smc_mask);
 927
 928         SMC_UNLOCK(sc);
 929 }
 930
 931 static uint32_t
 932 smc_mii_bitbang_read(device_t dev)
 933 {
 934         struct smc_softc        *sc;
 935         uint32_t                val;
 936
 937         sc = device_get_softc(dev);
 938
 939         SMC_ASSERT_LOCKED(sc);
 940         KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
 941             ("%s: smc_mii_bitbang_read called with bank %d (!= 3)",
 942             device_get_nameunit(sc->smc_dev),
 943             smc_read_2(sc, BSR) & BSR_BANK_MASK));
 944
 945         val = smc_read_2(sc, MGMT);
 946         smc_barrier(sc, MGMT, 2,
 947             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 948
 949         return (val);
 950 }
 951
 952 static void
 953 smc_mii_bitbang_write(device_t dev, uint32_t val)
 954 {
 955         struct smc_softc        *sc;
 956
 957         sc = device_get_softc(dev);
 958
 959         SMC_ASSERT_LOCKED(sc);
 960         KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
 961             ("%s: smc_mii_bitbang_write called with bank %d (!= 3)",
 962             device_get_nameunit(sc->smc_dev),
 963             smc_read_2(sc, BSR) & BSR_BANK_MASK));
 964
 965         smc_write_2(sc, MGMT, val);
 966         smc_barrier(sc, MGMT, 2,
 967             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 968 }
 969
 970 int
 971 smc_miibus_readreg(device_t dev, int phy, int reg)
 972 {
 973         struct smc_softc        *sc;
 974         int                     val;
 975
 976         sc = device_get_softc(dev);
 977
 978         SMC_LOCK(sc);
 979
 980         smc_select_bank(sc, 3);
 981
 982         val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg);
 983
 984         SMC_UNLOCK(sc);
 985         return (val);
 986 }
 987
 988 int
 989 smc_miibus_writereg(device_t dev, int phy, int reg, int data)
 990 {
 991         struct smc_softc        *sc;
 992
 993         sc = device_get_softc(dev);
 994
 995         SMC_LOCK(sc);
 996
 997         smc_select_bank(sc, 3);
 998
 999         mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data);
1000
1001         SMC_UNLOCK(sc);
1002         return (0);
1003 }
1004
1005 void
1006 smc_miibus_statchg(device_t dev)
1007 {
1008         struct smc_softc        *sc;
1009         struct mii_data         *mii;
1010         uint16_t                tcr;
1011
1012         sc = device_get_softc(dev);
1013         mii = device_get_softc(sc->smc_miibus);
1014
1015         SMC_LOCK(sc);
1016
1017         smc_select_bank(sc, 0);
1018         tcr = smc_read_2(sc, TCR);
1019
1020         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1021                 tcr |= TCR_SWFDUP;
1022         else
1023                 tcr &= ~TCR_SWFDUP;
1024
1025         smc_write_2(sc, TCR, tcr);
1026
1027         SMC_UNLOCK(sc);
1028 }
1029
1030 static int
1031 smc_mii_ifmedia_upd(struct ifnet *ifp)
1032 {
1033         struct smc_softc        *sc;
1034         struct mii_data         *mii;
1035
1036         sc = ifp->if_softc;
1037         if (sc->smc_miibus == NULL)
1038                 return (ENXIO);
1039
1040         mii = device_get_softc(sc->smc_miibus);
1041         return (mii_mediachg(mii));
1042 }
1043
1044 static void
1045 smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1046 {
1047         struct smc_softc        *sc;
1048         struct mii_data         *mii;
1049
1050         sc = ifp->if_softc;
1051         if (sc->smc_miibus == NULL)
1052                 return;
1053
1054         mii = device_get_softc(sc->smc_miibus);
1055         mii_pollstat(mii);
1056         ifmr->ifm_active = mii->mii_media_active;
1057         ifmr->ifm_status = mii->mii_media_status;
1058 }
1059
1060 static void
1061 smc_mii_tick(void *context)
1062 {
1063         struct smc_softc        *sc;
1064
1065         sc = (struct smc_softc *)context;
1066
1067         if (sc->smc_miibus == NULL)
1068                 return;
1069
1070         SMC_UNLOCK(sc);
1071
1072         mii_tick(device_get_softc(sc->smc_miibus));
1073         callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc);
1074 }
1075
1076 static void
1077 smc_mii_mediachg(struct smc_softc *sc)
1078 {
1079
1080         if (sc->smc_miibus == NULL)
1081                 return;
1082         mii_mediachg(device_get_softc(sc->smc_miibus));
1083 }
1084
1085 static int
1086 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command)
1087 {
1088         struct mii_data *mii;
1089
1090         if (sc->smc_miibus == NULL)
1091                 return (EINVAL);
1092
1093         mii = device_get_softc(sc->smc_miibus);
1094         return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command));
1095 }
1096
1097 static void
1098 smc_reset(struct smc_softc *sc)
1099 {
1100         u_int   ctr;
1101
1102         SMC_ASSERT_LOCKED(sc);
1103
1104         smc_select_bank(sc, 2);
1105
1106         /*
1107          * Mask all interrupts.
1108          */
1109         smc_write_1(sc, MSK, 0);
1110
1111         /*
1112          * Tell the device to reset.
1113          */
1114         smc_select_bank(sc, 0);
1115         smc_write_2(sc, RCR, RCR_SOFT_RST);
1116
1117         /*
1118          * Set up the configuration register.
1119          */
1120         smc_select_bank(sc, 1);
1121         smc_write_2(sc, CR, CR_EPH_POWER_EN);
1122         DELAY(1);
1123
1124         /*
1125          * Turn off transmit and receive.
1126          */
1127         smc_select_bank(sc, 0);
1128         smc_write_2(sc, TCR, 0);
1129         smc_write_2(sc, RCR, 0);
1130
1131         /*
1132          * Set up the control register.
1133          */
1134         smc_select_bank(sc, 1);
1135         ctr = smc_read_2(sc, CTR);
1136         ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE;
1137         smc_write_2(sc, CTR, ctr);
1138
1139         /*
1140          * Reset the MMU.
1141          */
1142         smc_select_bank(sc, 2);
1143         smc_mmu_wait(sc);
1144         smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET);
1145 }
1146
1147 static void
1148 smc_enable(struct smc_softc *sc)
1149 {
1150         struct ifnet            *ifp;
1151
1152         SMC_ASSERT_LOCKED(sc);
1153         ifp = sc->smc_ifp;
1154
1155         /*
1156          * Set up the receive/PHY control register.
1157          */
1158         smc_select_bank(sc, 0);
1159         smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT)
1160             | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT));
1161
1162         /*
1163          * Set up the transmit and receive control registers.
1164          */
1165         smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN);
1166         smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC);
1167
1168         /*
1169          * Set up the interrupt mask.
1170          */
1171         smc_select_bank(sc, 2);
1172         sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT;
1173         if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1174                 smc_write_1(sc, MSK, sc->smc_mask);
1175 }
1176
1177 static void
1178 smc_stop(struct smc_softc *sc)
1179 {
1180
1181         SMC_ASSERT_LOCKED(sc);
1182
1183         /*
1184          * Turn off callouts.
1185          */
1186         callout_stop(&sc->smc_watchdog);
1187         callout_stop(&sc->smc_mii_tick_ch);
1188
1189         /*
1190          * Mask all interrupts.
1191          */
1192         smc_select_bank(sc, 2);
1193         sc->smc_mask = 0;
1194         smc_write_1(sc, MSK, 0);
1195 #ifdef DEVICE_POLLING
1196         ether_poll_deregister(sc->smc_ifp);
1197         sc->smc_ifp->if_capenable &= ~IFCAP_POLLING;
1198         sc->smc_ifp->if_capenable &= ~IFCAP_POLLING_NOCOUNT;
1199 #endif
1200
1201         /*
1202          * Disable transmit and receive.
1203          */
1204         smc_select_bank(sc, 0);
1205         smc_write_2(sc, TCR, 0);
1206         smc_write_2(sc, RCR, 0);
1207
1208         sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1209 }
1210
1211 static void
1212 smc_watchdog(void *arg)
1213 {
1214         struct smc_softc        *sc;
1215
1216         sc = (struct smc_softc *)arg;
1217         device_printf(sc->smc_dev, "watchdog timeout\n");
1218         taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
1219 }
1220
1221 static void
1222 smc_init(void *context)
1223 {
1224         struct smc_softc        *sc;
1225
1226         sc = (struct smc_softc *)context;
1227         SMC_LOCK(sc);
1228         smc_init_locked(sc);
1229         SMC_UNLOCK(sc);
1230 }
1231
1232 static void
1233 smc_init_locked(struct smc_softc *sc)
1234 {
1235         struct ifnet    *ifp;
1236
1237         SMC_ASSERT_LOCKED(sc);
1238         ifp = sc->smc_ifp;
1239         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1240                 return;
1241
1242         smc_reset(sc);
1243         smc_enable(sc);
1244
1245         ifp->if_drv_flags |= IFF_DRV_RUNNING;
1246         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1247
1248         smc_start_locked(ifp);
1249
1250         if (sc->smc_mii_tick != NULL)
1251                 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc);
1252
1253 #ifdef DEVICE_POLLING
1254         SMC_UNLOCK(sc);
1255         ether_poll_register(smc_poll, ifp);
1256         SMC_LOCK(sc);
1257         ifp->if_capenable |= IFCAP_POLLING;
1258         ifp->if_capenable |= IFCAP_POLLING_NOCOUNT;
1259 #endif
1260 }
1261
1262 static int
1263 smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1264 {
1265         struct smc_softc        *sc;
1266         int                     error;
1267
1268         sc = ifp->if_softc;
1269         error = 0;
1270
1271         switch (cmd) {
1272         case SIOCSIFFLAGS:
1273                 if ((ifp->if_flags & IFF_UP) == 0 &&
1274                     (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1275                         SMC_LOCK(sc);
1276                         smc_stop(sc);
1277                         SMC_UNLOCK(sc);
1278                 } else {
1279                         smc_init(sc);
1280                         if (sc->smc_mii_mediachg != NULL)
1281                                 sc->smc_mii_mediachg(sc);
1282                 }
1283                 break;
1284
1285         case SIOCADDMULTI:
1286         case SIOCDELMULTI:
1287                 /* XXX
1288                 SMC_LOCK(sc);
1289                 smc_setmcast(sc);
1290                 SMC_UNLOCK(sc);
1291                 */
1292                 error = EINVAL;
1293                 break;
1294
1295         case SIOCGIFMEDIA:
1296         case SIOCSIFMEDIA:
1297                 if (sc->smc_mii_mediaioctl == NULL) {
1298                         error = EINVAL;
1299                         break;
1300                 }
1301                 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd);
1302                 break;
1303
1304         default:
1305                 error = ether_ioctl(ifp, cmd, data);
1306                 break;
1307         }
1308
1309         return (error);
1310 }